Commit 05b6ca9b authored by Bastian Koppelmann's avatar Bastian Koppelmann
Browse files

target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result 



If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.

Signed-off-by: default avatarBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
parent 97af820f

target-tricore/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -6451,8 +6451,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) 
        /* sv */

        tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);

        /* write result */

        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);

        tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);

        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);

        tcg_temp_free(temp);

        tcg_temp_free(temp2);

        tcg_temp_free(temp3);