Commit 056e6bae authored by Richard Henderson's avatar Richard Henderson
Browse files

hw/alpha: Don't use get_system_io 



Advancements in the ioport subsystem mean that we need no longer
thunk memory-mapped i/o through the system-io address space.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent c3cb8e77

hw/alpha/alpha_sys.h

+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4], 
                     pci_map_irq_fn);



/* alpha_pci.c.  */

extern const MemoryRegionOps alpha_pci_bw_io_ops;

extern const MemoryRegionOps alpha_pci_conf1_ops;

extern const MemoryRegionOps alpha_pci_iack_ops;

hw/alpha/pci.c

+0 −44
Original line number Diff line number Diff line
@@ -12,50 +12,6 @@ 
#include "sysemu/sysemu.h"





/* PCI IO reads/writes, to byte-word addressable memory.  */

/* ??? Doesn't handle multiple PCI busses.  */



static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)

{

    switch (size) {

    case 1:

        return cpu_inb(addr);

    case 2:

        return cpu_inw(addr);

    case 4:

        return cpu_inl(addr);

    }

    abort();

}



static void bw_io_write(void *opaque, hwaddr addr,

                        uint64_t val, unsigned size)

{

    switch (size) {

    case 1:

        cpu_outb(addr, val);

        break;

    case 2:

        cpu_outw(addr, val);

        break;

    case 4:

        cpu_outl(addr, val);

        break;

    default:

        abort();

    }

}



const MemoryRegionOps alpha_pci_bw_io_ops = {

    .read = bw_io_read,

    .write = bw_io_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .impl = {

        .min_access_size = 1,

        .max_access_size = 4,

    },

};



/* PCI config space reads/writes, to byte-word addressable memory.  */

static uint64_t bw_conf1_read(void *opaque, hwaddr addr,

                              unsigned size)

hw/alpha/typhoon.c

+8 −12
Original line number Diff line number Diff line
@@ -705,7 +705,6 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
    const uint64_t MB = 1024 * 1024;

    const uint64_t GB = 1024 * MB;

    MemoryRegion *addr_space = get_system_memory();

    MemoryRegion *addr_space_io = get_system_io();

    DeviceState *dev;

    TyphoonState *s;

    PCIHostState *phb;
@@ -765,28 +764,25 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
                                &s->pchip.reg_mem);



    /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB.  */

    /* ??? Ideally we drop the "system" i/o space on the floor and give the

       PCI subsystem the full address space reserved by the chipset.

       We can't do that until the MEM and IO paths in memory.c are unified.  */

    memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_bw_io_ops,

                          NULL, "pci0-io", 32*MB);

    memory_region_init(&s->pchip.reg_io, OBJECT(s), "pci0-io", 32*MB);

    memory_region_add_subregion(addr_space, 0x801fc000000ULL,

                                &s->pchip.reg_io);



    b = pci_register_bus(dev, "pci",

                         typhoon_set_irq, sys_map_irq, s,

                         &s->pchip.reg_mem, addr_space_io, 0, 64, TYPE_PCI_BUS);

                         &s->pchip.reg_mem, &s->pchip.reg_io,

                         0, 64, TYPE_PCI_BUS);

    phb->bus = b;



    /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB.  */

    memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, b,

                          "pci0-iack", 64*MB);

    memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,

                          b, "pci0-iack", 64*MB);

    memory_region_add_subregion(addr_space, 0x801f8000000ULL,

                                &s->pchip.reg_iack);



    /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB.  */

    memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, b,

                          "pci0-conf", 16*MB);

    memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops,

                          b, "pci0-conf", 16*MB);

    memory_region_add_subregion(addr_space, 0x801fe000000ULL,

                                &s->pchip.reg_conf);
@@ -804,7 +800,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
    {

        qemu_irq isa_pci_irq, *isa_irqs;



        *isa_bus = isa_bus_new(NULL, addr_space_io);

        *isa_bus = isa_bus_new(NULL, &s->pchip.reg_io);

        isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);

        isa_irqs = i8259_init(*isa_bus, isa_pci_irq);

        isa_bus_irqs(*isa_bus, isa_irqs);