Commit 05538220 authored by Nikunj A Dadhania's avatar Nikunj A Dadhania Committed by David Gibson
Browse files

target-ppc: Add xsxsigdp instruction 



xsxsigdp: VSX Scalar Extract Significand Dual Precision

Signed-off-by: default avatarNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 9eceae32

target/ppc/translate/vsx-impl.inc.c

+29 −0
Original line number Diff line number Diff line
@@ -1239,6 +1239,35 @@ static void gen_xsxexpqp(DisasContext *ctx) 
    tcg_gen_andi_i64(xth, xth, 0x7FFF);

    tcg_gen_movi_i64(xtl, 0);

}



static void gen_xsxsigdp(DisasContext *ctx)

{

    TCGv rt = cpu_gpr[rD(ctx->opcode)];

    TCGv_i64 t0, zr, nan, exp;



    if (unlikely(!ctx->vsx_enabled)) {

        gen_exception(ctx, POWERPC_EXCP_VSXU);

        return;

    }

    exp = tcg_temp_new_i64();

    t0 = tcg_temp_new_i64();

    zr = tcg_const_i64(0);

    nan = tcg_const_i64(2047);



    tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);

    tcg_gen_andi_i64(exp, exp, 0x7FF);

    tcg_gen_movi_i64(t0, 0x0010000000000000);

    tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);

    tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);

    tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF);

    tcg_gen_or_i64(rt, rt, t0);



    tcg_temp_free_i64(t0);

    tcg_temp_free_i64(exp);

    tcg_temp_free_i64(zr);

    tcg_temp_free_i64(nan);

}



#endif



#undef GEN_XX2FORM

target/ppc/translate/vsx-ops.inc.c

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), 
#ifdef TARGET_PPC64

GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),

GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),

GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),

#endif



GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),