Commit 05188cc7 authored by Emilio G. Cota's avatar Emilio G. Cota Committed by Richard Henderson
Browse files

target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} 



The exception is not emitted anymore; remove it and the associated
TCG variables.

Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarEmilio G. Cota <cota@braap.org>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
Message-Id: <1467054136-10430-31-git-send-email-cota@braap.org>
parent f4e6eb7f

target-arm/cpu.h

+0 −5
Original line number Diff line number Diff line
@@ -46,7 +46,6 @@ 
#define EXCP_BKPT            7

#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */

#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */

#define EXCP_STREX          10

#define EXCP_HVC            11   /* HyperVisor Call */

#define EXCP_HYP_TRAP       12

#define EXCP_SMC            13   /* Secure Monitor Call */
@@ -475,10 +474,6 @@ typedef struct CPUARMState { 
    uint64_t exclusive_addr;

    uint64_t exclusive_val;

    uint64_t exclusive_high;

#if defined(CONFIG_USER_ONLY)

    uint64_t exclusive_test;

    uint32_t exclusive_info;

#endif



    /* iwMMXt coprocessor state.  */

    struct {

target-arm/internals.h

+1 −3
Original line number Diff line number Diff line
@@ -46,8 +46,7 @@ static inline bool excp_is_internal(int excp) 
        || excp == EXCP_HALTED

        || excp == EXCP_EXCEPTION_EXIT

        || excp == EXCP_KERNEL_TRAP

        || excp == EXCP_SEMIHOST

        || excp == EXCP_STREX;

        || excp == EXCP_SEMIHOST;

}



/* Exception names for debug logging; note that not all of these
@@ -63,7 +62,6 @@ static const char * const excnames[] = { 
    [EXCP_BKPT] = "Breakpoint",

    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",

    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",

    [EXCP_STREX] = "QEMU intercept of STREX",

    [EXCP_HVC] = "Hypervisor Call",

    [EXCP_HYP_TRAP] = "Hypervisor Trap",

    [EXCP_SMC] = "Secure Monitor Call",

target-arm/translate.c

+0 −10
Original line number Diff line number Diff line
@@ -65,10 +65,6 @@ static TCGv_i32 cpu_R[16]; 
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;

TCGv_i64 cpu_exclusive_addr;

TCGv_i64 cpu_exclusive_val;

#ifdef CONFIG_USER_ONLY

TCGv_i64 cpu_exclusive_test;

TCGv_i32 cpu_exclusive_info;

#endif



/* FIXME:  These should be removed.  */

static TCGv_i32 cpu_F0s, cpu_F1s;
@@ -102,12 +98,6 @@ void arm_translate_init(void) 
        offsetof(CPUARMState, exclusive_addr), "exclusive_addr");

    cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env,

        offsetof(CPUARMState, exclusive_val), "exclusive_val");

#ifdef CONFIG_USER_ONLY

    cpu_exclusive_test = tcg_global_mem_new_i64(cpu_env,

        offsetof(CPUARMState, exclusive_test), "exclusive_test");

    cpu_exclusive_info = tcg_global_mem_new_i32(cpu_env,

        offsetof(CPUARMState, exclusive_info), "exclusive_info");

#endif



    a64_translate_init();

}

target-arm/translate.h

+0 −4
Original line number Diff line number Diff line
@@ -79,10 +79,6 @@ extern TCGv_env cpu_env; 
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;

extern TCGv_i64 cpu_exclusive_addr;

extern TCGv_i64 cpu_exclusive_val;

#ifdef CONFIG_USER_ONLY

extern TCGv_i64 cpu_exclusive_test;

extern TCGv_i32 cpu_exclusive_info;

#endif



static inline int arm_dc_feature(DisasContext *dc, int feature)

{