Merge remote-tracking branch 'remotes/stsquad/tags/pull-demacro-softmmu-100519-1' into staging (04d6556c) · Commits · SUMMER2020 / students / proj-2021291

accel/tcg/cputlb.c

+546 −80

Original line number	Diff line number	Diff line
		@@ -856,9 +856,8 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
		}

		static uint64_t io_readx(CPUArchState env, CPUIOTLBEntry iotlbentry,
		int mmu_idx,
		target_ulong addr, uintptr_t retaddr,
		bool recheck, MMUAccessType access_type, int size)
		int mmu_idx, target_ulong addr, uintptr_t retaddr,
		MMUAccessType access_type, int size)
		{
		CPUState *cpu = ENV_GET_CPU(env);
		hwaddr mr_offset;
		@@ -868,30 +867,6 @@ static uint64_t io_readx(CPUArchState env, CPUIOTLBEntry iotlbentry,
		bool locked = false;
		MemTxResult r;

		if (recheck) {
		/*
		* This is a TLB_RECHECK access, where the MMU protection
		* covers a smaller range than a target page, and we must
		* repeat the MMU check here. This tlb_fill() call might
		* longjump out if this access should cause a guest exception.
		*/
		CPUTLBEntry *entry;
		target_ulong tlb_addr;

		tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr);

		entry = tlb_entry(env, mmu_idx, addr);
		tlb_addr = (access_type == MMU_DATA_LOAD ?
		entry->addr_read : entry->addr_code);
		if (!(tlb_addr & ~(TARGET_PAGE_MASK \| TLB_RECHECK))) {
		/* RAM access */
		uintptr_t haddr = addr + entry->addend;

		return ldn_p((void *)haddr, size);
		}
		/* Fall through for handling IO accesses */
		}

		section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
		mr = section->mr;
		mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
		@@ -925,9 +900,8 @@ static uint64_t io_readx(CPUArchState env, CPUIOTLBEntry iotlbentry,
		}

		static void io_writex(CPUArchState env, CPUIOTLBEntry iotlbentry,
		int mmu_idx,
		uint64_t val, target_ulong addr,
		uintptr_t retaddr, bool recheck, int size)
		int mmu_idx, uint64_t val, target_ulong addr,
		uintptr_t retaddr, int size)
		{
		CPUState *cpu = ENV_GET_CPU(env);
		hwaddr mr_offset;
		@@ -936,30 +910,6 @@ static void io_writex(CPUArchState env, CPUIOTLBEntry iotlbentry,
		bool locked = false;
		MemTxResult r;

		if (recheck) {
		/*
		* This is a TLB_RECHECK access, where the MMU protection
		* covers a smaller range than a target page, and we must
		* repeat the MMU check here. This tlb_fill() call might
		* longjump out if this access should cause a guest exception.
		*/
		CPUTLBEntry *entry;
		target_ulong tlb_addr;

		tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);

		entry = tlb_entry(env, mmu_idx, addr);
		tlb_addr = tlb_addr_write(entry);
		if (!(tlb_addr & ~(TARGET_PAGE_MASK \| TLB_RECHECK))) {
		/* RAM access */
		uintptr_t haddr = addr + entry->addend;

		stn_p((void *)haddr, size, val);
		return;
		}
		/* Fall through for handling IO accesses */
		}

		section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
		mr = section->mr;
		mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
		@@ -1168,26 +1118,481 @@ static void atomic_mmu_lookup(CPUArchState env, target_ulong addr,
		}

		#ifdef TARGET_WORDS_BIGENDIAN
		# define TGT_BE(X) (X)
		# define TGT_LE(X) BSWAP(X)
		#define NEED_BE_BSWAP 0
		#define NEED_LE_BSWAP 1
		#else
		# define TGT_BE(X) BSWAP(X)
		# define TGT_LE(X) (X)
		#define NEED_BE_BSWAP 1
		#define NEED_LE_BSWAP 0
		#endif

		#define MMUSUFFIX _mmu
		/*
		* Byte Swap Helper
		*
		* This should all dead code away depending on the build host and
		* access type.
		*/

		#define DATA_SIZE 1
		#include "softmmu_template.h"
		static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian)
		{
		if ((big_endian && NEED_BE_BSWAP) \|\| (!big_endian && NEED_LE_BSWAP)) {
		switch (size) {
		case 1: return val;
		case 2: return bswap16(val);
		case 4: return bswap32(val);
		case 8: return bswap64(val);
		default:
		g_assert_not_reached();
		}
		} else {
		return val;
		}
		}

		#define DATA_SIZE 2
		#include "softmmu_template.h"
		/*
		* Load Helpers
		*
		* We support two different access types. SOFTMMU_CODE_ACCESS is
		* specifically for reading instructions from system memory. It is
		* called by the translation loop and in some helpers where the code
		* is disassembled. It shouldn't be called directly by guest code.
		*/

		#define DATA_SIZE 4
		#include "softmmu_template.h"
		typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr);

		#define DATA_SIZE 8
		#include "softmmu_template.h"
		static inline uint64_t __attribute__((always_inline))
		load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
		uintptr_t retaddr, size_t size, bool big_endian, bool code_read,
		FullLoadHelper *full_load)
		{
		uintptr_t mmu_idx = get_mmuidx(oi);
		uintptr_t index = tlb_index(env, mmu_idx, addr);
		CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
		target_ulong tlb_addr = code_read ? entry->addr_code : entry->addr_read;
		const size_t tlb_off = code_read ?
		offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read);
		const MMUAccessType access_type =
		code_read ? MMU_INST_FETCH : MMU_DATA_LOAD;
		unsigned a_bits = get_alignment_bits(get_memop(oi));
		void *haddr;
		uint64_t res;

		/* Handle CPU specific unaligned behaviour */
		if (addr & ((1 << a_bits) - 1)) {
		cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type,
		mmu_idx, retaddr);
		}

		/* If the TLB entry is for a different page, reload and try again. */
		if (!tlb_hit(tlb_addr, addr)) {
		if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
		addr & TARGET_PAGE_MASK)) {
		tlb_fill(ENV_GET_CPU(env), addr, size,
		access_type, mmu_idx, retaddr);
		index = tlb_index(env, mmu_idx, addr);
		entry = tlb_entry(env, mmu_idx, addr);
		}
		tlb_addr = code_read ? entry->addr_code : entry->addr_read;
		}

		/* Handle an IO access. */
		if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
		if ((addr & (size - 1)) != 0) {
		goto do_unaligned_access;
		}

		if (tlb_addr & TLB_RECHECK) {
		/*
		* This is a TLB_RECHECK access, where the MMU protection
		* covers a smaller range than a target page, and we must
		* repeat the MMU check here. This tlb_fill() call might
		* longjump out if this access should cause a guest exception.
		*/
		tlb_fill(ENV_GET_CPU(env), addr, size,
		access_type, mmu_idx, retaddr);
		index = tlb_index(env, mmu_idx, addr);
		entry = tlb_entry(env, mmu_idx, addr);

		tlb_addr = code_read ? entry->addr_code : entry->addr_read;
		tlb_addr &= ~TLB_RECHECK;
		if (!(tlb_addr & ~TARGET_PAGE_MASK)) {
		/* RAM access */
		goto do_aligned_access;
		}
		}

		res = io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr,
		retaddr, access_type, size);
		return handle_bswap(res, size, big_endian);
		}

		/* Handle slow unaligned access (it spans two pages or IO). */
		if (size > 1
		&& unlikely((addr & ~TARGET_PAGE_MASK) + size - 1
		>= TARGET_PAGE_SIZE)) {
		target_ulong addr1, addr2;
		tcg_target_ulong r1, r2;
		unsigned shift;
		do_unaligned_access:
		addr1 = addr & ~(size - 1);
		addr2 = addr1 + size;
		r1 = full_load(env, addr1, oi, retaddr);
		r2 = full_load(env, addr2, oi, retaddr);
		shift = (addr & (size - 1)) * 8;

		if (big_endian) {
		/* Big-endian combine. */
		res = (r1 << shift) \| (r2 >> ((size * 8) - shift));
		} else {
		/* Little-endian combine. */
		res = (r1 >> shift) \| (r2 << ((size * 8) - shift));
		}
		return res & MAKE_64BIT_MASK(0, size * 8);
		}

		do_aligned_access:
		haddr = (void *)((uintptr_t)addr + entry->addend);
		switch (size) {
		case 1:
		res = ldub_p(haddr);
		break;
		case 2:
		if (big_endian) {
		res = lduw_be_p(haddr);
		} else {
		res = lduw_le_p(haddr);
		}
		break;
		case 4:
		if (big_endian) {
		res = (uint32_t)ldl_be_p(haddr);
		} else {
		res = (uint32_t)ldl_le_p(haddr);
		}
		break;
		case 8:
		if (big_endian) {
		res = ldq_be_p(haddr);
		} else {
		res = ldq_le_p(haddr);
		}
		break;
		default:
		g_assert_not_reached();
		}

		return res;
		}

		/*
		* For the benefit of TCG generated code, we want to avoid the
		* complication of ABI-specific return type promotion and always
		* return a value extended to the register size of the host. This is
		* tcg_target_long, except in the case of a 32-bit host and 64-bit
		* data, and for that we always have uint64_t.
		*
		* We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
		*/

		static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 1, false, false,
		full_ldub_mmu);
		}

		tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_ldub_mmu(env, addr, oi, retaddr);
		}

		static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 2, false, false,
		full_le_lduw_mmu);
		}

		tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_le_lduw_mmu(env, addr, oi, retaddr);
		}

		static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 2, true, false,
		full_be_lduw_mmu);
		}

		tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_be_lduw_mmu(env, addr, oi, retaddr);
		}

		static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 4, false, false,
		full_le_ldul_mmu);
		}

		tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_le_ldul_mmu(env, addr, oi, retaddr);
		}

		static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 4, true, false,
		full_be_ldul_mmu);
		}

		tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_be_ldul_mmu(env, addr, oi, retaddr);
		}

		uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 8, false, false,
		helper_le_ldq_mmu);
		}

		uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 8, true, false,
		helper_be_ldq_mmu);
		}

		/*
		* Provide signed versions of the load routines as well. We can of course
		* avoid this for 64-bit data, or for 32-bit data on 32-bit host.
		*/


		tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
		}

		tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
		}

		tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
		}

		tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
		}

		tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
		}

		/*
		* Store Helpers
		*/

		static inline void __attribute__((always_inline))
		store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
		TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endian)
		{
		uintptr_t mmu_idx = get_mmuidx(oi);
		uintptr_t index = tlb_index(env, mmu_idx, addr);
		CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
		target_ulong tlb_addr = tlb_addr_write(entry);
		const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
		unsigned a_bits = get_alignment_bits(get_memop(oi));
		void *haddr;

		/* Handle CPU specific unaligned behaviour */
		if (addr & ((1 << a_bits) - 1)) {
		cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
		mmu_idx, retaddr);
		}

		/* If the TLB entry is for a different page, reload and try again. */
		if (!tlb_hit(tlb_addr, addr)) {
		if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
		addr & TARGET_PAGE_MASK)) {
		tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
		mmu_idx, retaddr);
		index = tlb_index(env, mmu_idx, addr);
		entry = tlb_entry(env, mmu_idx, addr);
		}
		tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
		}

		/* Handle an IO access. */
		if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
		if ((addr & (size - 1)) != 0) {
		goto do_unaligned_access;
		}

		if (tlb_addr & TLB_RECHECK) {
		/*
		* This is a TLB_RECHECK access, where the MMU protection
		* covers a smaller range than a target page, and we must
		* repeat the MMU check here. This tlb_fill() call might
		* longjump out if this access should cause a guest exception.
		*/
		tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
		mmu_idx, retaddr);
		index = tlb_index(env, mmu_idx, addr);
		entry = tlb_entry(env, mmu_idx, addr);

		tlb_addr = tlb_addr_write(entry);
		tlb_addr &= ~TLB_RECHECK;
		if (!(tlb_addr & ~TARGET_PAGE_MASK)) {
		/* RAM access */
		goto do_aligned_access;
		}
		}

		io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx,
		handle_bswap(val, size, big_endian),
		addr, retaddr, size);
		return;
		}

		/* Handle slow unaligned access (it spans two pages or IO). */
		if (size > 1
		&& unlikely((addr & ~TARGET_PAGE_MASK) + size - 1
		>= TARGET_PAGE_SIZE)) {
		int i;
		uintptr_t index2;
		CPUTLBEntry *entry2;
		target_ulong page2, tlb_addr2;
		do_unaligned_access:
		/*
		* Ensure the second page is in the TLB. Note that the first page
		* is already guaranteed to be filled, and that the second page
		* cannot evict the first.
		*/
		page2 = (addr + size) & TARGET_PAGE_MASK;
		index2 = tlb_index(env, mmu_idx, page2);
		entry2 = tlb_entry(env, mmu_idx, page2);
		tlb_addr2 = tlb_addr_write(entry2);
		if (!tlb_hit_page(tlb_addr2, page2)
		&& !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
		page2 & TARGET_PAGE_MASK)) {
		tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE,
		mmu_idx, retaddr);
		}

		/*
		* XXX: not efficient, but simple.
		* This loop must go in the forward direction to avoid issues
		* with self-modifying code in Windows 64-bit.
		*/
		for (i = 0; i < size; ++i) {
		uint8_t val8;
		if (big_endian) {
		/* Big-endian extract. */
		val8 = val >> (((size - 1) * 8) - (i * 8));
		} else {
		/* Little-endian extract. */
		val8 = val >> (i * 8);
		}
		helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr);
		}
		return;
		}

		do_aligned_access:
		haddr = (void *)((uintptr_t)addr + entry->addend);
		switch (size) {
		case 1:
		stb_p(haddr, val);
		break;
		case 2:
		if (big_endian) {
		stw_be_p(haddr, val);
		} else {
		stw_le_p(haddr, val);
		}
		break;
		case 4:
		if (big_endian) {
		stl_be_p(haddr, val);
		} else {
		stl_le_p(haddr, val);
		}
		break;
		case 8:
		if (big_endian) {
		stq_be_p(haddr, val);
		} else {
		stq_le_p(haddr, val);
		}
		break;
		default:
		g_assert_not_reached();
		break;
		}
		}

		void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 1, false);
		}

		void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 2, false);
		}

		void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 2, true);
		}

		void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 4, false);
		}

		void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 4, true);
		}

		void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 8, false);
		}

		void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		store_helper(env, addr, val, oi, retaddr, 8, true);
		}

		/* First set of helpers allows passing in of OI and RETADDR. This makes
		them callable from other helpers. */
		@@ -1248,20 +1653,81 @@ static void atomic_mmu_lookup(CPUArchState env, target_ulong addr,

		/* Code access functions. */

		#undef MMUSUFFIX
		#define MMUSUFFIX _cmmu
		#undef GETPC
		#define GETPC() ((uintptr_t)0)
		#define SOFTMMU_CODE_ACCESS
		static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 1, false, true,
		full_ldub_cmmu);
		}

		uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_ldub_cmmu(env, addr, oi, retaddr);
		}

		#define DATA_SIZE 1
		#include "softmmu_template.h"
		static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 2, false, true,
		full_le_lduw_cmmu);
		}

		#define DATA_SIZE 2
		#include "softmmu_template.h"
		uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_le_lduw_cmmu(env, addr, oi, retaddr);
		}

		#define DATA_SIZE 4
		#include "softmmu_template.h"
		static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 2, true, true,
		full_be_lduw_cmmu);
		}

		#define DATA_SIZE 8
		#include "softmmu_template.h"
		uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_be_lduw_cmmu(env, addr, oi, retaddr);
		}

		static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 4, false, true,
		full_le_ldul_cmmu);
		}

		uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_le_ldul_cmmu(env, addr, oi, retaddr);
		}

		static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 4, true, true,
		full_be_ldul_cmmu);
		}

		uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return full_be_ldul_cmmu(env, addr, oi, retaddr);
		}

		uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 8, false, true,
		helper_le_ldq_cmmu);
		}

		uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
		TCGMemOpIdx oi, uintptr_t retaddr)
		{
		return load_helper(env, addr, oi, retaddr, 8, true, true,
		helper_be_ldq_cmmu);
		}

accel/tcg/softmmu_template.h

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