Commit 041d95f4 authored by David Gibson's avatar David Gibson
Browse files

target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one 



ppc_tlb_invalidate_one() has a big switch handling many different MMU
types.  However, most of those branches can never be reached:

It is called from 3 places: from remove_hpte() and h_protect() in
spapr_hcall.c (which always has a 64-bit hash MMU type), and from
helper_tlbie() in mmu_helper.c.

Calls to helper_tlbie() are generated from gen_tlbiel, gen_tlbiel and
gen_tlbiva.  The first two are only used with the PPC_MEM_TLBIE flag,
set only with 32-bit or 64-bit hash MMU models, and gen_tlbiva() is
used only on 440 and 460 models with the BookE mmu model.

These means the exhaustive list of MMU types which may call
ppc_tlb_invalidate_one() is: POWERPC_MMU_SOFT_6xx, POWERPC_MMU_601,
POWERPC_MMU_32B, POWERPC_MMU_SOFT_74xx, POWERPC_MMU_64B, POWERPC_MMU_2_03,
POWERPC_MMU_2_06, POWERPC_MMU_2_07 and POWERPC_MMU_BOOKE.

Clean up by removing logic for all other MMU types from
ppc_tlb_invalidate_one().

This means that ppc4xx_tlb_invalidate_virt() now has no callers, or rather,
makes it obvious that it has no callers.  So, we remove that function as
well.

Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent be18b2b5

target-ppc/mmu_helper.c

+2 −44
Original line number Diff line number Diff line
@@ -658,32 +658,6 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) 
    tlb_flush(CPU(cpu), 1);

}



static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,

                                              target_ulong eaddr, uint32_t pid)

{

#if !defined(FLUSH_ALL_TLBS)

    CPUState *cs = CPU(ppc_env_get_cpu(env));

    ppcemb_tlb_t *tlb;

    hwaddr raddr;

    target_ulong page, end;

    int i;



    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb.tlbe[i];

        if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {

            end = tlb->EPN + tlb->size;

            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {

                tlb_flush_page(cs, page);

            }

            tlb->prot &= ~PAGE_VALID;

            break;

        }

    }

#else

    ppc4xx_tlb_invalidate_all(env);

#endif

}



static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,

                                       target_ulong address, int rw,

                                       int access_type)
@@ -1972,25 +1946,10 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
            ppc6xx_tlb_invalidate_virt(env, addr, 1);

        }

        break;

    case POWERPC_MMU_SOFT_4xx:

    case POWERPC_MMU_SOFT_4xx_Z:

        ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);

        break;

    case POWERPC_MMU_REAL:

        cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");

        break;

    case POWERPC_MMU_MPC8xx:

        /* XXX: TODO */

        cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");

        break;

    case POWERPC_MMU_BOOKE:

        /* XXX: TODO */

        cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");

        break;

    case POWERPC_MMU_BOOKE206:

        /* XXX: TODO */

        cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n");

        break;

    case POWERPC_MMU_32B:

    case POWERPC_MMU_601:

        /* tlbie invalidate TLBs for all segments */
@@ -2032,9 +1991,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
        break;

#endif /* defined(TARGET_PPC64) */

    default:

        /* XXX: TODO */

        cpu_abort(CPU(cpu), "Unknown MMU model\n");

        break;

        /* Should never reach here with other MMU models */

        assert(0);

    }

#else

    ppc_tlb_invalidate_all(env);