Commit 03a98189 authored by David Hildenbrand's avatar David Hildenbrand Committed by Richard Henderson
Browse files

tcg: Check for watchpoints in probe_write() 



Let size > 0 indicate a promise to write to those bytes.
Check for write watchpoints in the probed range.

Suggested-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Message-Id: <20190823100741.9621-10-david@redhat.com>
[rth: Recompute index after tlb_fill; check TLB_WATCHPOINT.]
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 50b107c5

accel/tcg/cputlb.c

+13 −2
Original line number Diff line number Diff line
@@ -1086,13 +1086,24 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, 
{

    uintptr_t index = tlb_index(env, mmu_idx, addr);

    CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);

    target_ulong tlb_addr = tlb_addr_write(entry);



    if (!tlb_hit(tlb_addr_write(entry), addr)) {

        /* TLB entry is for a different page */

    if (unlikely(!tlb_hit(tlb_addr, addr))) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,

                     mmu_idx, retaddr);

            /* TLB resize via tlb_fill may have moved the entry. */

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = tlb_addr_write(entry);

    }



    /* Handle watchpoints.  */

    if ((tlb_addr & TLB_WATCHPOINT) && size > 0) {

        cpu_check_watchpoint(env_cpu(env), addr, size,

                             env_tlb(env)->d[mmu_idx].iotlb[index].attrs,

                             BP_MEM_WRITE, retaddr);

    }

}