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Unverified Commit ba9e25a6 authored by Palmer Dabbelt's avatar Palmer Dabbelt
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Add documentation for __riscv_flush_icache

This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.

2018-01-29  Palmer Dabbelt  <palmer@sifive.com>

        * manual/platform.texi: Add RISC-V documenation for
        __riscv_flush_icache.
parent 4215e276
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