s390: Simplify (dis)assembly of insn operands with const bits

Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.

The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.

This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx

include/
	* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
	S390_OPERAND_OR8): Remove.

opcodes/
	* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
	(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
	as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
	(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
	respective insn fmt mask.
	(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
	Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
	mask.
	* s390-dis.c (s390_print_insn_with_opcode): Mask constant
	operand bits set in insn template of non-length unsigned
	integer operands.

gas/
	* config/tc-s390.c (s390_insert_operand): Do not OR constant
	operand value bits.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>