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Commit 94bf91ba authored by Vlad Zolotarov's avatar Vlad Zolotarov Committed by David S. Miller
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bnx2: Add missing memory barrier in bnx2_start_xmit()



Sync DMA descriptor before hitting the TX mailbox for weak memory model
CPUs.

There has been discussions several years ago about this.  Some believe
that writel() should guarantee ordering.  Others want explicit barriers
if necessary.  Today writel() does not have the ordering guarantee and
many other drivers use explicit barriers.

Signed-off-by: default avatarVlad Zolotarov <vlad@scalemp.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b033281f
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