From d900a1cd310de097fb94796ca575c118b2637b3b Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Sat, 16 Oct 2021 12:20:22 +0200 Subject: [PATCH 001/965] arm64: dts: allwinner: add 'chassis-type' property A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Allwinner ARM64 processors. Signed-off-by: Arnaud Ferraris Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211016102025.23346-2-arnaud.ferraris@collabora.com --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 34e67f5f82979..63571df24da4f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -15,6 +15,7 @@ / { model = "Pinebook"; compatible = "pine64,pinebook", "allwinner,sun50i-a64"; + chassis-type = "laptop"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 5b44a979f2503..87847116ab6d9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -12,6 +12,8 @@ #include / { + chassis-type = "handset"; + aliases { ethernet0 = &rtl8723cs; serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index adb0b28b06d83..0a5607f73049e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -16,6 +16,7 @@ / { model = "PineTab, Development Sample"; compatible = "pine64,pinetab", "allwinner,sun50i-a64"; + chassis-type = "tablet"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index aef571acd67fb..aff0660b899ce 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -14,6 +14,7 @@ / { model = "Olimex A64 Teres-I"; compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; + chassis-type = "laptop"; aliases { serial0 = &uart0; -- GitLab From 85744f2d938c5f3cfc44cb6533c157469634da93 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Sun, 17 Oct 2021 21:45:03 -0400 Subject: [PATCH 002/965] ARM: shmobile: rcar-gen2: Add missing of_node_put() Fix following coccicheck warning: ./arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c:156:1-33: Function for_each_matching_node_and_match should have of_node_put() before break and goto. Early exits from for_each_matching_node_and_match() should decrement the node reference counter. Signed-off-by: Wan Jiabing Link: https://lore.kernel.org/r/20211018014503.7598-1-wanjiabing@vivo.com Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c index ee949255ced3f..09ef73b99dd86 100644 --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c @@ -154,8 +154,10 @@ static int __init rcar_gen2_regulator_quirk(void) return -ENODEV; for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) { - if (!of_device_is_available(np)) + if (!of_device_is_available(np)) { + of_node_put(np); break; + } ret = of_property_read_u32(np, "reg", &addr); if (ret) /* Skip invalid entry and continue */ @@ -164,6 +166,7 @@ static int __init rcar_gen2_regulator_quirk(void) quirk = kzalloc(sizeof(*quirk), GFP_KERNEL); if (!quirk) { ret = -ENOMEM; + of_node_put(np); goto err_mem; } -- GitLab From 1ab0a62f28c9347a5abb9ff9ba544271deb45f87 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Oct 2021 16:44:12 +0200 Subject: [PATCH 003/965] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add missing camera regulators make dtbs_check: arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'AVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DOVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml Fix this by describing the missing regulators. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/300149c730931914b77e17df6bcce89b67c3005f.1634222546.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 16 ++++++++++++++++ .../r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 3 +++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 33db5938f2d45..3c8a7c8b1fdd5 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -44,6 +44,22 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; }; &avb { diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi index 70c72ba4fe724..40cef0b1d1e62 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -17,6 +17,9 @@ reg = <0x3c>; clocks = <&MCLK_CAM>; clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p8v>; status = "okay"; port { -- GitLab From 4c7924fb905b02323ff6d9d20f370892615dccfa Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 22 Oct 2021 14:21:01 +0200 Subject: [PATCH 004/965] soc: renesas: rcar-rst: Add support to set rproc boot address R-Car Gen3 SoC series has a realtime processor, the boot address of this processor can be set thanks to CR7BAR register of the reset module. Export this function so that it's possible to set the boot address from a remoteproc driver. Also drop the __initdata qualifier on rcar_rst_base, since we will use this address later than init time. Signed-off-by: Julien Massot Link: https://lore.kernel.org/r/20211022122101.66998-1-julien.massot@iot.bzh Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/rcar-rst.c | 43 ++++++++++++++++++++++++++-- include/linux/soc/renesas/rcar-rst.h | 2 ++ 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 8a1e402ea7996..1ad54e0c32e1c 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -13,15 +13,43 @@ #define WDTRSTCR_RESET 0xA55A0002 #define WDTRSTCR 0x0054 +#define CR7BAR 0x0070 +#define CR7BAREN BIT(4) +#define CR7BAR_MASK 0xFFFC0000 + +static void __iomem *rcar_rst_base; +static u32 saved_mode __initdata; +static int (*rcar_rst_set_rproc_boot_addr_func)(u64 boot_addr); + static int rcar_rst_enable_wdt_reset(void __iomem *base) { iowrite32(WDTRSTCR_RESET, base + WDTRSTCR); return 0; } +/* + * Most of the R-Car Gen3 SoCs have an ARM Realtime Core. + * Firmware boot address has to be set in CR7BAR before + * starting the realtime core. + * Boot address must be aligned on a 256k boundary. + */ +static int rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr) +{ + if (boot_addr & ~(u64)CR7BAR_MASK) { + pr_err("Invalid boot address got %llx\n", boot_addr); + return -EINVAL; + } + + iowrite32(boot_addr, rcar_rst_base + CR7BAR); + iowrite32(boot_addr | CR7BAREN, rcar_rst_base + CR7BAR); + + return 0; +} + struct rst_config { unsigned int modemr; /* Mode Monitoring Register Offset */ int (*configure)(void __iomem *base); /* Platform specific config */ + int (*set_rproc_boot_addr)(u64 boot_addr); }; static const struct rst_config rcar_rst_gen1 __initconst = { @@ -35,6 +63,7 @@ static const struct rst_config rcar_rst_gen2 __initconst = { static const struct rst_config rcar_rst_gen3 __initconst = { .modemr = 0x60, + .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; static const struct rst_config rcar_rst_r8a779a0 __initconst = { @@ -76,9 +105,6 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { /* sentinel */ } }; -static void __iomem *rcar_rst_base __initdata; -static u32 saved_mode __initdata; - static int __init rcar_rst_init(void) { const struct of_device_id *match; @@ -100,6 +126,8 @@ static int __init rcar_rst_init(void) rcar_rst_base = base; cfg = match->data; + rcar_rst_set_rproc_boot_addr_func = cfg->set_rproc_boot_addr; + saved_mode = ioread32(base + cfg->modemr); if (cfg->configure) { error = cfg->configure(base); @@ -130,3 +158,12 @@ int __init rcar_rst_read_mode_pins(u32 *mode) *mode = saved_mode; return 0; } + +int rcar_rst_set_rproc_boot_addr(u64 boot_addr) +{ + if (!rcar_rst_set_rproc_boot_addr_func) + return -EIO; + + return rcar_rst_set_rproc_boot_addr_func(boot_addr); +} +EXPORT_SYMBOL_GPL(rcar_rst_set_rproc_boot_addr); diff --git a/include/linux/soc/renesas/rcar-rst.h b/include/linux/soc/renesas/rcar-rst.h index 7899a5b8c2478..1f1fe8bfaa768 100644 --- a/include/linux/soc/renesas/rcar-rst.h +++ b/include/linux/soc/renesas/rcar-rst.h @@ -4,8 +4,10 @@ #ifdef CONFIG_RST_RCAR int rcar_rst_read_mode_pins(u32 *mode); +int rcar_rst_set_rproc_boot_addr(u64 boot_addr); #else static inline int rcar_rst_read_mode_pins(u32 *mode) { return -ENODEV; } +static inline int rcar_rst_set_rproc_boot_addr(u64 boot_addr) { return -ENODEV; } #endif #endif /* __LINUX_SOC_RENESAS_RCAR_RST_H__ */ -- GitLab From 68f8eb19c18a377181622e58c1fd2ca0f5c0d15d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Nov 2021 19:55:58 +0000 Subject: [PATCH 005/965] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 485ef5f0fea14..09bfdedfac2a0 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -194,6 +194,78 @@ status = "disabled"; }; + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + canfd: can@10050000 { compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; -- GitLab From 5a8aa63c9bca800e6049d90422abe5404227a703 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Nov 2021 19:56:00 +0000 Subject: [PATCH 006/965] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board SCIF2 interface is available on PMOD1 connector (CN7) on carrier board, This patch adds pinmux and scif2 node to carrier board dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211103195600.23964-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 2863e487a6402..4c32f068a1f03 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -21,9 +21,13 @@ * */ +/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + / { aliases { serial0 = &scif0; + serial1 = &scif2; i2c0 = &i2c0; i2c1 = &i2c1; i2c3 = &i2c3; @@ -208,6 +212,13 @@ ; /* RxD */ }; + scif2_pins: scif2 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; @@ -277,6 +288,23 @@ status = "okay"; }; +/* + * To enable SCIF2 (SER0) on PMOD1 (CN7) + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if PMOD1_SER0 +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; -- GitLab From f9a2adcc9e908907129c18518d4ea6195c44bf00 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 9 Nov 2021 12:31:10 +0000 Subject: [PATCH 007/965] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 09bfdedfac2a0..358db254c4eaa 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -266,6 +266,36 @@ status = "disabled"; }; + sci0: serial@1004d000 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI1_RST>; + status = "disabled"; + }; + canfd: can@10050000 { compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; -- GitLab From 83c9eee72603adbaaf0420eb2c4d537a9d65d5fe Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Thu, 7 Oct 2021 11:01:30 -0700 Subject: [PATCH 008/965] arm64: dts: meson-sm1-odroid: add cec nodes Enable CEC in same way it is done for other meson odroid devices Signed-off-by: Dmitry Shmidt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211007180130.805401-1-dimitrysh@google.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index 5779e70caccd3..0bd1e98a0eef6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -225,6 +225,20 @@ status = "okay"; }; +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + &clkc_audio { status = "okay"; }; -- GitLab From cdc5091694595606f0e38d651135d5d67fd397d0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 26 Oct 2021 20:28:11 +0200 Subject: [PATCH 009/965] arm64: dts: amlogic: meson-g12: Fix thermal-zones indent This node is currently at /soc/thermal-zones, but the later introduced bindings in commit 1202a442a31f ("dt-bindings: thermal: Add yaml bindings for thermal zones") put this at /thermal-zones. Fix dtb_check warning by moving the thermal-zones node to / Signed-off-by: Alexander Stein Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-1-alexander.stein@mailbox.org --- .../boot/dts/amlogic/meson-g12-common.dtsi | 110 +++++++++--------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 00c6f53290d43..ff987e7ccff22 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -159,61 +159,6 @@ status = "disabled"; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - ethmac: ethernet@ff3f0000 { compatible = "amlogic,meson-g12a-dwmac", "snps,dwmac-3.70a", @@ -2415,6 +2360,61 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&cpu_temp>; + + trips { + cpu_passive: cpu-passive { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cpu_hot: cpu-hot { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&ddr_temp>; + + trips { + ddr_passive: ddr-passive { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ddr_critical: ddr-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_passive>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Tue, 26 Oct 2021 20:28:12 +0200 Subject: [PATCH 010/965] arm64: dts: amlogic: meson-g12: Fix GPU operating point table node name Starting with commit 94274f20f6bf ("dt-bindings: opp: Convert to DT schema") the opp node name has a mandatory pattern. This change fixes the dtbs_check warning: gpu-opp-table: $nodename:0: 'gpu-opp-table' does not match '^opp-table(-[a-z0-9]+)?$' Put the 'gpu' part at the end to match the pattern. Fixes: 916a0edc43f0 ("arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS") Reviewed-by: Neil Armstrong Signed-off-by: Alexander Stein Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-2-alexander.stein@mailbox.org --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index ff987e7ccff22..517519e6e87f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -58,7 +58,7 @@ secure-monitor = <&sm>; }; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-124999998 { -- GitLab From 95d35256b564aca33fb661eac77dc94bfcffc8df Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 26 Oct 2021 20:28:13 +0200 Subject: [PATCH 011/965] arm64: dts: amlogic: Fix SPI NOR flash node name for ODROID N2/N2+ Fix the schema warning: "spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'" from jedec,spi-nor.yaml Fixes: a084eaf3096c ("arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node") Reviewed-by: Neil Armstrong Signed-off-by: Alexander Stein Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-3-alexander.stein@mailbox.org --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index e8a00a2f88128..3e968b2441918 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -609,7 +609,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - mx25u64: spi-flash@0 { + mx25u64: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; -- GitLab From 8182a35868db5f053111d5d9d4da8fcb3f99259d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:20 +0000 Subject: [PATCH 012/965] arm64: dts: meson-gxbb-wetek: fix HDMI in early boot Mark the VDDIO_AO18 regulator always-on and set hdmi-supply for the hdmi_tx node to ensure HDMI is powered in the early stages of boot. Fixes: fb72c03e0e32 ("ARM64: dts: meson-gxbb-wetek: add a wetek specific dtsi to cleanup hub and play2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-2-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index a350fee1264d7..8e2af986cebaf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -64,6 +64,7 @@ regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcc_3v3: regulator-vcc_3v3 { @@ -161,6 +162,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&vddio_ao18>; }; &hdmi_tx_tmds_port { -- GitLab From c019abb2feba3cbbd7cf7178f8e6499c4fa6fced Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:21 +0000 Subject: [PATCH 013/965] arm64: dts: meson-gxbb-wetek: fix missing GPIO binding The absence of this binding appears to be harmless in Linux but it breaks Ethernet support in mainline u-boot. So add the binding (which is present in all other u-boot supported GXBB device-trees). Fixes: fb72c03e0e32 ("ARM64: dts: meson-gxbb-wetek: add a wetek specific dtsi to cleanup hub and play2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-3-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index 8e2af986cebaf..a4d34398da358 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -6,6 +6,7 @@ */ #include "meson-gxbb.dtsi" +#include / { aliases { -- GitLab From 1e9fc71213d784dfbd153289daf08fdfc87f32ba Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:22 +0000 Subject: [PATCH 014/965] arm64: dts: meson-gxbb-wetek: use updated LED bindings Update the dts to use the newer style of LED bindings. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-4-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index a4d34398da358..94dafb955301b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -7,6 +7,7 @@ #include "meson-gxbb.dtsi" #include +#include / { aliases { @@ -26,8 +27,10 @@ leds { compatible = "gpio-leds"; - led-system { - label = "wetek-play:system-status"; + led-power { + /* red in suspend or power-off */ + color = ; + function = LED_FUNCTION_POWER; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; default-state = "on"; panic-indicator; -- GitLab From 5d978f8ad2ae14b6aaae00dc5520b9657675aeef Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Fri, 24 Sep 2021 11:39:35 +0800 Subject: [PATCH 015/965] arm64: dts: mt8183: change rpmsg property name The the rpmsg property name is changed to "mediatek," to sync with the vendor name defined in vendor-prefixes.yaml. Signed-off-by: Tinghan Shen Reviewed-By: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210924033935.2127-7-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index b42d81d26d721..a1a8fc7ba0072 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -813,7 +813,7 @@ cros_ec { compatible = "google,cros-ec-rpmsg"; - mtk,rpmsg-name = "cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; }; }; -- GitLab From 90dc0df9168b6c1ddb339481b440d7c13cc4417c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 11 Nov 2021 10:11:23 +0100 Subject: [PATCH 016/965] ARM: s3c: include header for prototype of s3c2410_modify_misccr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include the header with prototype of s3c2410_modify_misccr to fix W=1 warning: arch/arm/mach-s3c/gpio-samsung.c:1309:14: warning: no previous prototype for ‘s3c2410_modify_misccr’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Acked-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211111091123.50853-1-krzysztof.kozlowski@canonical.com --- arch/arm/mach-s3c/gpio-samsung.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index 76ef415789f25..fda2c01f5a08b 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -35,6 +35,7 @@ #include "gpio-core.h" #include "gpio-cfg.h" #include "gpio-cfg-helpers.h" +#include "hardware-s3c24xx.h" #include "pm.h" int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, -- GitLab From 9cb6de45a006a9799ec399bce60d64b6d4fcc4af Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:36 +0000 Subject: [PATCH 017/965] ARM: dts: exynos: Fix BCM4330 Bluetooth reset polarity in I9100 The reset GPIO was marked active-high, which is against what's specified in the documentation. Mark the reset GPIO as active-low. With this change, Bluetooth can now be used on the i9100. Fixes: 8620cc2f99b7 ("ARM: dts: exynos: Add devicetree file for the Galaxy S2") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-1-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 19bb7dc98b339..21b791150697d 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -828,7 +828,7 @@ compatible = "brcm,bcm4330-bt"; shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; }; -- GitLab From 8e14b530f8c90346eab43c7b59b03ff9fec7d171 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:37 +0000 Subject: [PATCH 018/965] ARM: dts: exynos: Use interrupt for BCM4330 host wakeup in I9100 Switch away from using the deprecated 'host-wakeup-gpios' property, and use a 'host-wakeup' interrupt instead, as suggested by the binding documentation. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-2-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 21b791150697d..33894054b8b0d 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -830,7 +830,10 @@ shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + interrupt-parent = <&gpx2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; }; }; -- GitLab From 51c7b6a0398f54b9120795796a4cff4fc9634f7d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 15 Nov 2021 00:12:07 +0100 Subject: [PATCH 019/965] power: supply: core: Break capacity loop We should not go on looking for more capacity tables after we realize we have looked at the last one in power_supply_find_ocv2cap_table(). Fixes: 3afb50d7125b ("power: supply: core: Add some helpers to use the battery OCV capacity table") Cc: Chunyan Zhang Cc: Baolin Wang Signed-off-by: Linus Walleij Reviewed-by: Baolin Wang Signed-off-by: Sebastian Reichel --- drivers/power/supply/power_supply_core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index fc12a4f407f43..6093754cebd56 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -853,6 +853,10 @@ power_supply_find_ocv2cap_table(struct power_supply_battery_info *info, return NULL; for (i = 0; i < POWER_SUPPLY_OCV_TEMP_MAX; i++) { + /* Out of capacity tables */ + if (!info->ocv_table[i]) + break; + temp_diff = abs(info->ocv_temp[i] - temp); if (temp_diff < best_temp_diff) { -- GitLab From 569e45a1135497d8dddc647bc615e26c49b070a8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 31 Oct 2021 21:52:12 +0100 Subject: [PATCH 020/965] soc: samsung: exynos-chipid: describe which SoCs go with compatibles The Exynos ChipID driver, like most of the Exynos drivers, uses one compatible for entire family of compatible devices using one devicetree "compatible". The compatibility is here described by programming interface (register layout), not by actual values, so the product ID register on one family of devices has different values for different SoCs. Describe which SoC goes with which compatible for documentation purposes, if the DTS is not available in mainline. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20211031205212.59505-1-krzysztof.kozlowski@canonical.com --- drivers/soc/samsung/exynos-chipid.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index a28053ec7e6a3..baf3afc69d79d 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -42,6 +42,7 @@ static const struct exynos_soc_id { unsigned int id; } soc_ids[] = { /* List ordered by SoC name */ + /* Compatible with: samsung,exynos4210-chipid */ { "EXYNOS3250", 0xE3472000 }, { "EXYNOS4210", 0x43200000 }, /* EVT0 revision */ { "EXYNOS4210", 0x43210000 }, @@ -55,6 +56,7 @@ static const struct exynos_soc_id { { "EXYNOS5440", 0xE5440000 }, { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, + /* Compatible with: samsung,exynos850-chipid */ { "EXYNOS850", 0xE3830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, }; -- GitLab From 214f78060713fe13e3ba3701dff51e46d9576a9c Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 1 Nov 2021 01:48:53 +0100 Subject: [PATCH 021/965] soc: samsung: exynos-chipid: add Exynos7885 SoC support Exynos 7885 has product ID "0xE7885000". Add this ID to the IDs with the name. Signed-off-by: David Virag Link: https://lore.kernel.org/r/20211101004853.55810-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index baf3afc69d79d..2746d05936d37 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -57,6 +57,7 @@ static const struct exynos_soc_id { { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, /* Compatible with: samsung,exynos850-chipid */ + { "EXYNOS7885", 0xE7885000 }, { "EXYNOS850", 0xE3830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, }; -- GitLab From a67cce83945170994fcef241b934699b6018b707 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 28 Oct 2021 17:43:12 +0300 Subject: [PATCH 022/965] dt-bindings: samsung: pmu: Document Exynos850 Exynos850 SoC can reuse PMU driver functionality. Add corresponding compatible string to PMU bindings documentation. Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211028144313.9444-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml index 17678d9686c17..0bbd89265b28c 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -24,6 +24,7 @@ select: - samsung,exynos5420-pmu - samsung,exynos5433-pmu - samsung,exynos7-pmu + - samsung,exynos850-pmu - samsung-s5pv210-pmu required: - compatible @@ -41,6 +42,7 @@ properties: - samsung,exynos5420-pmu - samsung,exynos5433-pmu - samsung,exynos7-pmu + - samsung,exynos850-pmu - samsung-s5pv210-pmu - const: syscon -- GitLab From f5dc0140d483fcc6417d1d655481f0ff1de390b0 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 28 Oct 2021 17:43:13 +0300 Subject: [PATCH 023/965] soc: samsung: exynos-pmu: Add Exynos850 support Exynos850 SoC can reuse PMU driver functionality. Add corresponding compatible string. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211028144313.9444-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-pmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index a18c93a4646c8..732c86ce2be8a 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -94,6 +94,8 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { .compatible = "samsung,exynos5433-pmu", }, { .compatible = "samsung,exynos7-pmu", + }, { + .compatible = "samsung,exynos850-pmu", }, { /*sentinel*/ }, }; -- GitLab From 80211be1b9dec04cc2805d3d81e2091ecac289a1 Mon Sep 17 00:00:00 2001 From: Yauhen Kharuzhy Date: Sun, 7 Nov 2021 23:20:01 +0300 Subject: [PATCH 024/965] power: bq25890: Enable continuous conversion for ADC at charging Instead of one shot run of ADC at beginning of charging, run continuous conversion to ensure that all charging-related values are monitored properly (input voltage, input current, themperature etc.). Signed-off-by: Yauhen Kharuzhy Reviewed-by: Hans de Goede Signed-off-by: Sebastian Reichel --- drivers/power/supply/bq25890_charger.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/bq25890_charger.c b/drivers/power/supply/bq25890_charger.c index 34ec186a2e9ab..b7eac54280838 100644 --- a/drivers/power/supply/bq25890_charger.c +++ b/drivers/power/supply/bq25890_charger.c @@ -581,12 +581,12 @@ static irqreturn_t __bq25890_handle_irq(struct bq25890_device *bq) if (!new_state.online && bq->state.online) { /* power removed */ /* disable ADC */ - ret = bq25890_field_write(bq, F_CONV_START, 0); + ret = bq25890_field_write(bq, F_CONV_RATE, 0); if (ret < 0) goto error; } else if (new_state.online && !bq->state.online) { /* power inserted */ /* enable ADC, to have control of charge current/voltage */ - ret = bq25890_field_write(bq, F_CONV_START, 1); + ret = bq25890_field_write(bq, F_CONV_RATE, 1); if (ret < 0) goto error; } -- GitLab From aa67bacb482ae66bdb18b78ddccf7b9180441588 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 24 Oct 2021 10:45:35 +0200 Subject: [PATCH 025/965] arm: dts: mt6589: Add device tree for Fairphone 1 Add rudimentary support for the Fairphone 1, based on MT6589 to boot to UART console. The recently added SMP support needs to be disabled for this board as the kernel panics executing /init with it, even though the CPUs seem to start up fine - maybe a stability issue. [ 0.072010] smp: Bringing up secondary CPUs ... [ 0.131888] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.191889] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.251890] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.251982] smp: Brought up 1 node, 4 CPUs [ 0.254745] SMP: Total of 4 processors activated (7982.28 BogoMIPS). [ 0.255582] CPU: All CPU(s) started in SVC mode. [ 0.472039] Run /init as init process [ 0.473317] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20211024084535.30959-1-luca@z3ntu.xyz Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/mt6589-fairphone-fp1.dts | 30 ++++++++++++++++++++++ arch/arm/boot/dts/mt6589.dtsi | 2 +- 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mt6589-fairphone-fp1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..8a2dfdf01ce3e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1457,6 +1457,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt2701-evb.dtb \ mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ mt6592-evb.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts new file mode 100644 index 0000000000000..c952347981de7 --- /dev/null +++ b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Luca Weiss + */ + +/dts-v1/; +#include "mt6589.dtsi" + +/ { + model = "Fairphone 1"; + compatible = "fairphone,fp1", "mediatek,mt6589"; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&cpus { + /* SMP is not stable on this board, makes the kernel panic */ + /delete-property/ enable-method; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 70df00a7bb267..c6babc8ad2ba6 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -14,7 +14,7 @@ compatible = "mediatek,mt6589"; interrupt-parent = <&sysirq>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "mediatek,mt6589-smp"; -- GitLab From 5f9cfe9e94a6eef576f89bbf5a946f8ae63c0f71 Mon Sep 17 00:00:00 2001 From: Matthew Hagan Date: Fri, 15 Oct 2021 23:50:22 +0100 Subject: [PATCH 026/965] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties This patch enables two properties for the QCA8337 switches on the MX65. Set the SGMII transmit clock to falling edge "qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1]. The new explicit PLL enable option "qca,sgmii-enable-pll" is required [2]. [1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be [2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6 Signed-off-by: Matthew Hagan Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index 102acd85fab28..ba01054a76cfe 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -118,6 +118,8 @@ reg = <0>; ethernet = <&sgmii1>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; @@ -194,6 +196,8 @@ reg = <0>; ethernet = <&sgmii0>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; -- GitLab From 8c9f00d4b05134164e462f27b21c8295255ffa64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Wed, 27 Oct 2021 00:57:03 +0800 Subject: [PATCH 027/965] ARM: dts: BCM5301X: remove unnecessary address & size cells from Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells & #size-cells in the gpio-keys node from the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 448060561cd0d..b0cee1d87600e 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -68,8 +68,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; -- GitLab From 3d2d52a0d1835b56f6bd67d268f6c39df0e41692 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Wed, 27 Oct 2021 00:57:06 +0800 Subject: [PATCH 028/965] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the Realtek RTL8365MB switch without interrupt support on the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Acked-by: Alvin Šipraga Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index b0cee1d87600e..16dea851719f2 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,6 +93,83 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { -- GitLab From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 28 Oct 2021 09:03:44 +0200 Subject: [PATCH 029/965] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit replaces the bit-banged i2c-gpio provided i2c functionality with the hardware in the SoC. During review of the MR32, Florian Fainelli pointed out that the SoC has a real I2C-controller. Furthermore, the connected pins (SDA and SCL) would line up perfectly for use. Back then I couldn't get it working though and I left it with i2c-gpio (which worked). Now we know the reason: the interrupt was incorrectly specified. (Hence, this patch depends on Florian Fainelli's "ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). Cc: Florian Fainelli Cc: Rafał Miłecki Cc: Matthew Hagan Signed-off-by: Christian Lamparter Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------ 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 64f973e1ef129..66c64a6ec4142 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -84,40 +84,6 @@ max-brightness = <255>; }; }; - - i2c { - /* - * The platform provided I2C does not budge. - * This is a replacement until I can figure - * out what are the missing bits... - */ - - compatible = "i2c-gpio"; - sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <10>; /* close to 100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - current_sense: ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; - }; }; &uart0 { @@ -228,3 +194,31 @@ }; }; }; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; -- GitLab From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 29 Oct 2021 18:05:23 +0200 Subject: [PATCH 030/965] ARM: dts: BCM5301X: update CRU block description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This describes CRU in a way matching documentation and fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d4f355015e3ca..e1cffef4935a0 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -421,14 +421,14 @@ #address-cells = <1>; #size-cells = <1>; - cru@100 { - compatible = "simple-bus"; + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x100 0x1a4>; ranges; #address-cells = <1>; #size-cells = <1>; - lcpll0: lcpll0@100 { + lcpll0: clock-controller@100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; reg = <0x100 0x14>; @@ -437,7 +437,7 @@ "sdio", "ddr_phy"; }; - genpll: genpll@140 { + genpll: clock-controller@140 { #clock-cells = <1>; compatible = "brcm,nsp-genpll"; reg = <0x140 0x24>; @@ -448,6 +448,11 @@ "sata1", "sata2"; }; + syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; -- GitLab From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 5 Nov 2021 11:14:12 +0100 Subject: [PATCH 031/965] dt-bindings: arm: bcm: document Netgear RAXE500 binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One more BCM4908 based device. Signed-off-by: Rafał Miłecki Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml index 2cd4e4a32278b..9b745531ff049 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - asus,gt-ac5300 + - netgear,raxe500 - const: brcm,bcm4908 - description: BCM49408 based boards -- GitLab From d0e68d354f345873e15876a7b35be1baaf5e3ec9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 5 Nov 2021 11:14:13 +0100 Subject: [PATCH 032/965] arm64: dts: broadcom: bcm4908: add DT for Netgear RAXE500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a home router based on BCM4908 SoC. It has: 1 GiB of RAM, 512 MiB NAND flash, 6 Ethernet ports and 3 x BCM43684 (WiFi). One of Ethernet ports is "2.5 G Multi-Gig port" that isn't described yet (it isn't known how it's wired up). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 + .../bcm4908/bcm4908-netgear-raxe500.dts | 50 +++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile index cc75854519ac3..6e364e304d4fd 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile +++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile @@ -2,3 +2,4 @@ dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb +dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts new file mode 100644 index 0000000000000..3c2cf2d238b6f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "bcm4908.dtsi" + +/ { + compatible = "netgear,raxe500", "brcm,bcm4908"; + model = "Netgear RAXE500"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@7 { + reg = <7>; + phy-mode = "internal"; + phy-handle = <&phy12>; + label = "wan"; + }; +}; -- GitLab From f5029f62d9ba9b99fd712514784f91f920a63d21 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Fri, 15 Oct 2021 02:49:23 -0400 Subject: [PATCH 033/965] soc: bcm: brcmstb: Add of_node_put() in pm-mips Fix following coccicheck warning: ./drivers/soc/bcm/brcmstb/pm/pm-mips.c:404:1-23: WARNING: Function for_each_matching_node should have of_node_put() before goto or break Early exits from for_each_matching_node should decrement the node reference counter. Signed-off-by: Wan Jiabing Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/pm/pm-mips.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/bcm/brcmstb/pm/pm-mips.c b/drivers/soc/bcm/brcmstb/pm/pm-mips.c index cdc3e387f049e..4dfb5a85032b7 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-mips.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-mips.c @@ -405,11 +405,14 @@ static int brcmstb_pm_init(void) i = ctrl.num_memc; if (i >= MAX_NUM_MEMC) { pr_warn("Too many MEMCs (max %d)\n", MAX_NUM_MEMC); + of_node_put(dn); break; } base = brcmstb_ioremap_node(dn, 0); - if (IS_ERR(base)) + if (IS_ERR(base)) { + of_node_put(dn); goto ddr_err; + } ctrl.memcs[i].ddr_phy_base = base; ctrl.num_memc++; -- GitLab From d6d261bded8a57aed4faa12d08a5b193418d3aa4 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:44 -0700 Subject: [PATCH 034/965] x86/sgx: Add new sgx_epc_page flag bit to mark free pages SGX EPC pages go through the following life cycle: DIRTY ---> FREE ---> IN-USE --\ ^ | \-----------------/ Recovery action for poison for a DIRTY or FREE page is simple. Just make sure never to allocate the page. IN-USE pages need some extra handling. Add a new flag bit SGX_EPC_PAGE_IS_FREE that is set when a page is added to a free list and cleared when the page is allocated. Notes: 1) These transitions are made while holding the node->lock so that future code that checks the flags while holding the node->lock can be sure that if the SGX_EPC_PAGE_IS_FREE bit is set, then the page is on the free list. 2) Initially while the pages are on the dirty list the SGX_EPC_PAGE_IS_FREE bit is cleared. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-2-tony.luck@intel.com --- arch/x86/kernel/cpu/sgx/main.c | 2 ++ arch/x86/kernel/cpu/sgx/sgx.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 63d3de02bbccb..825aa91516c8d 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -472,6 +472,7 @@ static struct sgx_epc_page *__sgx_alloc_epc_page_from_node(int nid) page = list_first_entry(&node->free_page_list, struct sgx_epc_page, list); list_del_init(&page->list); sgx_nr_free_pages--; + page->flags = 0; spin_unlock(&node->lock); @@ -626,6 +627,7 @@ void sgx_free_epc_page(struct sgx_epc_page *page) list_add_tail(&page->list, &node->free_page_list); sgx_nr_free_pages++; + page->flags = SGX_EPC_PAGE_IS_FREE; spin_unlock(&node->lock); } diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index 4628acec00091..5906471156c5c 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -26,6 +26,9 @@ /* Pages, which are being tracked by the page reclaimer. */ #define SGX_EPC_PAGE_RECLAIMER_TRACKED BIT(0) +/* Pages on free list */ +#define SGX_EPC_PAGE_IS_FREE BIT(1) + struct sgx_epc_page { unsigned int section; unsigned int flags; -- GitLab From 40e0e7843e23d164625b9031514f5672f8758bf4 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:45 -0700 Subject: [PATCH 035/965] x86/sgx: Add infrastructure to identify SGX EPC pages X86 machine check architecture reports a physical address when there is a memory error. Handling that error requires a method to determine whether the physical address reported is in any of the areas reserved for EPC pages by BIOS. SGX EPC pages do not have Linux "struct page" associated with them. Keep track of the mapping from ranges of EPC pages to the sections that contain them using an xarray. N.B. adds CONFIG_XARRAY_MULTI to the SGX dependecies. So "select" that in arch/x86/Kconfig for X86/SGX. Create a function arch_is_platform_page() that simply reports whether an address is an EPC page for use elsewhere in the kernel. The ACPI error injection code needs this function and is typically built as a module, so export it. Note that arch_is_platform_page() will be slower than other similar "what type is this page" functions that can simply check bits in the "struct page". If there is some future performance critical user of this function it may need to be implemented in a more efficient way. Note also that the current implementation of xarray allocates a few hundred kilobytes for this usage on a system with 4GB of SGX EPC memory configured. This isn't ideal, but worth it for the code simplicity. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-3-tony.luck@intel.com --- arch/x86/Kconfig | 1 + arch/x86/kernel/cpu/sgx/main.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 95dd1ee01546a..b9281fab4e3e4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1917,6 +1917,7 @@ config X86_SGX select SRCU select MMU_NOTIFIER select NUMA_KEEP_MEMINFO if NUMA + select XARRAY_MULTI help Intel(R) Software Guard eXtensions (SGX) is a set of CPU instructions that can be used by applications to set aside private regions of code diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 825aa91516c8d..5c02cffdabc86 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -20,6 +20,7 @@ struct sgx_epc_section sgx_epc_sections[SGX_MAX_EPC_SECTIONS]; static int sgx_nr_epc_sections; static struct task_struct *ksgxd_tsk; static DECLARE_WAIT_QUEUE_HEAD(ksgxd_waitq); +static DEFINE_XARRAY(sgx_epc_address_space); /* * These variables are part of the state of the reclaimer, and must be accessed @@ -650,6 +651,8 @@ static bool __init sgx_setup_epc_section(u64 phys_addr, u64 size, } section->phys_addr = phys_addr; + xa_store_range(&sgx_epc_address_space, section->phys_addr, + phys_addr + size - 1, section, GFP_KERNEL); for (i = 0; i < nr_pages; i++) { section->pages[i].section = index; @@ -661,6 +664,12 @@ static bool __init sgx_setup_epc_section(u64 phys_addr, u64 size, return true; } +bool arch_is_platform_page(u64 paddr) +{ + return !!xa_load(&sgx_epc_address_space, paddr); +} +EXPORT_SYMBOL_GPL(arch_is_platform_page); + /** * A section metric is concatenated in a way that @low bits 12-31 define the * bits 12-31 of the metric and @high bits 0-19 define the bits 32-51 of the -- GitLab From 992801ae92431761b3d8ec88abd5793d154d34ac Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:46 -0700 Subject: [PATCH 036/965] x86/sgx: Initial poison handling for dirty and free pages A memory controller patrol scrubber can report poison in a page that isn't currently being used. Add "poison" field in the sgx_epc_page that can be set for an sgx_epc_page. Check for it: 1) When sanitizing dirty pages 2) When freeing epc pages Poison is a new field separated from flags to avoid having to make all updates to flags atomic, or integrate poison state changes into some other locking scheme to protect flags (Currently just sgx_reclaimer_lock which protects the SGX_EPC_PAGE_RECLAIMER_TRACKED bit in page->flags). In both cases place the poisoned page on a per-node list of poisoned epc pages to make sure it will not be reallocated. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-4-tony.luck@intel.com --- arch/x86/kernel/cpu/sgx/main.c | 26 +++++++++++++++++++++++++- arch/x86/kernel/cpu/sgx/sgx.h | 4 +++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 5c02cffdabc86..e5fcb8354bcc4 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -62,6 +62,24 @@ static void __sgx_sanitize_pages(struct list_head *dirty_page_list) page = list_first_entry(dirty_page_list, struct sgx_epc_page, list); + /* + * Checking page->poison without holding the node->lock + * is racy, but losing the race (i.e. poison is set just + * after the check) just means __eremove() will be uselessly + * called for a page that sgx_free_epc_page() will put onto + * the node->sgx_poison_page_list later. + */ + if (page->poison) { + struct sgx_epc_section *section = &sgx_epc_sections[page->section]; + struct sgx_numa_node *node = section->node; + + spin_lock(&node->lock); + list_move(&page->list, &node->sgx_poison_page_list); + spin_unlock(&node->lock); + + continue; + } + ret = __eremove(sgx_get_epc_virt_addr(page)); if (!ret) { /* @@ -626,7 +644,11 @@ void sgx_free_epc_page(struct sgx_epc_page *page) spin_lock(&node->lock); - list_add_tail(&page->list, &node->free_page_list); + page->owner = NULL; + if (page->poison) + list_add(&page->list, &node->sgx_poison_page_list); + else + list_add_tail(&page->list, &node->free_page_list); sgx_nr_free_pages++; page->flags = SGX_EPC_PAGE_IS_FREE; @@ -658,6 +680,7 @@ static bool __init sgx_setup_epc_section(u64 phys_addr, u64 size, section->pages[i].section = index; section->pages[i].flags = 0; section->pages[i].owner = NULL; + section->pages[i].poison = 0; list_add_tail(§ion->pages[i].list, &sgx_dirty_page_list); } @@ -724,6 +747,7 @@ static bool __init sgx_page_cache_init(void) if (!node_isset(nid, sgx_numa_mask)) { spin_lock_init(&sgx_numa_nodes[nid].lock); INIT_LIST_HEAD(&sgx_numa_nodes[nid].free_page_list); + INIT_LIST_HEAD(&sgx_numa_nodes[nid].sgx_poison_page_list); node_set(nid, sgx_numa_mask); } diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index 5906471156c5c..9ec3136c78009 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -31,7 +31,8 @@ struct sgx_epc_page { unsigned int section; - unsigned int flags; + u16 flags; + u16 poison; struct sgx_encl_page *owner; struct list_head list; }; @@ -42,6 +43,7 @@ struct sgx_epc_page { */ struct sgx_numa_node { struct list_head free_page_list; + struct list_head sgx_poison_page_list; spinlock_t lock; }; -- GitLab From a495cbdffa30558b34f3c95555cecc4fd9688039 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:47 -0700 Subject: [PATCH 037/965] x86/sgx: Add SGX infrastructure to recover from poison Provide a recovery function sgx_memory_failure(). If the poison was consumed synchronously then send a SIGBUS. Note that the virtual address of the access is not included with the SIGBUS as is the case for poison outside of SGX enclaves. This doesn't matter as addresses of code/data inside an enclave is of little to no use to code executing outside the (now dead) enclave. Poison found in a free page results in the page being moved from the free list to the per-node poison page list. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-5-tony.luck@intel.com --- arch/x86/kernel/cpu/sgx/main.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index e5fcb8354bcc4..231c494dfd407 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -693,6 +693,82 @@ bool arch_is_platform_page(u64 paddr) } EXPORT_SYMBOL_GPL(arch_is_platform_page); +static struct sgx_epc_page *sgx_paddr_to_page(u64 paddr) +{ + struct sgx_epc_section *section; + + section = xa_load(&sgx_epc_address_space, paddr); + if (!section) + return NULL; + + return §ion->pages[PFN_DOWN(paddr - section->phys_addr)]; +} + +/* + * Called in process context to handle a hardware reported + * error in an SGX EPC page. + * If the MF_ACTION_REQUIRED bit is set in flags, then the + * context is the task that consumed the poison data. Otherwise + * this is called from a kernel thread unrelated to the page. + */ +int arch_memory_failure(unsigned long pfn, int flags) +{ + struct sgx_epc_page *page = sgx_paddr_to_page(pfn << PAGE_SHIFT); + struct sgx_epc_section *section; + struct sgx_numa_node *node; + + /* + * mm/memory-failure.c calls this routine for all errors + * where there isn't a "struct page" for the address. But that + * includes other address ranges besides SGX. + */ + if (!page) + return -ENXIO; + + /* + * If poison was consumed synchronously. Send a SIGBUS to + * the task. Hardware has already exited the SGX enclave and + * will not allow re-entry to an enclave that has a memory + * error. The signal may help the task understand why the + * enclave is broken. + */ + if (flags & MF_ACTION_REQUIRED) + force_sig(SIGBUS); + + section = &sgx_epc_sections[page->section]; + node = section->node; + + spin_lock(&node->lock); + + /* Already poisoned? Nothing more to do */ + if (page->poison) + goto out; + + page->poison = 1; + + /* + * If the page is on a free list, move it to the per-node + * poison page list. + */ + if (page->flags & SGX_EPC_PAGE_IS_FREE) { + list_move(&page->list, &node->sgx_poison_page_list); + goto out; + } + + /* + * TBD: Add additional plumbing to enable pre-emptive + * action for asynchronous poison notification. Until + * then just hope that the poison: + * a) is not accessed - sgx_free_epc_page() will deal with it + * when the user gives it back + * b) results in a recoverable machine check rather than + * a fatal one + */ +out: + spin_unlock(&node->lock); + return 0; +} + /** * A section metric is concatenated in a way that @low bits 12-31 define the * bits 12-31 of the metric and @high bits 0-19 define the bits 32-51 of the -- GitLab From 03b122da74b22fbe7cd98184fa5657a9ce13970c Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:48 -0700 Subject: [PATCH 038/965] x86/sgx: Hook arch_memory_failure() into mainline code Add a call inside memory_failure() to call the arch specific code to check if the address is an SGX EPC page and handle it. Note the SGX EPC pages do not have a "struct page" entry, so the hook goes in at the same point as the device mapping hook. Pull the call to acquire the mutex earlier so the SGX errors are also protected. Make set_mce_nospec() skip SGX pages when trying to adjust the 1:1 map. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Reviewed-by: Naoya Horiguchi Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-6-tony.luck@intel.com --- arch/x86/include/asm/processor.h | 8 ++++++++ arch/x86/include/asm/set_memory.h | 4 ++++ include/linux/mm.h | 13 +++++++++++++ mm/memory-failure.c | 19 +++++++++++++------ 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 355d38c0cf606..2c5f12ae7d042 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -855,4 +855,12 @@ enum mds_mitigations { MDS_MITIGATION_VMWERV, }; +#ifdef CONFIG_X86_SGX +int arch_memory_failure(unsigned long pfn, int flags); +#define arch_memory_failure arch_memory_failure + +bool arch_is_platform_page(u64 paddr); +#define arch_is_platform_page arch_is_platform_page +#endif + #endif /* _ASM_X86_PROCESSOR_H */ diff --git a/arch/x86/include/asm/set_memory.h b/arch/x86/include/asm/set_memory.h index 872617542bbc0..ff0f2d90338a1 100644 --- a/arch/x86/include/asm/set_memory.h +++ b/arch/x86/include/asm/set_memory.h @@ -2,6 +2,7 @@ #ifndef _ASM_X86_SET_MEMORY_H #define _ASM_X86_SET_MEMORY_H +#include #include #include @@ -99,6 +100,9 @@ static inline int set_mce_nospec(unsigned long pfn, bool unmap) unsigned long decoy_addr; int rc; + /* SGX pages are not in the 1:1 map */ + if (arch_is_platform_page(pfn << PAGE_SHIFT)) + return 0; /* * We would like to just call: * set_memory_XX((unsigned long)pfn_to_kaddr(pfn), 1); diff --git a/include/linux/mm.h b/include/linux/mm.h index a7e4a9e7d807a..57f1aa2a33b6d 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -3231,6 +3231,19 @@ extern void shake_page(struct page *p); extern atomic_long_t num_poisoned_pages __read_mostly; extern int soft_offline_page(unsigned long pfn, int flags); +#ifndef arch_memory_failure +static inline int arch_memory_failure(unsigned long pfn, int flags) +{ + return -ENXIO; +} +#endif + +#ifndef arch_is_platform_page +static inline bool arch_is_platform_page(u64 paddr) +{ + return false; +} +#endif /* * Error handlers for various types of pages. diff --git a/mm/memory-failure.c b/mm/memory-failure.c index 07c875fdeaf0c..fddee33bc6cbf 100644 --- a/mm/memory-failure.c +++ b/mm/memory-failure.c @@ -1651,21 +1651,28 @@ int memory_failure(unsigned long pfn, int flags) if (!sysctl_memory_failure_recovery) panic("Memory failure on page %lx", pfn); + mutex_lock(&mf_mutex); + p = pfn_to_online_page(pfn); if (!p) { + res = arch_memory_failure(pfn, flags); + if (res == 0) + goto unlock_mutex; + if (pfn_valid(pfn)) { pgmap = get_dev_pagemap(pfn, NULL); - if (pgmap) - return memory_failure_dev_pagemap(pfn, flags, - pgmap); + if (pgmap) { + res = memory_failure_dev_pagemap(pfn, flags, + pgmap); + goto unlock_mutex; + } } pr_err("Memory failure: %#lx: memory outside kernel control\n", pfn); - return -ENXIO; + res = -ENXIO; + goto unlock_mutex; } - mutex_lock(&mf_mutex); - try_again: if (PageHuge(p)) { res = memory_failure_hugetlb(pfn, flags); -- GitLab From c6acb1e7bf4656b9434335c72b8245cc84575fde Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:49 -0700 Subject: [PATCH 039/965] x86/sgx: Add hook to error injection address validation SGX reserved memory does not appear in the standard address maps. Add hook to call into the SGX code to check if an address is located in SGX memory. There are other challenges in injecting errors into SGX. Update the documentation with a sequence of operations to inject. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-7-tony.luck@intel.com --- .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ drivers/acpi/apei/einj.c | 3 ++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index c042176e17078..55e2331a64380 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -181,5 +181,24 @@ You should see something like this in dmesg:: [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) +Special notes for injection into SGX enclaves: + +There may be a separate BIOS setup option to enable SGX injection. + +The injection process consists of setting some special memory controller +trigger that will inject the error on the next write to the target +address. But the h/w prevents any software outside of an SGX enclave +from accessing enclave pages (even BIOS SMM mode). + +The following sequence can be used: + 1) Determine physical address of enclave page + 2) Use "notrigger=1" mode to inject (this will setup + the injection address, but will not actually inject) + 3) Enter the enclave + 4) Store data to the virtual address matching physical address from step 1 + 5) Execute CLFLUSH for that virtual address + 6) Spin delay for 250ms + 7) Read from the virtual address. This will trigger the error + For more information about EINJ, please refer to ACPI specification version 4.0, section 17.5 and ACPI 5.0, section 18.6. diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index edb2622fd35fe..95cc2a9f3e058 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -545,7 +545,8 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, ((region_intersects(base_addr, size, IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) != REGION_INTERSECTS) && (region_intersects(base_addr, size, IORESOURCE_MEM, IORES_DESC_PERSISTENT_MEMORY) - != REGION_INTERSECTS))) + != REGION_INTERSECTS) && + !arch_is_platform_page(base_addr))) return -EINVAL; inject: -- GitLab From 3ad6fd77a2d62e8f4465b429b65805eaf88e1b9e Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Oct 2021 15:00:50 -0700 Subject: [PATCH 040/965] x86/sgx: Add check for SGX pages to ghes_do_memory_failure() SGX EPC pages do not have a "struct page" associated with them so the pfn_valid() sanity check fails and results in a warning message to the console. Add an additional check to skip the warning if the address of the error is in an SGX EPC page. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Tested-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211026220050.697075-8-tony.luck@intel.com --- drivers/acpi/apei/ghes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 0c8330ed1ffd5..0c5c9acc6254e 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -449,7 +449,7 @@ static bool ghes_do_memory_failure(u64 physical_addr, int flags) return false; pfn = PHYS_PFN(physical_addr); - if (!pfn_valid(pfn)) { + if (!pfn_valid(pfn) && !arch_is_platform_page(physical_addr)) { pr_warn_ratelimited(FW_WARN GHES_PFX "Invalid address in generic error data: %#llx\n", physical_addr); -- GitLab From 18c3933c1983157df9dc06d4f3bfc764f161ed7a Mon Sep 17 00:00:00 2001 From: Brijesh Singh Date: Wed, 10 Nov 2021 16:06:50 -0600 Subject: [PATCH 041/965] x86/sev: Shorten GHCB terminate macro names Shorten macro names for improved readability. Suggested-by: Borislav Petkov Signed-off-by: Brijesh Singh Signed-off-by: Borislav Petkov Reviewed-by: Venu Busireddy Link: https://lkml.kernel.org/r/20211110220731.2396491-5-brijesh.singh@amd.com --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/sev-common.h | 4 ++-- arch/x86/kernel/sev-shared.c | 2 +- arch/x86/kernel/sev.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 670e998fe9306..28bcf04c022ea 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -122,7 +122,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) - sev_es_terminate(GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED); + sev_es_terminate(GHCB_SEV_ES_PROT_UNSUPPORTED); if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -175,7 +175,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) enum es_result result; if (!boot_ghcb && !early_setup_sev_es()) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); result = vc_init_em_ctxt(&ctxt, regs, exit_code); @@ -202,5 +202,5 @@ finish: if (result == ES_OK) vc_finish_insn(&ctxt); else if (result != ES_RETRY) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 2cef6c5a52c2a..855b0ec9c4e82 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -68,8 +68,8 @@ (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) -#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0 -#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1 +#define GHCB_SEV_ES_GEN_REQ 0 +#define GHCB_SEV_ES_PROT_UNSUPPORTED 1 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 787dc5f568b5d..ce987688bbc05 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -221,7 +221,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) fail: /* Terminate the guest */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 74f0ec9553848..0a6c82e060e00 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1411,7 +1411,7 @@ DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication) show_regs(regs); /* Ask hypervisor to sev_es_terminate */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); /* If that fails and we get here - just panic */ panic("Returned from Terminate-Request to Hypervisor\n"); @@ -1459,7 +1459,7 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) /* Do initial setup or terminate the guest */ if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb())) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); -- GitLab From 5064343fb155487362708bacc8c6ab9dc2c52bb8 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Mon, 15 Nov 2021 10:35:14 -0800 Subject: [PATCH 042/965] selftests/sgx: Fix a benign linker warning The enclave binary (test_encl.elf) is built with only three sections (tcs, text, and data) as controlled by its custom linker script. If gcc is built with "--enable-linker-build-id" (this appears to be a common configuration even if it is by default off) then gcc will pass "--build-id" to the linker that will prompt it (the linker) to write unique bits identifying the linked file to a ".note.gnu.build-id" section. The section ".note.gnu.build-id" does not exist in the test enclave resulting in the following warning emitted by the linker: /usr/bin/ld: warning: .note.gnu.build-id section discarded, --build-id ignored The test enclave does not use the build id within the binary so fix the warning by passing a build id of "none" to the linker that will disable the setting from any earlier "--build-id" options and thus disable the attempt to write the build id to a ".note.gnu.build-id" section that does not exist. Link: https://lore.kernel.org/linux-sgx/20191017030340.18301-2-sean.j.christopherson@intel.com/ Suggested-by: Cedric Xing Signed-off-by: Sean Christopherson Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/ca0f8a81fc1e78af9bdbc6a88e0f9c37d82e53f2.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/sgx/Makefile b/tools/testing/selftests/sgx/Makefile index 7f12d55b97f86..2956584e1e37f 100644 --- a/tools/testing/selftests/sgx/Makefile +++ b/tools/testing/selftests/sgx/Makefile @@ -45,7 +45,7 @@ $(OUTPUT)/sign_key.o: sign_key.S $(CC) $(HOST_CFLAGS) -c $< -o $@ $(OUTPUT)/test_encl.elf: test_encl.lds test_encl.c test_encl_bootstrap.S - $(CC) $(ENCL_CFLAGS) -T $^ -o $@ + $(CC) $(ENCL_CFLAGS) -T $^ -o $@ -Wl,--build-id=none EXTRA_CLEAN := \ $(OUTPUT)/test_encl.elf \ -- GitLab From 39f62536be2f6160bba7294b5208e240d34703c3 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:15 -0800 Subject: [PATCH 043/965] selftests/sgx: Assign source for each segment Define source per segment so that enclave pages can be added from different sources, e.g. anonymous VMA for zero pages. In other words, add 'src' field to struct encl_segment, and assign it to 'encl->src' for pages inherited from the enclave binary. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/7850709c3089fe20e4bcecb8295ba87c54cc2b4a.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/load.c | 5 +++-- tools/testing/selftests/sgx/main.h | 1 + tools/testing/selftests/sgx/sigstruct.c | 8 ++++---- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/sgx/load.c b/tools/testing/selftests/sgx/load.c index 3ebe5d1fe3370..5605474aab73e 100644 --- a/tools/testing/selftests/sgx/load.c +++ b/tools/testing/selftests/sgx/load.c @@ -107,7 +107,7 @@ static bool encl_ioc_add_pages(struct encl *encl, struct encl_segment *seg) memset(&secinfo, 0, sizeof(secinfo)); secinfo.flags = seg->flags; - ioc.src = (uint64_t)encl->src + seg->offset; + ioc.src = (uint64_t)seg->src; ioc.offset = seg->offset; ioc.length = seg->size; ioc.secinfo = (unsigned long)&secinfo; @@ -216,6 +216,7 @@ bool encl_load(const char *path, struct encl *encl) if (j == 0) { src_offset = phdr->p_offset & PAGE_MASK; + encl->src = encl->bin + src_offset; seg->prot = PROT_READ | PROT_WRITE; seg->flags = SGX_PAGE_TYPE_TCS << 8; @@ -228,13 +229,13 @@ bool encl_load(const char *path, struct encl *encl) seg->offset = (phdr->p_offset & PAGE_MASK) - src_offset; seg->size = (phdr->p_filesz + PAGE_SIZE - 1) & PAGE_MASK; + seg->src = encl->src + seg->offset; j++; } assert(j == encl->nr_segments); - encl->src = encl->bin + src_offset; encl->src_size = encl->segment_tbl[j - 1].offset + encl->segment_tbl[j - 1].size; diff --git a/tools/testing/selftests/sgx/main.h b/tools/testing/selftests/sgx/main.h index 68672fd86cf94..452d11dc4889d 100644 --- a/tools/testing/selftests/sgx/main.h +++ b/tools/testing/selftests/sgx/main.h @@ -7,6 +7,7 @@ #define MAIN_H struct encl_segment { + void *src; off_t offset; size_t size; unsigned int prot; diff --git a/tools/testing/selftests/sgx/sigstruct.c b/tools/testing/selftests/sgx/sigstruct.c index 92bbc5a15c39f..202a96fd81bf8 100644 --- a/tools/testing/selftests/sgx/sigstruct.c +++ b/tools/testing/selftests/sgx/sigstruct.c @@ -289,14 +289,14 @@ static bool mrenclave_eextend(EVP_MD_CTX *ctx, uint64_t offset, static bool mrenclave_segment(EVP_MD_CTX *ctx, struct encl *encl, struct encl_segment *seg) { - uint64_t end = seg->offset + seg->size; + uint64_t end = seg->size; uint64_t offset; - for (offset = seg->offset; offset < end; offset += PAGE_SIZE) { - if (!mrenclave_eadd(ctx, offset, seg->flags)) + for (offset = 0; offset < end; offset += PAGE_SIZE) { + if (!mrenclave_eadd(ctx, seg->offset + offset, seg->flags)) return false; - if (!mrenclave_eextend(ctx, offset, encl->src + offset)) + if (!mrenclave_eextend(ctx, seg->offset + offset, seg->src + offset)) return false; } -- GitLab From 5f0ce664d8c6c160ce4333e809545a8a57fe2baf Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:16 -0800 Subject: [PATCH 044/965] selftests/sgx: Make data measurement for an enclave segment optional For a heap makes sense to leave its contents "unmeasured" in the SGX enclave build process, meaning that they won't contribute to the cryptographic signature (a RSA-3072 signed SHA56 hash) of the enclave. Enclaves are signed blobs where the signature is calculated both from page data and also from "structural properties" of the pages. For instance a page offset of *every* page added to the enclave is hashed. For data, this is optional, not least because hashing a page has a significant contribution to the enclave load time. Thus, where there is no reason to hash, do not. The SGX ioctl interface supports this with SGX_PAGE_MEASURE flag. Only when the flag is *set*, data is measured. Add seg->measure boolean flag to struct encl_segment. Only when the flag is set, include the segment data to the signature (represented by SIGSTRUCT architectural structure). Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/625b6fe28fed76275e9238ec4e15ec3c0d87de81.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/load.c | 6 +++++- tools/testing/selftests/sgx/main.h | 1 + tools/testing/selftests/sgx/sigstruct.c | 6 ++++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/sgx/load.c b/tools/testing/selftests/sgx/load.c index 5605474aab73e..f1be78984c501 100644 --- a/tools/testing/selftests/sgx/load.c +++ b/tools/testing/selftests/sgx/load.c @@ -111,7 +111,10 @@ static bool encl_ioc_add_pages(struct encl *encl, struct encl_segment *seg) ioc.offset = seg->offset; ioc.length = seg->size; ioc.secinfo = (unsigned long)&secinfo; - ioc.flags = SGX_PAGE_MEASURE; + if (seg->measure) + ioc.flags = SGX_PAGE_MEASURE; + else + ioc.flags = 0; rc = ioctl(encl->fd, SGX_IOC_ENCLAVE_ADD_PAGES, &ioc); if (rc < 0) { @@ -230,6 +233,7 @@ bool encl_load(const char *path, struct encl *encl) seg->offset = (phdr->p_offset & PAGE_MASK) - src_offset; seg->size = (phdr->p_filesz + PAGE_SIZE - 1) & PAGE_MASK; seg->src = encl->src + seg->offset; + seg->measure = true; j++; } diff --git a/tools/testing/selftests/sgx/main.h b/tools/testing/selftests/sgx/main.h index 452d11dc4889d..aebc69e7cdc84 100644 --- a/tools/testing/selftests/sgx/main.h +++ b/tools/testing/selftests/sgx/main.h @@ -12,6 +12,7 @@ struct encl_segment { size_t size; unsigned int prot; unsigned int flags; + bool measure; }; struct encl { diff --git a/tools/testing/selftests/sgx/sigstruct.c b/tools/testing/selftests/sgx/sigstruct.c index 202a96fd81bf8..50c5ab1aa6fa1 100644 --- a/tools/testing/selftests/sgx/sigstruct.c +++ b/tools/testing/selftests/sgx/sigstruct.c @@ -296,8 +296,10 @@ static bool mrenclave_segment(EVP_MD_CTX *ctx, struct encl *encl, if (!mrenclave_eadd(ctx, seg->offset + offset, seg->flags)) return false; - if (!mrenclave_eextend(ctx, seg->offset + offset, seg->src + offset)) - return false; + if (seg->measure) { + if (!mrenclave_eextend(ctx, seg->offset + offset, seg->src + offset)) + return false; + } } return true; -- GitLab From 3200505d4de6436af799d7be743d9dc87450ee5a Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:17 -0800 Subject: [PATCH 045/965] selftests/sgx: Create a heap for the test enclave Create a heap for the test enclave, which is allocated from /dev/null, and left unmeasured. This is beneficial by its own because it verifies that an enclave built from multiple choices, works properly. If LSM hooks are added for SGX some day, a multi source enclave has higher probability to trigger bugs on access control checks. The immediate need comes from the need to implement page reclaim tests. In order to trigger the page reclaimer, one can just set the size of the heap to high enough. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/e070c5f23578c29608051cab879b1d276963a27a.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/load.c | 29 ++++++++++++++++++++++------- tools/testing/selftests/sgx/main.c | 2 +- tools/testing/selftests/sgx/main.h | 4 +++- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/sgx/load.c b/tools/testing/selftests/sgx/load.c index f1be78984c501..9d4322c946e2b 100644 --- a/tools/testing/selftests/sgx/load.c +++ b/tools/testing/selftests/sgx/load.c @@ -21,6 +21,8 @@ void encl_delete(struct encl *encl) { + struct encl_segment *heap_seg = &encl->segment_tbl[encl->nr_segments - 1]; + if (encl->encl_base) munmap((void *)encl->encl_base, encl->encl_size); @@ -30,6 +32,8 @@ void encl_delete(struct encl *encl) if (encl->fd) close(encl->fd); + munmap(heap_seg->src, heap_seg->size); + if (encl->segment_tbl) free(encl->segment_tbl); @@ -125,11 +129,10 @@ static bool encl_ioc_add_pages(struct encl *encl, struct encl_segment *seg) return true; } - - -bool encl_load(const char *path, struct encl *encl) +bool encl_load(const char *path, struct encl *encl, unsigned long heap_size) { const char device_path[] = "/dev/sgx_enclave"; + struct encl_segment *seg; Elf64_Phdr *phdr_tbl; off_t src_offset; Elf64_Ehdr *ehdr; @@ -181,6 +184,8 @@ bool encl_load(const char *path, struct encl *encl) ehdr = encl->bin; phdr_tbl = encl->bin + ehdr->e_phoff; + encl->nr_segments = 1; /* one for the heap */ + for (i = 0; i < ehdr->e_phnum; i++) { Elf64_Phdr *phdr = &phdr_tbl[i]; @@ -196,7 +201,6 @@ bool encl_load(const char *path, struct encl *encl) for (i = 0, j = 0; i < ehdr->e_phnum; i++) { Elf64_Phdr *phdr = &phdr_tbl[i]; unsigned int flags = phdr->p_flags; - struct encl_segment *seg; if (phdr->p_type != PT_LOAD) continue; @@ -238,10 +242,21 @@ bool encl_load(const char *path, struct encl *encl) j++; } - assert(j == encl->nr_segments); + assert(j == encl->nr_segments - 1); + + seg = &encl->segment_tbl[j]; + seg->offset = encl->segment_tbl[j - 1].offset + encl->segment_tbl[j - 1].size; + seg->size = heap_size; + seg->src = mmap(NULL, heap_size, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + seg->prot = PROT_READ | PROT_WRITE; + seg->flags = (SGX_PAGE_TYPE_REG << 8) | seg->prot; + seg->measure = false; + + if (seg->src == MAP_FAILED) + goto err; - encl->src_size = encl->segment_tbl[j - 1].offset + - encl->segment_tbl[j - 1].size; + encl->src_size = encl->segment_tbl[j].offset + encl->segment_tbl[j].size; for (encl->encl_size = 4096; encl->encl_size < encl->src_size; ) encl->encl_size <<= 1; diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index e252015e0c154..6858a35fed20d 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -122,7 +122,7 @@ FIXTURE_SETUP(enclave) unsigned int i; void *addr; - if (!encl_load("test_encl.elf", &self->encl)) { + if (!encl_load("test_encl.elf", &self->encl, ENCL_HEAP_SIZE_DEFAULT)) { encl_delete(&self->encl); ksft_exit_skip("cannot load enclaves\n"); } diff --git a/tools/testing/selftests/sgx/main.h b/tools/testing/selftests/sgx/main.h index aebc69e7cdc84..b45c52ec7ab3b 100644 --- a/tools/testing/selftests/sgx/main.h +++ b/tools/testing/selftests/sgx/main.h @@ -6,6 +6,8 @@ #ifndef MAIN_H #define MAIN_H +#define ENCL_HEAP_SIZE_DEFAULT 4096 + struct encl_segment { void *src; off_t offset; @@ -33,7 +35,7 @@ extern unsigned char sign_key[]; extern unsigned char sign_key_end[]; void encl_delete(struct encl *ctx); -bool encl_load(const char *path, struct encl *encl); +bool encl_load(const char *path, struct encl *encl, unsigned long heap_size); bool encl_measure(struct encl *encl); bool encl_build(struct encl *encl); -- GitLab From 1471721489090515f9f0f059b25124898928e559 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:18 -0800 Subject: [PATCH 046/965] selftests/sgx: Dump segments and /proc/self/maps only on failure Logging is always a compromise between clarity and detail. The main use case for dumping VMA's is when FIXTURE_SETUP() fails, and is less important for enclaves that do initialize correctly. Therefore, print the segments and /proc/self/maps only in the error case. Finally, if a single test ever creates multiple enclaves, the amount of log lines would become enormous. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/23cef0ae1de3a8a74cbfbbe74eca48ca3f300fde.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/main.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 6858a35fed20d..deab02f2f3ceb 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -127,12 +127,6 @@ FIXTURE_SETUP(enclave) ksft_exit_skip("cannot load enclaves\n"); } - for (i = 0; i < self->encl.nr_segments; i++) { - seg = &self->encl.segment_tbl[i]; - - TH_LOG("0x%016lx 0x%016lx 0x%02x", seg->offset, seg->size, seg->prot); - } - if (!encl_measure(&self->encl)) goto err; @@ -169,6 +163,17 @@ FIXTURE_SETUP(enclave) memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; + return; + +err: + encl_delete(&self->encl); + + for (i = 0; i < self->encl.nr_segments; i++) { + seg = &self->encl.segment_tbl[i]; + + TH_LOG("0x%016lx 0x%016lx 0x%02x", seg->offset, seg->size, seg->prot); + } + maps_file = fopen("/proc/self/maps", "r"); if (maps_file != NULL) { while (fgets(maps_line, sizeof(maps_line), maps_file) != NULL) { @@ -181,11 +186,7 @@ FIXTURE_SETUP(enclave) fclose(maps_file); } -err: - if (!sgx_enter_enclave_sym) - encl_delete(&self->encl); - - ASSERT_NE(sgx_enter_enclave_sym, NULL); + ASSERT_TRUE(false); } FIXTURE_TEARDOWN(enclave) -- GitLab From 1b35eb719549ab5143d61f9e09b0771cd3d00d94 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:19 -0800 Subject: [PATCH 047/965] selftests/sgx: Encpsulate the test enclave creation Introduce setup_test_encl() so that the enclave creation can be moved to TEST_F()'s. This is required for a reclaimer test where the heap size needs to be set large enough to triger the page reclaimer. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/bee0ca867a95828a569c1ba2a8e443a44047dc71.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/main.c | 44 ++++++++++++++++++------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index deab02f2f3ceb..5b3e49a363440 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -112,7 +112,8 @@ FIXTURE(enclave) { struct sgx_enclave_run run; }; -FIXTURE_SETUP(enclave) +static bool setup_test_encl(unsigned long heap_size, struct encl *encl, + struct __test_metadata *_metadata) { Elf64_Sym *sgx_enter_enclave_sym = NULL; struct vdso_symtab symtab; @@ -122,25 +123,25 @@ FIXTURE_SETUP(enclave) unsigned int i; void *addr; - if (!encl_load("test_encl.elf", &self->encl, ENCL_HEAP_SIZE_DEFAULT)) { - encl_delete(&self->encl); - ksft_exit_skip("cannot load enclaves\n"); + if (!encl_load("test_encl.elf", encl, heap_size)) { + encl_delete(encl); + TH_LOG("Failed to load the test enclave.\n"); } - if (!encl_measure(&self->encl)) + if (!encl_measure(encl)) goto err; - if (!encl_build(&self->encl)) + if (!encl_build(encl)) goto err; /* * An enclave consumer only must do this. */ - for (i = 0; i < self->encl.nr_segments; i++) { - struct encl_segment *seg = &self->encl.segment_tbl[i]; + for (i = 0; i < encl->nr_segments; i++) { + struct encl_segment *seg = &encl->segment_tbl[i]; - addr = mmap((void *)self->encl.encl_base + seg->offset, seg->size, - seg->prot, MAP_SHARED | MAP_FIXED, self->encl.fd, 0); + addr = mmap((void *)encl->encl_base + seg->offset, seg->size, + seg->prot, MAP_SHARED | MAP_FIXED, encl->fd, 0); EXPECT_NE(addr, MAP_FAILED); if (addr == MAP_FAILED) goto err; @@ -160,16 +161,13 @@ FIXTURE_SETUP(enclave) vdso_sgx_enter_enclave = addr + sgx_enter_enclave_sym->st_value; - memset(&self->run, 0, sizeof(self->run)); - self->run.tcs = self->encl.encl_base; - - return; + return true; err: - encl_delete(&self->encl); + encl_delete(encl); - for (i = 0; i < self->encl.nr_segments; i++) { - seg = &self->encl.segment_tbl[i]; + for (i = 0; i < encl->nr_segments; i++) { + seg = &encl->segment_tbl[i]; TH_LOG("0x%016lx 0x%016lx 0x%02x", seg->offset, seg->size, seg->prot); } @@ -186,7 +184,17 @@ err: fclose(maps_file); } - ASSERT_TRUE(false); + TH_LOG("Failed to initialize the test enclave.\n"); + + return false; +} + +FIXTURE_SETUP(enclave) +{ + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; } FIXTURE_TEARDOWN(enclave) -- GitLab From 065825db1fd60aa7695565613a69ed086a831869 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:20 -0800 Subject: [PATCH 048/965] selftests/sgx: Move setup_test_encl() to each TEST_F() Create the test enclave inside each TEST_F(), instead of FIXTURE_SETUP(), so that the heap size can be defined per test. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/70ca264535d2ca0dc8dcaf2281e7d6965f8d4a24.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/main.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 5b3e49a363440..f41fba919d06e 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -191,10 +191,6 @@ err: FIXTURE_SETUP(enclave) { - ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); - - memset(&self->run, 0, sizeof(self->run)); - self->run.tcs = self->encl.encl_base; } FIXTURE_TEARDOWN(enclave) @@ -226,6 +222,11 @@ TEST_F(enclave, unclobbered_vdso) { struct encl_op op; + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + op.type = ENCL_OP_PUT; op.buffer = MAGIC; @@ -248,6 +249,11 @@ TEST_F(enclave, clobbered_vdso) { struct encl_op op; + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + op.type = ENCL_OP_PUT; op.buffer = MAGIC; @@ -278,6 +284,11 @@ TEST_F(enclave, clobbered_vdso_and_user_function) { struct encl_op op; + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + self->run.user_handler = (__u64)test_handler; self->run.user_data = 0xdeadbeef; -- GitLab From f0ff2447b8613b883f41ae845b6cc7540d6e5f71 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:21 -0800 Subject: [PATCH 049/965] selftests/sgx: Add a new kselftest: Unclobbered_vdso_oversubscribed Add a variation of the unclobbered_vdso test. In the new test, create a heap for the test enclave, which has the same size as all available Enclave Page Cache (EPC) pages in the system. This will guarantee that all test_encl.elf pages *and* SGX Enclave Control Structure (SECS) have been swapped out by the page reclaimer during the load time. This test will trigger both the page reclaimer and the page fault handler. The page reclaimer triggered, while the heap is being created during the load time. The page fault handler is triggered for all the required pages, while the test case is executing. Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/41f7c508eea79a3198b5014d7691903be08f9ff1.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/main.c | 75 ++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index f41fba919d06e..ee8139a22a3c7 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -245,6 +245,81 @@ TEST_F(enclave, unclobbered_vdso) EXPECT_EQ(self->run.user_data, 0); } +/* + * A section metric is concatenated in a way that @low bits 12-31 define the + * bits 12-31 of the metric and @high bits 0-19 define the bits 32-51 of the + * metric. + */ +static unsigned long sgx_calc_section_metric(unsigned int low, + unsigned int high) +{ + return (low & GENMASK_ULL(31, 12)) + + ((high & GENMASK_ULL(19, 0)) << 32); +} + +/* + * Sum total available physical SGX memory across all EPC sections + * + * Return: total available physical SGX memory available on system + */ +static unsigned long get_total_epc_mem(void) +{ + unsigned int eax, ebx, ecx, edx; + unsigned long total_size = 0; + unsigned int type; + int section = 0; + + while (true) { + eax = SGX_CPUID; + ecx = section + SGX_CPUID_EPC; + __cpuid(&eax, &ebx, &ecx, &edx); + + type = eax & SGX_CPUID_EPC_MASK; + if (type == SGX_CPUID_EPC_INVALID) + break; + + if (type != SGX_CPUID_EPC_SECTION) + break; + + total_size += sgx_calc_section_metric(ecx, edx); + + section++; + } + + return total_size; +} + +TEST_F(enclave, unclobbered_vdso_oversubscribed) +{ + unsigned long total_mem; + struct encl_op op; + + total_mem = get_total_epc_mem(); + ASSERT_NE(total_mem, 0); + ASSERT_TRUE(setup_test_encl(total_mem, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + + op.type = ENCL_OP_PUT; + op.buffer = MAGIC; + + EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.user_data, 0); + + op.type = ENCL_OP_GET; + op.buffer = 0; + + EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + + EXPECT_EQ(op.buffer, MAGIC); + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.user_data, 0); + +} + TEST_F(enclave, clobbered_vdso) { struct encl_op op; -- GitLab From 41493a095e487c207b4b702aee2f8c59a7294e4f Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 15 Nov 2021 10:35:22 -0800 Subject: [PATCH 050/965] selftests/sgx: Provide per-op parameter structs for the test enclave To add more operations to the test enclave, the protocol needs to allow to have operations with varying parameters. Create a separate parameter struct for each existing operation, with the shared parameters in struct encl_op_header. [reinette: rebased to apply on top of oversubscription test series] Signed-off-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/f9a4a8c436b538003b8ebddaa66083992053cef1.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/defines.h | 14 ++++- tools/testing/selftests/sgx/main.c | 68 +++++++++++++------------ tools/testing/selftests/sgx/test_encl.c | 33 +++++++----- 3 files changed, 69 insertions(+), 46 deletions(-) diff --git a/tools/testing/selftests/sgx/defines.h b/tools/testing/selftests/sgx/defines.h index f88562afcaa08..6ff95a766287e 100644 --- a/tools/testing/selftests/sgx/defines.h +++ b/tools/testing/selftests/sgx/defines.h @@ -21,11 +21,21 @@ enum encl_op_type { ENCL_OP_PUT, ENCL_OP_GET, + ENCL_OP_MAX, }; -struct encl_op { +struct encl_op_header { uint64_t type; - uint64_t buffer; +}; + +struct encl_op_put { + struct encl_op_header header; + uint64_t value; +}; + +struct encl_op_get { + struct encl_op_header header; + uint64_t value; }; #endif /* DEFINES_H */ diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index ee8139a22a3c7..3996c00486b60 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -220,27 +220,28 @@ FIXTURE_TEARDOWN(enclave) TEST_F(enclave, unclobbered_vdso) { - struct encl_op op; + struct encl_op_put put_op; + struct encl_op_get get_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - op.type = ENCL_OP_PUT; - op.buffer = MAGIC; + put_op.header.type = ENCL_OP_PUT; + put_op.value = MAGIC; - EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + EXPECT_EQ(ENCL_CALL(&put_op, &self->run, false), 0); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - op.type = ENCL_OP_GET; - op.buffer = 0; + get_op.header.type = ENCL_OP_GET; + get_op.value = 0; - EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + EXPECT_EQ(ENCL_CALL(&get_op, &self->run, false), 0); - EXPECT_EQ(op.buffer, MAGIC); + EXPECT_EQ(get_op.value, MAGIC); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); } @@ -292,7 +293,8 @@ static unsigned long get_total_epc_mem(void) TEST_F(enclave, unclobbered_vdso_oversubscribed) { unsigned long total_mem; - struct encl_op op; + struct encl_op_put put_op; + struct encl_op_get get_op; total_mem = get_total_epc_mem(); ASSERT_NE(total_mem, 0); @@ -301,20 +303,20 @@ TEST_F(enclave, unclobbered_vdso_oversubscribed) memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - op.type = ENCL_OP_PUT; - op.buffer = MAGIC; + put_op.header.type = ENCL_OP_PUT; + put_op.value = MAGIC; - EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + EXPECT_EQ(ENCL_CALL(&put_op, &self->run, false), 0); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - op.type = ENCL_OP_GET; - op.buffer = 0; + get_op.header.type = ENCL_OP_GET; + get_op.value = 0; - EXPECT_EQ(ENCL_CALL(&op, &self->run, false), 0); + EXPECT_EQ(ENCL_CALL(&get_op, &self->run, false), 0); - EXPECT_EQ(op.buffer, MAGIC); + EXPECT_EQ(get_op.value, MAGIC); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); @@ -322,27 +324,28 @@ TEST_F(enclave, unclobbered_vdso_oversubscribed) TEST_F(enclave, clobbered_vdso) { - struct encl_op op; + struct encl_op_put put_op; + struct encl_op_get get_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - op.type = ENCL_OP_PUT; - op.buffer = MAGIC; + put_op.header.type = ENCL_OP_PUT; + put_op.value = MAGIC; - EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + EXPECT_EQ(ENCL_CALL(&put_op, &self->run, true), 0); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - op.type = ENCL_OP_GET; - op.buffer = 0; + get_op.header.type = ENCL_OP_GET; + get_op.value = 0; - EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + EXPECT_EQ(ENCL_CALL(&get_op, &self->run, true), 0); - EXPECT_EQ(op.buffer, MAGIC); + EXPECT_EQ(get_op.value, MAGIC); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); } @@ -357,7 +360,8 @@ static int test_handler(long rdi, long rsi, long rdx, long ursp, long r8, long r TEST_F(enclave, clobbered_vdso_and_user_function) { - struct encl_op op; + struct encl_op_put put_op; + struct encl_op_get get_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); @@ -367,20 +371,20 @@ TEST_F(enclave, clobbered_vdso_and_user_function) self->run.user_handler = (__u64)test_handler; self->run.user_data = 0xdeadbeef; - op.type = ENCL_OP_PUT; - op.buffer = MAGIC; + put_op.header.type = ENCL_OP_PUT; + put_op.value = MAGIC; - EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + EXPECT_EQ(ENCL_CALL(&put_op, &self->run, true), 0); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - op.type = ENCL_OP_GET; - op.buffer = 0; + get_op.header.type = ENCL_OP_GET; + get_op.value = 0; - EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + EXPECT_EQ(ENCL_CALL(&get_op, &self->run, true), 0); - EXPECT_EQ(op.buffer, MAGIC); + EXPECT_EQ(get_op.value, MAGIC); EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); } diff --git a/tools/testing/selftests/sgx/test_encl.c b/tools/testing/selftests/sgx/test_encl.c index 734ea52f99244..f11eb8315704c 100644 --- a/tools/testing/selftests/sgx/test_encl.c +++ b/tools/testing/selftests/sgx/test_encl.c @@ -16,20 +16,29 @@ static void *memcpy(void *dest, const void *src, size_t n) return dest; } -void encl_body(void *rdi, void *rsi) +static void do_encl_op_put(void *op) +{ + struct encl_op_put *op2 = op; + + memcpy(&encl_buffer[0], &op2->value, 8); +} + +static void do_encl_op_get(void *op) { - struct encl_op *op = (struct encl_op *)rdi; + struct encl_op_get *op2 = op; - switch (op->type) { - case ENCL_OP_PUT: - memcpy(&encl_buffer[0], &op->buffer, 8); - break; + memcpy(&op2->value, &encl_buffer[0], 8); +} + +void encl_body(void *rdi, void *rsi) +{ + const void (*encl_op_array[ENCL_OP_MAX])(void *) = { + do_encl_op_put, + do_encl_op_get, + }; - case ENCL_OP_GET: - memcpy(&op->buffer, &encl_buffer[0], 8); - break; + struct encl_op_header *op = (struct encl_op_header *)rdi; - default: - break; - } + if (op->type < ENCL_OP_MAX) + (*encl_op_array[op->type])(op); } -- GitLab From c085dfc7685c8c36698b851b03990b75a3226e97 Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Mon, 15 Nov 2021 10:35:23 -0800 Subject: [PATCH 051/965] selftests/sgx: Rename test properties in preparation for more enclave tests SGX selftests prepares a data structure outside of the enclave with the type of and data for the operation that needs to be run within the enclave. At this time only two complementary operations are supported by the enclave: copying a value from outside the enclave into a default buffer within the enclave and reading a value from the enclave's default buffer into a variable accessible outside the enclave. In preparation for more operations supported by the enclave the names of the current enclave operations are changed to more accurately reflect the operations and more easily distinguish it from future operations: * The enums ENCL_OP_PUT and ENCL_OP_GET are renamed to ENCL_OP_PUT_TO_BUFFER and ENCL_OP_GET_FROM_BUFFER respectively. * The structs encl_op_put and encl_op_get are renamed to encl_op_put_to_buf and encl_op_get_from_buf respectively. * The enclave functions do_encl_op_put and do_encl_op_get are renamed to do_encl_op_put_to_buf and do_encl_op_get_from_buf respectively. No functional changes. Suggested-by: Jarkko Sakkinen Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Acked-by: Jarkko Sakkinen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/023fda047c787cf330b88ed9337705edae6a0078.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/defines.h | 8 +++---- tools/testing/selftests/sgx/main.c | 32 ++++++++++++------------- tools/testing/selftests/sgx/test_encl.c | 12 +++++----- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/tools/testing/selftests/sgx/defines.h b/tools/testing/selftests/sgx/defines.h index 6ff95a766287e..9ea0c7882dfb1 100644 --- a/tools/testing/selftests/sgx/defines.h +++ b/tools/testing/selftests/sgx/defines.h @@ -19,8 +19,8 @@ #include "../../../../arch/x86/include/uapi/asm/sgx.h" enum encl_op_type { - ENCL_OP_PUT, - ENCL_OP_GET, + ENCL_OP_PUT_TO_BUFFER, + ENCL_OP_GET_FROM_BUFFER, ENCL_OP_MAX, }; @@ -28,12 +28,12 @@ struct encl_op_header { uint64_t type; }; -struct encl_op_put { +struct encl_op_put_to_buf { struct encl_op_header header; uint64_t value; }; -struct encl_op_get { +struct encl_op_get_from_buf { struct encl_op_header header; uint64_t value; }; diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 3996c00486b60..61321229e4855 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -220,15 +220,15 @@ FIXTURE_TEARDOWN(enclave) TEST_F(enclave, unclobbered_vdso) { - struct encl_op_put put_op; - struct encl_op_get get_op; + struct encl_op_get_from_buf get_op; + struct encl_op_put_to_buf put_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - put_op.header.type = ENCL_OP_PUT; + put_op.header.type = ENCL_OP_PUT_TO_BUFFER; put_op.value = MAGIC; EXPECT_EQ(ENCL_CALL(&put_op, &self->run, false), 0); @@ -236,7 +236,7 @@ TEST_F(enclave, unclobbered_vdso) EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - get_op.header.type = ENCL_OP_GET; + get_op.header.type = ENCL_OP_GET_FROM_BUFFER; get_op.value = 0; EXPECT_EQ(ENCL_CALL(&get_op, &self->run, false), 0); @@ -292,9 +292,9 @@ static unsigned long get_total_epc_mem(void) TEST_F(enclave, unclobbered_vdso_oversubscribed) { + struct encl_op_get_from_buf get_op; + struct encl_op_put_to_buf put_op; unsigned long total_mem; - struct encl_op_put put_op; - struct encl_op_get get_op; total_mem = get_total_epc_mem(); ASSERT_NE(total_mem, 0); @@ -303,7 +303,7 @@ TEST_F(enclave, unclobbered_vdso_oversubscribed) memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - put_op.header.type = ENCL_OP_PUT; + put_op.header.type = ENCL_OP_PUT_TO_BUFFER; put_op.value = MAGIC; EXPECT_EQ(ENCL_CALL(&put_op, &self->run, false), 0); @@ -311,7 +311,7 @@ TEST_F(enclave, unclobbered_vdso_oversubscribed) EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - get_op.header.type = ENCL_OP_GET; + get_op.header.type = ENCL_OP_GET_FROM_BUFFER; get_op.value = 0; EXPECT_EQ(ENCL_CALL(&get_op, &self->run, false), 0); @@ -324,15 +324,15 @@ TEST_F(enclave, unclobbered_vdso_oversubscribed) TEST_F(enclave, clobbered_vdso) { - struct encl_op_put put_op; - struct encl_op_get get_op; + struct encl_op_get_from_buf get_op; + struct encl_op_put_to_buf put_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); memset(&self->run, 0, sizeof(self->run)); self->run.tcs = self->encl.encl_base; - put_op.header.type = ENCL_OP_PUT; + put_op.header.type = ENCL_OP_PUT_TO_BUFFER; put_op.value = MAGIC; EXPECT_EQ(ENCL_CALL(&put_op, &self->run, true), 0); @@ -340,7 +340,7 @@ TEST_F(enclave, clobbered_vdso) EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - get_op.header.type = ENCL_OP_GET; + get_op.header.type = ENCL_OP_GET_FROM_BUFFER; get_op.value = 0; EXPECT_EQ(ENCL_CALL(&get_op, &self->run, true), 0); @@ -360,8 +360,8 @@ static int test_handler(long rdi, long rsi, long rdx, long ursp, long r8, long r TEST_F(enclave, clobbered_vdso_and_user_function) { - struct encl_op_put put_op; - struct encl_op_get get_op; + struct encl_op_get_from_buf get_op; + struct encl_op_put_to_buf put_op; ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); @@ -371,7 +371,7 @@ TEST_F(enclave, clobbered_vdso_and_user_function) self->run.user_handler = (__u64)test_handler; self->run.user_data = 0xdeadbeef; - put_op.header.type = ENCL_OP_PUT; + put_op.header.type = ENCL_OP_PUT_TO_BUFFER; put_op.value = MAGIC; EXPECT_EQ(ENCL_CALL(&put_op, &self->run, true), 0); @@ -379,7 +379,7 @@ TEST_F(enclave, clobbered_vdso_and_user_function) EXPECT_EEXIT(&self->run); EXPECT_EQ(self->run.user_data, 0); - get_op.header.type = ENCL_OP_GET; + get_op.header.type = ENCL_OP_GET_FROM_BUFFER; get_op.value = 0; EXPECT_EQ(ENCL_CALL(&get_op, &self->run, true), 0); diff --git a/tools/testing/selftests/sgx/test_encl.c b/tools/testing/selftests/sgx/test_encl.c index f11eb8315704c..4e8da738173f2 100644 --- a/tools/testing/selftests/sgx/test_encl.c +++ b/tools/testing/selftests/sgx/test_encl.c @@ -16,16 +16,16 @@ static void *memcpy(void *dest, const void *src, size_t n) return dest; } -static void do_encl_op_put(void *op) +static void do_encl_op_put_to_buf(void *op) { - struct encl_op_put *op2 = op; + struct encl_op_put_to_buf *op2 = op; memcpy(&encl_buffer[0], &op2->value, 8); } -static void do_encl_op_get(void *op) +static void do_encl_op_get_from_buf(void *op) { - struct encl_op_get *op2 = op; + struct encl_op_get_from_buf *op2 = op; memcpy(&op2->value, &encl_buffer[0], 8); } @@ -33,8 +33,8 @@ static void do_encl_op_get(void *op) void encl_body(void *rdi, void *rsi) { const void (*encl_op_array[ENCL_OP_MAX])(void *) = { - do_encl_op_put, - do_encl_op_get, + do_encl_op_put_to_buf, + do_encl_op_get_from_buf, }; struct encl_op_header *op = (struct encl_op_header *)rdi; -- GitLab From abc5cec4735080d12d644c2d39f96cf98c0a367c Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Mon, 15 Nov 2021 10:35:24 -0800 Subject: [PATCH 052/965] selftests/sgx: Add page permission and exception test The Enclave Page Cache Map (EPCM) is a secure structure used by the processor to track the contents of the enclave page cache. The EPCM contains permissions with which enclave pages can be accessed. SGX support allows EPCM and PTE page permissions to differ - as long as the PTE permissions do not exceed the EPCM permissions. Add a test that: (1) Creates an SGX enclave page with writable EPCM permission. (2) Changes the PTE permission on the page to read-only. This should be permitted because the permission does not exceed the EPCM permission. (3) Attempts a write to the page. This should generate a page fault (#PF) because of the read-only PTE even though the EPCM permissions allow the page to be written to. This introduces the first test of SGX exception handling. In this test the issue that caused the exception (PTE page permissions) can be fixed from outside the enclave and after doing so it is possible to re-enter enclave at original entrypoint with ERESUME. Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/3bcc73a4b9fe8780bdb40571805e7ced59e01df7.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/defines.h | 14 +++ tools/testing/selftests/sgx/main.c | 134 ++++++++++++++++++++++++ tools/testing/selftests/sgx/test_encl.c | 21 ++++ 3 files changed, 169 insertions(+) diff --git a/tools/testing/selftests/sgx/defines.h b/tools/testing/selftests/sgx/defines.h index 9ea0c7882dfb1..0bbda6f0c7d35 100644 --- a/tools/testing/selftests/sgx/defines.h +++ b/tools/testing/selftests/sgx/defines.h @@ -21,6 +21,8 @@ enum encl_op_type { ENCL_OP_PUT_TO_BUFFER, ENCL_OP_GET_FROM_BUFFER, + ENCL_OP_PUT_TO_ADDRESS, + ENCL_OP_GET_FROM_ADDRESS, ENCL_OP_MAX, }; @@ -38,4 +40,16 @@ struct encl_op_get_from_buf { uint64_t value; }; +struct encl_op_put_to_addr { + struct encl_op_header header; + uint64_t value; + uint64_t addr; +}; + +struct encl_op_get_from_addr { + struct encl_op_header header; + uint64_t value; + uint64_t addr; +}; + #endif /* DEFINES_H */ diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 61321229e4855..1b4858f8ca4e7 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -21,6 +21,7 @@ #include "main.h" static const uint64_t MAGIC = 0x1122334455667788ULL; +static const uint64_t MAGIC2 = 0x8877665544332211ULL; vdso_sgx_enter_enclave_t vdso_sgx_enter_enclave; struct vdso_symtab { @@ -107,6 +108,25 @@ static Elf64_Sym *vdso_symtab_get(struct vdso_symtab *symtab, const char *name) return NULL; } +/* + * Return the offset in the enclave where the data segment can be found. + * The first RW segment loaded is the TCS, skip that to get info on the + * data segment. + */ +static off_t encl_get_data_offset(struct encl *encl) +{ + int i; + + for (i = 1; i < encl->nr_segments; i++) { + struct encl_segment *seg = &encl->segment_tbl[i]; + + if (seg->prot == (PROT_READ | PROT_WRITE)) + return seg->offset; + } + + return -1; +} + FIXTURE(enclave) { struct encl encl; struct sgx_enclave_run run; @@ -389,4 +409,118 @@ TEST_F(enclave, clobbered_vdso_and_user_function) EXPECT_EQ(self->run.user_data, 0); } +/* + * Second page of .data segment is used to test changing PTE permissions. + * This spans the local encl_buffer within the test enclave. + * + * 1) Start with a sanity check: a value is written to the target page within + * the enclave and read back to ensure target page can be written to. + * 2) Change PTE permissions (RW -> RO) of target page within enclave. + * 3) Repeat (1) - this time expecting a regular #PF communicated via the + * vDSO. + * 4) Change PTE permissions of target page within enclave back to be RW. + * 5) Repeat (1) by resuming enclave, now expected to be possible to write to + * and read from target page within enclave. + */ +TEST_F(enclave, pte_permissions) +{ + struct encl_op_get_from_addr get_addr_op; + struct encl_op_put_to_addr put_addr_op; + unsigned long data_start; + int ret; + + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + + data_start = self->encl.encl_base + + encl_get_data_offset(&self->encl) + + PAGE_SIZE; + + /* + * Sanity check to ensure it is possible to write to page that will + * have its permissions manipulated. + */ + + /* Write MAGIC to page */ + put_addr_op.value = MAGIC; + put_addr_op.addr = data_start; + put_addr_op.header.type = ENCL_OP_PUT_TO_ADDRESS; + + EXPECT_EQ(ENCL_CALL(&put_addr_op, &self->run, true), 0); + + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); + + /* + * Read memory that was just written to, confirming that it is the + * value previously written (MAGIC). + */ + get_addr_op.value = 0; + get_addr_op.addr = data_start; + get_addr_op.header.type = ENCL_OP_GET_FROM_ADDRESS; + + EXPECT_EQ(ENCL_CALL(&get_addr_op, &self->run, true), 0); + + EXPECT_EQ(get_addr_op.value, MAGIC); + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); + + /* Change PTE permissions of target page within the enclave */ + ret = mprotect((void *)data_start, PAGE_SIZE, PROT_READ); + if (ret) + perror("mprotect"); + + /* + * PTE permissions of target page changed to read-only, EPCM + * permissions unchanged (EPCM permissions are RW), attempt to + * write to the page, expecting a regular #PF. + */ + + put_addr_op.value = MAGIC2; + + EXPECT_EQ(ENCL_CALL(&put_addr_op, &self->run, true), 0); + + EXPECT_EQ(self->run.exception_vector, 14); + EXPECT_EQ(self->run.exception_error_code, 0x7); + EXPECT_EQ(self->run.exception_addr, data_start); + + self->run.exception_vector = 0; + self->run.exception_error_code = 0; + self->run.exception_addr = 0; + + /* + * Change PTE permissions back to enable enclave to write to the + * target page and resume enclave - do not expect any exceptions this + * time. + */ + ret = mprotect((void *)data_start, PAGE_SIZE, PROT_READ | PROT_WRITE); + if (ret) + perror("mprotect"); + + EXPECT_EQ(vdso_sgx_enter_enclave((unsigned long)&put_addr_op, 0, + 0, ERESUME, 0, 0, &self->run), + 0); + + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); + + get_addr_op.value = 0; + + EXPECT_EQ(ENCL_CALL(&get_addr_op, &self->run, true), 0); + + EXPECT_EQ(get_addr_op.value, MAGIC2); + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); +} + TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/sgx/test_encl.c b/tools/testing/selftests/sgx/test_encl.c index 4e8da738173f2..5d86e3e6456ad 100644 --- a/tools/testing/selftests/sgx/test_encl.c +++ b/tools/testing/selftests/sgx/test_encl.c @@ -4,6 +4,11 @@ #include #include "defines.h" +/* + * Data buffer spanning two pages that will be placed first in .data + * segment. Even if not used internally the second page is needed by + * external test manipulating page permissions. + */ static uint8_t encl_buffer[8192] = { 1 }; static void *memcpy(void *dest, const void *src, size_t n) @@ -30,11 +35,27 @@ static void do_encl_op_get_from_buf(void *op) memcpy(&op2->value, &encl_buffer[0], 8); } +static void do_encl_op_put_to_addr(void *_op) +{ + struct encl_op_put_to_addr *op = _op; + + memcpy((void *)op->addr, &op->value, 8); +} + +static void do_encl_op_get_from_addr(void *_op) +{ + struct encl_op_get_from_addr *op = _op; + + memcpy(&op->value, (void *)op->addr, 8); +} + void encl_body(void *rdi, void *rsi) { const void (*encl_op_array[ENCL_OP_MAX])(void *) = { do_encl_op_put_to_buf, do_encl_op_get_from_buf, + do_encl_op_put_to_addr, + do_encl_op_get_from_addr, }; struct encl_op_header *op = (struct encl_op_header *)rdi; -- GitLab From 26e688f1263a3c226f3bb5e3441c310ae11e8001 Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Mon, 15 Nov 2021 10:35:25 -0800 Subject: [PATCH 053/965] selftests/sgx: Enable multiple thread support Each thread executing in an enclave is associated with a Thread Control Structure (TCS). The test enclave contains two hardcoded TCS. Each TCS contains meta-data used by the hardware to save and restore thread specific information when entering/exiting the enclave. The two TCS structures within the test enclave share their SSA (State Save Area) resulting in the threads clobbering each other's data. Fix this by providing each TCS their own SSA area. Additionally, there is an 8K stack space and its address is computed from the enclave entry point which is correctly done for TCS #1 that starts on the first address inside the enclave but results in out of bounds memory when entering as TCS #2. Split 8K stack space into two separate pages with offset symbol between to ensure the current enclave entry calculation can continue to be used for both threads. While using the enclave with multiple threads requires these fixes the impact is not apparent because every test up to this point enters the enclave from the first TCS. More detail about the stack fix: ------------------------------- Before this change the test enclave (test_encl) looks as follows: .tcs (2 pages): (page 1) TCS #1 (page 2) TCS #2 .text (1 page) One page of code .data (5 pages) (page 1) encl_buffer (page 2) encl_buffer (page 3) SSA (page 4 and 5) STACK encl_stack: As shown above there is a symbol, encl_stack, that points to the end of the .data segment (pointing to the end of page 5 in .data) which is also the end of the enclave. The enclave entry code computes the stack address by adding encl_stack to the pointer to the TCS that entered the enclave. When entering at TCS #1 the stack is computed correctly but when entering at TCS #2 the stack pointer would point to one page beyond the end of the enclave and a #PF would result when TCS #2 attempts to enter the enclave. The fix involves moving the encl_stack symbol between the two stack pages. Doing so enables the stack address computation in the entry code to compute the correct stack address for each TCS. Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/a49dc0d85401db788a0a3f0d795e848abf3b1f44.1636997631.git.reinette.chatre@intel.com --- .../selftests/sgx/test_encl_bootstrap.S | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/sgx/test_encl_bootstrap.S b/tools/testing/selftests/sgx/test_encl_bootstrap.S index 5d5680d4ea396..82fb0dfcbd238 100644 --- a/tools/testing/selftests/sgx/test_encl_bootstrap.S +++ b/tools/testing/selftests/sgx/test_encl_bootstrap.S @@ -12,7 +12,7 @@ .fill 1, 8, 0 # STATE (set by CPU) .fill 1, 8, 0 # FLAGS - .quad encl_ssa # OSSA + .quad encl_ssa_tcs1 # OSSA .fill 1, 4, 0 # CSSA (set by CPU) .fill 1, 4, 1 # NSSA .quad encl_entry # OENTRY @@ -23,10 +23,10 @@ .fill 1, 4, 0xFFFFFFFF # GSLIMIT .fill 4024, 1, 0 # Reserved - # Identical to the previous TCS. + # TCS2 .fill 1, 8, 0 # STATE (set by CPU) .fill 1, 8, 0 # FLAGS - .quad encl_ssa # OSSA + .quad encl_ssa_tcs2 # OSSA .fill 1, 4, 0 # CSSA (set by CPU) .fill 1, 4, 1 # NSSA .quad encl_entry # OENTRY @@ -40,8 +40,9 @@ .text encl_entry: - # RBX contains the base address for TCS, which is also the first address - # inside the enclave. By adding the value of le_stack_end to it, we get + # RBX contains the base address for TCS, which is the first address + # inside the enclave for TCS #1 and one page into the enclave for + # TCS #2. By adding the value of encl_stack to it, we get # the absolute address for the stack. lea (encl_stack)(%rbx), %rax xchg %rsp, %rax @@ -81,9 +82,15 @@ encl_entry: .section ".data", "aw" -encl_ssa: +encl_ssa_tcs1: + .space 4096 +encl_ssa_tcs2: .space 4096 .balign 4096 - .space 8192 + # Stack of TCS #1 + .space 4096 encl_stack: + .balign 4096 + # Stack of TCS #2 + .space 4096 -- GitLab From 688542e29fae655a8be25832f6a9959bdd308dd8 Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Mon, 15 Nov 2021 10:35:26 -0800 Subject: [PATCH 054/965] selftests/sgx: Add test for multiple TCS entry Each thread executing in an enclave is associated with a Thread Control Structure (TCS). The SGX test enclave contains two hardcoded TCS, thus supporting two threads in the enclave. Add a test to ensure it is possible to enter enclave at both entrypoints. Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Acked-by: Dave Hansen Link: https://lkml.kernel.org/r/7be151a57b4c7959a2364753b995e0006efa3da1.1636997631.git.reinette.chatre@intel.com --- tools/testing/selftests/sgx/defines.h | 1 + tools/testing/selftests/sgx/main.c | 32 +++++++++++++++++++++++++ tools/testing/selftests/sgx/test_encl.c | 6 +++++ 3 files changed, 39 insertions(+) diff --git a/tools/testing/selftests/sgx/defines.h b/tools/testing/selftests/sgx/defines.h index 0bbda6f0c7d35..02d775789ea7b 100644 --- a/tools/testing/selftests/sgx/defines.h +++ b/tools/testing/selftests/sgx/defines.h @@ -23,6 +23,7 @@ enum encl_op_type { ENCL_OP_GET_FROM_BUFFER, ENCL_OP_PUT_TO_ADDRESS, ENCL_OP_GET_FROM_ADDRESS, + ENCL_OP_NOP, ENCL_OP_MAX, }; diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 1b4858f8ca4e7..7e912db4c6c5e 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -409,6 +409,38 @@ TEST_F(enclave, clobbered_vdso_and_user_function) EXPECT_EQ(self->run.user_data, 0); } +/* + * Sanity check that it is possible to enter either of the two hardcoded TCS + */ +TEST_F(enclave, tcs_entry) +{ + struct encl_op_header op; + + ASSERT_TRUE(setup_test_encl(ENCL_HEAP_SIZE_DEFAULT, &self->encl, _metadata)); + + memset(&self->run, 0, sizeof(self->run)); + self->run.tcs = self->encl.encl_base; + + op.type = ENCL_OP_NOP; + + EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); + + /* Move to the next TCS. */ + self->run.tcs = self->encl.encl_base + PAGE_SIZE; + + EXPECT_EQ(ENCL_CALL(&op, &self->run, true), 0); + + EXPECT_EEXIT(&self->run); + EXPECT_EQ(self->run.exception_vector, 0); + EXPECT_EQ(self->run.exception_error_code, 0); + EXPECT_EQ(self->run.exception_addr, 0); +} + /* * Second page of .data segment is used to test changing PTE permissions. * This spans the local encl_buffer within the test enclave. diff --git a/tools/testing/selftests/sgx/test_encl.c b/tools/testing/selftests/sgx/test_encl.c index 5d86e3e6456ad..4fca01cfd8981 100644 --- a/tools/testing/selftests/sgx/test_encl.c +++ b/tools/testing/selftests/sgx/test_encl.c @@ -49,6 +49,11 @@ static void do_encl_op_get_from_addr(void *_op) memcpy(&op->value, (void *)op->addr, 8); } +static void do_encl_op_nop(void *_op) +{ + +} + void encl_body(void *rdi, void *rsi) { const void (*encl_op_array[ENCL_OP_MAX])(void *) = { @@ -56,6 +61,7 @@ void encl_body(void *rdi, void *rsi) do_encl_op_get_from_buf, do_encl_op_put_to_addr, do_encl_op_get_from_addr, + do_encl_op_nop, }; struct encl_op_header *op = (struct encl_op_header *)rdi; -- GitLab From dbc4c70e3cdfe204a67dd66bed78709ee3000ec0 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Wed, 10 Nov 2021 16:06:51 -0600 Subject: [PATCH 055/965] x86/sev: Get rid of excessive use of defines Remove all the defines of masks and bit positions for the GHCB MSR protocol and use comments instead which correspond directly to the spec so that following those can be a lot easier and straightforward with the spec opened in parallel to the code. Aligh vertically while at it. No functional changes. Signed-off-by: Borislav Petkov Signed-off-by: Brijesh Singh Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211110220731.2396491-6-brijesh.singh@amd.com --- arch/x86/include/asm/sev-common.h | 51 +++++++++++++++++-------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 855b0ec9c4e82..aac44c3f839c7 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -18,20 +18,19 @@ /* SEV Information Request/Response */ #define GHCB_MSR_SEV_INFO_RESP 0x001 #define GHCB_MSR_SEV_INFO_REQ 0x002 -#define GHCB_MSR_VER_MAX_POS 48 -#define GHCB_MSR_VER_MAX_MASK 0xffff -#define GHCB_MSR_VER_MIN_POS 32 -#define GHCB_MSR_VER_MIN_MASK 0xffff -#define GHCB_MSR_CBIT_POS 24 -#define GHCB_MSR_CBIT_MASK 0xff -#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ - ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ - (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ - (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ + +#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ + /* GHCBData[63:48] */ \ + ((((_max) & 0xffff) << 48) | \ + /* GHCBData[47:32] */ \ + (((_min) & 0xffff) << 32) | \ + /* GHCBData[31:24] */ \ + (((_cbit) & 0xff) << 24) | \ GHCB_MSR_SEV_INFO_RESP) + #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) -#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) -#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) +#define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) +#define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) /* CPUID Request/Response */ #define GHCB_MSR_CPUID_REQ 0x004 @@ -46,27 +45,33 @@ #define GHCB_CPUID_REQ_EBX 1 #define GHCB_CPUID_REQ_ECX 2 #define GHCB_CPUID_REQ_EDX 3 -#define GHCB_CPUID_REQ(fn, reg) \ - (GHCB_MSR_CPUID_REQ | \ - (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ - (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +#define GHCB_CPUID_REQ(fn, reg) \ + /* GHCBData[11:0] */ \ + (GHCB_MSR_CPUID_REQ | \ + /* GHCBData[31:12] */ \ + (((unsigned long)(reg) & 0x3) << 30) | \ + /* GHCBData[63:32] */ \ + (((unsigned long)fn) << 32)) /* AP Reset Hold */ -#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 -#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 /* GHCB Hypervisor Feature Request/Response */ -#define GHCB_MSR_HV_FT_REQ 0x080 -#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf #define GHCB_MSR_TERM_REASON_POS 16 #define GHCB_MSR_TERM_REASON_MASK 0xff -#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ - (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ - ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) + +#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ + /* GHCBData[15:12] */ \ + (((((u64)reason_set) & 0xf) << 12) | \ + /* GHCBData[23:16] */ \ + ((((u64)reason_val) & 0xff) << 16)) #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 -- GitLab From 5ed0a99b12aa2dd09afe7ba485145529b89f26e6 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Wed, 10 Nov 2021 16:06:52 -0600 Subject: [PATCH 056/965] x86/head64: Carve out the guest encryption postprocessing into a helper Carve it out so that it is abstracted out of the main boot path. All other encrypted guest-relevant processing should be placed in there. No functional changes. Signed-off-by: Borislav Petkov Signed-off-by: Brijesh Singh Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211110220731.2396491-7-brijesh.singh@amd.com --- arch/x86/kernel/head64.c | 60 +++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index fc5371a7e9d19..3be9dd213dad9 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -126,6 +126,36 @@ static bool __head check_la57_support(unsigned long physaddr) } #endif +static unsigned long sme_postprocess_startup(struct boot_params *bp, pmdval_t *pmd) +{ + unsigned long vaddr, vaddr_end; + int i; + + /* Encrypt the kernel and related (if SME is active) */ + sme_encrypt_kernel(bp); + + /* + * Clear the memory encryption mask from the .bss..decrypted section. + * The bss section will be memset to zero later in the initialization so + * there is no need to zero it after changing the memory encryption + * attribute. + */ + if (sme_get_me_mask()) { + vaddr = (unsigned long)__start_bss_decrypted; + vaddr_end = (unsigned long)__end_bss_decrypted; + for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { + i = pmd_index(vaddr); + pmd[i] -= sme_get_me_mask(); + } + } + + /* + * Return the SME encryption mask (if SME is active) to be used as a + * modifier for the initial pgdir entry programmed into CR3. + */ + return sme_get_me_mask(); +} + /* Code in __startup_64() can be relocated during execution, but the compiler * doesn't have to generate PC-relative relocations when accessing globals from * that function. Clang actually does not generate them, which leads to @@ -135,7 +165,6 @@ static bool __head check_la57_support(unsigned long physaddr) unsigned long __head __startup_64(unsigned long physaddr, struct boot_params *bp) { - unsigned long vaddr, vaddr_end; unsigned long load_delta, *p; unsigned long pgtable_flags; pgdval_t *pgd; @@ -276,34 +305,7 @@ unsigned long __head __startup_64(unsigned long physaddr, */ *fixup_long(&phys_base, physaddr) += load_delta - sme_get_me_mask(); - /* Encrypt the kernel and related (if SME is active) */ - sme_encrypt_kernel(bp); - - /* - * Clear the memory encryption mask from the .bss..decrypted section. - * The bss section will be memset to zero later in the initialization so - * there is no need to zero it after changing the memory encryption - * attribute. - * - * This is early code, use an open coded check for SME instead of - * using cc_platform_has(). This eliminates worries about removing - * instrumentation or checking boot_cpu_data in the cc_platform_has() - * function. - */ - if (sme_get_me_mask()) { - vaddr = (unsigned long)__start_bss_decrypted; - vaddr_end = (unsigned long)__end_bss_decrypted; - for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { - i = pmd_index(vaddr); - pmd[i] -= sme_get_me_mask(); - } - } - - /* - * Return the SME encryption mask (if SME is active) to be used as a - * modifier for the initial pgdir entry programmed into CR3. - */ - return sme_get_me_mask(); + return sme_postprocess_startup(bp, pmd); } unsigned long __startup_secondary_64(void) -- GitLab From 75cc9a84c9eb36e436e3fcee5158fe31d1dfd78f Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Wed, 10 Nov 2021 16:06:53 -0600 Subject: [PATCH 057/965] x86/sev: Remove do_early_exception() forward declarations There's a perfectly fine prototype in the asm/setup.h header. Use it. No functional changes. Signed-off-by: Borislav Petkov Signed-off-by: Brijesh Singh Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211110220731.2396491-8-brijesh.singh@amd.com --- arch/x86/kernel/sev.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 0a6c82e060e00..03f9aff9d1f7b 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -86,9 +87,6 @@ struct ghcb_state { static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); -/* Needed in vc_early_forward_exception */ -void do_early_exception(struct pt_regs *regs, int trapnr); - static __always_inline bool on_vc_stack(struct pt_regs *regs) { unsigned long sp = regs->sp; @@ -209,9 +207,6 @@ static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state) return ghcb; } -/* Needed in vc_early_forward_exception */ -void do_early_exception(struct pt_regs *regs, int trapnr); - static inline u64 sev_es_rd_ghcb_msr(void) { return __rdmsr(MSR_AMD64_SEV_ES_GHCB); -- GitLab From 82099d76cb6ff6738306e90e816754a5d6b046ce Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Thu, 4 Nov 2021 23:29:10 -0400 Subject: [PATCH 058/965] ARM: dts: aspeed: tyan-s7106: Update nct7802 config This change updates the configuration for the nct7802 hardware monitor to correctly configure its temperature sensors. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211105032910.446492-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 68f332ee1886f..60ac6d3f03b56 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -213,6 +213,30 @@ nct7802@28 { compatible = "nuvoton,nct7802"; reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + sensor-type = "temperature"; + }; }; /* Also connected to: -- GitLab From 8189162c66b7bc2d91224269b472aae57fc699e1 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:54 +0700 Subject: [PATCH 059/965] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices This commit adds configuration i2c busses for 24 NVMe slots and 2 M2 NVMe slots found on Mt.Jade hardware reference platform with Ampere's Altra processor family. Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-3-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 258 ++++++++++++++++++ 1 file changed, 258 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 3515d55bd3126..723c7063c223e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -7,6 +7,50 @@ model = "Ampere Mt. Jade BMC"; compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; + aliases { + /* + * i2c bus 50-57 assigned to NVMe slot 0-7 + */ + i2c50 = &nvmeslot_0; + i2c51 = &nvmeslot_1; + i2c52 = &nvmeslot_2; + i2c53 = &nvmeslot_3; + i2c54 = &nvmeslot_4; + i2c55 = &nvmeslot_5; + i2c56 = &nvmeslot_6; + i2c57 = &nvmeslot_7; + + /* + * i2c bus 60-67 assigned to NVMe slot 8-15 + */ + i2c60 = &nvmeslot_8; + i2c61 = &nvmeslot_9; + i2c62 = &nvmeslot_10; + i2c63 = &nvmeslot_11; + i2c64 = &nvmeslot_12; + i2c65 = &nvmeslot_13; + i2c66 = &nvmeslot_14; + i2c67 = &nvmeslot_15; + + /* + * i2c bus 70-77 assigned to NVMe slot 16-23 + */ + i2c70 = &nvmeslot_16; + i2c71 = &nvmeslot_17; + i2c72 = &nvmeslot_18; + i2c73 = &nvmeslot_19; + i2c74 = &nvmeslot_20; + i2c75 = &nvmeslot_21; + i2c76 = &nvmeslot_22; + i2c77 = &nvmeslot_23; + + /* + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 + */ + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; + }; + chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlycon"; @@ -445,6 +489,220 @@ &i2c5 { status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + nvmeslot_0_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8_15: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + nvmeslot_16_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + }; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; +}; + +&nvmeslot_0_7 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + + }; +}; + +&nvmeslot_8_15 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&nvmeslot_16_23 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; }; &i2c6 { -- GitLab From 16d6dc8d8030dfe88104616cd3dea4e055af506d Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:55 +0700 Subject: [PATCH 060/965] ARM: dts: aspeed: mtjade: Add uefi partition Add SPI NOR partition for uefi. Signed-off-by: Thang Q. Nguyen Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-4-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 723c7063c223e..4c3c3f1a12eae 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -374,6 +374,15 @@ m25p,fast-read; label = "pnor"; /* spi-max-frequency = <100000000>; */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + uefi@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-uefi"; + }; + }; }; }; -- GitLab From 7f9ec9b59c278f31b0c2c8fabcf564e6fc02d4d8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 Nov 2021 10:20:42 +0100 Subject: [PATCH 061/965] ARM: s3c: add one more "fallthrough" statement in Jive clang warns about one missing fallthrough that gcc ignores: arch/arm/mach-s3c/mach-jive.c:250:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] Add it here as well. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211116092053.4042799-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/mach-jive.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-s3c/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c index 0785638a9069b..285e1f0f4145a 100644 --- a/arch/arm/mach-s3c/mach-jive.c +++ b/arch/arm/mach-s3c/mach-jive.c @@ -247,6 +247,7 @@ static int __init jive_mtdset(char *options) case 1: nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part); nand->partitions = jive_imageB_nand_part; + break; case 0: /* this is already setup in the nand info */ break; -- GitLab From c271aa1f73515bcb35f977f30825832d41a2f504 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 25 Oct 2021 21:56:25 +0100 Subject: [PATCH 062/965] dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044 SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to the RPC-IF interface found on R-Car Gen3 SoC's. This patch adds a new compatible string to identify the RZ/G2L family so that the timing values on RZ/G2L can be adjusted. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211025205631.21151-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/renesas,rpc-if.yaml | 53 +++++++++++++------ 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 9da80e8f2444a..43391a2d5bc56 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -24,17 +24,23 @@ allOf: properties: compatible: - items: - - enum: - - renesas,r8a774a1-rpc-if # RZ/G2M - - renesas,r8a774b1-rpc-if # RZ/G2N - - renesas,r8a774c0-rpc-if # RZ/G2E - - renesas,r8a774e1-rpc-if # RZ/G2H - - renesas,r8a77970-rpc-if # R-Car V3M - - renesas,r8a77980-rpc-if # R-Car V3H - - renesas,r8a77995-rpc-if # R-Car D3 - - renesas,r8a779a0-rpc-if # R-Car V3U - - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device + oneOf: + - items: + - enum: + - renesas,r8a774a1-rpc-if # RZ/G2M + - renesas,r8a774b1-rpc-if # RZ/G2N + - renesas,r8a774c0-rpc-if # RZ/G2E + - renesas,r8a774e1-rpc-if # RZ/G2H + - renesas,r8a77970-rpc-if # R-Car V3M + - renesas,r8a77980-rpc-if # R-Car V3H + - renesas,r8a77995-rpc-if # R-Car D3 + - renesas,r8a779a0-rpc-if # R-Car V3U + - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2{E,H,M,N} device + + - items: + - enum: + - renesas,r9a07g044-rpc-if # RZ/G2{L,LC} + - const: renesas,rzg2l-rpc-if # RZ/G2L family reg: items: @@ -48,8 +54,7 @@ properties: - const: dirmap - const: wbuf - clocks: - maxItems: 1 + clocks: true power-domains: maxItems: 1 @@ -67,8 +72,6 @@ patternProperties: - cfi-flash - jedec,spi-nor -unevaluatedProperties: false - required: - compatible - reg @@ -79,6 +82,26 @@ required: - '#address-cells' - '#size-cells' +if: + properties: + compatible: + contains: + enum: + - renesas,rzg2l-rpc-if +then: + properties: + clocks: + items: + - description: SPI Multi IO Register access clock (SPI_CLK2) + - description: SPI Multi IO Main clock (SPI_CLK). + +else: + properties: + clocks: + maxItems: 1 + +unevaluatedProperties: false + examples: - | #include -- GitLab From 4b5a231ff617d5cdc9e99f39a7268ad491400195 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 25 Oct 2021 21:56:26 +0100 Subject: [PATCH 063/965] dt-bindings: memory: renesas,rpc-if: Add optional interrupts property For completeness add optional interrupts property. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Wolfram Sang Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211025205631.21151-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 43391a2d5bc56..294f1036420de 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -56,6 +56,9 @@ properties: clocks: true + interrupts: + maxItems: 1 + power-domains: maxItems: 1 -- GitLab From 818fdfa89baac77a8df5a2c30f4fb798cc937aa0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 25 Oct 2021 21:56:29 +0100 Subject: [PATCH 064/965] memory: renesas-rpc-if: Return error in case devm_ioremap_resource() fails Make sure we return error in case devm_ioremap_resource() fails for dirmap resource. Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211025205631.21151-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 7435baad00075..ff8bcbccac637 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -243,7 +243,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); rpc->dirmap = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(rpc->dirmap)) - rpc->dirmap = NULL; + return PTR_ERR(rpc->dirmap); rpc->size = resource_size(res); rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); -- GitLab From 5da9b59b23d8112709034a07338e03dcc65fa11f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 25 Oct 2021 21:56:30 +0100 Subject: [PATCH 065/965] memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro RPCIF_DIRMAP_SIZE may differ on various SoC's. Instead of using RPCIF_DIRMAP_SIZE macro use resource size to get dirmap size which is already part of struct rpcif. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211025205631.21151-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index ff8bcbccac637..0c56decc91f2f 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -147,8 +147,6 @@ #define RPCIF_PHYINT 0x0088 /* R/W */ #define RPCIF_PHYINT_WPVAL BIT(1) -#define RPCIF_DIRMAP_SIZE 0x4000000 - static const struct regmap_range rpcif_volatile_ranges[] = { regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), @@ -588,8 +586,8 @@ static void memcpy_fromio_readw(void *to, ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) { - loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1); - size_t size = RPCIF_DIRMAP_SIZE - from; + loff_t from = offs & (rpc->size - 1); + size_t size = rpc->size - from; if (len > size) len = size; -- GitLab From b04cc0d912eb80d3c438b11d96ca847c3e77e8ab Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 25 Oct 2021 21:56:31 +0100 Subject: [PATCH 066/965] memory: renesas-rpc-if: Add support for RZ/G2L SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to the RPC-IF interface found on R-Car Gen3 SoC's. This patch adds a new compatible string for the RZ/G2L family so that the timing values on RZ/G2L can be adjusted. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/20211025205631.21151-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 72 ++++++++++++++++++++++++++++----- drivers/mtd/hyperbus/rpc-if.c | 4 +- drivers/spi/spi-rpc-if.c | 4 +- include/memory/renesas-rpc-if.h | 8 +++- 4 files changed, 75 insertions(+), 13 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 0c56decc91f2f..8c51145c0f5cb 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -27,8 +28,8 @@ #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \ RPCIF_CMNCR_MOIIO1(3) | \ RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3)) -#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */ -#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */ +#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */ +#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */ #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \ RPCIF_CMNCR_IO3FV(3)) @@ -126,6 +127,9 @@ #define RPCIF_SMDRENR_OPDRE BIT(4) #define RPCIF_SMDRENR_SPIDRE BIT(0) +#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ +#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ + #define RPCIF_PHYCNT 0x007C /* R/W */ #define RPCIF_PHYCNT_CAL BIT(31) #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) @@ -133,10 +137,12 @@ #define RPCIF_PHYCNT_OCT BIT(20) #define RPCIF_PHYCNT_DDRCAL BIT(19) #define RPCIF_PHYCNT_HS BIT(18) -#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) +#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */ +#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */ #define RPCIF_PHYCNT_WBUF2 BIT(4) #define RPCIF_PHYCNT_WBUF BIT(2) #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) +#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0) #define RPCIF_PHYOFFSET1 0x0080 /* R/W */ #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) @@ -244,18 +250,46 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) return PTR_ERR(rpc->dirmap); rpc->size = resource_size(res); + rpc->type = (enum rpcif_type)of_device_get_match_data(dev); rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); return PTR_ERR_OR_ZERO(rpc->rstc); } EXPORT_SYMBOL(rpcif_sw_init); -void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) +static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc) +{ + u32 data; + + regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); + + regmap_read(rpc->regmap, RPCIF_PHYCNT, &data); + regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3)); + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); +} + +int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) { u32 dummy; pm_runtime_get_sync(rpc->dev); + if (rpc->type == RPCIF_RZ_G2L) { + int ret; + + ret = reset_control_reset(rpc->rstc); + if (ret) + return ret; + usleep_range(200, 300); + rpcif_rzg2l_timing_adjust_sdr(rpc); + } + /* * NOTE: The 0x260 are undocumented bits, but they must be set. * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits, @@ -264,8 +298,15 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) * On H3 ES1.x, the value should be 0, while on others, * the value should be 7. */ - regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) | - RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260); + if (rpc->type == RPCIF_RCAR_GEN3) { + regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) | + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260); + } else { + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy); + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK; + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260; + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy); + } /* * NOTE: The 0x1511144 are undocumented bits, but they must be set @@ -282,9 +323,17 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYINT, RPCIF_PHYINT_WPVAL, 0); - regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | - RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | - RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + if (rpc->type == RPCIF_RCAR_GEN3) + regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | + RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | + RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + else + regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | + RPCIF_CMNCR_MOIIO3(1) | RPCIF_CMNCR_MOIIO2(1) | + RPCIF_CMNCR_MOIIO1(1) | RPCIF_CMNCR_MOIIO0(1) | + RPCIF_CMNCR_IO3FV(2) | RPCIF_CMNCR_IO2FV(2) | + RPCIF_CMNCR_IO0FV(2) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + /* Set RCF after BSZ update */ regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); /* Dummy read according to spec */ @@ -295,6 +344,8 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) pm_runtime_put(rpc->dev); rpc->bus_size = hyperflash ? 2 : 1; + + return 0; } EXPORT_SYMBOL(rpcif_hw_init); @@ -657,7 +708,8 @@ static int rpcif_remove(struct platform_device *pdev) } static const struct of_device_id rpcif_of_match[] = { - { .compatible = "renesas,rcar-gen3-rpc-if", }, + { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, + { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, {}, }; MODULE_DEVICE_TABLE(of, rpcif_of_match); diff --git a/drivers/mtd/hyperbus/rpc-if.c b/drivers/mtd/hyperbus/rpc-if.c index ecb050ba95cdf..8daa296f6eb63 100644 --- a/drivers/mtd/hyperbus/rpc-if.c +++ b/drivers/mtd/hyperbus/rpc-if.c @@ -130,7 +130,9 @@ static int rpcif_hb_probe(struct platform_device *pdev) rpcif_enable_rpm(&hyperbus->rpc); - rpcif_hw_init(&hyperbus->rpc, true); + error = rpcif_hw_init(&hyperbus->rpc, true); + if (error) + return error; hyperbus->hbdev.map.size = hyperbus->rpc.size; hyperbus->hbdev.map.virt = hyperbus->rpc.dirmap; diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c index 83796a4ead34a..fe82f3575df4f 100644 --- a/drivers/spi/spi-rpc-if.c +++ b/drivers/spi/spi-rpc-if.c @@ -156,7 +156,9 @@ static int rpcif_spi_probe(struct platform_device *pdev) ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD; ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; - rpcif_hw_init(rpc, false); + error = rpcif_hw_init(rpc, false); + if (error) + return error; error = spi_register_controller(ctlr); if (error) { diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 77c694a19149d..7c93f5177532f 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -57,6 +57,11 @@ struct rpcif_op { } data; }; +enum rpcif_type { + RPCIF_RCAR_GEN3, + RPCIF_RZ_G2L, +}; + struct rpcif { struct device *dev; void __iomem *base; @@ -64,6 +69,7 @@ struct rpcif { struct regmap *regmap; struct reset_control *rstc; size_t size; + enum rpcif_type type; enum rpcif_data_dir dir; u8 bus_size; void *buffer; @@ -78,7 +84,7 @@ struct rpcif { }; int rpcif_sw_init(struct rpcif *rpc, struct device *dev); -void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); +int rpcif_hw_init(struct rpcif *rpc, bool hyperflash); void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, size_t *len); int rpcif_manual_xfer(struct rpcif *rpc); -- GitLab From 644106cdb89844be2496b21175b7c0c2e0fab381 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Fri, 5 Nov 2021 08:20:50 -0700 Subject: [PATCH 067/965] power: reset: ltc2952: Fix use of floating point literals A new commit in LLVM causes an error on the use of 'long double' when '-mno-x87' is used, which the kernel does through an alias, '-mno-80387' (see the LLVM commit below for more details around why it does this). drivers/power/reset/ltc2952-poweroff.c:162:28: error: expression requires 'long double' type support, but target 'x86_64-unknown-linux-gnu' does not support it data->wde_interval = 300L * 1E6L; ^ drivers/power/reset/ltc2952-poweroff.c:162:21: error: expression requires 'long double' type support, but target 'x86_64-unknown-linux-gnu' does not support it data->wde_interval = 300L * 1E6L; ^ drivers/power/reset/ltc2952-poweroff.c:163:41: error: expression requires 'long double' type support, but target 'x86_64-unknown-linux-gnu' does not support it data->trigger_delay = ktime_set(2, 500L*1E6L); ^ 3 errors generated. This happens due to the use of a 'long double' literal. The 'E6' part of '1E6L' causes the literal to be a 'double' then the 'L' suffix promotes it to 'long double'. There is no visible reason for floating point values in this driver, as the values are only assigned to integer types. Use NSEC_PER_MSEC, which is the same integer value as '1E6L', to avoid changing functionality but fix the error. Fixes: 6647156c00cc ("power: reset: add LTC2952 poweroff driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1497 Link: https://github.com/llvm/llvm-project/commit/a8083d42b1c346e21623a1d36d1f0cadd7801d83 Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Sebastian Reichel --- drivers/power/reset/ltc2952-poweroff.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/reset/ltc2952-poweroff.c b/drivers/power/reset/ltc2952-poweroff.c index fbb344353fe40..65d9528cc9899 100644 --- a/drivers/power/reset/ltc2952-poweroff.c +++ b/drivers/power/reset/ltc2952-poweroff.c @@ -159,8 +159,8 @@ static void ltc2952_poweroff_kill(void) static void ltc2952_poweroff_default(struct ltc2952_poweroff *data) { - data->wde_interval = 300L * 1E6L; - data->trigger_delay = ktime_set(2, 500L*1E6L); + data->wde_interval = 300L * NSEC_PER_MSEC; + data->trigger_delay = ktime_set(2, 500L * NSEC_PER_MSEC); hrtimer_init(&data->timer_trigger, CLOCK_MONOTONIC, HRTIMER_MODE_REL); data->timer_trigger.function = ltc2952_poweroff_timer_trigger; -- GitLab From e927f53f7dd9b3cd389696161b72c8c079770941 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 15 Nov 2021 21:11:12 +0100 Subject: [PATCH 068/965] arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF Tanix TX6 board has SPDIF connector in form of 3.5 mm jack. Add support for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211115201112.452696-1-jernej.skrabec@gmail.com --- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 8f2a80f128de4..6c10ff7f4b1ca 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -52,6 +52,24 @@ regulator-min-microvolt = <1135000>; regulator-max-microvolt = <1135000>; }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &cpu0 { @@ -127,6 +145,10 @@ status = "okay"; }; +&spdif { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; -- GitLab From 0fe4ff885f8a50082d9dc241b657472894caba16 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 16 Nov 2021 17:14:21 +0100 Subject: [PATCH 069/965] x86/fpu: Correct AVX512 state tracking Add a separate, local mask for tracking AVX512 usage which does not include the opmask xfeature set. Opmask registers usage does not cause frequency throttling so it is a completely unnecessary false positive. While at it, carve it out into a separate function to keep that abomination extracted out. [ bp: Rediff and cleanup ontop of 5.16-rc1. ] Signed-off-by: Noah Goldstein Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20210920053951.4093668-1-goldstein.w.n@gmail.com --- arch/x86/kernel/fpu/core.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 8ea306b1bf8ec..dd3777ac0443f 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -98,6 +98,19 @@ bool irq_fpu_usable(void) } EXPORT_SYMBOL(irq_fpu_usable); +/* + * Track AVX512 state use because it is known to slow the max clock + * speed of the core. + */ +static void update_avx_timestamp(struct fpu *fpu) +{ + +#define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM) + + if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK) + fpu->avx512_timestamp = jiffies; +} + /* * Save the FPU register state in fpu->fpstate->regs. The register state is * preserved. @@ -116,13 +129,7 @@ void save_fpregs_to_fpstate(struct fpu *fpu) { if (likely(use_xsave())) { os_xsave(fpu->fpstate); - - /* - * AVX512 state is tracked here because its use is - * known to slow the max clock speed of the core. - */ - if (fpu->fpstate->regs.xsave.header.xfeatures & XFEATURE_MASK_AVX512) - fpu->avx512_timestamp = jiffies; + update_avx_timestamp(fpu); return; } -- GitLab From 63d5bc420f460162cc5318136c2bddba87cfbb29 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Tue, 15 Jun 2021 22:23:44 +0200 Subject: [PATCH 070/965] docs: staging/tee.rst: add a section on OP-TEE notifications Adds a section on notifications used by OP-TEE, synchronous and asynchronous. Reviewed-by: Sumit Garg Acked-by: Marc Zyngier Signed-off-by: Jens Wiklander --- Documentation/staging/tee.rst | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/staging/tee.rst b/Documentation/staging/tee.rst index 4d4b5f8896032..3c63d8dcd61eb 100644 --- a/Documentation/staging/tee.rst +++ b/Documentation/staging/tee.rst @@ -184,6 +184,36 @@ order to support device enumeration. In other words, OP-TEE driver invokes this application to retrieve a list of Trusted Applications which can be registered as devices on the TEE bus. +OP-TEE notifications +-------------------- + +There are two kinds of notifications that secure world can use to make +normal world aware of some event. + +1. Synchronous notifications delivered with ``OPTEE_RPC_CMD_NOTIFICATION`` + using the ``OPTEE_RPC_NOTIFICATION_SEND`` parameter. +2. Asynchronous notifications delivered with a combination of a non-secure + edge-triggered interrupt and a fast call from the non-secure interrupt + handler. + +Synchronous notifications are limited by depending on RPC for delivery, +this is only usable when secure world is entered with a yielding call via +``OPTEE_SMC_CALL_WITH_ARG``. This excludes such notifications from secure +world interrupt handlers. + +An asynchronous notification is delivered via a non-secure edge-triggered +interrupt to an interrupt handler registered in the OP-TEE driver. The +actual notification value are retrieved with the fast call +``OPTEE_SMC_GET_ASYNC_NOTIF_VALUE``. Note that one interrupt can represent +multiple notifications. + +One notification value ``OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF`` has a +special meaning. When this value is received it means that normal world is +supposed to make a yielding call ``OPTEE_MSG_CMD_DO_BOTTOM_HALF``. This +call is done from the thread assisting the interrupt handler. This is a +building block for OP-TEE OS in secure world to implement the top half and +bottom half style of device drivers. + AMD-TEE driver ============== -- GitLab From ff5fdc34d0aed9931c01e6d50f7f873ecf8df8d3 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Tue, 15 Jun 2021 22:23:48 +0200 Subject: [PATCH 071/965] dt-bindings: arm: optee: add interrupt property Adds an optional interrupt property to the optee binding. Reviewed-by: Sumit Garg Reviewed-by: Rob Herring Acked-by: Marc Zyngier Signed-off-by: Jens Wiklander --- .../devicetree/bindings/arm/firmware/linaro,optee-tz.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml index c24047c1fdd58..9a426110a14a9 100644 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -24,6 +24,12 @@ properties: compatible: const: linaro,optee-tz + interrupts: + maxItems: 1 + description: | + This interrupt which is used to signal an event by the secure world + software is expected to be edge-triggered. + method: enum: [smc, hvc] description: | @@ -42,10 +48,12 @@ additionalProperties: false examples: - | + #include firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; + interrupts = ; }; }; -- GitLab From f18397ab3ae23e8e43bba9986e66af6d4497f2ad Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Tue, 15 Jun 2021 22:23:50 +0200 Subject: [PATCH 072/965] tee: fix put order in teedev_close_context() Prior to this patch was teedev_close_context() calling tee_device_put() before teedev_ctx_put() leading to teedev_ctx_release() accessing ctx->teedev just after the reference counter was decreased on the teedev. Fix this by calling teedev_ctx_put() before tee_device_put(). Fixes: 217e0250cccb ("tee: use reference counting for tee_context") Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/tee_core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index 2b37bc408fc3d..85102d12d7169 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -98,8 +98,10 @@ void teedev_ctx_put(struct tee_context *ctx) static void teedev_close_context(struct tee_context *ctx) { - tee_device_put(ctx->teedev); + struct tee_device *teedev = ctx->teedev; + teedev_ctx_put(ctx); + tee_device_put(teedev); } static int tee_open(struct inode *inode, struct file *filp) -- GitLab From 1e2c3ef0496e72ba9001da5fd1b7ed56ccb30597 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Mon, 4 Oct 2021 16:11:52 +0200 Subject: [PATCH 073/965] tee: export teedev_open() and teedev_close_context() Exports the two functions teedev_open() and teedev_close_context() in order to make it easier to create a driver internal struct tee_context. Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/tee_core.c | 6 ++++-- include/linux/tee_drv.h | 14 ++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index 85102d12d7169..3fc426dad2df3 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -43,7 +43,7 @@ static DEFINE_SPINLOCK(driver_lock); static struct class *tee_class; static dev_t tee_devt; -static struct tee_context *teedev_open(struct tee_device *teedev) +struct tee_context *teedev_open(struct tee_device *teedev) { int rc; struct tee_context *ctx; @@ -70,6 +70,7 @@ err: return ERR_PTR(rc); } +EXPORT_SYMBOL_GPL(teedev_open); void teedev_ctx_get(struct tee_context *ctx) { @@ -96,13 +97,14 @@ void teedev_ctx_put(struct tee_context *ctx) kref_put(&ctx->refcount, teedev_ctx_release); } -static void teedev_close_context(struct tee_context *ctx) +void teedev_close_context(struct tee_context *ctx) { struct tee_device *teedev = ctx->teedev; teedev_ctx_put(ctx); tee_device_put(teedev); } +EXPORT_SYMBOL_GPL(teedev_close_context); static int tee_open(struct inode *inode, struct file *filp) { diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h index a1f03461369bd..468a7d83dc6c2 100644 --- a/include/linux/tee_drv.h +++ b/include/linux/tee_drv.h @@ -587,4 +587,18 @@ struct tee_client_driver { #define to_tee_client_driver(d) \ container_of(d, struct tee_client_driver, driver) +/** + * teedev_open() - Open a struct tee_device + * @teedev: Device to open + * + * @return a pointer to struct tee_context on success or an ERR_PTR on failure. + */ +struct tee_context *teedev_open(struct tee_device *teedev); + +/** + * teedev_close_context() - closes a struct tee_context + * @ctx: The struct tee_context to close + */ +void teedev_close_context(struct tee_context *ctx); + #endif /*__TEE_DRV_H*/ -- GitLab From 787c80cc7b22804aa370f04a19f9fe0fa98b1e49 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Tue, 15 Jun 2021 22:23:53 +0200 Subject: [PATCH 074/965] optee: separate notification functions Renames struct optee_wait_queue to struct optee_notif and all related functions to optee_notif_*(). The implementation is changed to allow sending a notification from an atomic state, that is from the top half of an interrupt handler. Waiting for keys is currently only used when secure world is waiting for a mutex or condition variable. The old implementation could handle any 32-bit key while this new implementation is restricted to only 8 bits or the maximum value 255. A upper value is needed since a bitmap is allocated to allow an interrupt handler to only set a bit in case the waiter hasn't had the time yet to allocate and register a completion. The keys are currently only representing secure world threads which number usually are never even close to 255 so it should be safe for now. In future ABI updates the maximum value of the key will be communicated while the driver is initializing. Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/optee/Makefile | 1 + drivers/tee/optee/core.c | 2 +- drivers/tee/optee/ffa_abi.c | 6 +- drivers/tee/optee/notif.c | 125 ++++++++++++++++++++++++++++++ drivers/tee/optee/optee_private.h | 26 +++++-- drivers/tee/optee/optee_rpc_cmd.h | 31 ++++---- drivers/tee/optee/rpc.c | 71 ++--------------- drivers/tee/optee/smc_abi.c | 10 ++- 8 files changed, 181 insertions(+), 91 deletions(-) create mode 100644 drivers/tee/optee/notif.c diff --git a/drivers/tee/optee/Makefile b/drivers/tee/optee/Makefile index 66b8a17f14c4f..a6eff388d300d 100644 --- a/drivers/tee/optee/Makefile +++ b/drivers/tee/optee/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_OPTEE) += optee.o optee-objs += core.o optee-objs += call.o +optee-objs += notif.o optee-objs += rpc.o optee-objs += supp.o optee-objs += device.o diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index ab2edfcc6c704..ba7300ca9ddf9 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -159,6 +159,7 @@ void optee_remove_common(struct optee *optee) /* Unregister OP-TEE specific client devices on TEE bus */ optee_unregister_devices(); + optee_notif_uninit(optee); /* * The two devices have to be unregistered before we can free the * other resources. @@ -167,7 +168,6 @@ void optee_remove_common(struct optee *optee) tee_device_unregister(optee->teedev); tee_shm_pool_free(optee->pool); - optee_wait_queue_exit(&optee->wait_queue); optee_supp_uninit(&optee->supp); mutex_destroy(&optee->call_queue.mutex); } diff --git a/drivers/tee/optee/ffa_abi.c b/drivers/tee/optee/ffa_abi.c index 45424824e0f9f..3577781e5df77 100644 --- a/drivers/tee/optee/ffa_abi.c +++ b/drivers/tee/optee/ffa_abi.c @@ -856,9 +856,13 @@ static int optee_ffa_probe(struct ffa_device *ffa_dev) mutex_init(&optee->ffa.mutex); mutex_init(&optee->call_queue.mutex); INIT_LIST_HEAD(&optee->call_queue.waiters); - optee_wait_queue_init(&optee->wait_queue); optee_supp_init(&optee->supp); ffa_dev_set_drvdata(ffa_dev, optee); + rc = optee_notif_init(optee, OPTEE_DEFAULT_MAX_NOTIF_VALUE); + if (rc) { + optee_ffa_remove(ffa_dev); + return rc; + } rc = optee_enumerate_devices(PTA_CMD_GET_DEVICES); if (rc) { diff --git a/drivers/tee/optee/notif.c b/drivers/tee/optee/notif.c new file mode 100644 index 0000000000000..a28fa03dcd0e1 --- /dev/null +++ b/drivers/tee/optee/notif.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, Linaro Limited + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include "optee_private.h" + +struct notif_entry { + struct list_head link; + struct completion c; + u_int key; +}; + +static bool have_key(struct optee *optee, u_int key) +{ + struct notif_entry *entry; + + list_for_each_entry(entry, &optee->notif.db, link) + if (entry->key == key) + return true; + + return false; +} + +int optee_notif_wait(struct optee *optee, u_int key) +{ + unsigned long flags; + struct notif_entry *entry; + int rc = 0; + + if (key > optee->notif.max_key) + return -EINVAL; + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + init_completion(&entry->c); + entry->key = key; + + spin_lock_irqsave(&optee->notif.lock, flags); + + /* + * If the bit is already set it means that the key has already + * been posted and we must not wait. + */ + if (test_bit(key, optee->notif.bitmap)) { + clear_bit(key, optee->notif.bitmap); + goto out; + } + + /* + * Check if someone is already waiting for this key. If there is + * it's a programming error. + */ + if (have_key(optee, key)) { + rc = -EBUSY; + goto out; + } + + list_add_tail(&entry->link, &optee->notif.db); + + /* + * Unlock temporarily and wait for completion. + */ + spin_unlock_irqrestore(&optee->notif.lock, flags); + wait_for_completion(&entry->c); + spin_lock_irqsave(&optee->notif.lock, flags); + + list_del(&entry->link); +out: + spin_unlock_irqrestore(&optee->notif.lock, flags); + + kfree(entry); + + return rc; +} + +int optee_notif_send(struct optee *optee, u_int key) +{ + unsigned long flags; + struct notif_entry *entry; + + if (key > optee->notif.max_key) + return -EINVAL; + + spin_lock_irqsave(&optee->notif.lock, flags); + + list_for_each_entry(entry, &optee->notif.db, link) + if (entry->key == key) { + complete(&entry->c); + goto out; + } + + /* Only set the bit in case there where nobody waiting */ + set_bit(key, optee->notif.bitmap); +out: + spin_unlock_irqrestore(&optee->notif.lock, flags); + + return 0; +} + +int optee_notif_init(struct optee *optee, u_int max_key) +{ + spin_lock_init(&optee->notif.lock); + INIT_LIST_HEAD(&optee->notif.db); + optee->notif.bitmap = bitmap_zalloc(max_key, GFP_KERNEL); + if (!optee->notif.bitmap) + return -ENOMEM; + + optee->notif.max_key = max_key; + + return 0; +} + +void optee_notif_uninit(struct optee *optee) +{ + kfree(optee->notif.bitmap); +} diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 6660e05298db8..68fd28f8c6e95 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -28,6 +28,13 @@ #define TEEC_ORIGIN_COMMS 0x00000002 +/* + * This value should be larger than the number threads in secure world to + * meet the need from secure world. The number of threads in secure world + * are usually not even close to 255 so we should be safe for now. + */ +#define OPTEE_DEFAULT_MAX_NOTIF_VALUE 255 + typedef void (optee_invoke_fn)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, @@ -44,10 +51,12 @@ struct optee_call_queue { struct list_head waiters; }; -struct optee_wait_queue { - /* Serializes access to this struct */ - struct mutex mu; +struct optee_notif { + u_int max_key; + /* Serializes access to the elements below in this struct */ + spinlock_t lock; struct list_head db; + u_long *bitmap; }; /** @@ -129,8 +138,7 @@ struct optee_ops { * @smc: specific to SMC ABI * @ffa: specific to FF-A ABI * @call_queue: queue of threads waiting to call @invoke_fn - * @wait_queue: queue of threads from secure world waiting for a - * secure world sync object + * @notif: notification synchronization struct * @supp: supplicant synchronization struct for RPC to supplicant * @pool: shared memory pool * @rpc_arg_count: If > 0 number of RPC parameters to make room for @@ -147,7 +155,7 @@ struct optee { struct optee_ffa ffa; }; struct optee_call_queue call_queue; - struct optee_wait_queue wait_queue; + struct optee_notif notif; struct optee_supp supp; struct tee_shm_pool *pool; unsigned int rpc_arg_count; @@ -185,8 +193,10 @@ struct optee_call_ctx { size_t num_entries; }; -void optee_wait_queue_init(struct optee_wait_queue *wq); -void optee_wait_queue_exit(struct optee_wait_queue *wq); +int optee_notif_init(struct optee *optee, u_int max_key); +void optee_notif_uninit(struct optee *optee); +int optee_notif_wait(struct optee *optee, u_int key); +int optee_notif_send(struct optee *optee, u_int key); u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, struct tee_param *param); diff --git a/drivers/tee/optee/optee_rpc_cmd.h b/drivers/tee/optee/optee_rpc_cmd.h index b8275140cef8e..f3f06e0994a75 100644 --- a/drivers/tee/optee/optee_rpc_cmd.h +++ b/drivers/tee/optee/optee_rpc_cmd.h @@ -28,24 +28,27 @@ #define OPTEE_RPC_CMD_GET_TIME 3 /* - * Wait queue primitive, helper for secure world to implement a wait queue. + * Notification from/to secure world. * - * If secure world needs to wait for a secure world mutex it issues a sleep - * request instead of spinning in secure world. Conversely is a wakeup - * request issued when a secure world mutex with a thread waiting thread is - * unlocked. + * If secure world needs to wait for something, for instance a mutex, it + * does a notification wait request instead of spinning in secure world. + * Conversely can a synchronous notification can be sent when a secure + * world mutex with a thread waiting thread is unlocked. * - * Waiting on a key - * [in] value[0].a OPTEE_RPC_WAIT_QUEUE_SLEEP - * [in] value[0].b Wait key + * This interface can also be used to wait for a asynchronous notification + * which instead is sent via a non-secure interrupt. * - * Waking up a key - * [in] value[0].a OPTEE_RPC_WAIT_QUEUE_WAKEUP - * [in] value[0].b Wakeup key + * Waiting on notification + * [in] value[0].a OPTEE_RPC_NOTIFICATION_WAIT + * [in] value[0].b notification value + * + * Sending a synchronous notification + * [in] value[0].a OPTEE_RPC_NOTIFICATION_SEND + * [in] value[0].b notification value */ -#define OPTEE_RPC_CMD_WAIT_QUEUE 4 -#define OPTEE_RPC_WAIT_QUEUE_SLEEP 0 -#define OPTEE_RPC_WAIT_QUEUE_WAKEUP 1 +#define OPTEE_RPC_CMD_NOTIFICATION 4 +#define OPTEE_RPC_NOTIFICATION_WAIT 0 +#define OPTEE_RPC_NOTIFICATION_SEND 1 /* * Suspend execution diff --git a/drivers/tee/optee/rpc.c b/drivers/tee/optee/rpc.c index cd642e340eaf5..e69bc6380683a 100644 --- a/drivers/tee/optee/rpc.c +++ b/drivers/tee/optee/rpc.c @@ -12,23 +12,6 @@ #include "optee_private.h" #include "optee_rpc_cmd.h" -struct wq_entry { - struct list_head link; - struct completion c; - u32 key; -}; - -void optee_wait_queue_init(struct optee_wait_queue *priv) -{ - mutex_init(&priv->mu); - INIT_LIST_HEAD(&priv->db); -} - -void optee_wait_queue_exit(struct optee_wait_queue *priv) -{ - mutex_destroy(&priv->mu); -} - static void handle_rpc_func_cmd_get_time(struct optee_msg_arg *arg) { struct timespec64 ts; @@ -144,48 +127,6 @@ static void handle_rpc_func_cmd_i2c_transfer(struct tee_context *ctx, } #endif -static struct wq_entry *wq_entry_get(struct optee_wait_queue *wq, u32 key) -{ - struct wq_entry *w; - - mutex_lock(&wq->mu); - - list_for_each_entry(w, &wq->db, link) - if (w->key == key) - goto out; - - w = kmalloc(sizeof(*w), GFP_KERNEL); - if (w) { - init_completion(&w->c); - w->key = key; - list_add_tail(&w->link, &wq->db); - } -out: - mutex_unlock(&wq->mu); - return w; -} - -static void wq_sleep(struct optee_wait_queue *wq, u32 key) -{ - struct wq_entry *w = wq_entry_get(wq, key); - - if (w) { - wait_for_completion(&w->c); - mutex_lock(&wq->mu); - list_del(&w->link); - mutex_unlock(&wq->mu); - kfree(w); - } -} - -static void wq_wakeup(struct optee_wait_queue *wq, u32 key) -{ - struct wq_entry *w = wq_entry_get(wq, key); - - if (w) - complete(&w->c); -} - static void handle_rpc_func_cmd_wq(struct optee *optee, struct optee_msg_arg *arg) { @@ -197,11 +138,13 @@ static void handle_rpc_func_cmd_wq(struct optee *optee, goto bad; switch (arg->params[0].u.value.a) { - case OPTEE_RPC_WAIT_QUEUE_SLEEP: - wq_sleep(&optee->wait_queue, arg->params[0].u.value.b); + case OPTEE_RPC_NOTIFICATION_WAIT: + if (optee_notif_wait(optee, arg->params[0].u.value.b)) + goto bad; break; - case OPTEE_RPC_WAIT_QUEUE_WAKEUP: - wq_wakeup(&optee->wait_queue, arg->params[0].u.value.b); + case OPTEE_RPC_NOTIFICATION_SEND: + if (optee_notif_send(optee, arg->params[0].u.value.b)) + goto bad; break; default: goto bad; @@ -319,7 +262,7 @@ void optee_rpc_cmd(struct tee_context *ctx, struct optee *optee, case OPTEE_RPC_CMD_GET_TIME: handle_rpc_func_cmd_get_time(arg); break; - case OPTEE_RPC_CMD_WAIT_QUEUE: + case OPTEE_RPC_CMD_NOTIFICATION: handle_rpc_func_cmd_wq(optee, arg); break; case OPTEE_RPC_CMD_SUSPEND: diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 6196d7c3888f5..00a7ff00a7c02 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -1288,11 +1288,17 @@ static int optee_probe(struct platform_device *pdev) mutex_init(&optee->call_queue.mutex); INIT_LIST_HEAD(&optee->call_queue.waiters); - optee_wait_queue_init(&optee->wait_queue); optee_supp_init(&optee->supp); optee->smc.memremaped_shm = memremaped_shm; optee->pool = pool; + platform_set_drvdata(pdev, optee); + rc = optee_notif_init(optee, OPTEE_DEFAULT_MAX_NOTIF_VALUE); + if (rc) { + optee_remove(pdev); + return rc; + } + /* * Ensure that there are no pre-existing shm objects before enabling * the shm cache so that there's no chance of receiving an invalid @@ -1307,8 +1313,6 @@ static int optee_probe(struct platform_device *pdev) if (optee->smc.sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM) pr_info("dynamic shared memory is enabled\n"); - platform_set_drvdata(pdev, optee); - rc = optee_enumerate_devices(PTA_CMD_GET_DEVICES); if (rc) { optee_smc_remove(pdev); -- GitLab From 6749e69c4dadd352bdfdb306513aa48cc15fbdd6 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Tue, 15 Jun 2021 22:23:54 +0200 Subject: [PATCH 075/965] optee: add asynchronous notifications Adds support for asynchronous notifications from secure world to normal world. This allows a design with a top half and bottom half type of driver where the top half runs in secure interrupt context and a notifications tells normal world to schedule a yielding call to do the bottom half processing. The protocol is defined in optee_msg.h optee_rpc_cmd.h and optee_smc.h. A notification consists of a 32-bit value which normal world can retrieve using a fastcall into secure world. The value OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF (0) has a special meaning. When this value is sent it means that normal world is supposed to make a yielding call OPTEE_MSG_CMD_DO_BOTTOM_HALF. Notification capability is negotiated while the driver is initialized. If both sides supports these notifications then they are enabled. An interrupt is used to notify the driver that there are asynchronous notifications pending. The maximum needed notification value is communicated at this stage. This allows scaling up when needed. Reviewed-by: Sumit Garg Acked-by: Ard Biesheuvel Signed-off-by: Jens Wiklander --- drivers/tee/optee/optee_msg.h | 9 ++ drivers/tee/optee/optee_private.h | 2 + drivers/tee/optee/optee_smc.h | 75 +++++++++- drivers/tee/optee/smc_abi.c | 239 +++++++++++++++++++++++++----- 4 files changed, 289 insertions(+), 36 deletions(-) diff --git a/drivers/tee/optee/optee_msg.h b/drivers/tee/optee/optee_msg.h index 2422e185d4000..70e9cc2ee96b0 100644 --- a/drivers/tee/optee/optee_msg.h +++ b/drivers/tee/optee/optee_msg.h @@ -318,6 +318,13 @@ struct optee_msg_arg { * [in] param[0].u.rmem.shm_ref holds shared memory reference * [in] param[0].u.rmem.offs 0 * [in] param[0].u.rmem.size 0 + * + * OPTEE_MSG_CMD_DO_BOTTOM_HALF does the scheduled bottom half processing + * of a driver. + * + * OPTEE_MSG_CMD_STOP_ASYNC_NOTIF informs secure world that from now is + * normal world unable to process asynchronous notifications. Typically + * used when the driver is shut down. */ #define OPTEE_MSG_CMD_OPEN_SESSION 0 #define OPTEE_MSG_CMD_INVOKE_COMMAND 1 @@ -325,6 +332,8 @@ struct optee_msg_arg { #define OPTEE_MSG_CMD_CANCEL 3 #define OPTEE_MSG_CMD_REGISTER_SHM 4 #define OPTEE_MSG_CMD_UNREGISTER_SHM 5 +#define OPTEE_MSG_CMD_DO_BOTTOM_HALF 6 +#define OPTEE_MSG_CMD_STOP_ASYNC_NOTIF 7 #define OPTEE_MSG_FUNCID_CALL_WITH_ARG 0x0004 #endif /* _OPTEE_MSG_H */ diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 68fd28f8c6e95..46f74ab07c7ed 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -53,6 +53,7 @@ struct optee_call_queue { struct optee_notif { u_int max_key; + struct tee_context *ctx; /* Serializes access to the elements below in this struct */ spinlock_t lock; struct list_head db; @@ -88,6 +89,7 @@ struct optee_smc { optee_invoke_fn *invoke_fn; void *memremaped_shm; u32 sec_caps; + unsigned int notif_irq; }; /** diff --git a/drivers/tee/optee/optee_smc.h b/drivers/tee/optee/optee_smc.h index 80eb763a8a80b..d44a6ae994f85 100644 --- a/drivers/tee/optee/optee_smc.h +++ b/drivers/tee/optee/optee_smc.h @@ -107,6 +107,12 @@ struct optee_smc_call_get_os_revision_result { /* * Call with struct optee_msg_arg as argument * + * When calling this function normal world has a few responsibilities: + * 1. It must be able to handle eventual RPCs + * 2. Non-secure interrupts should not be masked + * 3. If asynchronous notifications has been negotiated successfully, then + * asynchronous notifications should be unmasked during this call. + * * Call register usage: * a0 SMC Function ID, OPTEE_SMC*CALL_WITH_ARG * a1 Upper 32 bits of a 64-bit physical pointer to a struct optee_msg_arg @@ -195,7 +201,8 @@ struct optee_smc_get_shm_config_result { * Normal return register usage: * a0 OPTEE_SMC_RETURN_OK * a1 bitfield of secure world capabilities OPTEE_SMC_SEC_CAP_* - * a2-7 Preserved + * a2 The maximum secure world notification number + * a3-7 Preserved * * Error return register usage: * a0 OPTEE_SMC_RETURN_ENOTAVAIL, can't use the capabilities from normal world @@ -218,6 +225,8 @@ struct optee_smc_get_shm_config_result { #define OPTEE_SMC_SEC_CAP_VIRTUALIZATION BIT(3) /* Secure world supports Shared Memory with a NULL reference */ #define OPTEE_SMC_SEC_CAP_MEMREF_NULL BIT(4) +/* Secure world supports asynchronous notification of normal world */ +#define OPTEE_SMC_SEC_CAP_ASYNC_NOTIF BIT(5) #define OPTEE_SMC_FUNCID_EXCHANGE_CAPABILITIES 9 #define OPTEE_SMC_EXCHANGE_CAPABILITIES \ @@ -226,8 +235,8 @@ struct optee_smc_get_shm_config_result { struct optee_smc_exchange_capabilities_result { unsigned long status; unsigned long capabilities; + unsigned long max_notif_value; unsigned long reserved0; - unsigned long reserved1; }; /* @@ -319,6 +328,68 @@ struct optee_smc_disable_shm_cache_result { #define OPTEE_SMC_GET_THREAD_COUNT \ OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_GET_THREAD_COUNT) +/* + * Inform OP-TEE that normal world is able to receive asynchronous + * notifications. + * + * Call requests usage: + * a0 SMC Function ID, OPTEE_SMC_ENABLE_ASYNC_NOTIF + * a1-6 Not used + * a7 Hypervisor Client ID register + * + * Normal return register usage: + * a0 OPTEE_SMC_RETURN_OK + * a1-7 Preserved + * + * Not supported return register usage: + * a0 OPTEE_SMC_RETURN_ENOTAVAIL + * a1-7 Preserved + */ +#define OPTEE_SMC_FUNCID_ENABLE_ASYNC_NOTIF 16 +#define OPTEE_SMC_ENABLE_ASYNC_NOTIF \ + OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_ENABLE_ASYNC_NOTIF) + +/* + * Retrieve a value of notifications pending since the last call of this + * function. + * + * OP-TEE keeps a record of all posted values. When an interrupt is + * received which indicates that there are posted values this function + * should be called until all pended values have been retrieved. When a + * value is retrieved, it's cleared from the record in secure world. + * + * Call requests usage: + * a0 SMC Function ID, OPTEE_SMC_GET_ASYNC_NOTIF_VALUE + * a1-6 Not used + * a7 Hypervisor Client ID register + * + * Normal return register usage: + * a0 OPTEE_SMC_RETURN_OK + * a1 value + * a2 Bit[0]: OPTEE_SMC_ASYNC_NOTIF_VALUE_VALID if the value in a1 is + * valid, else 0 if no values where pending + * a2 Bit[1]: OPTEE_SMC_ASYNC_NOTIF_VALUE_PENDING if another value is + * pending, else 0. + * Bit[31:2]: MBZ + * a3-7 Preserved + * + * Not supported return register usage: + * a0 OPTEE_SMC_RETURN_ENOTAVAIL + * a1-7 Preserved + */ +#define OPTEE_SMC_ASYNC_NOTIF_VALUE_VALID BIT(0) +#define OPTEE_SMC_ASYNC_NOTIF_VALUE_PENDING BIT(1) + +/* + * Notification that OP-TEE expects a yielding call to do some bottom half + * work in a driver. + */ +#define OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF 0 + +#define OPTEE_SMC_FUNCID_GET_ASYNC_NOTIF_VALUE 17 +#define OPTEE_SMC_GET_ASYNC_NOTIF_VALUE \ + OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_GET_ASYNC_NOTIF_VALUE) + /* * Resume from RPC (for example after processing a foreign interrupt) * diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 00a7ff00a7c02..92759d70bfcef 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -8,13 +8,16 @@ #include #include +#include #include -#include +#include #include #include #include +#include #include #include +#include #include #include #include @@ -34,7 +37,8 @@ * 2. Low level support functions to register shared memory in secure world * 3. Dynamic shared memory pool based on alloc_pages() * 4. Do a normal scheduled call into secure world - * 5. Driver initialization. + * 5. Asynchronous notification + * 6. Driver initialization. */ #define OPTEE_SHM_NUM_PRIV_PAGES CONFIG_OPTEE_SHM_NUM_PRIV_PAGES @@ -875,10 +879,137 @@ static int optee_smc_do_call_with_arg(struct tee_context *ctx, return rc; } +static int simple_call_with_arg(struct tee_context *ctx, u32 cmd) +{ + struct optee_msg_arg *msg_arg; + struct tee_shm *shm; + + shm = optee_get_msg_arg(ctx, 0, &msg_arg); + if (IS_ERR(shm)) + return PTR_ERR(shm); + + msg_arg->cmd = cmd; + optee_smc_do_call_with_arg(ctx, shm); + + tee_shm_free(shm); + return 0; +} + +static int optee_smc_do_bottom_half(struct tee_context *ctx) +{ + return simple_call_with_arg(ctx, OPTEE_MSG_CMD_DO_BOTTOM_HALF); +} + +static int optee_smc_stop_async_notif(struct tee_context *ctx) +{ + return simple_call_with_arg(ctx, OPTEE_MSG_CMD_STOP_ASYNC_NOTIF); +} + /* - * 5. Driver initialization + * 5. Asynchronous notification + */ + +static u32 get_async_notif_value(optee_invoke_fn *invoke_fn, bool *value_valid, + bool *value_pending) +{ + struct arm_smccc_res res; + + invoke_fn(OPTEE_SMC_GET_ASYNC_NOTIF_VALUE, 0, 0, 0, 0, 0, 0, 0, &res); + + if (res.a0) + return 0; + *value_valid = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_VALID); + *value_pending = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_PENDING); + return res.a1; +} + +static irqreturn_t notif_irq_handler(int irq, void *dev_id) +{ + struct optee *optee = dev_id; + bool do_bottom_half = false; + bool value_valid; + bool value_pending; + u32 value; + + do { + value = get_async_notif_value(optee->smc.invoke_fn, + &value_valid, &value_pending); + if (!value_valid) + break; + + if (value == OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF) + do_bottom_half = true; + else + optee_notif_send(optee, value); + } while (value_pending); + + if (do_bottom_half) + return IRQ_WAKE_THREAD; + return IRQ_HANDLED; +} + +static irqreturn_t notif_irq_thread_fn(int irq, void *dev_id) +{ + struct optee *optee = dev_id; + + optee_smc_do_bottom_half(optee->notif.ctx); + + return IRQ_HANDLED; +} + +static int optee_smc_notif_init_irq(struct optee *optee, u_int irq) +{ + struct tee_context *ctx; + int rc; + + ctx = teedev_open(optee->teedev); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + optee->notif.ctx = ctx; + rc = request_threaded_irq(irq, notif_irq_handler, + notif_irq_thread_fn, + 0, "optee_notification", optee); + if (rc) + goto err_close_ctx; + + optee->smc.notif_irq = irq; + + return 0; + +err_close_ctx: + teedev_close_context(optee->notif.ctx); + optee->notif.ctx = NULL; + + return rc; +} + +static void optee_smc_notif_uninit_irq(struct optee *optee) +{ + if (optee->notif.ctx) { + optee_smc_stop_async_notif(optee->notif.ctx); + if (optee->smc.notif_irq) { + free_irq(optee->smc.notif_irq, optee); + irq_dispose_mapping(optee->smc.notif_irq); + } + + /* + * The thread normally working with optee->notif.ctx was + * stopped with free_irq() above. + * + * Note we're not using teedev_close_context() or + * tee_client_close_context() since we have already called + * tee_device_put() while initializing to avoid a circular + * reference counting. + */ + teedev_close_context(optee->notif.ctx); + } +} + +/* + * 6. Driver initialization * - * During driver inititialization is secure world probed to find out which + * During driver initialization is secure world probed to find out which * features it supports so the driver can be initialized with a matching * configuration. This involves for instance support for dynamic shared * memory instead of a static memory carvout. @@ -950,6 +1081,17 @@ static const struct optee_ops optee_ops = { .from_msg_param = optee_from_msg_param, }; +static int enable_async_notif(optee_invoke_fn *invoke_fn) +{ + struct arm_smccc_res res; + + invoke_fn(OPTEE_SMC_ENABLE_ASYNC_NOTIF, 0, 0, 0, 0, 0, 0, 0, &res); + + if (res.a0) + return -EINVAL; + return 0; +} + static bool optee_msg_api_uid_is_optee_api(optee_invoke_fn *invoke_fn) { struct arm_smccc_res res; @@ -999,7 +1141,7 @@ static bool optee_msg_api_revision_is_compatible(optee_invoke_fn *invoke_fn) } static bool optee_msg_exchange_capabilities(optee_invoke_fn *invoke_fn, - u32 *sec_caps) + u32 *sec_caps, u32 *max_notif_value) { union { struct arm_smccc_res smccc; @@ -1022,6 +1164,11 @@ static bool optee_msg_exchange_capabilities(optee_invoke_fn *invoke_fn, return false; *sec_caps = res.result.capabilities; + if (*sec_caps & OPTEE_SMC_SEC_CAP_ASYNC_NOTIF) + *max_notif_value = res.result.max_notif_value; + else + *max_notif_value = OPTEE_DEFAULT_MAX_NOTIF_VALUE; + return true; } @@ -1186,6 +1333,8 @@ static int optee_smc_remove(struct platform_device *pdev) */ optee_disable_shm_cache(optee); + optee_smc_notif_uninit_irq(optee); + optee_remove_common(optee); if (optee->smc.memremaped_shm) @@ -1215,6 +1364,7 @@ static int optee_probe(struct platform_device *pdev) struct optee *optee = NULL; void *memremaped_shm = NULL; struct tee_device *teedev; + u32 max_notif_value; u32 sec_caps; int rc; @@ -1234,7 +1384,8 @@ static int optee_probe(struct platform_device *pdev) return -EINVAL; } - if (!optee_msg_exchange_capabilities(invoke_fn, &sec_caps)) { + if (!optee_msg_exchange_capabilities(invoke_fn, &sec_caps, + &max_notif_value)) { pr_warn("capabilities mismatch\n"); return -EINVAL; } @@ -1257,7 +1408,7 @@ static int optee_probe(struct platform_device *pdev) optee = kzalloc(sizeof(*optee), GFP_KERNEL); if (!optee) { rc = -ENOMEM; - goto err; + goto err_free_pool; } optee->ops = &optee_ops; @@ -1267,24 +1418,24 @@ static int optee_probe(struct platform_device *pdev) teedev = tee_device_alloc(&optee_clnt_desc, NULL, pool, optee); if (IS_ERR(teedev)) { rc = PTR_ERR(teedev); - goto err; + goto err_free_optee; } optee->teedev = teedev; teedev = tee_device_alloc(&optee_supp_desc, NULL, pool, optee); if (IS_ERR(teedev)) { rc = PTR_ERR(teedev); - goto err; + goto err_unreg_teedev; } optee->supp_teedev = teedev; rc = tee_device_register(optee->teedev); if (rc) - goto err; + goto err_unreg_supp_teedev; rc = tee_device_register(optee->supp_teedev); if (rc) - goto err; + goto err_unreg_supp_teedev; mutex_init(&optee->call_queue.mutex); INIT_LIST_HEAD(&optee->call_queue.waiters); @@ -1293,10 +1444,27 @@ static int optee_probe(struct platform_device *pdev) optee->pool = pool; platform_set_drvdata(pdev, optee); - rc = optee_notif_init(optee, OPTEE_DEFAULT_MAX_NOTIF_VALUE); - if (rc) { - optee_remove(pdev); - return rc; + rc = optee_notif_init(optee, max_notif_value); + if (rc) + goto err_supp_uninit; + + if (sec_caps & OPTEE_SMC_SEC_CAP_ASYNC_NOTIF) { + unsigned int irq; + + rc = platform_get_irq(pdev, 0); + if (rc < 0) { + pr_err("platform_get_irq: ret %d\n", rc); + goto err_notif_uninit; + } + irq = rc; + + rc = optee_smc_notif_init_irq(optee, irq); + if (rc) { + irq_dispose_mapping(irq); + goto err_notif_uninit; + } + enable_async_notif(optee->smc.invoke_fn); + pr_info("Asynchronous notifications enabled\n"); } /* @@ -1314,28 +1482,31 @@ static int optee_probe(struct platform_device *pdev) pr_info("dynamic shared memory is enabled\n"); rc = optee_enumerate_devices(PTA_CMD_GET_DEVICES); - if (rc) { - optee_smc_remove(pdev); - return rc; - } + if (rc) + goto err_disable_shm_cache; pr_info("initialized driver\n"); return 0; -err: - if (optee) { - /* - * tee_device_unregister() is safe to call even if the - * devices hasn't been registered with - * tee_device_register() yet. - */ - tee_device_unregister(optee->supp_teedev); - tee_device_unregister(optee->teedev); - kfree(optee); - } - if (pool) - tee_shm_pool_free(pool); - if (memremaped_shm) - memunmap(memremaped_shm); + +err_disable_shm_cache: + optee_disable_shm_cache(optee); + optee_smc_notif_uninit_irq(optee); + optee_unregister_devices(); +err_notif_uninit: + optee_notif_uninit(optee); +err_supp_uninit: + optee_supp_uninit(&optee->supp); + mutex_destroy(&optee->call_queue.mutex); +err_unreg_supp_teedev: + tee_device_unregister(optee->supp_teedev); +err_unreg_teedev: + tee_device_unregister(optee->teedev); +err_free_optee: + kfree(optee); +err_free_pool: + tee_shm_pool_free(pool); + if (optee->smc.memremaped_shm) + memunmap(optee->smc.memremaped_shm); return rc; } -- GitLab From 379e4de9e140850cf699dd390f21ea4b923c955d Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Fri, 29 Oct 2021 10:49:56 -0700 Subject: [PATCH 076/965] x86/sgx: Fix minor documentation issues The SGX documentation has a few repeated or one-off issues: * Remove capitalization from regular words in the middle of a sentence. * Remove punctuation found in the middle of a sentence. * Fix name of SGX daemon to consistently be ksgxd. * Fix typo of SGX instruction: ENIT -> EINIT [ dhansen: tweaked subject and changelog ] Signed-off-by: Reinette Chatre Signed-off-by: Dave Hansen Reviewed-by: Jarkko Sakkinen Link: https://lkml.kernel.org/r/ab99a87368eef69e3fb96f073368becff3eff874.1635529506.git.reinette.chatre@intel.com --- Documentation/x86/sgx.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/x86/sgx.rst b/Documentation/x86/sgx.rst index a608f667fb953..265568a9292cb 100644 --- a/Documentation/x86/sgx.rst +++ b/Documentation/x86/sgx.rst @@ -10,7 +10,7 @@ Overview Software Guard eXtensions (SGX) hardware enables for user space applications to set aside private memory regions of code and data: -* Privileged (ring-0) ENCLS functions orchestrate the construction of the. +* Privileged (ring-0) ENCLS functions orchestrate the construction of the regions. * Unprivileged (ring-3) ENCLU functions allow an application to enter and execute inside the regions. @@ -91,7 +91,7 @@ In addition to the traditional compiler and linker build process, SGX has a separate enclave “build” process. Enclaves must be built before they can be executed (entered). The first step in building an enclave is opening the **/dev/sgx_enclave** device. Since enclave memory is protected from direct -access, special privileged instructions are Then used to copy data into enclave +access, special privileged instructions are then used to copy data into enclave pages and establish enclave page permissions. .. kernel-doc:: arch/x86/kernel/cpu/sgx/ioctl.c @@ -126,13 +126,13 @@ the need to juggle signal handlers. ksgxd ===== -SGX support includes a kernel thread called *ksgxwapd*. +SGX support includes a kernel thread called *ksgxd*. EPC sanitization ---------------- ksgxd is started when SGX initializes. Enclave memory is typically ready -For use when the processor powers on or resets. However, if SGX has been in +for use when the processor powers on or resets. However, if SGX has been in use since the reset, enclave pages may be in an inconsistent state. This might occur after a crash and kexec() cycle, for instance. At boot, ksgxd reinitializes all enclave pages so that they can be allocated and re-used. @@ -147,7 +147,7 @@ Page reclaimer Similar to the core kswapd, ksgxd, is responsible for managing the overcommitment of enclave memory. If the system runs out of enclave memory, -*ksgxwapd* “swaps” enclave memory to normal memory. +*ksgxd* “swaps” enclave memory to normal memory. Launch Control ============== @@ -156,7 +156,7 @@ SGX provides a launch control mechanism. After all enclave pages have been copied, kernel executes EINIT function, which initializes the enclave. Only after this the CPU can execute inside the enclave. -ENIT function takes an RSA-3072 signature of the enclave measurement. The function +EINIT function takes an RSA-3072 signature of the enclave measurement. The function checks that the measurement is correct and signature is signed with the key hashed to the four **IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}** MSRs representing the SHA256 of a public key. @@ -184,7 +184,7 @@ CPUs starting from Icelake use Total Memory Encryption (TME) in the place of MEE. TME-based SGX implementations do not have an integrity Merkle tree, which means integrity and replay-attacks are not mitigated. B, it includes additional changes to prevent cipher text from being returned and SW memory -aliases from being Created. +aliases from being created. DMA to enclave memory is blocked by range registers on both MEE and TME systems (SDM section 41.10). -- GitLab From 7f1a9f47df618f19c943e5673b3b42b849de7e8d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:49:59 +0100 Subject: [PATCH 077/965] arm64: dts: mediatek: mt8192: fix i2c node names Fix the i2c node names to be compliant to the YAML schema. The I2C node name should match the following pattern: "^i2c@[0-9a-f]+$". Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110194959.20611-4-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017aed..53d790c335f99 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -479,7 +479,7 @@ #clock-cells = <1>; }; - i2c3: i2c3@11cb0000 { + i2c3: i2c@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, <0 0x10217300 0 0x80>; @@ -498,7 +498,7 @@ #clock-cells = <1>; }; - i2c7: i2c7@11d00000 { + i2c7: i2c@11d00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d00000 0 0x1000>, <0 0x10217600 0 0x180>; @@ -511,7 +511,7 @@ status = "disabled"; }; - i2c8: i2c8@11d01000 { + i2c8: i2c@11d01000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d01000 0 0x1000>, <0 0x10217780 0 0x180>; @@ -524,7 +524,7 @@ status = "disabled"; }; - i2c9: i2c9@11d02000 { + i2c9: i2c@11d02000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d02000 0 0x1000>, <0 0x10217900 0 0x180>; @@ -543,7 +543,7 @@ #clock-cells = <1>; }; - i2c1: i2c1@11d20000 { + i2c1: i2c@11d20000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d20000 0 0x1000>, <0 0x10217100 0 0x80>; @@ -556,7 +556,7 @@ status = "disabled"; }; - i2c2: i2c2@11d21000 { + i2c2: i2c@11d21000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d21000 0 0x1000>, <0 0x10217180 0 0x180>; @@ -569,7 +569,7 @@ status = "disabled"; }; - i2c4: i2c4@11d22000 { + i2c4: i2c@11d22000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d22000 0 0x1000>, <0 0x10217380 0 0x180>; @@ -588,7 +588,7 @@ #clock-cells = <1>; }; - i2c5: i2c5@11e00000 { + i2c5: i2c@11e00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11e00000 0 0x1000>, <0 0x10217500 0 0x80>; @@ -607,7 +607,7 @@ #clock-cells = <1>; }; - i2c0: i2c0@11f00000 { + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, <0 0x10217080 0 0x80>; @@ -620,7 +620,7 @@ status = "disabled"; }; - i2c6: i2c6@11f01000 { + i2c6: i2c@11f01000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f01000 0 0x1000>, <0 0x10217580 0 0x80>; -- GitLab From 9cf6a26ae352a6a150662c0c4ddff87664cc6e3c Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:35:20 +0100 Subject: [PATCH 078/965] arm64: dts: mediatek: mt8516: remove 2 invalid i2c clocks The two clocks "main-source" and "main-sel" are not present in the driver and not defined in the binding documentation. Remove them as they are not used and not described in the documentation. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110193520.488-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 27 ++++++------------------ 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index bbe5a1419effc..d1b67c82d7617 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -345,14 +345,9 @@ reg = <0 0x11009000 0 0x90>, <0 0x11000180 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C0_SEL>, - <&topckgen CLK_TOP_I2C0>, + clocks = <&topckgen CLK_TOP_I2C0>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -364,14 +359,9 @@ reg = <0 0x1100a000 0 0x90>, <0 0x11000200 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C1_SEL>, - <&topckgen CLK_TOP_I2C1>, + clocks = <&topckgen CLK_TOP_I2C1>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -383,14 +373,9 @@ reg = <0 0x1100b000 0 0x90>, <0 0x11000280 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C2_SEL>, - <&topckgen CLK_TOP_I2C2>, + clocks = <&topckgen CLK_TOP_I2C2>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- GitLab From ff9ea5c62279790eea8c0cd7295836db06da174d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:26:31 +0100 Subject: [PATCH 079/965] arm64: dts: mediatek: mt8183-evb: Add node for thermistor Add node to be able to read the temperature for the thermistor connected to AUXIN0. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110192631.4182485-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 7bc0a6a7fadf9..f3fd3cca23e9c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -36,6 +36,14 @@ no-map; }; }; + + ntc@0 { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <390000>; + pulldown-ohm = <0>; + io-channels = <&auxadc 0>; + }; }; &auxadc { -- GitLab From 2706707b225d29aae6f79a21eff277b53b7b05e9 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:12 +0800 Subject: [PATCH 080/965] arm64: dts: mt8183: jacuzzi: remove unused ddc-i2c-bus EDID is read from bridge, so the ddc-i2c-bus is unused. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index d8826c82bcda2..8f7bf33f607da 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -9,7 +9,6 @@ panel: panel { compatible = "auo,b116xw03"; power-supply = <&pp3300_panel>; - ddc-i2c-bus = <&i2c4>; backlight = <&backlight_lcd0>; port { -- GitLab From 52e84f23345904e91ea35199033fe8b0772f2f39 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:13 +0800 Subject: [PATCH 081/965] arm64: dts: mt8183: Add kukui-jacuzzi-cozmo board Cozmo is known as Acer Chromebook 314 (CB314-2H/CB314-2HT) Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8183-kukui-jacuzzi-cozmo.dts | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 4f68ebed2e318..045927402269a 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts new file mode 100644 index 0000000000000..072133fb0f016 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google cozmo board"; + compatible = "google,cozmo", "mediatek,mt8183"; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_COZMO"; +}; -- GitLab From 1c1f350be884fcd8280913d10f18231b5faff4da Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:14 +0800 Subject: [PATCH 082/965] arm64: dts: mt8183: Add more fennel SKUs Add fennel sku7 and fennel14 sku2, which use different audio codec than previous fennel/fennel14 boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-3-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ .../mt8183-kukui-jacuzzi-fennel-sku1.dts | 1 + .../mt8183-kukui-jacuzzi-fennel-sku6.dts | 1 + .../mt8183-kukui-jacuzzi-fennel-sku7.dts | 33 +++++++++++++++++++ .../mediatek/mt8183-kukui-jacuzzi-fennel.dtsi | 1 - .../mt8183-kukui-jacuzzi-fennel14-sku2.dts | 17 ++++++++++ .../mt8183-kukui-jacuzzi-fennel14.dts | 1 + 7 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 045927402269a..9834bd659d153 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -18,7 +18,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index ef6257c9a2d2f..dec11a4eb59e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel sku1 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 899c2e42385c2..37e6e58f63b7e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel sku6 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts new file mode 100644 index 0000000000000..0e09604004d5e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel sku7 board"; + compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi index 577519a775c05..bbe6c338f465e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -5,7 +5,6 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" -#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" &mt6358codec { mediatek,dmic-mode = <1>; /* one-wire */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts new file mode 100644 index 0000000000000..3fc5a6181d7e6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel14 sku2 board"; + compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts index e8c41f6b4b0d4..23ad0b91e9776 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel14 sku0 board"; -- GitLab From 3831b385147f9c1bc23f46ef156ffa165b8307f9 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:15 +0800 Subject: [PATCH 083/965] arm64: dts: mt8183: Add kakadu sku22 Kakadu sku22 is using mediatek,mt8183_mt6358_ts3a227_rt1015p audio codec Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-4-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8183-kukui-kakadu-sku22.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 9834bd659d153..1613259b68657 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts new file mode 100644 index 0000000000000..3a724e6f915cd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-kakadu.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +/ { + model = "MediaTek kakadu board sku22"; + compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", + "google,kakadu", "mediatek,mt8183"; +}; + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p"; +}; + -- GitLab From 7358101393123aae68878fc05835f5add649ea6b Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:16 +0800 Subject: [PATCH 084/965] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-cozmo Cozmo is known as Acer Chromebook 314 (CB314-2H/CB314-2HT) Chromebook. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-5-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0fa55497b96fd..7cf0c76cd3100 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -134,6 +134,10 @@ properties: - google,krane-sku176 - const: google,krane - const: mediatek,mt8183 + - description: Google Cozmo (Acer Chromebook 314) + items: + - const: google,cozmo + - const: mediatek,mt8183 - description: Google Damu (ASUS Chromebook Flip CM3) items: - const: google,damu -- GitLab From bf08726b34c18dc917d9155ee52ee9cba94fb9e1 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:17 +0800 Subject: [PATCH 085/965] dt-bindings: arm64: dts: mediatek: Add more SKUs for mt8183 fennel board Add sku2 and sku7 which uses different audio codec than other fennel boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-6-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 7cf0c76cd3100..99e7f8e294cd0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -147,7 +147,9 @@ properties: - enum: - google,fennel-sku0 - google,fennel-sku1 + - google,fennel-sku2 - google,fennel-sku6 + - google,fennel-sku7 - const: google,fennel - const: mediatek,mt8183 - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) -- GitLab From 861a08874fdbf625fea5ac265ff6aabbf6b68c56 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:18 +0800 Subject: [PATCH 086/965] dt-bindings: arm64: dts: mediatek: Add sku22 for mt8183 kakadu board Add sku22 which uses different audio codec than previous kakadu board. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-7-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 99e7f8e294cd0..723810cffce2e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -165,6 +165,12 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kakadu (ASUS Chromebook Detachable CM3) + items: + - const: google,kakadu-rev3-sku22 + - const: google,kakadu-rev2-sku22 + - const: google,kakadu + - const: mediatek,mt8183 - description: Google Kappa (HP Chromebook 11a) items: - const: google,kappa -- GitLab From ab0c1e34536c8077bf92ed9ec92941339acf9045 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 4 Nov 2021 14:52:54 +0100 Subject: [PATCH 087/965] arm64: dts: mediatek: mt8173: Add gce-client-reg to display od/ufo In order to use CMDQ commands on these two IPs, we need to declare the appropriate mediatek,gce-client-reg for them. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211104135254.580257-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index dee66e5f054c1..2b7d331a45883 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1212,6 +1212,7 @@ interrupts = ; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; dsi0: dsi@1401b000 { @@ -1316,6 +1317,7 @@ compatible = "mediatek,mt8173-disp-od"; reg = <0 0x14023000 0 0x1000>; clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; }; hdmi0: hdmi@14025000 { -- GitLab From 98c3384fa770da1e782c6e07e0077825ec46c23f Mon Sep 17 00:00:00 2001 From: Ben Tseng Date: Wed, 3 Nov 2021 11:30:44 +0800 Subject: [PATCH 088/965] arm64: dts: mt8183-kukui: Update Tboard sensor mapping table According to auxadc change the readback value from raw data to Vsense. Update the tboard table that temperature map to Vsense. pull-up voltage: 1800 mv pull-up resistor: 75K Vsense = pull-up voltage * Rntc / ( pull-up resistor + Rntc ) Signed-off-by: Ben Tseng Tested-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211103033044.2777-1-ben.tseng@mediatek.com Signed-off-by: Matthias Brugger --- .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 108 +++++++++--------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a1a8fc7ba0072..94c13c4591944 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -157,33 +157,33 @@ #thermal-sensor-cells = <0>; io-channels = <&auxadc 0>; io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; }; tboard_thermistor2: thermal-sensor2 { @@ -191,33 +191,33 @@ #thermal-sensor-cells = <0>; io-channels = <&auxadc 1>; io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; }; }; -- GitLab From 24f52ef0c4bfee3b18ca42bef47efa76abab56ab Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:09 +0100 Subject: [PATCH 089/965] arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters SM8250 has TX and RX macros with SoundWire Controllers to attach with codecs like WCD938x. Add these nodes for sm8250 mtp audio use case. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-2-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 157 +++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6f6129b39c9cc..c46c35a74601f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1831,6 +1831,101 @@ #sound-dai-cells = <1>; }; + rxmacro: rxmacro@3200000 { + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_active>; + compatible = "qcom,sm8250-lpass-rx-macro"; + reg = <0 0x3200000 0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire-controller@3210000 { + reg = <0 0x3210000 0 0x2000>; + compatible = "qcom,soundwire-v1.5.1"; + interrupts = ; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + txmacro: txmacro@3220000 { + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_active>; + compatible = "qcom,sm8250-lpass-tx-macro"; + reg = <0 0x3220000 0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #address-cells = <2>; + #size-cells = <2>; + #sound-dai-cells = <1>; + }; + + /* tx macro */ + swr2: soundwire-controller@3230000 { + reg = <0 0x3230000 0 0x2000>; + compatible = "qcom,soundwire-v1.5.1"; + interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core"; + + clocks = <&txmacro>; + clock-names = "iface"; + label = "TX"; + + qcom,din-ports = <5>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; + qcom,port-offset = <1>; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + aoncc: clock-controller@3380000 { compatible = "qcom,sm8250-lpass-aoncc"; reg = <0 0x03380000 0 0x40000>; @@ -1923,6 +2018,68 @@ input-enable; }; }; + + rx_swr_active: rx_swr-active-pins { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_active: tx_swr-active-pins { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx_swr-sleep-pins { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + + data1 { + pins = "gpio1"; + function = "swr_tx_data"; + drive-strength = <2>; + input-enable; + bias-bus-hold; + }; + + data2 { + pins = "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; }; gpu: gpu@3d00000 { -- GitLab From 5a263cf629a85aa831081de4b9f85926bb067c08 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:10 +0100 Subject: [PATCH 090/965] arm64: dts: qcom: sm8250-mtp: Add wcd9380 audio codec node SM8250-MTP has WCD9380 codec for headset playback and capture via rx and tx macro respectively. Add node for this device to be able to use it for sound card device. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-3-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 5ffbcdd387bad..7cf4fc97e825b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -6,6 +6,9 @@ /dts-v1/; #include +#include +#include +#include #include "sm8250.dtsi" #include "pm8150.dtsi" #include "pm8150b.dtsi" @@ -624,8 +627,72 @@ firmware-name = "qcom/sm8250/slpi.mbn"; }; +&soc { + wcd938x: codec { + compatible = "qcom,wcd9380-codec"; + #sound-dai-cells = <1>; + reset-gpios = <&tlmm 32 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-rxtx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + }; +}; + +&swr1 { + wcd_rx: wcd9380-rx@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + wcd_tx: wcd9380-tx@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <40 4>; + + wcd938x_reset_default: wcd938x_reset_default { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + output-high; + }; + }; + + wcd938x_reset_sleep: wcd938x_reset_sleep { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; }; &uart12 { -- GitLab From 6fcda0b556cce2afee8322e3e01eeb9e3993eb6a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:11 +0100 Subject: [PATCH 091/965] arm64: dts: qcom: sm8250-mtp: Add wsa8810 audio codec node SM8250-MTP has WSA8810 via wsa macro for Speaker playback use case. Add node for this device to be able to use it for sound card device. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-4-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 7cf4fc97e825b..ee8a6c36d06fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -648,6 +648,26 @@ }; }; +&swr0 { + left_spkr: wsa8810-right@0,3{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-left@0,4{ + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; +}; + &swr1 { wcd_rx: wcd9380-rx@0,4 { compatible = "sdw20217010d00"; -- GitLab From fa244dca404c8b02999348098be7f2ae62670af0 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:12 +0100 Subject: [PATCH 092/965] arm64: dts: qcom: sm8250-mtp: add sound card support This patch adds sound card support for MTP using WCD938x headset playback, capture, WSA8810 Speaker Playback and DMICs via VA macro. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-5-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 104 ++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index ee8a6c36d06fc..fb99cc2827c76 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -648,6 +648,110 @@ }; }; +&sound { + compatible = "qcom,sm8250-sndcard"; + model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_ADC3", "ADC4_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; + }; + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + cpu { + sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&vamacro 0>; + }; + }; +}; + &swr0 { left_spkr: wsa8810-right@0,3{ compatible = "sdw10217211000"; -- GitLab From 0112b06fde557d407c0d477ee7ed973e44e65c75 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 25 Oct 2021 12:22:24 +0200 Subject: [PATCH 093/965] arm64: dts: qcom: Add missing 'chassis-type's Add the "chassis-type" to msm8916-samsung-serranove and sm7225-fairphone-fp4 that were posted before the patch that added the chassis-type to existing device trees, but merged after it. Also, looks like sdm636-sony-xperia-ganges-mermaid was missing in commit eaa744b1c101 ("arm64: dts: qcom: add 'chassis-type' property") so add it there as well. Cc: Luca Weiss Cc: Arnaud Ferraris Signed-off-by: Stephan Gerhold Reviewed-by: Arnaud Ferraris Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211025102224.23746-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 1 + arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts | 1 + arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index a78f87a5bf4f4..58dfbfff4c7d4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -23,6 +23,7 @@ / { model = "Samsung Galaxy S4 Mini Value Edition"; compatible = "samsung,serranove", "qcom,msm8916"; + chassis-type = "handset"; aliases { serial0 = &blsp1_uart2; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index bba1c2bce2131..b96da53f2f1ee 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -11,6 +11,7 @@ / { model = "Sony Xperia 10 Plus"; compatible = "sony,mermaid-row", "qcom,sdm636"; + chassis-type = "handset"; /* SDM636 v1 */ qcom,msm-id = <345 0>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 8d6fd22873e0b..a6937642736e7 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -15,6 +15,7 @@ / { model = "Fairphone 4"; compatible = "fairphone,fp4", "qcom,sm7225"; + chassis-type = "handset"; /* required for bootloader to select correct board */ qcom,msm-id = <434 0x10000>, <459 0x10000>; -- GitLab From 37613aee217928dddf62d91d3db831827f860833 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Tue, 26 Oct 2021 20:22:02 +0530 Subject: [PATCH 094/965] arm64: dts: qcom: sc7280: Add venus DT node Add DT entries for the sc7280 venus encoder/decoder. Co-developed-by: Mansur Alisha Shaik Signed-off-by: Mansur Alisha Shaik Signed-off-by: Dikshita Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635259922-25378-1-git-send-email-quic_dikshita@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 365a2e04e285b..e4988ea2011c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -129,6 +129,11 @@ no-map; }; + video_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + ipa_fw_mem: memory@8b700000 { reg = <0 0x8b700000 0 0x10000>; no-map; @@ -2675,6 +2680,76 @@ }; }; + venus: video-codec@aa00000 { + compatible = "qcom,sc7280-venus"; + reg = <0 0x0aa00000 0 0xd0600>; + interrupts = ; + + clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_AXI_CLK>; + clock-names = "core", "bus", "iface", + "vcodec_core", "vcodec_bus"; + + power-domains = <&videocc MVSC_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC7280_CX>; + power-domain-names = "venus", "vcodec0", "cx"; + operating-points-v2 = <&venus_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cpu-cfg", "video-mem"; + + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x2184 0x20>; + memory-region = <&video_mem>; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + + video-firmware { + iommus = <&apps_smmu 0x21a2 0x0>; + }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-133330000 { + opp-hz = /bits/ 64 <133330000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-335000000 { + opp-hz = /bits/ 64 <335000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-424000000 { + opp-hz = /bits/ 64 <424000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-460000048 { + opp-hz = /bits/ 64 <460000048>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0xaaf0000 0 0x10000>; -- GitLab From 00128a57c0fe6ed90278cfec2adeccb83b7b49f4 Mon Sep 17 00:00:00 2001 From: Kate Doeen Date: Thu, 28 Oct 2021 12:19:57 +0200 Subject: [PATCH 095/965] arm64: dts: qcom: sdm845-oneplus-common: set venus firmware path Enable loading the Qualcomm Venus video accelerator firmware on OnePlus sdm845 devices. Signed-off-by: Kate Doeen Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211028101957.106034-1-jld3103yt@gmail.com --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 3e04aeb479d11..7f42e5315ecba 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -646,6 +646,7 @@ &venus { status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; &wifi { -- GitLab From 42dd1efffebd731e22623008058dd9c659812d1e Mon Sep 17 00:00:00 2001 From: Kate Doeen Date: Thu, 28 Oct 2021 12:20:16 +0200 Subject: [PATCH 096/965] arm64: dts: qcom: sdm845-xiaomi-beryllium: set venus firmware path Enable loading the Qualcomm Venus video accelerator firmware on Xiaomi Pocophone F1. Signed-off-by: Kate Doeen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211028102016.106063-1-jld3103yt@gmail.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 580d4cc1296f0..367389526b418 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -514,6 +514,7 @@ &venus { status = "okay"; + firmware-name = "qcom/sdm845/beryllium/venus.mbn"; }; &wcd9340{ -- GitLab From d201f67714a302b12ad3d78b982963342939629c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 7 Oct 2021 13:58:46 +0200 Subject: [PATCH 097/965] arm64: dts: qcom: ipq8074: add MDIO bus IPQ8074 uses an IPQ4019 compatible MDIO controller that is already supported in the kernel, so add the DT node in order to use it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 6c6a0f853669e..e6cc261201efe 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -230,6 +230,18 @@ }; }; + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + prng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; -- GitLab From 801cd261718e44adeb033c428390761adc03e2fc Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 29 Oct 2021 12:33:39 +0200 Subject: [PATCH 098/965] ARM: dts: qcom: update USB nodes with new platform specific compatible To match dwc3 documentation, add compatible for platform. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029103340.26828-2-david@ixit.cz --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index ff1bdb10ad198..7dec0553636e5 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -637,7 +637,7 @@ }; usb3: usb3@8af8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x8af8800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -669,7 +669,7 @@ }; usb2: usb2@60f8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x60f8800 0x100>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb69..996f4458d9fc5 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1080,7 +1080,7 @@ }; usb3_0: usb3@100f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x100f8800 0x8000>; @@ -1122,7 +1122,7 @@ }; usb3_1: usb3@110f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x110f8800 0x8000>; -- GitLab From bd9ccaec6ac998196baa11380ad4651a7df62ef0 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sat, 13 Nov 2021 13:53:58 +0800 Subject: [PATCH 099/965] soc: qcom: qmi: Fix a typo in a comment The double word `client' in a comment is repeated, thus one of them should be removed. Signed-off-by: Jason Wang Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211113055358.206533-1-wangborong@cdjrlc.com --- drivers/soc/qcom/qmi_interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 1a03eaa38c46c..c8c4c730b1353 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -96,7 +96,7 @@ static void qmi_recv_del_server(struct qmi_handle *qmi, * @node: id of the dying node * * Signals the client that all previously registered services on this node are - * now gone and then calls the bye callback to allow the client client further + * now gone and then calls the bye callback to allow the client further * cleaning up resources associated with this remote. */ static void qmi_recv_bye(struct qmi_handle *qmi, -- GitLab From 7ba9dd0d04a8af868bc0785d79bde4ac0240328f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 8 Nov 2021 21:44:40 +0800 Subject: [PATCH 100/965] soc: qcom: rpmpd: Drop unused res_name from struct rpmpd The res_name field in struct rpmpd is unused. Drop it. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211108134442.30051-2-shawn.guo@linaro.org --- drivers/soc/qcom/rpmpd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 4f69fb9b2e0e7..3e7905854eb90 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -102,7 +102,6 @@ struct rpmpd { const bool active_only; unsigned int corner; bool enabled; - const char *res_name; const int res_type; const int res_id; struct qcom_smd_rpm *rpm; -- GitLab From 2475fcfbe4e383d586c5a58711e436d83a2bdfe6 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 8 Nov 2021 21:44:41 +0800 Subject: [PATCH 101/965] dt-bindings: power: rpmpd: Add QCM2290 support Add compatible and constants for the power domains exposed by the QCM2290 RPM. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211108134442.30051-3-shawn.guo@linaro.org --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index e810480e3eb73..a6d51d51d2c77 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -24,6 +24,7 @@ properties: - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd - qcom,msm8998-rpmpd + - qcom,qcm2290-rpmpd - qcom,qcs404-rpmpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 960f7976a8076..340b0ffe5eb80 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -219,6 +219,16 @@ #define SM6115_VDD_LPI_CX 6 #define SM6115_VDD_LPI_MX 7 +/* QCM2290 Power Domains */ +#define QCM2290_VDDCX 0 +#define QCM2290_VDDCX_AO 1 +#define QCM2290_VDDCX_VFL 2 +#define QCM2290_VDDMX 3 +#define QCM2290_VDDMX_AO 4 +#define QCM2290_VDDMX_VFL 5 +#define QCM2290_VDD_LPI_CX 6 +#define QCM2290_VDD_LPI_MX 7 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 -- GitLab From 1cd3921aa95ebf4a6d1f93fb736449441c530aa1 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 8 Nov 2021 21:44:42 +0800 Subject: [PATCH 102/965] soc: qcom: rpmpd: Add QCM2290 support QCM2290 has the same RPM power domains as SM6115. Add QCM2290 support by reusing SM6115 power domains. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211108134442.30051-4-shawn.guo@linaro.org --- drivers/soc/qcom/rpmpd.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 3e7905854eb90..36b2381039e62 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -395,6 +395,23 @@ static const struct rpmpd_desc sm6115_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; +static struct rpmpd *qcm2290_rpmpds[] = { + [QCM2290_VDDCX] = &sm6115_vddcx, + [QCM2290_VDDCX_AO] = &sm6115_vddcx_ao, + [QCM2290_VDDCX_VFL] = &sm6115_vddcx_vfl, + [QCM2290_VDDMX] = &sm6115_vddmx, + [QCM2290_VDDMX_AO] = &sm6115_vddmx_ao, + [QCM2290_VDDMX_VFL] = &sm6115_vddmx_vfl, + [QCM2290_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, + [QCM2290_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, +}; + +static const struct rpmpd_desc qcm2290_desc = { + .rpmpds = qcm2290_rpmpds, + .num_pds = ARRAY_SIZE(qcm2290_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, @@ -404,6 +421,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8994-rpmpd", .data = &msm8994_desc }, { .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc }, { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, + { .compatible = "qcom,qcm2290-rpmpd", .data = &qcm2290_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, -- GitLab From 52e844ee9a6f460e6160736a43ef13317a91ca74 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 10 Nov 2021 20:15:57 +0100 Subject: [PATCH 103/965] arm64: dts: reneas: rzg2: Add SDnH clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 9 ++++++--- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++---- 4 files changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 6f4fffacfca21..f9c4ae6f26a98 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2276,7 +2276,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2288,7 +2289,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2300,7 +2302,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2312,7 +2315,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 0f7bdfc90a0dc..0c175b8c2088f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2133,7 +2133,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2145,7 +2146,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2157,7 +2159,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2169,7 +2172,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index d597772c4c37e..5e16f6b1771e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1626,7 +1626,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1638,7 +1639,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1650,7 +1652,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 379a1300272ba..673fcc631972d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2362,7 +2362,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2375,7 +2376,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2388,7 +2390,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2401,7 +2404,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 311>; -- GitLab From eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 10 Nov 2021 20:16:01 +0100 Subject: [PATCH 104/965] arm64: dts: reneas: rcar-gen3: Add SDnH clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211110191610.5664-13-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-14-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-15-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-16-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-17-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-18-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-19-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-22-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 9 ++++++--- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 ++- 8 files changed, 44 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 1768a3e6bb8da..391ffe6ca03e4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2668,7 +2668,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2681,7 +2682,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2694,7 +2696,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2707,7 +2710,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 2bd8169735d35..b1a6cf76633dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2468,7 +2468,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2481,7 +2482,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2494,7 +2496,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2507,7 +2510,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 86d59e7e1a876..1c1da6d7be490 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2312,7 +2312,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2325,7 +2326,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2338,7 +2340,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2351,7 +2354,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 08df75606430b..3a357d958d4ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2315,7 +2315,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2328,7 +2329,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2341,7 +2343,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2354,7 +2357,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 6347d15e66b64..2a4513e7e2b5e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1339,7 +1339,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 314>; max-frequency = <200000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0ea300a8147d0..8698058f25f39 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1788,7 +1788,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1801,7 +1802,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1814,7 +1816,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 16ad5fc23a671..f29f3982a492c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1216,7 +1216,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 312>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 43bf2cbfbd8f7..940e4990379d8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1993,7 +1993,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 706>; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; -- GitLab From e1a9faddffe7e555304dc2e3284c84fbee0679ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 15 Nov 2021 14:28:30 +0000 Subject: [PATCH 105/965] arm64: dts: renesas: cat875: Add rx/tx delays The CAT875 sub board from Silicon Linux uses a Realtek PHY. The phy driver commit bbc4d71d63549bcd003 ("net: phy: realtek: fix rtl8211e rx/tx delay config") introduced NFS mount failures. Now it needs both rx/tx delays for the NFS mount to work. This patch fixes the NFS mount failure issue by adding "rgmii-id" mode to the avb device node. Signed-off-by: Biju Das Fixes: bbc4d71d63549bcd ("net: phy: realtek: fix rtl8211e rx/tx delay config") Link: https://lore.kernel.org/r/20211115142830.12651-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/cat875.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index a69d24e9c61db..8c9da8b4bd60b 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -18,6 +18,7 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-id"; status = "okay"; phy0: ethernet-phy@0 { -- GitLab From a5c29f61466995d0d2c1370c709ef7fda534d386 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 17 Nov 2021 01:12:46 +0000 Subject: [PATCH 106/965] arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211117011247.27621-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 358db254c4eaa..2dd6eff471cb1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -176,6 +176,54 @@ status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; + resets = <&cpg R9A07G044_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; + resets = <&cpg R9A07G044_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; + resets = <&cpg R9A07G044_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; -- GitLab From 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 17 Nov 2021 01:12:47 +0000 Subject: [PATCH 107/965] arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211117011247.27621-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 4c32f068a1f03..6f2a8bdfa225e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -263,6 +263,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + ssi0_pins: ssi0 { pinmux = , /* BCK */ , /* RCK */ @@ -318,6 +325,13 @@ status = "okay"; }; +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &ssi0 { pinctrl-0 = <&ssi0_pins>; pinctrl-names = "default"; -- GitLab From e051025efac3929ca7e3e2f2c8860d3447366ebc Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Nov 2021 17:06:00 +0100 Subject: [PATCH 108/965] dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock This only applies to R-Car Gen2 and later generations, so we need to distinguish. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211115160600.4455-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 38 ++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 9f1e7092cf44d..f5107a641790a 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -129,15 +129,35 @@ allOf: - clock-names - resets else: - properties: - clocks: - minItems: 1 - maxItems: 2 - clock-names: - minItems: 1 - items: - - const: core - - const: cd + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd - if: properties: -- GitLab From 663eede58f83783ff246573937615f0792788876 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:15 +0900 Subject: [PATCH 109/965] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Add device tree bindings documentation for Renesas R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5172065078014..36197f53b3109 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -315,6 +315,10 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: -- GitLab From 06bd71cd2ebd98bb177fc7c35c10fed855781b82 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:17 +0900 Subject: [PATCH 110/965] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Document bindings for the R-Car S4-8 (R8A779F0) reset module. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 620cd0538bbe9..bbe313bf17967 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 reg: maxItems: 1 -- GitLab From c014e935596b2637e00dcd32077ac5019d9a7e64 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:18 +0900 Subject: [PATCH 111/965] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Document bindings for the R-Car S4-8 (aka R8A779F0) SYSC block. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 99e8042ac111d..62a49ca319ece 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -41,6 +41,7 @@ properties: - renesas,r8a77990-sysc # R-Car E3 - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U + - renesas,r8a779f0-sysc # R-Car S4-8 reg: maxItems: 1 -- GitLab From 08c40de81b77bd030f2a065464e7362b7467ed78 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 2 Nov 2021 15:42:23 +0100 Subject: [PATCH 112/965] arm64: dts: mediatek: mt8173-elm: Move pwm pinctrl to pwm0 node The PWM pinctrl belongs to the PWM0 node, as it's strictly pwm related. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211102144224.457446-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index e666ebb28980a..f292ca459a9a1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -27,8 +27,6 @@ power-supply = <&bl_fixed_reg>; enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; status = "okay"; }; @@ -901,6 +899,8 @@ }; &pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; status = "okay"; }; -- GitLab From 54337a96f31b87e34f62af4c510e2fa80a908400 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 2 Nov 2021 15:42:24 +0100 Subject: [PATCH 113/965] arm64: dts: mediatek: mt8173-elm: Add backlight enable pin config Add the proper pinctrl for GPIO95 backlight enable pin and assign it to the pwm-backlight node. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211102144224.457446-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index f292ca459a9a1..9c75fbb31f985 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -27,6 +27,8 @@ power-supply = <&bl_fixed_reg>; enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_backlight_en_pins>; status = "okay"; }; @@ -825,6 +827,12 @@ }; }; + panel_backlight_en_pins: panel_backlight_en_pins { + pins1 { + pinmux = ; + }; + }; + panel_fixed_pins: panel_fixed_pins { pins1 { pinmux = ; -- GitLab From 7781083fd609f849adcab88bf7467614ed4d29a6 Mon Sep 17 00:00:00 2001 From: Seiya Wang Date: Tue, 2 Nov 2021 17:02:30 +0800 Subject: [PATCH 114/965] arm64: dts: mt8183: support coresight-cpu-debug for mt8183 Add coresight-cpu-debug nodes to mt8183 for dumping EDPRSR, EDPCSR, EDCIDSR, EDVIDSR while kernel panic happens Signed-off-by: Seiya Wang Link: https://lore.kernel.org/r/20211102090230.25013-1-seiya.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index ba4584faca5ae..00f2ddd245e10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -367,6 +367,70 @@ reg = <0 0x0c530a80 0 0x50>; }; + cpu_debug0: cpu-debug@d410000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd410000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu_debug1: cpu-debug@d510000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd510000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu_debug2: cpu-debug@d610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd610000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu_debug3: cpu-debug@d710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd710000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + cpu_debug4: cpu-debug@d810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd810000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + cpu_debug5: cpu-debug@d910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd910000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + cpu_debug6: cpu-debug@da10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xda10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + cpu_debug7: cpu-debug@db10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xdb10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + topckgen: syscon@10000000 { compatible = "mediatek,mt8183-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; -- GitLab From 963070f762137cff817d33c102309ab0a345eb32 Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:40 -0700 Subject: [PATCH 115/965] arm64: dts: qcom: sc7180: Include gpio.h in edp bridge dts The edp bridge dts fragment files use the macros defined in 'dt-bindings/gpio/gpio.h'. To help us more flexibly order the #include lines of dts files in a board-revision-specific dts file, let's include the gpio header in the bridge dts fragment files themselves. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.1.Ie17e51ad3eb91d72826ce651ca2786534a360210@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index a3d69540d4e47..6a84fba178d61 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -5,6 +5,8 @@ * Copyright 2021 Google LLC. */ +#include + / { pp3300_brij_ps8640: pp3300-brij-ps8640 { compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 97d5e45abd1de..6dbf413e4e5b8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -5,6 +5,8 @@ * Copyright 2021 Google LLC. */ +#include + &dsi0_out { remote-endpoint = <&sn65dsi86_in>; data-lanes = <0 1 2 3>; -- GitLab From 0417a86b200b4da1dff73e9f4bd7743346e5565b Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:41 -0700 Subject: [PATCH 116/965] arm64: dts: qcom: sc7180: Specify "data-lanes" for DSI host output MSM DSI host driver actually parses "data-lanes" in DT and compare it with the number of DSI lanes the bridge driver sets for mipi_dsi_device. So we need to always specify "data-lanes" for the DSI host output. As of now, "data-lanes" is added to ti-sn65dsi86 dts fragment, but missing in parade-ps8640 dts fragment, which requires a fixup. Since we'll do 4-lane DSI regardless of which bridge chip is used, instead of adding "data-lanes" to parade-ps8640 dts fragment, let's just move "data-lanes" from the bridge dts to sc7180-trogdor.dtsi. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.2.If23c83a786fc4d318a1986f43803f22b4b1d82cd@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 6dbf413e4e5b8..f869e6a343c1b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -9,7 +9,6 @@ &dsi0_out { remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; }; edp_brij_i2c: &i2c2 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index d4f4441179fcc..bd5909ffb3dc0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -603,6 +603,10 @@ vdda-supply = <&vdda_mipi_dsi0_1p2>; }; +&dsi0_out { + data-lanes = <0 1 2 3>; +}; + &dsi_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi0_pll>; -- GitLab From 7624b41b3379e664f074137001fc2e44bc1f5eaf Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:42 -0700 Subject: [PATCH 117/965] arm64: dts: qcom: sc7180: Support Lazor/Limozeen rev9 Support Lazor/Limozeen rev9 board where Parade ps8640 is added as the second source edp bridge. To support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.3.Ie56f55924f5c7706fe3194e710bbef6fdb8b5bc6@changeid --- arch/arm64/boot/dts/qcom/Makefile | 9 +++- .../sc7180-trogdor-lazor-limozeen-nots-r4.dts | 2 +- .../sc7180-trogdor-lazor-limozeen-nots-r5.dts | 31 +++++++++++++ ...sc7180-trogdor-lazor-limozeen-nots-r9.dts} | 8 ++-- .../qcom/sc7180-trogdor-lazor-limozeen-r4.dts | 46 +++++++++++++++++++ ...s => sc7180-trogdor-lazor-limozeen-r9.dts} | 6 ++- .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 2 + .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 2 + .../dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 9 +++- .../dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 9 +++- .../boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 8 +++- .../dts/qcom/sc7180-trogdor-lazor-r9-kb.dts | 22 +++++++++ .../dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 30 ++++++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r9.dts | 18 ++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 -- 15 files changed, 188 insertions(+), 17 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-lazor-limozeen-nots.dts => sc7180-trogdor-lazor-limozeen-nots-r9.dts} (60%) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-lazor-limozeen.dts => sc7180-trogdor-lazor-limozeen-r9.dts} (82%) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6b816eb333099..f637c4d3729f2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -64,9 +64,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-kb.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts index 6ebde0828550c..850776c5323d1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts @@ -5,7 +5,7 @@ * Copyright 2020 Google LLC. */ -#include "sc7180-trogdor-lazor-limozeen-nots.dts" +#include "sc7180-trogdor-lazor-limozeen-nots-r5.dts" / { model = "Google Lazor Limozeen without Touchscreen (rev4)"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts new file mode 100644 index 0000000000000..f360ff27226e6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor Limozeen board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor Limozeen without Touchscreen (rev5 - rev8)"; + /* No sku5 post-rev5 */ + compatible = "google,lazor-rev5-sku5", "google,lazor-rev5-sku6", + "google,lazor-rev6-sku6", "google,lazor-rev7-sku6", + "google,lazor-rev8-sku6", "qcom,sc7180"; +}; + +/delete-node/&ap_ts; + +&panel { + compatible = "innolux,n116bca-ea1", "innolux,n116bge"; +}; + +&sdhc_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts similarity index 60% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index 0456c7e05d007..4e35aec6a1e55 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -2,17 +2,19 @@ /* * Google Lazor Limozeen board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor Limozeen without Touchscreen"; - compatible = "google,lazor-sku6", "google,lazor-sku5", "qcom,sc7180"; + model = "Google Lazor Limozeen without Touchscreen (rev9+)"; + compatible = "google,lazor-sku6", "qcom,sc7180"; }; /delete-node/&ap_ts; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts new file mode 100644 index 0000000000000..42b4bbcc76f4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor Limozeen board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor Limozeen (rev4 - rev8)"; + compatible = "google,lazor-rev4-sku4", "google,lazor-rev5-sku4", + "google,lazor-rev6-sku4", "google,lazor-rev7-sku4", + "google,lazor-rev8-sku4", "qcom,sc7180"; +}; + +/delete-node/&ap_ts; + +&ap_ts_pen_1v8 { + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&panel { + compatible = "auo,b116xa01"; +}; + +&sdhc_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts similarity index 82% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts index e6ad6dae4e603..dc47842bc6623 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts @@ -2,16 +2,18 @@ /* * Google Lazor Limozeen board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor Limozeen"; + model = "Google Lazor Limozeen (rev9+)"; compatible = "google,lazor-sku4", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index 30e3e769d2b4f..b142006478eab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index c2ef06367baf7..59740799fa3a9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index dcb41afdc82a6..18ef9da719989 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -7,12 +7,17 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" / { - model = "Google Lazor (rev3+) with KB Backlight"; - compatible = "google,lazor-sku2", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8) with KB Backlight"; + compatible = "google,lazor-rev3-sku2", "google,lazor-rev4-sku2", + "google,lazor-rev5-sku2", "google,lazor-rev6-sku2", + "google,lazor-rev7-sku2", "google,lazor-rev8-sku2", + "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index be44900602d74..c5c9feff41b87 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -7,12 +7,17 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor (rev3+) with LTE"; - compatible = "google,lazor-sku0", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8) with LTE"; + compatible = "google,lazor-rev3-sku0", "google,lazor-rev4-sku0", + "google,lazor-rev5-sku0", "google,lazor-rev6-sku0", + "google,lazor-rev7-sku0", "google,lazor-rev8-sku0", + "qcom,sc7180"; }; &ap_sar_sensor { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index b474df47cd70b..7adcedbf080d5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -7,10 +7,14 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" / { - model = "Google Lazor (rev3+)"; - compatible = "google,lazor", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8)"; + compatible = "google,lazor-rev3", "google,lazor-rev4", + "google,lazor-rev5", "google,lazor-rev6", "google,lazor-rev7", + "google,lazor-rev8", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts new file mode 100644 index 0000000000000..7f5c015e1ecba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-lite.dtsi" + +/ { + model = "Google Lazor (rev9+) with KB Backlight"; + compatible = "google,lazor-sku2", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts new file mode 100644 index 0000000000000..344b57c035d08 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor (rev9+) with LTE"; + compatible = "google,lazor-sku0", "qcom,sc7180"; +}; + +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts new file mode 100644 index 0000000000000..83f6a4eb5ae5b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-lite.dtsi" + +/ { + model = "Google Lazor (rev9+)"; + compatible = "google,lazor", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 8b79fbb757569..69666f92176aa 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,13 +5,10 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" - ap_ec_spi: &spi6 {}; ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" &ap_sar_sensor { semtech,cs0-ground; -- GitLab From 3922ccaed4ac9dab5087fc5f20d319cc55765afa Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:43 -0700 Subject: [PATCH 118/965] arm64: dts: qcom: sc7180: Support Homestar rev4 Support Homestar rev4 board where Parade ps8640 is added as the second source edp bridge. Support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.4.If7aaa8e36f1269acae5488035bd62ce543756bf8@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sc7180-trogdor-homestar-r2.dts | 2 ++ .../dts/qcom/sc7180-trogdor-homestar-r3.dts | 6 ++++-- .../dts/qcom/sc7180-trogdor-homestar-r4.dts | 17 +++++++++++++++++ .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 3 --- 5 files changed, 24 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f637c4d3729f2..ba99aba1d51aa 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts index db6c2da67ceab..70032983fb65f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts index 3fd8aa5bb7a6d..e92e2e9e48edd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts @@ -7,9 +7,11 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" / { - model = "Google Homestar (rev3+)"; - compatible = "google,homestar", "qcom,sc7180"; + model = "Google Homestar (rev3)"; + compatible = "google,homestar-rev3", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts new file mode 100644 index 0000000000000..fb27106bbb4ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Homestar board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-homestar.dtsi" + +/ { + model = "Google Homestar (rev4+)"; + compatible = "google,homestar", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 4ab890b2a1d43..f32369af13517 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,13 +5,10 @@ * Copyright 2021 Google LLC. */ -#include "sc7180.dtsi" - ap_ec_spi: &spi6 {}; ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { /* BOARD-SPECIFIC TOP LEVEL NODES */ -- GitLab From c41910f257a22dc406c60d8826b4a3b5398003a3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 30 Oct 2021 12:04:12 +0200 Subject: [PATCH 119/965] arm64: dts: qcom: msm8996: drop not documented adreno properties These properties aren't documented nor implemented in the driver. Drop them. Fixes warnings as: $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/msm/gpu.yaml ... arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: gpu@b00000: 'qcom,gpu-quirk-fault-detect-mask', 'qcom,gpu-quirk-two-pass-use-wfi' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/display/msm/gpu.yaml ... Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211030100413.28370-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index bccc2d0b35a84..1ac78d9909abf 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -987,9 +987,6 @@ nvmem-cells = <&speedbin_efuse>; nvmem-cell-names = "speed_bin"; - qcom,gpu-quirk-two-pass-use-wfi; - qcom,gpu-quirk-fault-detect-mask; - operating-points-v2 = <&gpu_opp_table>; status = "disabled"; -- GitLab From 30a7f99befc655cb3eacdd3a0f2394a5209a492f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 11 Nov 2021 19:46:28 +0100 Subject: [PATCH 120/965] arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform) Add support for SONY Xperia XZ2, XZ2 Compact and XZ3 smartphones, all based on the Qualcomm SDM845 chipset. There also exists a fourth Tama device, the XZ2 Premium (Aurora) with a 4K display, but it's relatively rare. The devices are affected by a scary UFS behaviour where sending a certain UFS command (which is worked around on downstream) renders the device unbootable, by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly disabled for now. Downstream workaround: https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561 This platform's bootloader is not very nice either. To boot mainline you need to flash a bogus DTBO (fastboot erasing may cut it, but it takes an inhumane amount of time) - one that's just 4 bytes (all zeroes) seems to work just fine. Of course, one can also provide a "normal" DTBO (device-specific DT overlayed on top of the SoC DT), but that's not yet supported by the mainline kernel build system. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Martin Botka Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211111184630.605035-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../qcom/sdm845-sony-xperia-tama-akari.dts | 13 + .../qcom/sdm845-sony-xperia-tama-akatsuki.dts | 29 ++ .../qcom/sdm845-sony-xperia-tama-apollo.dts | 13 + .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 438 ++++++++++++++++++ 5 files changed, 496 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ba99aba1d51aa..4906712e3cfd1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -97,6 +97,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts new file mode 100644 index 0000000000000..34f84f1f1eb4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ2"; + compatible = "sony,akari-row", "qcom,sdm845"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts new file mode 100644 index 0000000000000..8a0d94e7f5985 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ3"; + compatible = "sony,akatsuki-row", "qcom,sdm845"; +}; + +/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */ +&vreg_l14a_1p8 { + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <1840000>; +}; + +&vreg_l22a_2p8 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&vreg_l28a_2p8 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts new file mode 100644 index 0000000000000..c9e62c72f60e6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ2 Compact"; + compatible = "sony,apollo-row", "qcom,sdm845"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi new file mode 100644 index 0000000000000..281fe6dea62a9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include "sdm845.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ + qcom,board-id = <8 0>; + + gpio-keys { + compatible = "gpio-keys"; + + /* Neither Camera Focus, nor Camera Shutter seem to work... */ + + vol-down { + label = "volume_down"; + gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + /* SONY was cool and didn't diverge from MTP this time, yay! */ + cont_splash_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_0p9>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p3>; + vdd-l3-l11-supply = <&vreg_s7a_0p9>; + vdd-l4-l5-supply = <&vreg_s7a_0p9>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l9-supply = <&vreg_s5a_1p9>; + vdd-l10-l23-l25-supply = <&src_vreg_bob>; + vdd-l13-l19-l21-supply = <&src_vreg_bob>; + vdd-l16-l28-supply = <&src_vreg_bob>; + vdd-l18-l22-supply = <&src_vreg_bob>; + vdd-l20-l24-supply = <&src_vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p3>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p1: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p3: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_1p9: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_0p9: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p9: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p7: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p7: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p7: ldo19 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + + /* + * The driver *really* doesn't want this regualtor to exist, + * saying that it could not get the current voltage (-ENOTRECOVERABLE) + * even though it surely is used on these devices (as a voltage + * source for camera autofocus) + */ + status = "disabled"; + }; + + vreg_l20a_2p7: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p7: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p8: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p0: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p1: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p0: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_2p8: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + src_vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + /* Synaptics touchscreen @ 2c, 3c */ +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + /* Qcom SMB1355 @ 8, c */ + /* NXP PN547 NFC @ 28 */ + /* Renesas IDTP9221 Qi charger @ 61 */ +}; + +&i2c14 { + status = "okay"; + clock-frequency = <400000>; + + /* SONY ToF sensor @ 52 */ + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l21a_2p7>; + vqmmc-supply = <&vreg_l13a_1p8>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default_state>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2_default_state: sdc2-default-state { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; +}; + +&uart6 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p1>; +}; -- GitLab From e2bbebf3b04c62fc3f7e64525c43bf5118a3cc88 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:45 +0300 Subject: [PATCH 121/965] arm64: dts: qcom: apq8096-db820c: specify adsp firmware name Specify firmware name to be used for the ADSP. Quoting Bjorn from the respective apq8016-sbc commit: The firmware for the modem and WiFi subsystems platform specific and is signed with a OEM specific key (or a test key). In order to support more than a single device it is therefor not possible to rely on the default path and stash these files directly in the firmware directory. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index d01a512634cfe..7e7b416e7d214 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -166,6 +166,7 @@ &adsp_pil { status = "okay"; + firmware-name = "qcom/apq8096/adsp.mbn"; }; &blsp2_i2c1 { -- GitLab From 7c57dcae949d1d39068f1e92233a9bc2dc7dcfba Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:46 +0300 Subject: [PATCH 122/965] arm64: dts: qcom: apq8096-db820c: add missing regulator details Specify that S11 (well, whole block of s8+s9+s10+s11) of pm8994 and S2 (s2 + s3) of pmi8994 are supplied by vph_pwr. While we are at it, add regulator name to S11, so that is displayed as VDD_APCC in the system. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 7e7b416e7d214..9dbac589482b6 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -633,6 +633,8 @@ &pm8994_spmi_regulators { qcom,saw-reg = <&saw3>; + vdd_s11-supply = <&vph_pwr>; + s9 { qcom,saw-slave; }; @@ -641,6 +643,7 @@ }; s11 { qcom,saw-leader; + regulator-name = "VDD_APCC"; regulator-always-on; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; @@ -673,6 +676,8 @@ }; &pmi8994_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + vdd_gfx: s2@1700 { reg = <0x1700 0x100>; regulator-name = "VDD_GFX"; -- GitLab From a49c3dd1f7827fa7ee3a861b4292dd7d1c346fb2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:47 +0300 Subject: [PATCH 123/965] arm64: dts: qcom: apq8096-db820c: correct lvs1 and lvs2 supply property The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 9dbac589482b6..28403d2ffd31f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -715,7 +715,7 @@ vdd_l17_l29-supply = <&vph_pwr_bbyp>; vdd_l20_l21-supply = <&vph_pwr_bbyp>; vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; vreg_s3a_1p3: s3 { regulator-name = "vreg_s3a_1p3"; -- GitLab From 227ee1583ba4b3bb973e2a3e32351c242fdfc49d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:48 +0300 Subject: [PATCH 124/965] arm64: dts: qcom: msm8994-sony-xperia-kitakami: correct lvs1 and lvs2 supply property The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Cc: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 48de66bf19c4c..7cc564d8ca7c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -223,7 +223,7 @@ vdd_l17_l29-supply = <&pmi8994_bby>; vdd_l20_l21-supply = <&pmi8994_bby>; vdd_l25-supply = <&pm8994_s3>; - vdd_lvs1_lvs2-supply = <&pm8994_s4>; + vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ -- GitLab From 4c821bd42ccceca5e0fdc5491374e3d7e6941c2e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:49 +0300 Subject: [PATCH 125/965] arm64: dts: qcom: msm8996-sony-xperia-tone: fix SPMI regulators declaration Device tree for the Sony Xperia tone family of devices specifies S9+S10+S11 SAW regulator as a part of the pmi8994_spmi_regulators device tree node. However PMI8994 does not have these regulators, they are part of the PM8994 device. All other MSM8996-based devices list them in the pm8994_spmi_regulators device tree node. Move them accordingly. Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-5-dmitry.baryshkov@linaro.org --- .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 29 ++++++++++--------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ff7f39d29dd55..137b2d14f5e3e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -589,34 +589,37 @@ }; }; -&pmi8994_spmi_regulators { +&pm8994_spmi_regulators { qcom,saw-reg = <&saw3>; - vdd_gfx: - pmi8994_s2: s2 { - /* Pinned to a high value for now to avoid random crashes. */ - regulator-min-microvolt = <1015000>; - regulator-max-microvolt = <1015000>; - regulator-name = "vdd_gfx"; - regulator-always-on; - }; - - pmi8994_s9: s9 { + pm8994_s9: s9 { qcom,saw-slave; }; - pmi8994_s10: s10 { + pm8994_s10: s10 { qcom,saw-slave; }; - pmi8994_s11: s11 { + pm8994_s11: s11 { qcom,saw-leader; + regulator-name = "vdd_apcc"; regulator-always-on; regulator-min-microvolt = <470000>; regulator-max-microvolt = <1140000>; }; }; +&pmi8994_spmi_regulators { + vdd_gfx: + pmi8994_s2: s2 { + /* Pinned to a high value for now to avoid random crashes. */ + regulator-min-microvolt = <1015000>; + regulator-max-microvolt = <1015000>; + regulator-name = "vdd_gfx"; + regulator-always-on; + }; +}; + &pmi8994_wled { status = "okay"; default-brightness = <512>; -- GitLab From 25fdaae63a6927efad2f6c0428622712f0eb20dd Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 4 Nov 2021 10:49:58 +0000 Subject: [PATCH 126/965] arm64: dts: qcom: msm8996-xiaomi-scorpio: Add touchkey controller Add a node and pin states for Cypress StreetFighter touchkey controller. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104104932.104046-1-y.oudjana@protonmail.com --- .../boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index e5b8402b1ed65..27a45ddbb5bd2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -60,6 +60,20 @@ }; &blsp2_i2c6 { + touchkey: touchkey@28 { + compatible = "cypress,sf3155"; + reg = <0x28>; + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vreg_l6a_1p8>; + vdd-supply = <&vdd_3v2_tp>; + linux,keycodes = ; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchkey_default>; + pinctrl-1 = <&touchkey_sleep>; + }; + touchscreen: atmel-mxt-ts@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; @@ -416,6 +430,20 @@ "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ + touchkey_default: touchkey_default { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + touchkey_sleep: touchkey_sleep { + pins = "gpio77"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen_default { pins = "gpio75", "gpio125"; function = "gpio"; -- GitLab From de0a2ae359ef9ccbaab86cce44d442cd0ca36985 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 4 Nov 2021 11:15:18 +0000 Subject: [PATCH 127/965] arm64: dts: qcom: msm8996-xiaomi-common: Change TUSB320 to TUSB320L This platform actually doesn't have TUSB320, but rather TUSB320L. The TUSB320 compatible string was used due to lack of support for TUSB320L, and it was close enough to detect cable plug-in and direction, but it was limited to upstream facing port mode only. Now that support for TUSB320L is added[1], change node name and compatible to match and allow it to be properly reset and have its mode set to dual-role port. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ce0320bd3872038569be360870e2d5251b975692 Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104111454.105875-1-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 01e573f0dfbf8..7a9fcbe9bb31d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -207,8 +207,8 @@ status = "okay"; label = "TYPEC_I2C"; - typec: tusb320@47 { - compatible = "ti,tusb320"; + typec: tusb320l@47 { + compatible = "ti,tusb320l"; reg = <0x47>; interrupt-parent = <&tlmm>; interrupts = <63 IRQ_TYPE_EDGE_RISING>; -- GitLab From 5663ca59bb4f1dfd2501f2af0bfdca93c4d47b3a Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 28 Sep 2021 10:20:02 +0800 Subject: [PATCH 128/965] arm64: dts: qcom: Add missing vdd-supply for QUSB2 PHY QUSB2 PHY requires vdd-supply for digital circuit operation. Add it for platforms that miss it. Signed-off-by: Shawn Guo Acked-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210928022002.26286-4-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 28403d2ffd31f..f623db8451f1c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -233,6 +233,7 @@ &hsusb_phy1 { status = "okay"; + vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; @@ -240,6 +241,7 @@ &hsusb_phy2 { status = "okay"; + vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 137b2d14f5e3e..3bb50cecd62de 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -184,6 +184,7 @@ &hsusb_phy1 { status = "okay"; + vdd-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-dpdm-supply = <&pm8994_l24>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index 3f60575a351ce..b3b352530d76e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -102,6 +102,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 654188027f795..9823d48a91b10 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -260,6 +260,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; -- GitLab From f0360a7c1742681c390f2d94bb876ce80a8012b1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:40 +0100 Subject: [PATCH 129/965] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index be062377c9362..1e5e9405d8b19 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 06eedbe52c423..122c282a62df2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" #include "pm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d134280e29390..ee183f00dbaf8 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include -- GitLab From e84d04a2b221153b88f644d98b5902c3705f5348 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:41 +0100 Subject: [PATCH 130/965] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2 Add the missing third QUPv3 master node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-2-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ee183f00dbaf8..6cfe1f38dae9b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -597,6 +597,18 @@ #mbox-cells = <2>; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; -- GitLab From f4d4ca9f3934844b99af289cf38d4892c73f683e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:42 +0100 Subject: [PATCH 131/965] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3 The redistributor properties were missing. Add them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-3-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 6cfe1f38dae9b..a30ba3193d84b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1020,6 +1020,8 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; -- GitLab From ed9500c1df59437856d43e657f185fb1eb5d817d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:43 +0100 Subject: [PATCH 132/965] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Arch timer runs at 19.2 MHz. Specify the rate in the timer node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-4-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a30ba3193d84b..60866a20a55c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2484,5 +2484,6 @@ , , ; + clock-frequency = <19200000>; }; }; -- GitLab From 9e7f7b65c7f04c5cfda97d6bd0d452a49e60f24e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:44 +0100 Subject: [PATCH 133/965] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as the &pdc-nth range of the main interrupt controller (GIC). Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-5-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 973e18fe3b674..cd55797facf69 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -631,7 +631,7 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -642,7 +642,7 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 60866a20a55c9..f3e8549c65726 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -923,7 +923,7 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <15>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -934,7 +934,7 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <14>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; -- GitLab From f52dd33943ca5f84ae76890f352f6d9e12512c3f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:45 +0100 Subject: [PATCH 134/965] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name Thermal zone names should not be longer than 20 names, which is indicated by a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-6-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f3e8549c65726..7e0aa4c250942 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2462,7 +2462,7 @@ }; }; - camera-thermal-bottom { + cam-thermal-bottom { polling-delay-passive = <250>; polling-delay = <1000>; -- GitLab From 2dab7aac493df72f57498044cb38ca0a6c18e7e1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:46 +0100 Subject: [PATCH 135/965] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage Disable PON/RESIN keys by default and keep the RESIN keycode set-per-board, as these settings are not common between devices (one cannot even assume all devices have buttons nowadays..). Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-7-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 9 +++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 769f9726806ff..0f94c46a14443 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -19,16 +19,17 @@ compatible = "qcom,pm8998-pon"; reg = <0x1300>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; linux,code = ; + status = "disabled"; }; - resin { + pon_resin: resin { compatible = "qcom,pmk8350-resin"; interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 122c282a62df2..52cf3045602f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -289,6 +289,15 @@ status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + &qupv3_id_0 { status = "okay"; }; -- GitLab From 9ea9eb36b3c046fc48e737db4de69f7acd12f9be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:47 +0100 Subject: [PATCH 136/965] arm64: dts: qcom: sm8350: Describe GCC dependency clocks Add all the clock names that the GCC driver expects to get via DT, so that the clock handles can be filled as the development progresses. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-8-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7e0aa4c250942..3d0d80e61405c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -584,8 +584,30 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "ufs_card_rx_symbol_0_clk", + "ufs_card_rx_symbol_1_clk", + "ufs_card_tx_symbol_0_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; }; ipcc: mailbox@408000 { -- GitLab From cf03cd7e12bdb43d624dbd55d8467b29e9b608c2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:48 +0100 Subject: [PATCH 137/965] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-9-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3d0d80e61405c..4b864fcb04e0c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -619,6 +619,25 @@ #mbox-cells = <2>; }; + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -642,6 +661,84 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0098c000 0 0x4000>; @@ -650,6 +747,140 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 3 seems to be strictly SPI-only */ + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1017,6 +1248,62 @@ }; }; + qup_uart6_default: qup-uart6-default { + pins = "gpio30", "gpio31"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio4", "gpio5"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default { + pins = "gpio8", "gpio9"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio12", "gpio13"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default { + pins = "gpio20", "gpio21"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default { + pins = "gpio24", "gpio25"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio28", "gpio29"; + function = "qup6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio32", "gpio33"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c13_default_state: qup-i2c13-default-state { mux { pins = "gpio0", "gpio1"; -- GitLab From 8934535531c875e6ec67876905982a44e8306c1c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:49 +0100 Subject: [PATCH 138/965] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-10-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 213 +++++++++++++++++++++++++-- 1 file changed, 202 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4b864fcb04e0c..033d3984d572e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -638,6 +638,25 @@ }; }; + qup_opp_table_120mhz: qup-120mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -898,18 +917,161 @@ ranges; status = "disabled"; + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default_state>; + pinctrl-0 = <&qup_i2c13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; apps_smmu: iommu@15000000 { @@ -1304,17 +1466,46 @@ bias-disable; }; - qup_i2c13_default_state: qup-i2c13-default-state { - mux { - pins = "gpio0", "gpio1"; - function = "qup13"; - }; + qup_i2c8_default: qup-i2c8-default { + pins = "gpio36", "gpio37"; + function = "qup8"; + drive-strength = <2>; + bias-pull-up; + }; - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; + qup_i2c9_default: qup-i2c9-default { + pins = "gpio40", "gpio41"; + function = "qup9"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio44", "gpio45"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default { + pins = "gpio48", "gpio49"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default { + pins = "gpio52", "gpio53"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default { + pins = "gpio0", "gpio1"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; }; }; -- GitLab From 98374e6925b88cfc4e528faed230a835f91a576d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:50 +0100 Subject: [PATCH 139/965] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-11-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 200 +++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 033d3984d572e..944ad864f73ec 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -667,6 +667,164 @@ #size-cells = <2>; ranges; status = "disabled"; + + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c16_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c17_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 18 seems to be strictly SPI/UART-only */ + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart18_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c19_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -1417,6 +1575,13 @@ bias-disable; }; + qup_uart18_default: qup-uart18-default { + pins = "gpio58", "gpio59"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-default { pins = "gpio4", "gpio5"; function = "qup0"; @@ -1507,6 +1672,41 @@ drive-strength = <2>; bias-pull-up; }; + + qup_i2c14_default: qup-i2c14-default { + pins = "gpio56", "gpio57"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c15_default: qup-i2c15-default { + pins = "gpio60", "gpio61"; + function = "qup15"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c16_default: qup-i2c16-default { + pins = "gpio64", "gpio65"; + function = "qup16"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c17_default: qup-i2c17-default { + pins = "gpio72", "gpio73"; + function = "qup17"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c19_default: qup-i2c19-default { + pins = "gpio76", "gpio77"; + function = "qup19"; + drive-strength = <2>; + bias-disable; + }; }; rng: rng@10d3000 { -- GitLab From 9bc2c8fea55c12d3720a80a59f99fdf68b8de773 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:51 +0100 Subject: [PATCH 140/965] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs Assign the iommus property to allow access to QUP hosts that were not set up by the bootloader. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-12-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 944ad864f73ec..0ea735d0df49e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -663,6 +663,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5e3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -833,6 +834,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1070,6 +1072,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0>; #address-cells = <2>; #size-cells = <2>; ranges; -- GitLab From c2721b0c23d975c73bce68d40435d66fbab19047 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:52 +0100 Subject: [PATCH 141/965] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Add support for SONY Xperia 1 III (PDX215) and 5 III (PDX214) smartphones. Both are based on the SM8350 Sagami platform and feature some really high-end specs, such as: - 4K (1 III / PRO-I) / 1080p (5 III), 120Hz HDR OLED 10-bit panels - USB-C 3.1 with HDMI in (yes, phone as display!) and DP out - 5G - 8 or 12 gigs of ram, 128/256/512 gigs of storage - A 3.5mm headphone jack, a RGB notification LED and a uSD card slot :) - IP65/68 dust/water resistance - Dual front-firing speakers and a lot of microphones - Crazy complex camera hardware (especially on the PRO-I), which includes 4 cameras, an RGBIR sensor and a 3D iToF The aforementioned PRO-I (PDX217) is not supported in this patch, because even though it shares most of the code with 1 III, nobody really has it (yet?) This only adds basic support for booting to a USB shell with a bootloader-enabled display, support for all the awesome hardware listed above will (hopefully) come (hopefully) soon. In order to get a working boot image, you need to run (e.g. for 1 III): cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8350-sony-xperia-\ sagami-pdx215.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 11 \ --os_patch_level 2021-10 \ # or newer -o boot.img-sony-xperia-pdx215 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: fastboot flash boot boot.img-sony-xperia-pdx215 fastboot erase vendor_boot fastboot flash dtbo emptydtbo.img fastboot reboot Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-13-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sm8350-sony-xperia-sagami-pdx214.dts | 19 +++ .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 13 ++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 132 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4906712e3cfd1..50572419dca95 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -116,3 +116,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts new file mode 100644 index 0000000000000..cc650508dc2d6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 5 III"; + compatible = "sony,pdx214-generic", "qcom,sm8350"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts new file mode 100644 index 0000000000000..d21bbeb603a6c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 1 III"; + compatible = "sony,pdx215-generic", "qcom,sm8350"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi new file mode 100644 index 0000000000000..b50f04ffee95b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "sm8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" + +/ { + /* + * Yes, you are correct, there is NO MORE {msm,board,pmic}-id on SM8350! + * Adding it will cause the bootloader to go crazy and randomly crash + * shortly after closing UEFI boot services.. Perhaps that has something + * to do with the OS running inside a VM now..? + */ + + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@e1000000 { + compatible = "simple-framebuffer"; + reg = <0 0xe1000000 0 0x2300000>; + + /* The display, even though it's 4K, initializes at 1080-ish p */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ + + vol-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + reserved-memory { + cont_splash_mem: memory@e1000000 { + reg = <0 0xe1000000 0 0x2300000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; + console-size = <0x40000>; + record-size = <0x1000>; + no-map; + }; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */ +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_1_qmpphy { + status = "okay"; +}; -- GitLab From 1209e9246632d93f557c651110533bf44f8335f3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:53 +0100 Subject: [PATCH 142/965] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes Based on current driver availability, add either nodes or comments regarding peripherals connected via I2C/SPI. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-14-konrad.dybcio@somainline.org --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index b50f04ffee95b..c44376aa07429 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,93 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <1000000>; + + /* Some subset of SONY IMX663 camera sensor @ 38 */ +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* Samsung Touchscreen (needs I2C GPI DMA) @ 48 */ +}; + +&i2c11 { + status = "okay"; + clock-frequency = <1000000>; + + cs35l41_l: cs35l41@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; + + cs35l41_r: cs35l41@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; +}; + +&i2c12 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c13 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */ + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + /* NXP SN1X0 NFC @ 28 */ +}; + +&i2c17 { + status = "okay"; + clock-frequency = <1000000>; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + &pmk8350_rtc { status = "okay"; }; @@ -100,8 +187,22 @@ status = "okay"; }; +&spi14 { + status = "okay"; + + /* NXP SN1X0 NFC Secure Element @ 0 */ +}; + &tlmm { gpio-reserved-ranges = <44 4>; + + ts_int_default: ts-int-default { + pin = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; /* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ -- GitLab From ce2762aec7378892d398b784a4bfd4856dd71043 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:54 +0100 Subject: [PATCH 143/965] arm64: dts: qcom: sm8350-sagami: Configure remote processors Configure ADSP, CDSP, MPSS, SLPI and IPA on SoMC Sagami. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-15-konrad.dybcio@somainline.org --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index c44376aa07429..90b13cbe2fa63 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,16 @@ }; }; +&adsp { + status = "okay"; + firmware-name = "qcom/adsp.mbn"; +}; + +&cdsp { + status = "okay"; + firmware-name = "qcom/cdsp.mbn"; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; @@ -162,6 +172,17 @@ /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ }; +&ipa { + status = "okay"; + memory-region = <&pil_ipa_fw_mem>; + firmware-name = "qcom/ipa_fws.mbn"; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/modem.mbn"; +}; + &pmk8350_rtc { status = "okay"; }; @@ -187,6 +208,11 @@ status = "okay"; }; +&slpi { + status = "okay"; + firmware-name = "qcom/slpi.mbn"; +}; + &spi14 { status = "okay"; -- GitLab From 9ac8999e8d6c05826664a61bc89509824f45621d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:55 +0100 Subject: [PATCH 144/965] arm64: dts: qcom: sm8350: Add LLCC node Configure the Last-Level Cache Controller for SM8350. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-16-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 0ea735d0df49e..7323ed74f41a7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2232,6 +2232,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8350-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; -- GitLab From 96e1e3a15273a99d89b1389e4487e734c7d37d8e Mon Sep 17 00:00:00 2001 From: yangcong Date: Mon, 15 Nov 2021 11:01:55 +0800 Subject: [PATCH 145/965] arm64: dts: qcom: sc7180: Fix ps8640 power sequence for Homestar rev4 When powering up the ps8640, we need to deassert PD right after we turn on the vdd33 regulator. Unfortunately, the vdd33 regulator takes some time (~4ms) to turn on. Add in the delay for the vdd33 regulator so that when the driver deasserts PD that the regulator has had time to ramp. Signed-off-by: yangcong Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211115030155.9395-1-yangcong5@huaqin.corp-partner.google.com --- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts index fb27106bbb4ab..0de0c97f57286 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -15,3 +15,7 @@ model = "Google Homestar (rev4+)"; compatible = "google,homestar", "qcom,sc7180"; }; + +&pp3300_brij_ps8640 { + regulator-enable-ramp-delay = <4000>; +}; -- GitLab From fa09b2248714c64644576d8064e9bd292a504a0e Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:46 +0530 Subject: [PATCH 146/965] arm64: dts: qcom: sc7280: Fix incorrect clock name Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk To match with dt binding. Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node") Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-2-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e4988ea2011c4..f14fed538022a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -581,7 +581,7 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", - "pcie_0_pipe_clk", "pcie_1_pipe-clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; -- GitLab From bd7d507935ca73fba6b6f0f52a3d08d77b143c58 Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:47 +0530 Subject: [PATCH 147/965] arm64: dts: qcom: sc7280: Add pcie clock support Add pcie clock phandle for sc7280 SoC. Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-3-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f14fed538022a..5b8f549e1e8ba 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -579,7 +579,8 @@ reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, <0>, <0>; + <0>, <&pcie1_lane 0>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", -- GitLab From 66b788133030f0c69a0ecc7f72f7939b119c9a69 Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:48 +0530 Subject: [PATCH 148/965] arm64: dts: qcom: sc7280: Fix 'interrupt-map' parent address cells Update interrupt-map parent address cells for sc7280 Similar to existing Qcom SoCs. Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-4-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b8f549e1e8ba..40b409f279f5f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1598,10 +1598,10 @@ interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, -- GitLab From b139425115b801e56fe2d6dbcd2e798be87e2e06 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:20 +0700 Subject: [PATCH 149/965] arm64: dts: qcom: sdm630: Assign numbers to eMMC and SD This makes eMMC/SD device number consistent. Reviewed-by: Martin Botka Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-2-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3e0165bb61c50..b75bb87ed2900 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -19,6 +19,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + chosen { }; clocks { -- GitLab From 9f6cbe37a72fc9dafe8f560e557c93209cc100e7 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:21 +0700 Subject: [PATCH 150/965] arm64: dts: qcom: sdm630-pm660: Move RESIN to pm660 dtsi It's not worth duplicating the same node over and over again, so let's keep the common bits in the pm660 DTSI, making only changing the status and keycode necessary. Also, disable RESIN/PWR by default just in case if there are devices that doesn't use them. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-3-danct12@riseup.net --- arch/arm64/boot/dts/qcom/pm660.dtsi | 12 +++++++++++- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 16 ++++++++-------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index d0ef8a1675e2d..c482663aad569 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -54,14 +54,24 @@ mode-bootloader = <0x2>; mode-recovery = <0x1>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; bias-pull-up; linux,code = ; + + status = "disabled"; }; + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + + status = "disabled"; + }; }; pm660_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 11d0a8c1cf35a..e90c9ec846753 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -215,14 +215,14 @@ /* HCI Bluetooth */ }; -&pon { - volup { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; }; &qusb2phy { -- GitLab From 262a8ad19cdfd8e177d32bfbec1691a2069951b1 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:22 +0700 Subject: [PATCH 151/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulators Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-4-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 266 ++++++++++++++++++ 1 file changed, 266 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 1edc53fd69418..eccbeecef1925 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2021, Dang Huynh */ /dts-v1/; #include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" / { model = "Xiaomi Redmi Note 7"; @@ -20,6 +23,16 @@ stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +53,259 @@ status = "okay"; }; +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + /* SDHCI 3.3V signal doesn't seem to be supported. */ + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-always-on; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; -- GitLab From 4c420a0449ce0882f225e6e7ae3edc87becd2e85 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:23 +0700 Subject: [PATCH 152/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Add PWRKEY and RESIN This enables the volume down key as well as the power button. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-5-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index eccbeecef1925..9a6684922804f 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -53,6 +53,16 @@ status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; -- GitLab From cf85e9aee210fefd7a85c1ced0a73382e5edcfd0 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:25 +0700 Subject: [PATCH 153/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD This commit enable the SD card slot and internal MMC. Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-7-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 9a6684922804f..264a8f50db663 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -316,6 +316,25 @@ }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; -- GitLab From e631e904e1d89650e3c8facdfb37cfca3491a52d Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:26 +0700 Subject: [PATCH 154/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple Framebuffer This lets the user sees the framebuffer console. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-8-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 264a8f50db663..95c1518bb52dc 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -20,7 +20,20 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; }; vph_pwr: vph-pwr-regulator { @@ -46,6 +59,11 @@ ftrace-size = <0x0>; pmsg-size = <0x20000>; }; + + framebuffer_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; }; }; -- GitLab From e5d3e752b050e03d2046011a3865721a3f200216 Mon Sep 17 00:00:00 2001 From: Alexey Min Date: Sun, 21 Nov 2021 04:42:27 +0700 Subject: [PATCH 155/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Alexey Min Co-developed-by: Dang Huynh Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-9-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 95c1518bb52dc..d042e3883b9e8 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -65,6 +65,15 @@ no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp1_uart2 { @@ -81,6 +90,13 @@ linux,code = ; }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -356,3 +372,12 @@ &tlmm { gpio-reserved-ranges = <8 4>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; -- GitLab From b70bf26a704c74b3b611e8ff639f1262de19aaef Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Sat, 16 Oct 2021 12:20:23 +0200 Subject: [PATCH 156/965] arm64: dts: freescale: add 'chassis-type' property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on NXP ARM64 processors. Signed-off-by: Arnaud Ferraris Reviewed-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 60d47c71499b3..515446e996996 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -14,6 +14,7 @@ / { model = "Purism Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; + chassis-type = "handset"; backlight_dsi: backlight-dsi { compatible = "led-backlight"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 4f2db6197b392..fa721a13de206 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -12,6 +12,7 @@ / { model = "MNT Reform 2"; compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + chassis-type = "laptop"; pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; -- GitLab From f756f435f7dd823f2d4bd593ce1bf3168def1308 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 16 Oct 2021 23:05:47 +0200 Subject: [PATCH 157/965] soc: imx: gpcv2: Synchronously suspend MIX domains In case the following power domain sequence happens, iMX8M Mini always hangs: gpumix:on -> gpu:on -> gpu:off -> gpu:on This is likely due to another quirk of the GPC block. This situation can be prevented by always synchronously powering off both the domain and MIX domain. Make it so. This turns the aforementioned sequence into: gpumix:on -> gpu:on -> gpu:off -> gpumix:off -> gpumix:on -> gpu:on Signed-off-by: Marek Vasut Cc: Frieder Schrempf Cc: Lucas Stach Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Acked-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index b8d52d8d29dbb..e757044ab7512 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -377,7 +377,7 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } } - pm_runtime_put(domain->dev); + pm_runtime_put_sync_suspend(domain->dev); return 0; -- GitLab From 38c0b9496127da7c8ea0e58fdd256a9e54b1ab8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 18 Oct 2021 15:59:02 +0200 Subject: [PATCH 158/965] arm64: dts: imx: imx8mn-beacon: Drop undocumented clock-names reference The wlf,wm8962 Device Tree bindings do not specify a clock-names property. Drop it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 376ca8ff72133..0f40b43ac091c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -126,7 +126,6 @@ compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "xclk"; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; -- GitLab From f9d3b807daa69728e59a5171e8e7b40cfa848383 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Wed, 20 Oct 2021 16:50:13 +0100 Subject: [PATCH 159/965] ARM: dts: vf610-zii-dev-rev-b: correct phy-mode for 6185 dsa link DT currently lists the port mode for the 88E6352 switch 1 to 88E6185 switch 2 as "rgmii-id" but referring to the schematics, it is in fact a serdes link. The 88E6352 is configured with P5_MODE=6, S_SEL=1 and S_MODE=1, which means port 5 is configured as 1000BASE-X. This is confirmed by the value in the 88E6352 port 5 status register, 0x4e09, where C_MODE=9 meaning 1000BASE-X. It is also confirmed by the 88E6185 port 9 status register, 0x5e8c, where C_MODE=4 meaning cross-chip SERDES mode is selected. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 043ddd70372f0..80698e98dafe1 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -149,7 +149,7 @@ reg = <5>; label = "dsa"; link = <&switch2port9>; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; fixed-link { speed = <1000>; @@ -252,7 +252,7 @@ switch2port9: port@9 { reg = <9>; label = "dsa"; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; link = <&switch1port5 &switch0port5>; -- GitLab From 52c612692848bbe6ae2feb31706911641b17afc9 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Tue, 26 Oct 2021 10:34:23 +0100 Subject: [PATCH 160/965] ARM: dts: vf610-zii-dev-rev-b: specify phy-mode for external PHYs Specify the phy-mode for the external PHYs on the third switch on the ZII development rev B board so phylink and phylib knows what mode these interfaces are configured for. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 80698e98dafe1..1f9686c33a845 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -211,12 +211,14 @@ reg = <0>; label = "lan6"; phy-handle = <&switch2phy0>; + phy-mode = "sgmii"; }; port@1 { reg = <1>; label = "lan7"; phy-handle = <&switch2phy1>; + phy-mode = "sgmii"; }; port@2 { -- GitLab From efe33befc2ffc94248159978902a374c7b2882d0 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:32 +0200 Subject: [PATCH 161/965] ARM: imx: remove dead left-over from i.MX{27,31,35} removal The commits: commit 879c0e5e0ac7 ("ARM: imx: Remove i.MX27 board files") commit c93197b0041d ("ARM: imx: Remove i.MX31 board files") commit e1324ece2af4 ("ARM: imx: Remove i.MX35 board files") remove the config MACH_MX27_3DS, MACH_MX31_3DS and MACH_MX35_3DS. Commit a542fc18168c ("ARM: imx31: Remove remaining i.MX31 board code") further removes arch/arm/mach-imx/3ds_debugboard.{c,h}. So, only some dead left-over in Kconfig and Makefile remains. Remove this remaining left-over. This issue was identified with ./scripts/checkkconfigsymbols.py, which warns on references to the non-existing configs MACH_MX{27,31,35}_3DS in ./arch/arm/mach-imx/Kconfig. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 12 ------------ arch/arm/mach-imx/Makefile | 2 -- 2 files changed, 14 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b407b024dde34..f296bac467c85 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -21,18 +21,6 @@ config MXC_TZIC config MXC_AVIC bool -config MXC_DEBUG_BOARD - bool "Enable MXC debug board(for 3-stack)" - depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS - help - The debug board is an integral part of the MXC 3-stack(PDK) - platforms, it can be attached or removed from the peripheral - board. On debug board, several debug devices(ethernet, UART, - buttons, LEDs and JTAG) are implemented. Between the MCU and - these devices, a CPLD is added as a bridge which performs - data/address de-multiplexing and decode, signal level shift, - interrupt control and various board functions. - config HAVE_IMX_ANATOP bool diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d1506ef7a5374..d5291ed9186af 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -14,8 +14,6 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y) obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o -obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o - ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -- GitLab From b0100bce4ff82ec1ccd3c1f3d339fd2df6a81784 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:33 +0200 Subject: [PATCH 162/965] ARM: imx: rename DEBUG_IMX21_IMX27_UART to DEBUG_IMX27_UART Since commit 4b563a066611 ("ARM: imx: Remove imx21 support"), the config DEBUG_IMX21_IMX27_UART is really only debug support for IMX27. So, rename this option to DEBUG_IMX27_UART and adjust dependencies in Kconfig and rename the definitions to IMX27 as further clean-up. This issue was discovered with ./scripts/checkkconfigsymbols.py, which reported that DEBUG_IMX21_IMX27_UART depends on the non-existing config SOC_IMX21. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/Kconfig.debug | 14 +++++++------- arch/arm/include/debug/imx-uart.h | 18 +++++++++--------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 98436702e0c7e..644875d73ba15 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -410,12 +410,12 @@ choice Say Y here if you want kernel low-level debugging support on i.MX25. - config DEBUG_IMX21_IMX27_UART - bool "i.MX21 and i.MX27 Debug UART" - depends on SOC_IMX21 || SOC_IMX27 + config DEBUG_IMX27_UART + bool "i.MX27 Debug UART" + depends on SOC_IMX27 help Say Y here if you want kernel low-level debugging support - on i.MX21 or i.MX27. + on i.MX27. config DEBUG_IMX28_UART bool "i.MX28 Debug UART" @@ -1481,7 +1481,7 @@ config DEBUG_IMX_UART_PORT int "i.MX Debug UART Port Selection" depends on DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ - DEBUG_IMX21_IMX27_UART || \ + DEBUG_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX50_UART || \ @@ -1540,12 +1540,12 @@ config DEBUG_LL_INCLUDE default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ - DEBUG_IMX21_IMX27_UART || \ + DEBUG_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX50_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX53_UART ||\ + DEBUG_IMX53_UART || \ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index c8eb83d4b8964..3edbb3c5b42bf 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -11,13 +11,6 @@ #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) -#define IMX21_UART1_BASE_ADDR 0x1000a000 -#define IMX21_UART2_BASE_ADDR 0x1000b000 -#define IMX21_UART3_BASE_ADDR 0x1000c000 -#define IMX21_UART4_BASE_ADDR 0x1000d000 -#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR -#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) - #define IMX25_UART1_BASE_ADDR 0x43f90000 #define IMX25_UART2_BASE_ADDR 0x43f94000 #define IMX25_UART3_BASE_ADDR 0x5000c000 @@ -26,6 +19,13 @@ #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) +#define IMX27_UART1_BASE_ADDR 0x1000a000 +#define IMX27_UART2_BASE_ADDR 0x1000b000 +#define IMX27_UART3_BASE_ADDR 0x1000c000 +#define IMX27_UART4_BASE_ADDR 0x1000d000 +#define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR +#define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n) + #define IMX31_UART1_BASE_ADDR 0x43f90000 #define IMX31_UART2_BASE_ADDR 0x43f94000 #define IMX31_UART3_BASE_ADDR 0x5000c000 @@ -112,10 +112,10 @@ #ifdef CONFIG_DEBUG_IMX1_UART #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) -#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) -#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) #elif defined(CONFIG_DEBUG_IMX25_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) +#elif defined(CONFIG_DEBUG_IMX27_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX27) #elif defined(CONFIG_DEBUG_IMX31_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) #elif defined(CONFIG_DEBUG_IMX35_UART) -- GitLab From 745fa3e40ff5245c8551f2ec9ad9d3c77c8065e7 Mon Sep 17 00:00:00 2001 From: Meng Li Date: Wed, 3 Nov 2021 11:38:38 +0800 Subject: [PATCH 163/965] arm64: dts: fsl-ls1043a-rdb: add delay between CS and CLK signal for flash device Based on commit d59c90a2400f("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode ") and 6c1c26ecd9a3("spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible"), on ls1043a-rdb platform, the spi work mode is changed from TCFQ mode to XSPI mode. In order to keep the transmission sequence matches with flash device, it is need to add delay between CS and CLK signal. The strategy of generating delay value refers to QorIQ LS1043A Reference Manual. Signed-off-by: Meng Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index 3516af4726a5d..b290605e92cfb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -94,6 +94,8 @@ compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; }; slic@2 { -- GitLab From 3ac5f9db26bb7a227ccbf160c36a5567b5394299 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sun, 21 Nov 2021 17:05:58 +0200 Subject: [PATCH 164/965] ARM: samsung: Remove HAVE_S3C2410_I2C and use direct dependencies A separate Kconfig option HAVE_S3C2410_I2C for Samsung SoCs is not really needed and the i2c-s3c24xx driver can depend on Samsung ARM architectures instead. This also enables i2c-s3c2410 for arm64 Exynos SoCs, which is required for example by Exynos850. This is basically continuation of work made in following commits: - commit d96890fca9fd ("rtc: s3c: remove HAVE_S3C_RTC in favor of direct dependencies") - commit 7dd3cae90d85 ("ARM: samsung: remove HAVE_S3C2410_WATCHDOG and use direct dependencies") Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211121150558.21801-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/Kconfig | 1 - arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-s3c/Kconfig.s3c64xx | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - drivers/i2c/busses/Kconfig | 10 ++-------- 5 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0f9e8bec83ac..391f07c170962 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -479,7 +479,6 @@ config ARCH_S3C24XX select GPIO_SAMSUNG select GPIOLIB select GENERIC_IRQ_MULTI_HANDLER - select HAVE_S3C2410_I2C if I2C select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index dd1ae5571f431..f7d993628cb70 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -20,7 +20,6 @@ menuconfig ARCH_EXYNOS select GPIOLIB select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_SCU if SMP - select HAVE_S3C2410_I2C if I2C select PINCTRL select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx index f3fcb570edf56..af01675d8769b 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c64xx +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -12,7 +12,6 @@ menuconfig ARCH_S3C64XX select COMMON_CLK_SAMSUNG select GPIO_SAMSUNG if ATAGS select GPIOLIB - select HAVE_S3C2410_I2C if I2C select HAVE_TCM select PLAT_SAMSUNG select PM_GENERIC_DOMAINS if PM diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 5a96099af9913..055de578b57fa 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -12,7 +12,6 @@ config ARCH_S5PV210 select CLKSRC_SAMSUNG_PWM select COMMON_CLK_SAMSUNG select GPIOLIB - select HAVE_S3C2410_I2C if I2C select PINCTRL select PINCTRL_EXYNOS select SOC_SAMSUNG diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index dce3928390176..c6b854a9e4761 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -963,16 +963,10 @@ config I2C_RK3X This driver can also be built as a module. If so, the module will be called i2c-rk3x. -config HAVE_S3C2410_I2C - bool - help - This will include I2C support for Samsung SoCs. If you want to - include I2C support for any machine, kindly select this in the - respective Kconfig file. - config I2C_S3C2410 tristate "S3C/Exynos I2C Driver" - depends on HAVE_S3C2410_I2C || COMPILE_TEST + depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || \ + ARCH_S5PV210 || COMPILE_TEST help Say Y here to include support for I2C controller in the Samsung SoCs (S3C, S5Pv210, Exynos). -- GitLab From c681c6fcc5ddfa0492ca015b0bf325cd4881ce07 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 27 Oct 2021 16:37:26 +0200 Subject: [PATCH 165/965] arm64: dts: rockchip: add interrupt and headphone-detection for Rock Pi4's audio codec As schematics at [1] and [2] show C- and plus-revisions have interrupt and headphone detection lines of ES8316 codec connected. Add them to the respective device trees. [1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf [2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4b_plus_v16_sch_20200628.pdf Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20211027143726.165809-2-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 12 +++++++++++- .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 11 +++++++++++ .../boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 11 +++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 98136c88fa497..54f5957e704cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -36,7 +36,7 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; - sound { + sound: sound { compatible = "audio-graph-card"; label = "Analog"; dais = <&i2s0_p0>; @@ -543,6 +543,16 @@ }; }; + es8316 { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hp_int: hp-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts index 281a04b2f5e92..f5a68d8d072d2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts @@ -12,3 +12,14 @@ model = "Radxa ROCK Pi 4A+"; compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; }; + +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index dfad13d2ab249..81bea953c891c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 99169bcd51c03..0ad7b6e22f701 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; -- GitLab From e92df2c61c1046d26379b97141e1e968f3ccc63d Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Tue, 26 Oct 2021 10:07:47 -0500 Subject: [PATCH 166/965] arm64: dts: rockchip: define usb hub and 2.5GbE nic on helios64 Add the 4 ports on the internal hub and define and turn on the 2.5GbE nic. Signed-off-by: Dennis Gilmore Tested-by: Florian Klink Link: https://lore.kernel.org/r/20211026150751.70115-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 63c7681843daa..8767dd2891ae7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -101,6 +101,18 @@ vin-supply = <&vcc5v0_perdev>; }; + usblan_power: usblan-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_lan_en>; + regulator-name = "usblan_power"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_usb>; + }; + vcc1v8_sys_s0: vcc1v8-sys-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys_s0"; @@ -432,6 +444,10 @@ vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + usb_lan_en: usb-lan-en { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; vcc3v0-sd { @@ -530,5 +546,41 @@ usb@fe900000 { dr_mode = "host"; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb2109,0815"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + + port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + + device@4 { + compatible = "usbbda,8156"; + reg = <4>; + #address-cells = <2>; + #size-cells = <0>; + + interface@0 { /* interface 0 of configuration 1 */ + compatible = "usbbda,8156.config1.0"; + reg = <0 1>; + }; + }; + }; }; }; -- GitLab From 755fff528b1b760c700dbf39928ff3dda825f748 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Thu, 28 Oct 2021 19:53:19 -0500 Subject: [PATCH 167/965] arm64: dts: rockchip: add variables for pcie completion to helios64 without ep-gpios defined u-boot does not initialise PCIe rockchip_pcie pcie@f8000000: failed to find ep-gpios property additionally set max-link-speed and pinctrl-names for completeness with this patch and the ones from Florian Klink applied to the dts file in u-boot sata drives show up in both u-boot and linux Signed-off-by: Dennis Gilmore Acked-By: Florian Klink Link: https://lore.kernel.org/r/20211029005323.144652-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 8767dd2891ae7..ac193e5a22952 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -401,7 +401,10 @@ }; &pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; num-lanes = <2>; + pinctrl-names = "default"; status = "okay"; vpcie12v-supply = <&vcc12v_dcin>; -- GitLab From 8169b9894dbd2d4e440cfbc5fe9f733e5876a564 Mon Sep 17 00:00:00 2001 From: Florian Klink Date: Wed, 20 Oct 2021 11:59:22 +0200 Subject: [PATCH 168/965] arm64: dts: rockchip: Enable HDD power on helios64 This adds the hdd_{a,b}_power blocks present in the armbian helios64 dts. [1] Without those powered up, no HDDs will appear (except one connected via the m.2 slot). >From https://wiki.kobol.io/helios64/sata/#hdd-power: > The power delivery of the HDDs is divided into two group: > > HDD Rail A (Max. 3x Drives) > HDD Rail B (Max. 2x Drives) > > Helios64 implements a power staggering approach where HDD Rail A will be > powered up first, then few seconds later HDD Rail B will be powered up. > This power control scenario is performed to reduce the inrush current > during disk spin-up. In practice, this power staggering approach will be included in the bootloader (not in the kernel), as we might want to boot from a SATA drive. >From my experiments, if the bootloader doesn't implement the power staggering, only one HDD will get recognized (probably cause the others didn't boot due to few power). Still, it makes sense to expose this block in the device-tree, so the kernel can ensure both rails are on (and this can be shared with u-boot). [1] https://github.com/armbian/build/blob/744ea89a589d62cb6f409baab60fc6664520bc39/patch/kernel/archive/rockchip64-5.14/add-board-helios64.patch Signed-off-by: Florian Klink Tested-by: Dennis Gilmore Link: https://lore.kernel.org/r/20211020095926.735938-1-flokli@flokli.de Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index ac193e5a22952..627ee88e9dc21 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -89,6 +89,30 @@ }; }; + hdd_a_power: hdd-a-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_a_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_a_power"; + startup-delay-us = <2000000>; + }; + + hdd_b_power: hdd-b-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_b_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_b_power"; + startup-delay-us = <2000000>; + }; + pcie_power: pcie-power { compatible = "regulator-fixed"; enable-active-high; @@ -444,6 +468,14 @@ }; power { + hdd_a_power_en: hdd-a-power-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd_b_power_en: hdd-b-power-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; -- GitLab From e3f775070e06bb9b5c29c499a98de95cb5cad7cf Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 4 Nov 2021 07:34:11 -0500 Subject: [PATCH 169/965] arm64: dts: imx8mm-beacon: Enable USB Controllers The i.MX8M Mini has two available USB controllers. On the imx8mm-beacon board, USB1 is routed to a mini-USB port with OTG functionality. USB2 is routed to a USB hub which has three host-only ports connected to it. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../freescale/imx8mm-beacon-baseboard.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 6f5e63696ec0a..4097a66163b2a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -43,6 +43,17 @@ enable-active-high; }; + reg_usbotg1: regulator-usbotg1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -169,6 +180,24 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usbotg1>; + disable-over-current; + dr_mode="otg"; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + disable-over-current; + dr_mode="host"; + status = "okay"; +}; + +&usbphynop2 { + reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -215,6 +244,12 @@ >; }; + pinctrl_reg_usb_otg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -- GitLab From b43e6c03a85423db959f88d96ddd682e5c09f8fd Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:10 +0100 Subject: [PATCH 170/965] arm64: dts: split out a shared imx8mq-librem5-r3.dtsi description The Librem 5 r3 ("Dogwood") and r4 ("Evergreen") revisions are quite similar. Add a shared imx8mq-librem5-r3.dtsi description to be included in r3 and later dts files in order to avoid duplication. This is no change in the descriptions but only refactoring. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5-r3.dts | 25 ++------------- .../boot/dts/freescale/imx8mq-librem5-r3.dtsi | 32 +++++++++++++++++++ .../boot/dts/freescale/imx8mq-librem5-r4.dts | 16 ++-------- 3 files changed, 36 insertions(+), 37 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts index cd3c3edd48fa3..4533a84fb0b95 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts @@ -1,14 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC +// Copyright (C) 2021 Purism SPC /dts-v1/; -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; +#include "imx8mq-librem5-r3.dtsi" &a53_opp_table { opp-1000000000 { @@ -16,22 +11,6 @@ }; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &buck3_reg { regulator-always-on; }; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi new file mode 100644 index 0000000000000..e872eb4b1cf97 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2021 Purism SPC + +/dts-v1/; + +/* + * This file describes hardware that is shared among r3 ("Dogwood") and + * later revisions of the Librem 5 so it has to be included in dts there. + */ + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index cbfb49aa2563d..30d65bef69391 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -1,31 +1,19 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC +// Copyright (C) 2021 Purism SPC /dts-v1/; -#include "imx8mq-librem5.dtsi" +#include "imx8mq-librem5-r3.dtsi" / { model = "Purism Librem 5r4"; compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - &bat { maxim,rsns-microohm = <1667>; }; -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &led_backlight { led-max-microamp = <25000>; }; -- GitLab From 1019b783696aa0705517d8a23f29dbbc8ec64048 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:11 +0100 Subject: [PATCH 171/965] arm64: dts: imx8mq-librem5: describe power supply for cameras CAMERA_PWR_EN controls two different power supplies that cameras will use. The hardware killswitch controls a third one. Describe that appropriately. The pinctrl that describes the gpio that is used in 2 places here is added to the pmic. This is done because pmic is powered early enough to make sure this will work. When we would have put the same pinctrl property into the 2 regulator nodes (instead of the pmic), we'd get: imx8mq-pinctrl 30330000.pinctrl: pin MX8MQ_IOMUXC_GPIO1_IO00 already requested by regulator-csi-1v8; cannot claim for regulator-vcam-2v8 imx8mq-pinctrl 30330000.pinctrl: pin-10 (regulator-vcam-2v8) status -22 imx8mq-pinctrl 30330000.pinctrl: could not request pin 10 (MX8MQ_IOMUXC_GPIO1_IO00) from group camerapwrgrp on device 30330000.pinctrl Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 515446e996996..0c0e2602c20ac 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -63,6 +63,40 @@ enable-active-high; }; + /* + * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC + * since we can't have it twice in the 2 different regulator nodes. + */ + reg_csi_1v8: regulator-csi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* controlled by the CAMERA_POWER_KEY HKS */ + reg_vcam_1v2: regulator-vcam-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_vdd_1v8>; + enable-active-high; + }; + + reg_vcam_2v8: regulator-vcam-2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_gnss: regulator-gnss { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -330,6 +364,20 @@ >; }; + pinctrl_camera_pwr: camerapwrgrp { + fsl,pins = < + /* CAMERA_PWR_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + /* CSI1_NRST */ + MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ @@ -726,7 +774,7 @@ compatible = "rohm,bd71837"; reg = <0x4b>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; + pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; -- GitLab From fed7603597fa660219eb49ef7ed37fafd42f9869 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:12 +0100 Subject: [PATCH 172/965] arm64: dts: imx8mq-librem5: describe the selfie cam Enable the CSI1 MIPI RX controller and CSI1 bridge on the SoC. Describe the Librem 5 front-facing camera, connected to the CSI1 MIPI. the following sets formats, streams 10 frames and saves one: #!/bin/bash WIDTH=1632 HEIGHT=1224 SKIP=10 media-ctl -d "platform:30a90000.csi" --set-v4l2 "'csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'imx8mq-mipi-csi2 30a70000.csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'hi846 2-0020':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" -l "'hi846 2-0020':0 -> 'imx8mq-mipi-csi2 30a70000.csi':0 [1]" v4l2-ctl -d "/dev/v4l/by-path/platform-30a90000.csi-video-index0" --set-fmt-video=width=${WIDTH},height=${HEIGHT},pixelformat=GB16 --stream-mmap --stream-to=$WIDTH.raw --stream-skip=$SKIP --stream-count=1 Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0c0e2602c20ac..f3e3418f7edc0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -272,6 +272,10 @@ cpu-supply = <&buck2_reg>; }; +&csi1 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -1007,6 +1011,31 @@ >; }; + camera_front: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-rates = <25000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + vdda-supply = <®_vcam_2v8>; + vddd-supply = <®_vcam_1v2>; + vddio-supply = <®_csi_1v8>; + rotation = <90>; + orientation = <0>; + + port { + camera1_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <80000000 200000000 300000000>; + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + backlight@36 { compatible = "ti,lm36922"; reg = <0x36>; @@ -1080,6 +1109,23 @@ status = "okay"; }; +&mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi1_sensor_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; -- GitLab From c190510714df168b9d6387bc29844acbe9a39521 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:13 +0100 Subject: [PATCH 173/965] arm64: dts: imx8mq-librem5-r3.dtsi: describe selfie cam XSHUTDOWN pin The r3 and later revisions of the Librem 5 phone include an additional switch to control the hi846 XSHUTDOWN pin. Describe it. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index e872eb4b1cf97..e4f8b47cce4f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -27,6 +27,19 @@ ti,termination-current = <144000>; /* uA */ }; +&camera_front { + pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_r3_camera_pwr: r3camerapwrgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 + >; + }; +}; + &proximity { proximity-near-level = <25>; }; -- GitLab From f7e47d85f3f5913bcf508589c8dabbfbd3f4fe56 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 21 Nov 2021 12:50:02 +0100 Subject: [PATCH 174/965] arm64: dts: allwinner: h6: tanix-tx6: Add I2C node Tanix TX6 has a LED display driven by FD650. Currently there is no Linux driver nor any binding for it. However, we can at least provide I2C node in DT, so user space scripts or programs can manually control it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211121115002.693329-1-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 6c10ff7f4b1ca..7c37aa4c60cb9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -32,6 +32,14 @@ }; }; + /* used for FD650 LED display driver */ + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ + scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ + i2c-gpio,delay-us = <5>; + }; + reg_vcc1v8: regulator-vcc1v8 { compatible = "regulator-fixed"; regulator-name = "vcc1v8"; -- GitLab From 725bc607aa02d570c35c5f21c3eadc3342bf4e06 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 21 Nov 2021 08:03:21 +0100 Subject: [PATCH 175/965] ARM: dts: sun8i: h3: beelink-x2: Sort nodes Nodes are not sorted alphabetically. Do it. There is no functional change. Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211121070321.601659-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index f0e591e1c7717..9dfd1a86b6c60 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -87,11 +87,15 @@ }; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; + r-gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; }; sound_spdif { @@ -112,15 +116,11 @@ compatible = "linux,spdif-dit"; }; - r-gpio-keys { - compatible = "gpio-keys"; - - power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; -- GitLab From 3047444def125d9e1fb788541e8dc18a7058a47a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 08:34:47 +0100 Subject: [PATCH 176/965] arm64: dts: allwinner: a64: Add CEC clock to HDMI Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120073448.32480-2-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5ba379078500f..741bd19fa8ec2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1220,8 +1220,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; -- GitLab From 38df5750962c61b96d4e53358f31955fe310d4f5 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 08:34:48 +0100 Subject: [PATCH 177/965] ARM: dts: sunxi: Add CEC clock to DW-HDMI Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 4 ++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee4..f10436b7869c1 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -1212,8 +1212,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c7428df9469e6..d1e974886fdf1 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -813,8 +813,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; -- GitLab From bbdde16e5d7ebfd2e04bc41f800ebbd5468336b1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 11:20:24 +0100 Subject: [PATCH 178/965] ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has dedicated GPIO pin for that purpose. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120102024.439456-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 9dfd1a86b6c60..cd9f655e4f924 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -57,6 +57,12 @@ ethernet1 = &sdiowifi; }; + cec-gpio { + compatible = "cec-gpio"; + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ + hdmi-phandle = <&hdmi>; + }; + chosen { stdout-path = "serial0:115200n8"; }; -- GitLab From 34734edd06f84290a3fc6f2a4ae61969e9d25801 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Nov 2021 15:32:55 +0100 Subject: [PATCH 179/965] dt-bindings: crypto: Add optional dma properties Some platforms, like the v3s, have DMA channels assigned to the crypto engine, which were in the DTSI but were never documented. Let's make sure they are. Signed-off-by: Maxime Ripard Acked-by: Corentin Labbe Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20211116143255.385480-1-maxime@cerno.tech --- .../bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 0429fb774f10e..dedc99e34ebcf 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -44,6 +44,16 @@ properties: - const: ahb - const: mod + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx + resets: maxItems: 1 -- GitLab From 2602dc10f9d930bcc537467d13de4cfbfaa2126d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 21 Nov 2021 18:01:55 +0000 Subject: [PATCH 180/965] memory: renesas-rpc-if: Silence clang warning This patch silences the following clang warning: | drivers/memory/renesas-rpc-if.c:253:14: warning: cast to smaller integer | type 'enum rpcif_type' from 'const void *' [-Wvoid-pointer-to-enum-cast] | rpc->type = (enum rpcif_type)of_device_get_match_data(dev); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: b04cc0d912eb8 ("memory: renesas-rpc-if: Add support for RZ/G2L") Reported-by: kernel test robot Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211121180155.9062-1-prabhakar.mahadev-lad.rj@bp.renesas.com [krzysztof: drop enum rpcif_type cast] Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 8c51145c0f5cb..77c53cd4e1d5b 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -250,7 +250,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) return PTR_ERR(rpc->dirmap); rpc->size = resource_size(res); - rpc->type = (enum rpcif_type)of_device_get_match_data(dev); + rpc->type = (uintptr_t)of_device_get_match_data(dev); rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); return PTR_ERR_OR_ZERO(rpc->rstc); -- GitLab From 2db468d6fda4c33d26ba9dde7c72e081b2b86ad1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 17 Nov 2021 11:29:02 +0100 Subject: [PATCH 181/965] memory: renesas-rpc-if: simplify register update No need to open code regmap_update_bits(). Signed-off-by: Wolfram Sang Tested-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211117102902.20062-1-wsa+renesas@sang-engineering.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 77c53cd4e1d5b..edd7eb4486e13 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -259,17 +259,14 @@ EXPORT_SYMBOL(rpcif_sw_init); static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc) { - u32 data; - regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); - - regmap_read(rpc->regmap, RPCIF_PHYCNT, &data); - regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3)); + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3), + RPCIF_PHYCNT_CKSEL(3)); regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); } -- GitLab From 57ea9daad51f7707f61a602a743decf10cf9fea9 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 17 Nov 2021 10:37:10 +0100 Subject: [PATCH 182/965] memory: renesas-rpc-if: avoid use of undocumented bits Instead of writing fixed values with undocumented bits which happen to be set on some SoCs, better switch to read-modify-write operations changing only bits which are documented. This is way more future-proof as we don't know yet how these bits may be on upcoming SoCs. Signed-off-by: Wolfram Sang Tested-by: Lad Prabhakar Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211117093710.14430-1-wsa+renesas@sang-engineering.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 58 +++++++++++++-------------------- 1 file changed, 22 insertions(+), 36 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index edd7eb4486e13..ccd662ee2acbf 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -20,7 +20,6 @@ #define RPCIF_CMNCR 0x0000 /* R/W */ #define RPCIF_CMNCR_MD BIT(31) -#define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */ #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) @@ -287,49 +286,36 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) rpcif_rzg2l_timing_adjust_sdr(rpc); } - /* - * NOTE: The 0x260 are undocumented bits, but they must be set. - * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits, - * 0x0 : the delay is biggest, - * 0x1 : the delay is 2nd biggest, - * On H3 ES1.x, the value should be 0, while on others, - * the value should be 7. - */ - if (rpc->type == RPCIF_RCAR_GEN3) { - regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) | - RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260); - } else { - regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy); - dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK; - dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260; - regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy); - } + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); + + if (rpc->type == RPCIF_RCAR_GEN3) + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, + RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); - /* - * NOTE: The 0x1511144 are undocumented bits, but they must be set - * for RPCIF_PHYOFFSET1. - * The 0x31 are undocumented bits, but they must be set - * for RPCIF_PHYOFFSET2. - */ - regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 | - RPCIF_PHYOFFSET1_DDRTMG(3)); - regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 | - RPCIF_PHYOFFSET2_OCTTMG(4)); + regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), + RPCIF_PHYOFFSET1_DDRTMG(3)); + regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7), + RPCIF_PHYOFFSET2_OCTTMG(4)); if (hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYINT, RPCIF_PHYINT_WPVAL, 0); if (rpc->type == RPCIF_RCAR_GEN3) - regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | - RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | - RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + regmap_update_bits(rpc->regmap, RPCIF_CMNCR, + RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_BSZ(3), + RPCIF_CMNCR_MOIIO_HIZ | + RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); else - regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | - RPCIF_CMNCR_MOIIO3(1) | RPCIF_CMNCR_MOIIO2(1) | - RPCIF_CMNCR_MOIIO1(1) | RPCIF_CMNCR_MOIIO0(1) | - RPCIF_CMNCR_IO3FV(2) | RPCIF_CMNCR_IO2FV(2) | - RPCIF_CMNCR_IO0FV(2) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + regmap_update_bits(rpc->regmap, RPCIF_CMNCR, + RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | + RPCIF_CMNCR_BSZ(3), + RPCIF_CMNCR_MOIIO3(1) | RPCIF_CMNCR_MOIIO2(1) | + RPCIF_CMNCR_MOIIO1(1) | RPCIF_CMNCR_MOIIO0(1) | + RPCIF_CMNCR_IO3FV(2) | RPCIF_CMNCR_IO2FV(2) | + RPCIF_CMNCR_IO0FV(2) | + RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); /* Set RCF after BSZ update */ regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); -- GitLab From 3542de6a5b159fac0e7ca84d77a57ea99125d6b1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 19 Nov 2021 12:04:42 +0100 Subject: [PATCH 183/965] memory: renesas-rpc-if: refactor MOIIO and IOFV macros Don't use _HIZ macros but also provide a val. This is more consistent with the other macros and, thus, easier to read. Also shorter. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211119110442.4946-1-wsa+renesas@sang-engineering.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index ccd662ee2acbf..e4cc64f560196 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -24,14 +24,13 @@ #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) -#define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \ - RPCIF_CMNCR_MOIIO1(3) | \ - RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3)) +#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \ + RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val)) #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */ #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */ #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) -#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \ - RPCIF_CMNCR_IO3FV(3)) +#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \ + RPCIF_CMNCR_IO3FV(val)) #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) #define RPCIF_SSLDR 0x0004 /* R/W */ @@ -304,17 +303,14 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) if (rpc->type == RPCIF_RCAR_GEN3) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, - RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_BSZ(3), - RPCIF_CMNCR_MOIIO_HIZ | + RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), + RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); else regmap_update_bits(rpc->regmap, RPCIF_CMNCR, - RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | + RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(3), - RPCIF_CMNCR_MOIIO3(1) | RPCIF_CMNCR_MOIIO2(1) | - RPCIF_CMNCR_MOIIO1(1) | RPCIF_CMNCR_MOIIO0(1) | - RPCIF_CMNCR_IO3FV(2) | RPCIF_CMNCR_IO2FV(2) | - RPCIF_CMNCR_IO0FV(2) | + RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); /* Set RCF after BSZ update */ -- GitLab From 8e0150fe5cf5b86df55257d800258e57d7d34202 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:53 +0900 Subject: [PATCH 184/965] ARM: dts: milbeaut: add a clock node for M10V Add a clock node for the platform of the Milbeaut M10V. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-2-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index aa7c6caeb7507..28aee25d939e4 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -65,6 +65,13 @@ <0x1d002000 0x1000>; /* CPU I/f base and size */ }; + clk: clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + timer@1e000050 { /* 32-bit Reload Timers */ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; -- GitLab From 2fc4dfc294eef022889e56ebcd4f0c6c6e34e3c5 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:54 +0900 Subject: [PATCH 185/965] ARM: dts: milbeaut: set clock phandle to timer node Set clock phandle to timer node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-3-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 28aee25d939e4..9f70784bad0c0 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -76,6 +76,7 @@ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; interrupts = <0 91 4>; + clocks = <&clk 4>; }; uart1: serial@1e700010 { /* PE4, PE5 */ -- GitLab From 69a25d34f377b5602d188a05827f6173c26ff0de Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:55 +0900 Subject: [PATCH 186/965] ARM: dts: milbeaut: set clock phandle to uart node Set clock phandle to uart node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-4-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 9f70784bad0c0..75f0c0af22705 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -85,6 +85,7 @@ reg = <0x1e700010 0x10>; interrupts = <0 141 0x4>, <0 149 0x4>; interrupt-names = "rx", "tx"; + clocks = <&clk 2>; }; }; -- GitLab From 8aa35e0bb5eaa42bac415ad0847985daa7b4890c Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 21 Jun 2021 20:08:28 +0200 Subject: [PATCH 187/965] soc: ti: pruss: fix referenced node in error message So far, "(null)" is reported for the node that is missing clocks. Signed-off-by: Jan Kiszka Acked-by: Suman Anna Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/d6e24953-ea89-fd1c-6e16-7a0142118054@siemens.com --- drivers/soc/ti/pruss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 49da387d77494..b36779309e49b 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -129,7 +129,7 @@ static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node) clks_np = of_get_child_by_name(cfg_node, "clocks"); if (!clks_np) { - dev_err(dev, "%pOF is missing its 'clocks' node\n", clks_np); + dev_err(dev, "%pOF is missing its 'clocks' node\n", cfg_node); return -ENODEV; } -- GitLab From 7c1c1d36e83073aab18d3dd596b735bcc6ea7984 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sun, 14 Nov 2021 13:53:33 +0800 Subject: [PATCH 188/965] firmware: ti_sci: rm: remove unneeded semicolon The semicolon after `}' is unneeded. So, just remove it. Signed-off-by: Jason Wang Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20211114055333.217919-1-wangborong@cdjrlc.com --- drivers/firmware/ti_sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 235c7e7869aa7..5ae2040b8b02a 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1759,7 +1759,7 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, desc->num = resp->range_num; desc->start_sec = resp->range_start_sec; desc->num_sec = resp->range_num_sec; - }; + } fail: ti_sci_put_one_xfer(&info->minfo, xfer); -- GitLab From cb551b5e3bab54265f374a394e239f5e492a5742 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:02 +0800 Subject: [PATCH 189/965] arm64: dts: imx8m: add cache info i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache. - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache. So add the cache info in device tree and let use could see that from /sys/devices/system/cpu/cpu[x]/cache/ Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 28 +++++++++++++++++++++++ 4 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e2..5b9c2cca9ac4b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -65,6 +65,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -80,6 +86,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -93,6 +105,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -106,6 +124,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -114,6 +138,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index da6c942fb7f9d..ba23b416b5e6c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -63,6 +63,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -78,6 +84,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -91,6 +103,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -104,6 +122,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -112,6 +136,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 04d259de56676..977783784342b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -51,6 +51,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -62,6 +68,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -84,12 +102,22 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15e..95d8b95d61203 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -102,6 +102,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -116,6 +122,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -128,6 +140,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -140,6 +158,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -147,6 +171,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; -- GitLab From b0b46118ed265592b935d7a39098c24f20c49620 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:03 +0800 Subject: [PATCH 190/965] arm64: dts: imx8qm: add cache info i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - L2Cache is 16-way set-associative - Line size are 64bytes Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index aebbe2b84aa13..4a7c017b5f31c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -57,6 +57,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -65,6 +71,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -73,6 +85,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -81,6 +99,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -89,6 +113,12 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&A72_L2>; }; @@ -102,10 +132,18 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; A72_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; -- GitLab From ebd922967f33be0ace3f53b2143f77c167c7e99d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:04 +0800 Subject: [PATCH 191/965] arm64: dts: imx8qxp: add cache info i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 8-way set associative - Line size are 64bytes Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 617618edf77e0..dbec7c106e0b6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -58,6 +58,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -69,6 +75,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -80,6 +92,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -91,6 +109,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -99,6 +123,10 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; -- GitLab From 95f04048325cb808f4ca98f0a4d075bbb23576f8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 20 Jun 2021 00:42:59 +0200 Subject: [PATCH 192/965] ARM: dts: ux500: Add reset lines to IP blocks The new reset controller makes is possible to add reset lines to a host of IP blocks in the DB8500/U8500. Cc: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 68607e4ad80cb..dc0bcc7020f1a 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -300,6 +301,10 @@ #clock-cells = <2>; }; + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + rtc_clk: rtc32k-clock { #clock-cells = <0>; }; @@ -662,6 +667,7 @@ clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; status = "disabled"; }; @@ -680,6 +686,7 @@ clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; status = "disabled"; }; @@ -698,6 +705,7 @@ clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; status = "disabled"; }; @@ -716,6 +724,7 @@ clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; status = "disabled"; }; @@ -734,6 +743,7 @@ clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; status = "disabled"; }; @@ -750,6 +760,7 @@ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; status = "disabled"; }; @@ -766,6 +777,7 @@ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; status = "disabled"; }; @@ -834,6 +846,7 @@ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; status = "disabled"; }; @@ -849,6 +862,7 @@ clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; status = "disabled"; }; @@ -864,6 +878,7 @@ clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; status = "disabled"; }; @@ -879,6 +894,7 @@ clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; status = "disabled"; }; @@ -895,6 +911,7 @@ clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; status = "disabled"; }; @@ -911,6 +928,7 @@ clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; status = "disabled"; }; @@ -927,6 +945,7 @@ clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; status = "disabled"; }; @@ -943,6 +962,7 @@ clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; status = "disabled"; }; @@ -959,6 +979,7 @@ clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; status = "disabled"; }; @@ -975,6 +996,7 @@ clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; status = "disabled"; }; @@ -996,6 +1018,7 @@ clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; status = "disabled"; }; @@ -1012,6 +1035,7 @@ clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; status = "disabled"; }; @@ -1030,6 +1054,7 @@ clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; status = "disabled"; }; @@ -1046,6 +1071,7 @@ clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; status = "disabled"; }; -- GitLab From 71b597ef5d46a326fb0d5cbfc1c6ff1d73cdc7f9 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:36 -0600 Subject: [PATCH 193/965] dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq The MBUS node needs to reference the CLK_DRAM clock, as the MBUS hardware implements memory dynamic frequency scaling using this clock. Export this clock for SoCs which will be getting a devfreq driver. Acked-by: Rob Herring Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-2-samuel@sholland.org --- drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 2 -- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 2 -- include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +- 4 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h index 54d1f96f4b689..a8c11c0b4e067 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -51,8 +51,6 @@ #define CLK_USB_OHCI1_12M 92 -#define CLK_DRAM 94 - /* All the DRAM gates are exported */ /* And the DSI and GPU module clock is exported */ diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index d8c38447e11b6..e13f3c4b57d01 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -42,8 +42,6 @@ /* The first bunch of module clocks are exported */ -#define CLK_DRAM 96 - /* All the DRAM gates are exported */ /* Some more module clocks are exported */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index 318eb15c414ce..175892189e9dc 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -113,7 +113,7 @@ #define CLK_USB_OHCI0 91 #define CLK_USB_OHCI1 93 - +#define CLK_DRAM 94 #define CLK_DRAM_VE 95 #define CLK_DRAM_CSI 96 #define CLK_DRAM_DEINTERLACE 97 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index 30d2d15373a25..5d4ada2c22e60 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -126,7 +126,7 @@ #define CLK_USB_OHCI1 93 #define CLK_USB_OHCI2 94 #define CLK_USB_OHCI3 95 - +#define CLK_DRAM 96 #define CLK_DRAM_VE 97 #define CLK_DRAM_CSI 98 #define CLK_DRAM_DEINTERLACE 99 -- GitLab From 245578ba9f03e07132bcaf60cbdfeb0e89457104 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:37 -0600 Subject: [PATCH 194/965] dt-bindings: arm: sunxi: Expand MBUS binding The MBUS provides more than address translation and bandwidth control. It also provides a PMU to measure bandwidth usage by certain masters, and it provides notification via IRQ when they are active or idle. The MBUS is also tightly integrated with the DRAM controller to provide a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the MBUS binding needs to represent the hardware resources needed for MDFS, which include the clocks and MMIO range of the adjacent DRAM controller. Add the additional resources for the H3 and A64 compatibles, and a new example showing how they are used. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-3-samuel@sholland.org --- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 29c9961ee2d8c..2b3829e0e240c 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -34,10 +34,35 @@ properties: - allwinner,sun50i-a64-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth limit/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + minItems: 1 + items: + - const: mbus + - const: dram clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + minItems: 1 + items: + - const: mbus + - const: dram + - const: bus + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -54,13 +79,54 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + additionalProperties: false examples: - | - #include + #include + #include - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -70,4 +136,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ... -- GitLab From 9f193dedd6efeb4e193d706856f26fcf11ae0ff2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:38 -0600 Subject: [PATCH 195/965] dt-bindings: arm: sunxi: Add H5 MBUS compatible The H5 SoC has a MBUS very similar to the H3 SoC, but it has a smaller MDFS divider range (1-4 instead of 1-16). Add a separate compatible for this variant. Acked-by: Rob Herring Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-4-samuel@sholland.org --- .../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 2b3829e0e240c..8eee312c2e6f5 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus reg: minItems: 1 @@ -86,6 +87,7 @@ if: enum: - allwinner,sun8i-h3-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus then: properties: -- GitLab From c8f7b50785ca3a8b81f615da6e2f4e7b6380b20a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:39 -0600 Subject: [PATCH 196/965] ARM: dts: sunxi: h3/h5: Update MBUS node In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Since the H3 and H5 have different clock divider limits, they need separate compatibles. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-5-samuel@sholland.org --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 ++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index ae4f933abb895..845f252354078 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -282,6 +282,10 @@ compatible = "allwinner,sun8i-h3-de2-clk"; }; +&mbus { + compatible = "allwinner,sun8i-h3-mbus"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d1e974886fdf1..4aeca9e7e30d2 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -568,9 +568,14 @@ }; mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-h3-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu CLK_MBUS>; + /* compatible is in per SoC .dtsi file */ + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 9988e87ea7b3d..a56fae761a1f3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -233,6 +233,10 @@ compatible = "allwinner,sun50i-h5-de2-clk"; }; +&mbus { + compatible = "allwinner,sun50i-h5-mbus"; +}; + &mmc0 { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; -- GitLab From 00b9773b128a509581555faef838b09468236d48 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:40 -0600 Subject: [PATCH 197/965] arm64: dts: allwinner: a64: Update MBUS node In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-6-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 741bd19fa8ec2..de77c87481fd1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1146,8 +1146,14 @@ mbus: dram-controller@1c62000 { compatible = "allwinner,sun50i-a64-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 112>; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; -- GitLab From 1aa590c85ae4a66bd686146392708704828691a2 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sat, 13 Nov 2021 11:21:56 +0800 Subject: [PATCH 198/965] ARM: dts: imx: Fix typo in pinfunc comments Remove the repeated `configurable' in some comments in imx1-pinfunc.h and imx27-pinfunc.h. Signed-off-by: Jason Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1-pinfunc.h | 6 +++--- arch/arm/boot/dts/imx27-pinfunc.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h index 050a1fc46a77d..bd2e679cb26c0 100644 --- a/arch/arm/boot/dts/imx1-pinfunc.h +++ b/arch/arm/boot/dts/imx1-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX1_PAD_A24__A24 0x00 0x004 diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h index 1514d80a31125..75aea0c701d4c 100644 --- a/arch/arm/boot/dts/imx27-pinfunc.h +++ b/arch/arm/boot/dts/imx27-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 -- GitLab From 8361b8b29f9389084b679db854cf733375c64763 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 20 Nov 2021 13:39:16 -0600 Subject: [PATCH 199/965] soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active Enable the vpu-h1 clock when the domain is active because reading or writing to the VPU-H1 IP block cause the system to hang. Fixes: 656ade7aa42a ("soc: imx: gpcv2: keep i.MX8M* bus clocks enabled") Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index e757044ab7512..8176380b02e6e 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -734,6 +734,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .map = IMX8MM_VPUH1_A53_DOMAIN, }, .pgc = BIT(IMX8MM_PGC_VPUH1), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_DISPMIX] = { -- GitLab From 11611eecb8aa1ab07f78e9bf0f2d8c40188e7826 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Nov 2021 11:23:11 +0100 Subject: [PATCH 200/965] ARM: dts: ux500: Fixup Gavini magnetometer The Gavini device tree had the wrong magnetometer specified, this should be a YAS530. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-gavini.dts | 39 +++++++++---------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 47bbf5ab267fe..1c0e5cfeddacb 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -232,19 +232,18 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: Memsic MMC328 magnetometer */ - magnetometer@30 { - compatible = "memsic,mmc328"; - reg = <0x30>; - /* TODO: if you have the schematic, check if both voltages come from AUX2 */ - /* VDA 1.8 V */ - vda-supply = <&ab8500_ldo_aux2_reg>; - /* VDD 1.8V */ - vdd-supply = <&ab8500_ldo_aux2_reg>; - /* GPIO204 */ + /* Yamaha YAS530 magnetometer */ + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + /* VDD 3V */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + /* IOVDD 1.8V */ + iovdd-supply = <&ab8500_ldo_aux2_reg>; + /* GPIO204 COMPASS_RST_N */ reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&mmc328_default>; + pinctrl-0 = <&yas530_default>; }; /* TODO: this should also be used by the NCP6914 Camera power management unit */ }; @@ -645,6 +644,15 @@ }; }; }; + /* Reset line for the Yamaha YAS530 magnetometer */ + yas530 { + yas530_default: yas530_janice { + janice_cfg1 { + pins = "GPIO204_AF23"; + ste,config = <&gpio_out_hi>; + }; + }; + }; /* Flash and torch */ flash { gpio_flash_default_mode: flash_default { @@ -747,15 +755,6 @@ }; }; }; - /* Reset line for the Memsic MMC328 magnetometer */ - mmc328 { - mmc328_default: mmc328_gavini { - gavini_cfg1 { - pins = "GPIO204_AF23"; - ste,config = <&gpio_out_hi>; - }; - }; - }; /* Interrupt line for Invensense MPU3050 gyroscope */ mpu3050 { mpu3050_default: mpu3050 { -- GitLab From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 23 Nov 2021 10:03:33 +0100 Subject: [PATCH 201/965] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new binding covers a single reg and uses syscon to reference shared register. References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index e1cffef4935a0..588e57db68591 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -148,15 +148,6 @@ }; }; - usb2_phy: usb2-phy@1800c000 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -448,7 +439,16 @@ "sata1", "sata2"; }; - syscon@180 { + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { compatible = "brcm,cru-clkset", "syscon"; reg = <0x180 0x4>; }; -- GitLab From 9c7e2634f647630db4e0719391dd80cd81132a66 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Thu, 18 Nov 2021 19:58:03 -0800 Subject: [PATCH 202/965] x86/cpu: Don't write CSTAR MSR on Intel CPUs Intel CPUs do not support SYSCALL in 32-bit mode, but the kernel initializes MSR_CSTAR unconditionally. That MSR write is normally ignored by the CPU, but in a TDX guest it raises a #VE trap. Exclude Intel CPUs from the MSR_CSTAR initialization. [ tglx: Fixed the subject line and removed the redundant comment. ] Signed-off-by: Andi Kleen Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Thomas Gleixner Reviewed-by: Tony Luck Link: https://lore.kernel.org/r/20211119035803.4012145-1-sathyanarayanan.kuppuswamy@linux.intel.com --- arch/x86/kernel/cpu/common.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0083464de5e31..0663642d61995 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1787,6 +1787,17 @@ EXPORT_PER_CPU_SYMBOL(__preempt_count); DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; +static void wrmsrl_cstar(unsigned long val) +{ + /* + * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR + * is so far ignored by the CPU, but raises a #VE trap in a TDX + * guest. Avoid the pointless write on all Intel CPUs. + */ + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + wrmsrl(MSR_CSTAR, val); +} + /* May not be marked __init: used by software suspend */ void syscall_init(void) { @@ -1794,7 +1805,7 @@ void syscall_init(void) wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); #ifdef CONFIG_IA32_EMULATION - wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); + wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); /* * This only works on Intel CPUs. * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. @@ -1806,7 +1817,7 @@ void syscall_init(void) (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); #else - wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); + wrmsrl_cstar((unsigned long)ignore_sysret); wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); -- GitLab From b046049e59dca5e5830dc75ed16acf7657a95161 Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Sat, 24 Jul 2021 11:44:02 +0800 Subject: [PATCH 203/965] ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco Since the compatible string defined from ilitek,ili9341.yaml is "st,sf-tc240t-9370-t", "ilitek,ili9341" so, append "ilitek,ili9341" to avoid the below dtbs_check warning. arch/arm/boot/dts/stm32f429-disco.dt.yaml: display@1: compatible: ['st,sf-tc240t-9370-t'] is too short Fixes: a726e2f000ec ("ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board") Signed-off-by: Dillon Min Reported-by: kernel test robot Reviewed-by: Linus Walleij Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429-disco.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 075ac57d0bf4a..6435e099c6326 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -192,7 +192,7 @@ display: display@1{ /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t"; + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; reg = <1>; spi-3wire; spi-max-frequency = <10000000>; -- GitLab From 958b18a404152a982b511bc251768ca969a87630 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:03:11 +0200 Subject: [PATCH 204/965] ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards Add pull-up to USART3 and UART7 RX pins to allow loop tests between USART3 and UART7 on stm32mp15 DKx boards. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 2ebafe27a865b..1c413a04ba9c5 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1816,7 +1816,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1826,7 +1826,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1971,7 +1971,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -1988,7 +1988,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; @@ -2012,7 +2012,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -2029,7 +2029,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; -- GitLab From a2368f89660728284b749cc14537d7628e3fc318 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:02:30 +0200 Subject: [PATCH 205/965] ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 Clean useless spaces in uart4_idle_pins_a node. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 1c413a04ba9c5..5f060feaf6390 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1737,20 +1737,20 @@ }; uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; }; uart4_sleep_pins_a: uart4-sleep-0 { - pins { + pins { pinmux = , /* UART4_TX */ ; /* UART4_RX */ - }; + }; }; uart4_pins_b: uart4-1 { -- GitLab From 2312a6e7b301f43f02fb30b1dee932df5a87a7d0 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:49 +0200 Subject: [PATCH 206/965] ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 48beed0f1f30a..6caeb448c1904 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -694,10 +694,26 @@ &usbphyc_port0 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &vrefbuf { -- GitLab From 28f645fc9424bf455528cb92bd6a7120281bca45 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:50 +0200 Subject: [PATCH 207/965] ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 5c5b1ddf7bfd2..e222d2d2cb449 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -375,3 +375,25 @@ &usbphyc { status = "okay"; }; + +&usbphyc_port0 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; -- GitLab From 7a0df1f969c14939f60a7f9a6af72adcc314675f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:31:55 +0800 Subject: [PATCH 208/965] arm64: dts: ti: k3-j721e: correct cache-sets info A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes So correct the cache-sets info. Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC") Signed-off-by: Peng Fan Reviewed-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 214359e7288b2..a5967ba139d7e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -64,7 +64,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -78,7 +78,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; -- GitLab From 217c7d1840b5377543eff84fe28409d0bd4d3433 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:04 +0000 Subject: [PATCH 209/965] dt-bindings: mmc: renesas,sdhi: Rename RZ/G2L clocks Rename the below RZ/G2L clocks to match with the clock names used in R-Car Gen2 and later generations. imclk->core clk_hs->clkh imclk2->cd This changes will avoid using fallback for RZ/G2L high speed clock, if "clkh" is not used in device tree and also the code changes in driver related to this clocks. Signed-off-by: Biju Das Reviewed-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index f5107a641790a..9ce6e06c19db7 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -113,17 +113,17 @@ allOf: clocks: items: - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this clock is turned off, external SD card detection cannot be detected. - - description: CLK_HS, SDHI channel High speed clock which operates - 4 times that of SDHI channel main clock1. - description: ACLK, SDHI channel bus clock. clock-names: items: - - const: imclk - - const: imclk2 - - const: clk_hs + - const: core + - const: clkh + - const: cd - const: aclk required: - clock-names -- GitLab From 5fcf8b0656cf842ae642298c2874ea6148d0129d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 12 Nov 2021 08:10:02 +0000 Subject: [PATCH 210/965] arm64: dts: renesas: r9a07g044: Sort psci node Sort psci node alphabetically. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211112081003.15453-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2dd6eff471cb1..a7818dbeb271a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,11 +42,6 @@ clock-frequency = <0>; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,6 +80,11 @@ }; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; -- GitLab From 59a7d68b69846ac012c33c1ac425b9388661d1f2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 18 Nov 2021 19:18:24 +0000 Subject: [PATCH 211/965] arm64: dts: renesas: r9a07g044: Add OSTM nodes Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index a7818dbeb271a..be9e5c4955539 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -791,6 +791,39 @@ power-domains = <&cpg>; status = "disabled"; }; + + ostm0: timer@12801000 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801000 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; + resets = <&cpg R9A07G044_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@12801400 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801400 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; + resets = <&cpg R9A07G044_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@12801800 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801800 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; + resets = <&cpg R9A07G044_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { -- GitLab From 00d071e23c61b1be528227427da3f805feddef19 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 18 Nov 2021 19:18:25 +0000 Subject: [PATCH 212/965] arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2L SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211118191826.2026-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 7e84a29dddfaa..3bea97f165576 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -130,6 +130,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { adc_pins: adc { pinmux = ; /* ADC_TRG */ -- GitLab From c81bd70f47cef36f88074d119e6e49cf92707fdb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 21 Nov 2021 23:49:06 +0000 Subject: [PATCH 213/965] arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 3bea97f165576..28af63324422d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -186,6 +186,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -251,6 +263,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if SDHI &sdhi0 { pinctrl-0 = <&sdhi0_pins>; -- GitLab From fee3eae1334a454a8c2e16313a374cc53ff722d8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:05 +0000 Subject: [PATCH 214/965] arm64: dts: renesas: r9a07g044: Rename SDHI clocks Rename the below SDHI clocks to match with the clocks used in driver. imclk->core clk_hs->clkh imclk2->cd Also re-arrange the clocks to match with the sorting order used in the binding document. Signed-off-by: Biju Das Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index be9e5c4955539..71f1701a1b662 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -613,10 +613,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -629,10 +629,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; -- GitLab From eb7621ce3362639025e7db125559e235a76d814f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 23 Nov 2021 14:14:19 +0000 Subject: [PATCH 215/965] arm64: dts: renesas: r9a07g044: Add WDT nodes Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 71f1701a1b662..82d9c620a4dec 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -792,6 +792,51 @@ status = "disabled"; }; + wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800C00 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + ostm0: timer@12801000 { compatible = "renesas,r9a07g044-ostm", "renesas,ostm"; -- GitLab From 44c2d2c2d25e87741b84aaa9e0dad396abdd148d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 23 Nov 2021 14:14:20 +0000 Subject: [PATCH 216/965] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog Enable watchdog{0, 1, 2} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211123141420.23529-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 28af63324422d..41fdae7ba66bd 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -321,3 +321,18 @@ status = "okay"; }; #endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt1 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; -- GitLab From 7744b393c95ac470a3ac279fa277e50d947f1bea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 24 Nov 2021 15:39:40 +0100 Subject: [PATCH 217/965] arm64: dts: renesas: Fix operating point table node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the node names of device nodes representing operating point v2 tables with the expectations of the DT bindings in Documentation/devicetree/bindings/opp/opp-v2.yaml. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/ac885456ffb00fa4cc4069b9967761df2c98c3d8.1637764588.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f9c4ae6f26a98..09976adf99c20 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -58,7 +58,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -80,7 +80,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 0c175b8c2088f..c504f50283806 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -47,7 +47,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 5e16f6b1771e5..b8dcbbbf3db53 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -44,7 +44,7 @@ clock-frequency = <0>; }; - cluster1_opp: opp_table10 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 673fcc631972d..e4dd6ccc8b10c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -47,7 +47,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -69,7 +69,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 391ffe6ca03e4..2353d3034bb5e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -62,7 +62,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -96,7 +96,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index b1a6cf76633dc..0f2424f125465 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -57,7 +57,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -97,7 +97,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 1c1da6d7be490..7468a2df1808c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -46,7 +46,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -86,7 +86,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 3a357d958d4ac..0c44de8669963 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -62,7 +62,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 8698058f25f39..14caedd0c959e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -55,7 +55,7 @@ clock-frequency = <0>; }; - cluster1_opp: opp_table10 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { -- GitLab From 36959e2108b6e3d66a3a6a1526e8e45f8abad14c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 24 Nov 2021 15:43:16 +0000 Subject: [PATCH 218/965] arm64: dts: renesas: r9a07g044: Add OPP table Add OPP table for RZ/G2L SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 82d9c620a4dec..439870930fb3f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -63,6 +90,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -71,6 +100,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { -- GitLab From 9fd8bbefc31286e702e8cc9fe8766301f02fd4be Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 24 Nov 2021 15:28:14 +0000 Subject: [PATCH 219/965] arm64: dts: renesas: ulcb: Merge hdmi0_con The remote endpoint for the hdmi connector is specfied through a reference to the hdmi0_con endpoint, which is in the same file. Simplify by specifying the remote-endpoint directly in the hdmi0_con endpoint. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211124152815.3926961-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 7edffe7f8cfa3..a7e93df4ced87 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -48,6 +48,7 @@ port { hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; }; }; }; @@ -199,10 +200,6 @@ }; }; -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; -- GitLab From bd4fa23731a5786a8aa711945a5b76aa62b86117 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 24 Nov 2021 15:28:15 +0000 Subject: [PATCH 220/965] arm64: dts: renesas: salvator-common: Merge hdmi0_con The remote endpoint for the hdmi connector is specfied through a reference to the hdmi0_con endpoint, which is in the same file. Simplify by specifying the remote-endpoint directly in the hdmi0_con endpoint. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211124152815.3926961-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index bf37777dca315..6092dc4531adf 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -97,6 +97,7 @@ port { hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; }; }; }; @@ -424,10 +425,6 @@ }; }; -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - #ifdef SOC_HAS_HDMI1 &hdmi1 { status = "okay"; -- GitLab From cdda01947bbae8f1b1d19f8aac1f81ae5ce6f37e Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 26 Nov 2021 09:54:42 +0000 Subject: [PATCH 221/965] arm64: dts: renesas: r8a779a0: Add DU support Provide the device nodes for the DU on the V3U platforms. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211126095445.932930-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 940e4990379d8..6e83bcb0287cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2269,6 +2269,38 @@ }; }; + du: display@feb00000 { + compatible = "renesas,du-r8a779a0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + }; + }; + }; + }; + isp0: isp@fed00000 { compatible = "renesas,r8a779a0-isp"; reg = <0 0xfed00000 0 0x10000>; -- GitLab From 3d24568b01c5a7a9e88f73f917477b60edb35bfe Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 10 Oct 2021 16:10:32 +0200 Subject: [PATCH 222/965] RISC-V: Add StarFive SoC Kconfig option Add StarFive Kconfig option to select SoC specific and common drivers required for these SoCs. Select subsystems required to boot so the required drivers gets enabled by default. Reviewed-by: Geert Uytterhoeven Acked-by: Palmer Dabbelt Signed-off-by: Emil Renner Berthing --- arch/riscv/Kconfig.socs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 30676ebb16ebd..6ec44a22278a4 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -19,6 +19,14 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. +config SOC_STARFIVE + bool "StarFive SoCs" + select PINCTRL + select RESET_CONTROLLER + select SIFIVE_PLIC + help + This enables support for StarFive SoC platform hardware. + config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE -- GitLab From 3234d3a1374308615c0cde5e83e52f6b644eaf53 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 10 Oct 2021 16:48:27 +0200 Subject: [PATCH 223/965] dt-bindings: timer: Add StarFive JH7100 clint Add compatible string for the StarFive JH7100 clint. Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Emil Renner Berthing --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a35952f487426..8d5f4687add9e 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - sifive,fu540-c000-clint + - starfive,jh7100-clint - canaan,k210-clint - const: sifive,clint0 -- GitLab From 9ac16169b4d4359d3832669bf06aab9e51184828 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 10 Oct 2021 16:48:27 +0200 Subject: [PATCH 224/965] dt-bindings: interrupt-controller: Add StarFive JH7100 plic Add compatible string for StarFive JH7100 plic. Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Emil Renner Berthing --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 08d5a57ce00ff..28b6b17fe4b26 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -45,6 +45,7 @@ properties: items: - enum: - sifive,fu540-c000-plic + - starfive,jh7100-plic - canaan,k210-plic - const: sifive,plic-1.0.0 -- GitLab From 376e3fdecb0dcae216c0ac559cff066f460bf47b Mon Sep 17 00:00:00 2001 From: Finn Thain Date: Fri, 19 Nov 2021 09:29:38 +1100 Subject: [PATCH 225/965] m68k: Enable memtest functionality Enable the memtest functionality and rearrange some code to prevent it from clobbering the initrd. The code to implement CONFIG_BLK_DEV_INITRD was conditional on !defined(CONFIG_SUN3). For simplicity, remove that test on the basis that m68k_ramdisk.size == 0 on Sun 3. The SLIME source code at http://sammy.net/sun3/ftp/pub/m68k/sun3/slime/slime-2.0.tar.gz indicates that no BI_RAMDISK entry is ever passed to the kernel due to #ifdef 0 around the relevant code. Cc: Mike Rapoport Cc: Sam Creasey Cc: Jonathan Corbet Signed-off-by: Finn Thain Acked-by: Mike Rapoport Link: https://lore.kernel.org/r/8170fe1d1c62426d82275d36ba409ecc18754292.1637274578.git.fthain@linux-m68k.org Signed-off-by: Geert Uytterhoeven --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/m68k/Kconfig | 1 + arch/m68k/kernel/setup_mm.c | 15 ++++++--------- arch/m68k/mm/motorola.c | 2 ++ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9725c546a0d46..3a28ec79f3aad 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2934,7 +2934,7 @@ both parameters are enabled, hugetlb_free_vmemmap takes precedence over memory_hotplug.memmap_on_memory. - memtest= [KNL,X86,ARM,PPC,RISCV] Enable memtest + memtest= [KNL,X86,ARM,M68K,PPC,RISCV] Enable memtest Format: default : 0 Specifies the number of memtest passes to be diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 0b50da08a9c56..4cae3fbe7f974 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -9,6 +9,7 @@ config M68K select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS select ARCH_MIGHT_HAVE_PC_PARPORT if ISA select ARCH_NO_PREEMPT if !COLDFIRE + select ARCH_USE_MEMTEST if MMU_MOTOROLA select ARCH_WANT_IPC_PARSE_VERSION select BINFMT_FLAT_ARGVP_ENVP_ON_STACK select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c index 4b51bfd38e5f2..49e573b943268 100644 --- a/arch/m68k/kernel/setup_mm.c +++ b/arch/m68k/kernel/setup_mm.c @@ -338,13 +338,6 @@ void __init setup_arch(char **cmdline_p) panic("No configuration setup"); } - paging_init(); - -#ifdef CONFIG_NATFEAT - nf_init(); -#endif - -#ifndef CONFIG_SUN3 #ifdef CONFIG_BLK_DEV_INITRD if (m68k_ramdisk.size) { memblock_reserve(m68k_ramdisk.addr, m68k_ramdisk.size); @@ -354,6 +347,12 @@ void __init setup_arch(char **cmdline_p) } #endif + paging_init(); + +#ifdef CONFIG_NATFEAT + nf_init(); +#endif + #ifdef CONFIG_ATARI if (MACH_IS_ATARI) atari_stram_reserve_pages((void *)availmem); @@ -364,8 +363,6 @@ void __init setup_arch(char **cmdline_p) } #endif -#endif /* !CONFIG_SUN3 */ - /* set ISA defs early as possible */ #if defined(CONFIG_ISA) && defined(MULTI_ISA) if (MACH_IS_Q40) { diff --git a/arch/m68k/mm/motorola.c b/arch/m68k/mm/motorola.c index 2b05bb2bac00d..ecbe948f4c1aa 100644 --- a/arch/m68k/mm/motorola.c +++ b/arch/m68k/mm/motorola.c @@ -457,6 +457,8 @@ void __init paging_init(void) flush_tlb_all(); + early_memtest(min_addr, max_addr); + /* * initialize the bad page table and bad page to point * to a couple of allocated pages -- GitLab From 1149ccc5e89145a344cfdd8832d83bcc919dc1ed Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 26 Nov 2021 12:33:40 +0100 Subject: [PATCH 226/965] ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk A pinctrl handle is used to setup a pull-up on the stusb1600 IRQ pin (that is open drain). When in ANALOG state, no pull-up can be applied in the GPIO HW controller, still the setting is done into the register. The pull-up is effective currently, only when the GPIO IRQ is requested. The correct setting is to use directly the GPIO, instead of ANALOG state. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 5f060feaf6390..3b65130affec8 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1718,7 +1718,7 @@ stusb1600_pins_a: stusb1600-0 { pins { - pinmux = ; + pinmux = ; bias-pull-up; }; }; -- GitLab From b98aee466d194788bd651cb375b0e0f7e0e69865 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Mon, 22 Nov 2021 10:20:50 +0800 Subject: [PATCH 227/965] optee: Fix NULL but dereferenced coccicheck error Eliminate the following coccicheck warning: ./drivers/tee/optee/smc_abi.c:1508:12-15: ERROR: optee is NULL but dereferenced. Reported-by: Abaci Robot Fixes: 6749e69c4dad ("optee: add asynchronous notifications") Signed-off-by: Yang Li Signed-off-by: Jens Wiklander --- drivers/tee/optee/smc_abi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 92759d70bfcef..d7c8235c1c420 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -1505,8 +1505,8 @@ err_free_optee: kfree(optee); err_free_pool: tee_shm_pool_free(pool); - if (optee->smc.memremaped_shm) - memunmap(optee->smc.memremaped_shm); + if (memremaped_shm) + memunmap(memremaped_shm); return rc; } -- GitLab From 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 Nov 2021 20:00:52 +0100 Subject: [PATCH 228/965] soc: renesas: Consolidate product register handling Currently renesas_soc_init() scans the whole device tree up to three times, to find a device node describing a product register. Furthermore, the product register handling for the different variants is very similar, with the major difference being the location of the product bitfield inside the product register. Reduce scanning to a single pass using of_find_matching_node_and_match() instead. Switch to a common handling of product registers, by storing the intrinsics of each product register type in the data field of the corresponding match entry. Signed-off-by: Geert Uytterhoeven Tested-by: Lad Prabhakar Link: https://lore.kernel.org/r/057721f46c7499de4133135488f0f3da7fb39265.1636570669.git.geert+renesas@glider.be --- drivers/soc/renesas/renesas-soc.c | 115 +++++++++++++++--------------- 1 file changed, 56 insertions(+), 59 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 7961b0be18509..dff90f5049632 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -328,94 +328,92 @@ static const struct of_device_id renesas_socs[] __initconst = { { /* sentinel */ } }; +struct renesas_id { + unsigned int offset; + u32 mask; +}; + +static const struct renesas_id id_bsid __initconst = { + .offset = 0, + .mask = 0xff0000, + /* + * TODO: Upper 4 bits of BSID are for chip version, but the format is + * not known at this time so we don't know how to specify eshi and eslo + */ +}; + +static const struct renesas_id id_rzg2l __initconst = { + .offset = 0xa04, + .mask = 0xfffffff, +}; + +static const struct renesas_id id_prr __initconst = { + .offset = 0, + .mask = 0xff00, +}; + +static const struct of_device_id renesas_ids[] __initconst = { + { .compatible = "renesas,bsid", .data = &id_bsid }, + { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,prr", .data = &id_prr }, + { /* sentinel */ } +}; + static int __init renesas_soc_init(void) { struct soc_device_attribute *soc_dev_attr; + unsigned int product, eshi = 0, eslo; const struct renesas_family *family; const struct of_device_id *match; const struct renesas_soc *soc; + const struct renesas_id *id; void __iomem *chipid = NULL; struct soc_device *soc_dev; struct device_node *np; - unsigned int product, eshi = 0, eslo; + const char *soc_id; match = of_match_node(renesas_socs, of_root); if (!match) return -ENODEV; + soc_id = strchr(match->compatible, ',') + 1; soc = match->data; family = soc->family; - np = of_find_compatible_node(NULL, NULL, "renesas,bsid"); + np = of_find_matching_node_and_match(NULL, renesas_ids, &match); if (np) { + id = match->data; chipid = of_iomap(np, 0); of_node_put(np); - - if (chipid) { - product = readl(chipid); - iounmap(chipid); - - if (soc->id && ((product >> 16) & 0xff) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", - product); - return -ENODEV; - } - } - - /* - * TODO: Upper 4 bits of BSID are for chip version, but the - * format is not known at this time so we don't know how to - * specify eshi and eslo - */ - - goto done; + } else if (soc->id && family->reg) { + /* Try hardcoded CCCR/PRR fallback */ + id = &id_prr; + chipid = ioremap(family->reg, 4); } - np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc"); - if (np) { - chipid = of_iomap(np, 0); - of_node_put(np); + if (chipid) { + product = readl(chipid + id->offset); + iounmap(chipid); - if (chipid) { - product = readl(chipid + 0x0a04); - iounmap(chipid); + if (id == &id_prr) { + /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ + if ((product & 0x7fff) == 0x5210) + product ^= 0x11; + /* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */ + if ((product & 0x7fff) == 0x5211) + product ^= 0x12; - if (soc->id && (product & 0xfffffff) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", - product); - return -ENODEV; - } + eshi = ((product >> 4) & 0x0f) + 1; + eslo = product & 0xf; } - goto done; - } - - /* Try PRR first, then hardcoded fallback */ - np = of_find_compatible_node(NULL, NULL, "renesas,prr"); - if (np) { - chipid = of_iomap(np, 0); - of_node_put(np); - } else if (soc->id && family->reg) { - chipid = ioremap(family->reg, 4); - } - if (chipid) { - product = readl(chipid); - iounmap(chipid); - /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ - if ((product & 0x7fff) == 0x5210) - product ^= 0x11; - /* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */ - if ((product & 0x7fff) == 0x5211) - product ^= 0x12; - if (soc->id && ((product >> 8) & 0xff) != soc->id) { + if (soc->id && + ((product & id->mask) >> __ffs(id->mask)) != soc->id) { pr_warn("SoC mismatch (product = 0x%x)\n", product); return -ENODEV; } - eshi = ((product >> 4) & 0x0f) + 1; - eslo = product & 0xf; } -done: soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) return -ENOMEM; @@ -425,8 +423,7 @@ done: of_node_put(np); soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); - soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1, - GFP_KERNEL); + soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); if (eshi) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, eslo); -- GitLab From f4c35356e0fce4bbe2994185cc014f13630a1a1d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 30 Nov 2021 14:10:44 -0600 Subject: [PATCH 229/965] arm64: dts: n5x: add qspi, usb, and ethernet support Populate the N5X board dts file with support for QSPI, USB, and ethernet. Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_n5x_socdk.dts | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 01f1307ce4acb..f3c1310dae0ae 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -29,6 +29,36 @@ compatible = "intel,easic-n5x-clkmgr"; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + &mmc { status = "okay"; cap-sd-highspeed; @@ -40,10 +70,51 @@ clock-frequency = <25000000>; }; +&qspi { + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x03FE0000 0x0C020000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; +&usb0 { + status = "okay"; + disable-over-current; +}; + &watchdog0 { status = "okay"; }; -- GitLab From 6da5175dbe1c2f02f1301b6d987e3ce24742bfd4 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 30 Nov 2021 21:55:32 +0300 Subject: [PATCH 230/965] x86/paravirt: Fix build PARAVIRT_XXL=y without XEN_PV Kernel fails to compile with PARAVIRT_XXL=y if XEN_PV is not enabled: ld.lld: error: undefined symbol: xen_iret It happens because INTERRUPT_RETURN defined to use xen_iret if CONFIG_PARAVIRT_XXL enabled regardless of CONFIG_XEN_PV. The issue is not visible in the current kernel because CONFIG_XEN_PV is the only user of CONFIG_PARAVIRT_XXL and there's no way to enable them separately. Rework code to define INTERRUPT_RETURN based on CONFIG_XEN_PV, not CONFIG_PARAVIRT_XXL. Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross Link: https://lkml.kernel.org/r/20211130185533.32658-1-kirill.shutemov@linux.intel.com --- arch/x86/include/asm/irqflags.h | 7 +++++-- arch/x86/include/asm/paravirt.h | 5 ----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h index c5ce9845c9998..87761396e8cc0 100644 --- a/arch/x86/include/asm/irqflags.h +++ b/arch/x86/include/asm/irqflags.h @@ -114,8 +114,6 @@ static __always_inline unsigned long arch_local_irq_save(void) #define SAVE_FLAGS pushfq; popq %rax #endif -#define INTERRUPT_RETURN jmp native_iret - #endif #endif /* __ASSEMBLY__ */ @@ -143,8 +141,13 @@ static __always_inline void arch_local_irq_restore(unsigned long flags) #ifdef CONFIG_X86_64 #ifdef CONFIG_XEN_PV #define SWAPGS ALTERNATIVE "swapgs", "", X86_FEATURE_XENPV +#define INTERRUPT_RETURN \ + ANNOTATE_RETPOLINE_SAFE; \ + ALTERNATIVE_TERNARY("jmp *paravirt_iret(%rip);", \ + X86_FEATURE_XENPV, "jmp xen_iret;", "jmp native_iret;") #else #define SWAPGS swapgs +#define INTERRUPT_RETURN jmp native_iret #endif #endif #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 21c4a694ca114..27d276232c802 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -752,11 +752,6 @@ extern void default_banner(void); #define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .quad, 8) #define PARA_INDIRECT(addr) *addr(%rip) -#define INTERRUPT_RETURN \ - ANNOTATE_RETPOLINE_SAFE; \ - ALTERNATIVE_TERNARY("jmp *paravirt_iret(%rip);", \ - X86_FEATURE_XENPV, "jmp xen_iret;", "jmp native_iret;") - #ifdef CONFIG_DEBUG_ENTRY .macro PARA_IRQ_save_fl PARA_SITE(PARA_PATCH(PV_IRQ_save_fl), -- GitLab From 23ef731e4365196bfc186358eb4f6265d60ab352 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 30 Nov 2021 21:49:30 +0300 Subject: [PATCH 231/965] x86/insn-eval: Handle insn_get_opcode() failure is_string_insn() calls insn_get_opcode() that can fail, but does not handle the failure. is_string_insn() interface does not allow to communicate an error to the caller. Push insn_get_opcode() to the only non-static user of is_string_insn() and fail it early if insn_get_opcode() fails. [ dhansen: fix tabs-versus-spaces breakage ] Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Tested-by: Joerg Roedel Acked-by: Tom Lendacky Link: https://lkml.kernel.org/r/20211130184933.31005-2-kirill.shutemov@linux.intel.com --- arch/x86/lib/insn-eval.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index eb3ccffb9b9dc..1c51e8a415e28 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -37,8 +37,6 @@ enum reg_type { */ static bool is_string_insn(struct insn *insn) { - insn_get_opcode(insn); - /* All string instructions have a 1-byte opcode. */ if (insn->opcode.nbytes != 1) return false; @@ -1405,6 +1403,9 @@ void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs) if (!insn || !regs) return (void __user *)-1L; + if (insn_get_opcode(insn)) + return (void __user *)-1L; + switch (insn->addr_bytes) { case 2: return get_addr_ref_16(insn, regs); -- GitLab From d5ec1877df6da6a14bbc353aff50689528930dd2 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 30 Nov 2021 21:49:31 +0300 Subject: [PATCH 232/965] x86/insn-eval: Introduce insn_get_modrm_reg_ptr() The helper returns a pointer to the register indicated by ModRM byte. It's going to replace vc_insn_get_reg() in the SEV MMIO implementation. TDX MMIO implementation will also use it. Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Tested-by: Joerg Roedel Acked-by: Tom Lendacky Link: https://lkml.kernel.org/r/20211130184933.31005-3-kirill.shutemov@linux.intel.com --- arch/x86/include/asm/insn-eval.h | 1 + arch/x86/lib/insn-eval.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h index 4ec3613551e3b..33ae4040c7ee5 100644 --- a/arch/x86/include/asm/insn-eval.h +++ b/arch/x86/include/asm/insn-eval.h @@ -19,6 +19,7 @@ bool insn_has_rep_prefix(struct insn *insn); void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs); int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs); int insn_get_modrm_reg_off(struct insn *insn, struct pt_regs *regs); +unsigned long *insn_get_modrm_reg_ptr(struct insn *insn, struct pt_regs *regs); unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx); int insn_get_code_seg_params(struct pt_regs *regs); int insn_get_effective_ip(struct pt_regs *regs, unsigned long *ip); diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index 1c51e8a415e28..8df6236e441cb 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -848,6 +848,26 @@ int insn_get_modrm_reg_off(struct insn *insn, struct pt_regs *regs) return get_reg_offset(insn, regs, REG_TYPE_REG); } +/** + * insn_get_modrm_reg_ptr() - Obtain register pointer based on ModRM byte + * @insn: Instruction containing the ModRM byte + * @regs: Register values as seen when entering kernel mode + * + * Returns: + * + * The register indicated by the reg part of the ModRM byte. + * The register is obtained as a pointer within pt_regs. + */ +unsigned long *insn_get_modrm_reg_ptr(struct insn *insn, struct pt_regs *regs) +{ + int offset; + + offset = insn_get_modrm_reg_off(insn, regs); + if (offset < 0) + return NULL; + return (void *)regs + offset; +} + /** * get_seg_base_limit() - obtain base address and limit of a segment * @insn: Instruction. Must be valid. -- GitLab From 70a81f99e45b15b3e77f70720742545e1c7541da Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 30 Nov 2021 21:49:32 +0300 Subject: [PATCH 233/965] x86/insn-eval: Introduce insn_decode_mmio() In preparation for sharing MMIO instruction decode between SEV-ES and TDX, factor out the common decode into a new insn_decode_mmio() helper. For regular virtual machine, MMIO is handled by the VMM and KVM emulates instructions that caused MMIO. But, this model doesn't work for a secure VMs (like SEV or TDX) as VMM doesn't have access to the guest memory and register state. So, for TDX or SEV VMM needs assistance in handling MMIO. It induces exception in the guest. Guest has to decode the instruction and handle it on its own. The code is based on the current SEV MMIO implementation. Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Tested-by: Joerg Roedel Acked-by: Tom Lendacky Link: https://lkml.kernel.org/r/20211130184933.31005-4-kirill.shutemov@linux.intel.com --- arch/x86/include/asm/insn-eval.h | 12 +++++ arch/x86/lib/insn-eval.c | 84 ++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h index 33ae4040c7ee5..43785ee363f1c 100644 --- a/arch/x86/include/asm/insn-eval.h +++ b/arch/x86/include/asm/insn-eval.h @@ -30,4 +30,16 @@ int insn_fetch_from_user_inatomic(struct pt_regs *regs, bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE], int buf_size); +enum mmio_type { + MMIO_DECODE_FAILED, + MMIO_WRITE, + MMIO_WRITE_IMM, + MMIO_READ, + MMIO_READ_ZERO_EXTEND, + MMIO_READ_SIGN_EXTEND, + MMIO_MOVS, +}; + +enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes); + #endif /* _ASM_X86_INSN_EVAL_H */ diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index 8df6236e441cb..53e57ef5925c8 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -1560,3 +1560,87 @@ bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs, return true; } + +/** + * insn_decode_mmio() - Decode a MMIO instruction + * @insn: Structure to store decoded instruction + * @bytes: Returns size of memory operand + * + * Decodes instruction that used for Memory-mapped I/O. + * + * Returns: + * + * Type of the instruction. Size of the memory operand is stored in + * @bytes. If decode failed, MMIO_DECODE_FAILED returned. + */ +enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) +{ + enum mmio_type type = MMIO_DECODE_FAILED; + + *bytes = 0; + + if (insn_get_opcode(insn)) + return MMIO_DECODE_FAILED; + + switch (insn->opcode.bytes[0]) { + case 0x88: /* MOV m8,r8 */ + *bytes = 1; + fallthrough; + case 0x89: /* MOV m16/m32/m64, r16/m32/m64 */ + if (!*bytes) + *bytes = insn->opnd_bytes; + type = MMIO_WRITE; + break; + + case 0xc6: /* MOV m8, imm8 */ + *bytes = 1; + fallthrough; + case 0xc7: /* MOV m16/m32/m64, imm16/imm32/imm64 */ + if (!*bytes) + *bytes = insn->opnd_bytes; + type = MMIO_WRITE_IMM; + break; + + case 0x8a: /* MOV r8, m8 */ + *bytes = 1; + fallthrough; + case 0x8b: /* MOV r16/r32/r64, m16/m32/m64 */ + if (!*bytes) + *bytes = insn->opnd_bytes; + type = MMIO_READ; + break; + + case 0xa4: /* MOVS m8, m8 */ + *bytes = 1; + fallthrough; + case 0xa5: /* MOVS m16/m32/m64, m16/m32/m64 */ + if (!*bytes) + *bytes = insn->opnd_bytes; + type = MMIO_MOVS; + break; + + case 0x0f: /* Two-byte instruction */ + switch (insn->opcode.bytes[1]) { + case 0xb6: /* MOVZX r16/r32/r64, m8 */ + *bytes = 1; + fallthrough; + case 0xb7: /* MOVZX r32/r64, m16 */ + if (!*bytes) + *bytes = 2; + type = MMIO_READ_ZERO_EXTEND; + break; + + case 0xbe: /* MOVSX r16/r32/r64, m8 */ + *bytes = 1; + fallthrough; + case 0xbf: /* MOVSX r32/r64, m16 */ + if (!*bytes) + *bytes = 2; + type = MMIO_READ_SIGN_EXTEND; + break; + } + break; + } + + return type; +} -- GitLab From c494eb366dbfc5095c0f159bbb5c6d4ec3ed37ec Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 30 Nov 2021 21:49:33 +0300 Subject: [PATCH 234/965] x86/sev-es: Use insn_decode_mmio() for MMIO implementation Switch SEV implementation to insn_decode_mmio(). The helper is going to be used by TDX too. No functional changes. Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Tested-by: Joerg Roedel Acked-by: Tom Lendacky Link: https://lkml.kernel.org/r/20211130184933.31005-5-kirill.shutemov@linux.intel.com --- arch/x86/kernel/sev.c | 172 ++++++++++-------------------------------- 1 file changed, 41 insertions(+), 131 deletions(-) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 74f0ec9553848..09c06c0256261 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -776,22 +776,6 @@ static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt) do_early_exception(ctxt->regs, trapnr); } -static long *vc_insn_get_reg(struct es_em_ctxt *ctxt) -{ - long *reg_array; - int offset; - - reg_array = (long *)ctxt->regs; - offset = insn_get_modrm_reg_off(&ctxt->insn, ctxt->regs); - - if (offset < 0) - return NULL; - - offset /= sizeof(long); - - return reg_array + offset; -} - static long *vc_insn_get_rm(struct es_em_ctxt *ctxt) { long *reg_array; @@ -839,76 +823,6 @@ static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt, return sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, exit_info_1, exit_info_2); } -static enum es_result vc_handle_mmio_twobyte_ops(struct ghcb *ghcb, - struct es_em_ctxt *ctxt) -{ - struct insn *insn = &ctxt->insn; - unsigned int bytes = 0; - enum es_result ret; - int sign_byte; - long *reg_data; - - switch (insn->opcode.bytes[1]) { - /* MMIO Read w/ zero-extension */ - case 0xb6: - bytes = 1; - fallthrough; - case 0xb7: - if (!bytes) - bytes = 2; - - ret = vc_do_mmio(ghcb, ctxt, bytes, true); - if (ret) - break; - - /* Zero extend based on operand size */ - reg_data = vc_insn_get_reg(ctxt); - if (!reg_data) - return ES_DECODE_FAILED; - - memset(reg_data, 0, insn->opnd_bytes); - - memcpy(reg_data, ghcb->shared_buffer, bytes); - break; - - /* MMIO Read w/ sign-extension */ - case 0xbe: - bytes = 1; - fallthrough; - case 0xbf: - if (!bytes) - bytes = 2; - - ret = vc_do_mmio(ghcb, ctxt, bytes, true); - if (ret) - break; - - /* Sign extend based on operand size */ - reg_data = vc_insn_get_reg(ctxt); - if (!reg_data) - return ES_DECODE_FAILED; - - if (bytes == 1) { - u8 *val = (u8 *)ghcb->shared_buffer; - - sign_byte = (*val & 0x80) ? 0xff : 0x00; - } else { - u16 *val = (u16 *)ghcb->shared_buffer; - - sign_byte = (*val & 0x8000) ? 0xff : 0x00; - } - memset(reg_data, sign_byte, insn->opnd_bytes); - - memcpy(reg_data, ghcb->shared_buffer, bytes); - break; - - default: - ret = ES_UNSUPPORTED; - } - - return ret; -} - /* * The MOVS instruction has two memory operands, which raises the * problem that it is not known whether the access to the source or the @@ -976,83 +890,79 @@ static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt, return ES_RETRY; } -static enum es_result vc_handle_mmio(struct ghcb *ghcb, - struct es_em_ctxt *ctxt) +static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) { struct insn *insn = &ctxt->insn; unsigned int bytes = 0; + enum mmio_type mmio; enum es_result ret; + u8 sign_byte; long *reg_data; - switch (insn->opcode.bytes[0]) { - /* MMIO Write */ - case 0x88: - bytes = 1; - fallthrough; - case 0x89: - if (!bytes) - bytes = insn->opnd_bytes; + mmio = insn_decode_mmio(insn, &bytes); + if (mmio == MMIO_DECODE_FAILED) + return ES_DECODE_FAILED; - reg_data = vc_insn_get_reg(ctxt); + if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) { + reg_data = insn_get_modrm_reg_ptr(insn, ctxt->regs); if (!reg_data) return ES_DECODE_FAILED; + } + switch (mmio) { + case MMIO_WRITE: memcpy(ghcb->shared_buffer, reg_data, bytes); - ret = vc_do_mmio(ghcb, ctxt, bytes, false); break; - - case 0xc6: - bytes = 1; - fallthrough; - case 0xc7: - if (!bytes) - bytes = insn->opnd_bytes; - + case MMIO_WRITE_IMM: memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes); - ret = vc_do_mmio(ghcb, ctxt, bytes, false); break; - - /* MMIO Read */ - case 0x8a: - bytes = 1; - fallthrough; - case 0x8b: - if (!bytes) - bytes = insn->opnd_bytes; - + case MMIO_READ: ret = vc_do_mmio(ghcb, ctxt, bytes, true); if (ret) break; - reg_data = vc_insn_get_reg(ctxt); - if (!reg_data) - return ES_DECODE_FAILED; - /* Zero-extend for 32-bit operation */ if (bytes == 4) *reg_data = 0; memcpy(reg_data, ghcb->shared_buffer, bytes); break; + case MMIO_READ_ZERO_EXTEND: + ret = vc_do_mmio(ghcb, ctxt, bytes, true); + if (ret) + break; + + /* Zero extend based on operand size */ + memset(reg_data, 0, insn->opnd_bytes); + memcpy(reg_data, ghcb->shared_buffer, bytes); + break; + case MMIO_READ_SIGN_EXTEND: + ret = vc_do_mmio(ghcb, ctxt, bytes, true); + if (ret) + break; - /* MOVS instruction */ - case 0xa4: - bytes = 1; - fallthrough; - case 0xa5: - if (!bytes) - bytes = insn->opnd_bytes; + if (bytes == 1) { + u8 *val = (u8 *)ghcb->shared_buffer; - ret = vc_handle_mmio_movs(ctxt, bytes); + sign_byte = (*val & 0x80) ? 0xff : 0x00; + } else { + u16 *val = (u16 *)ghcb->shared_buffer; + + sign_byte = (*val & 0x8000) ? 0xff : 0x00; + } + + /* Sign extend based on operand size */ + memset(reg_data, sign_byte, insn->opnd_bytes); + memcpy(reg_data, ghcb->shared_buffer, bytes); break; - /* Two-Byte Opcodes */ - case 0x0f: - ret = vc_handle_mmio_twobyte_ops(ghcb, ctxt); + case MMIO_MOVS: + ret = vc_handle_mmio_movs(ctxt, bytes); break; default: ret = ES_UNSUPPORTED; + break; } return ret; -- GitLab From 8e0e8016cb797c38eea8641e8b77a5780c4614ac Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 10 Nov 2021 16:53:30 -0500 Subject: [PATCH 235/965] arm64: dts: qcom: sm8250: Add CPU opp tables Add OPP tables to scale DDR and L3 with CPUs for SM8250 SoCs. Signed-off-by: Thara Gopinath Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211110215330.74257-1-thara.gopinath@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 314 +++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c46c35a74601f..40f18d539d80e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -99,6 +99,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -118,6 +121,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -134,6 +140,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -150,6 +159,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -166,6 +178,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -182,6 +197,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -199,6 +217,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -215,6 +236,9 @@ dynamic-power-coefficient = <444>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -259,6 +283,296 @@ }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp3: opp-518400000 { + opp-hz = /bits/ 64 <518400000>; + opp-peak-kBps = <800000 16588800>; + }; + + cpu0_opp4: opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <800000 16588800>; + }; + + cpu0_opp5: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 19660800>; + }; + + cpu0_opp6: opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu0_opp7: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <1804000 23347200>; + }; + + cpu0_opp8: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1804000 26419200>; + }; + + cpu0_opp9: opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <1804000 29491200>; + }; + + cpu0_opp10: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <1804000 32563200>; + }; + + cpu0_opp11: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <1804000 36249600>; + }; + + cpu0_opp12: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <2188000 36249600>; + }; + + cpu0_opp13: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <2188000 39321600>; + }; + + cpu0_opp14: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 42393600>; + }; + + cpu0_opp15: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <3072000 42393600>; + }; + + cpu0_opp16: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 42393600>; + }; + + cpu0_opp17: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 42393600>; + }; + }; + + cpu4_opp_table: cpu4_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-710400000 { + opp-hz = /bits/ 64 <710400000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu4_opp2: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 23347200>; + }; + + cpu4_opp3: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 26419200>; + }; + + cpu4_opp4: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 26419200>; + }; + + cpu4_opp5: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 29491200>; + }; + + cpu4_opp6: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 29491200>; + }; + + cpu4_opp7: opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu4_opp8: opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu4_opp9: opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <5412000 39321600>; + }; + + cpu4_opp10: opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <5412000 42393600>; + }; + + cpu4_opp11: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <5412000 45465600>; + }; + + cpu4_opp12: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 45465600>; + }; + + cpu4_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <6220000 48537600>; + }; + + cpu4_opp14: opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <7216000 48537600>; + }; + + cpu4_opp15: opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu4_opp16: opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu4_opp17: opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu4_opp18: opp-2419200000 { + opp-hz = /bits/ 64 <2419200000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + + cpu7_opp_table: cpu7_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp1: opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <2188000 19660800>; + }; + + cpu7_opp2: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <2188000 26419200>; + }; + + cpu7_opp3: opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <3072000 26419200>; + }; + + cpu7_opp4: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <3072000 29491200>; + }; + + cpu7_opp5: opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu7_opp6: opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu7_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 36249600>; + }; + + cpu7_opp8: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <5412000 39321600>; + }; + + cpu7_opp9: opp-1747200000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <5412000 42393600>; + }; + + cpu7_opp10: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 45465600>; + }; + + cpu7_opp11: opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <6220000 48537600>; + }; + + cpu7_opp12: opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <7216000 48537600>; + }; + + cpu7_opp13: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu7_opp14: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu7_opp15: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp16: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp17: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp18: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp19: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp20: opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm"; -- GitLab From 1c0ac047bbfb3efd6549d18c3ca47aa0afedcfbe Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 19 Nov 2021 22:39:53 +0100 Subject: [PATCH 236/965] arm64: dts: qcom: msm8916: Add RPM sleep stats MSM8916 is similar to the other SoCs that had the RPM stats node added in commit 290bc6846547 ("arm64: dts: qcom: Enable RPM Sleep stats"). However, the dynamic offset readable at 0x14 seems only available on some of the newer firmware versions. To be absolutely sure, make use of the new qcom,msm8916-rpm-stats compatible that reads the sleep stats from a fixed offset of 0xdba0. Statistics are available for a "vmin" and "xosd" low power mode: $ cat /sys/kernel/debug/qcom_stats/vmin Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 $ cat /sys/kernel/debug/qcom_stats/xosd Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 Cc: Maulik Shah Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211119213953.31970-4-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c1c42f26b61e0..9044eb41a81db 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -453,6 +453,11 @@ reg = <0x00060000 0x8000>; }; + sram@290000 { + compatible = "qcom,msm8916-rpm-stats"; + reg = <0x00290000 0x10000>; + }; + bimc: interconnect@400000 { compatible = "qcom,msm8916-bimc"; reg = <0x00400000 0x62000>; -- GitLab From 6867430332655cfb0880e0e7576ea4eb786d50fc Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 22 Nov 2021 00:04:49 +0700 Subject: [PATCH 237/965] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button This enables the volume up key. Signed-off-by: Dang Huynh Tested-by: Alexey Minnekhanov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211121170449.1124048-1-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index d042e3883b9e8..dcbaacf18f66d 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -9,6 +9,8 @@ #include "sdm660.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" +#include +#include / { model = "Xiaomi Redmi Note 7"; @@ -46,6 +48,17 @@ regulator-boot-on; }; + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- GitLab From 254a27585eb135f35887579ebc7d0e02b9788b92 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:15 +0530 Subject: [PATCH 238/965] ARM: dts: qcom: sdx55: Add support for PCIe PHY Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-2-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 44526ad9d210b..16995782dfdf4 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -309,6 +309,41 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; -- GitLab From a5a2661287b450f2b1f751ae7b4da4f39976571b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:16 +0530 Subject: [PATCH 239/965] ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY Enable PCIE0 PHY on Telit FN980 TLB for PCIE EP. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-3-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 80c40da79604f..e8b5327afbe7b 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,13 @@ status = "ok"; }; +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + &qpic_bam { status = "ok"; }; -- GitLab From e6b69813283f9babc6892c1324d2c3bd2a577d9c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:17 +0530 Subject: [PATCH 240/965] ARM: dts: qcom: sdx55: Add support for PCIe EP Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 16995782dfdf4..5d769b3f2d353 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -391,6 +392,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "syscon"; + reg = <0x01fc0000 0x1000>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; @@ -403,6 +409,45 @@ status = "disabled"; }; + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x10000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; -- GitLab From 7cecfb53cad8e9f564fdf11e56502c7d8607b3a3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:18 +0530 Subject: [PATCH 241/965] ARM: dts: qcom: sdx55-fn980: Enable PCIe EP Enable PCIe Endpoint controller on the Telit FN980 TLB board based on Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org --- .../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index e8b5327afbe7b..01ac91738f34b 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,6 +243,14 @@ vdda-pll-supply = <&vreg_l4e_bb_0p875>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -267,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; -- GitLab From e1fb17ee85bc85808eeb103afa63581d065c7328 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:19 +0530 Subject: [PATCH 242/965] ARM: dts: qcom: sdx55-fn980: Enable IPA Enable IP Accelerator (IPA) on Telit FN980 TLB for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-6-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 01ac91738f34b..a4fa468a095fc 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &pcie0_phy { status = "okay"; -- GitLab From 1f7fe79d03b2ac0991c8a229ca50a9f45b71df80 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:20 +0530 Subject: [PATCH 243/965] ARM: dts: qcom: sdx55-t55: Enable IPA Enable IP Accelerator (IPA) on Thundercomm T55 board for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-7-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 2ffcd085904db..7ed8feb99afbe 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &qpic_bam { status = "ok"; }; -- GitLab From 95dcb997772e966919987b6dd96eb9a6212402eb Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 23 Nov 2021 23:24:37 +0700 Subject: [PATCH 244/965] arm64: dts: qcom: Drop input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211123162436.1507341-1-danct12@riseup.net --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 1 - arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 3 --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 1 - 7 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 69fcb6b0398de..84558ab5fe86b 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -42,7 +42,6 @@ gpio_keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 3a3790a52a2ce..cc038f9b641fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -62,7 +62,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; autorepeat; volupkey { diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 7cc564d8ca7c3..dde7ed159c4d1 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -29,7 +29,6 @@ gpio_keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 3d495ce3f46ac..dc5b9b274df3b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -29,7 +29,6 @@ gpio-hall-sensors { compatible = "gpio-keys"; - input-name = "hall-sensors"; label = "Hall sensors"; pinctrl-names = "default"; pinctrl-0 = <&hall_sensor1_default>; @@ -46,7 +45,6 @@ gpio-kb-extra-keys { compatible = "gpio-keys"; - input-name = "extra-kb-keys"; label = "Keyboard extra keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_kb_pins_extra>; @@ -102,7 +100,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "side-buttons"; label = "Side buttons"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 91e3912821813..47488a1aecaef 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -93,7 +93,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, @@ -126,7 +125,6 @@ gpio-hall-sensor { compatible = "gpio-keys"; - input-name = "hall-sensors"; label = "Hall sensors"; pinctrl-names = "default"; pinctrl-0 = <&hall_sensor0_default>; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index e90c9ec846753..42af1fade461b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -90,7 +90,6 @@ gpio_keys { status = "okay"; compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 45eab0235d668..871ccbba445bb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,7 +42,6 @@ gpio-keys { status = "okay"; compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; -- GitLab From 7a21328bb3ade238e35c4de81da3ad8d76437b72 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 29 Nov 2021 17:01:34 +0530 Subject: [PATCH 245/965] dt-bindings: arm: qcom: Document qcom,sc7280-crd board Document the qcom,sc7280-crd board based off sc7280 SoC, The board is also known as hoglin in the Chrome OS builds, so document the google,hoglin compatible as well. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-2-git-send-email-quic_rjendra@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64b..41e1d781e43f3 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -201,8 +201,10 @@ properties: - items: - enum: + - qcom,sc7280-crd - qcom,sc7280-idp - qcom,sc7280-idp2 + - google,hoglin - google,piglin - google,senor - const: qcom,sc7280 -- GitLab From 427b249504ea48e9af2014df4b22fe8b31ddb563 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 29 Nov 2021 17:01:35 +0530 Subject: [PATCH 246/965] arm64: dts: qcom: sc7280-crd: Add device tree files for CRD CRD (Compute Reference Design) is a sc7280 based board, largely derived from the existing IDP board design with some key deltas 1. has EC and H1 over SPI similar to IDP2 2. touchscreen and trackpad support 3. eDP display We just add the barebones dts file here, subsequent patches will add support for EC/H1 and other components. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-3-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-crd.dts | 31 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 50572419dca95..7f26ec20d2384 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts new file mode 100644 index 0000000000000..2da6603c38dc8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 CRD board device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sc7280-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; + compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +}; + +&nvme_pwren { + pins = "gpio51"; +}; -- GitLab From 248da168fbae5ab7294a37428256acc570ed552a Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Mon, 29 Nov 2021 17:01:36 +0530 Subject: [PATCH 247/965] arm64: dts: qcom: sc7280: Define EC and H1 nodes for IDP/CRD The IDP2 and CRD boards share the EC and H1 parts, so define all related device nodes into a common file and include them in the idp2 and crd dts files to avoid duplication. Signed-off-by: Kshitiz Godara Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-4-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 1 + .../arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 105 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 1 + 3 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index 2da6603c38dc8..1e3e2f360b6e5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-idp.dtsi" +#include "sc7280-idp-ec-h1.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi new file mode 100644 index 0000000000000..0896a61518177 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 EC/H1 over SPI (common between IDP2 and CRD) + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +ap_ec_spi: &spi10 { + status = "okay"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; + cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +#include +#include + +ap_h1_spi: &spi14 { + status = "okay"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs_gpio_init_high>, <&qup_spi14_cs_gpio>; + cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + + cr50: tpm@0 { + compatible = "google,cr50"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + spi-max-frequency = <800000>; + interrupt-parent = <&tlmm>; + interrupts = <104 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tlmm { + ap_ec_int_l: ap-ec-int-l { + pins = "gpio18"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + h1_ap_int_odl: h1-ap-int-odl { + pins = "gpio104"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + pins = "gpio43"; + output-high; + }; + + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high { + pins = "gpio59"; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 3ae99697d8932..0382c770650a8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-idp.dtsi" +#include "sc7280-idp-ec-h1.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform"; -- GitLab From 3ebf11fa4a355116eb2a69a46114ec92f245dbcc Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Mon, 29 Nov 2021 17:01:37 +0530 Subject: [PATCH 248/965] arm64: dts: qcom: sc7280-crd: Add Touchscreen and touchpad support Add Touchscreen and touchpad hid-over-i2c node for the sc7280 CRD board Signed-off-by: Kshitiz Godara Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-5-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index 1e3e2f360b6e5..cd2755ce530d9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -23,6 +23,47 @@ }; }; +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&vreg_l18b_1p8>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&vreg_l19b_1p8>; + }; +}; + &nvme_3v3_regulator { gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; }; @@ -30,3 +71,23 @@ &nvme_pwren { pins = "gpio51"; }; + +&tlmm { + tp_int_odl: tp-int-odl { + pins = "gpio7"; + function = "gpio"; + bias-disable; + }; + + ts_int_l: ts-int-l { + pins = "gpio55"; + function = "gpio"; + bias-pull-up; + }; + + ts_reset_l: ts-reset-l { + pins = "gpio54"; + function = "gpio"; + bias-disable; + }; +}; -- GitLab From d0bfc92303dde7f13fac1873c25a3bee913bfef3 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:31 +0100 Subject: [PATCH 249/965] arm64: dts: qcom: sm6125: Add RPMPD node Add RPM Power Distribution node for sm6125 SoC. Signed-off-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-3-martin.botka@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 51286ddbdb10f..a501e8788c512 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -302,6 +302,56 @@ compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,sm6125-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + }; + }; }; }; -- GitLab From 556a9f3ae17ef19deecac130fea38f258d5abeb2 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:32 +0100 Subject: [PATCH 250/965] arm64: dts: qcom: sm6125: Add power domains to sdhc Add RPM Power Domains to internal eMMC and SDCard. Signed-off-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-4-martin.botka@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a501e8788c512..e81b2a7794fb7 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -448,6 +448,9 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd SM6125_VDDCX>; + bus-width = <8>; non-removable; status = "disabled"; @@ -471,6 +474,8 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; + power-domains = <&rpmpd SM6125_VDDCX>; + bus-width = <4>; status = "disabled"; }; -- GitLab From b0293c19d42f6d6951c2fab9a47fed50baf2c14d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 05:05:59 +0300 Subject: [PATCH 251/965] arm64: dts: qcom: msm8916: fix MMC controller aliases Change sdhcN aliases to mmcN to make them actually work. Currently the board uses non-standard aliases sdhcN, which do not work, resulting in mmc0 and mmc1 hosts randomly changing indices between boots. Fixes: c4da5a561627 ("arm64: dts: qcom: Add msm8916 sdhci configuration nodes") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201020559.1611890-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9044eb41a81db..41897eb3736ac 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -19,8 +19,8 @@ #size-cells = <2>; aliases { - sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; chosen { }; -- GitLab From 145988cff2a10ec8c720eccdcfc94748f497cd8d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 29 Nov 2021 17:55:10 +0100 Subject: [PATCH 252/965] ARM: dts: sun8i: Adjust power key nodes Several H3 and one H2+ board have power key nodes, which are slightly off. Some are missing wakeup-source property and some have BTN_0 code assigned instead of KEY_POWER. Adjust them, so they can function as intended by designer. Co-developed-by: Michael Klein Signed-off-by: Michael Klein Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211129165510.370717-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 3 ++- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 1 + 6 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 8e8634ff2f9d3..d5c7b7984d857 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -52,8 +52,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c7c3e7d8b3c81..fc45d5aaa67ff 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,6 +81,7 @@ label = "k1"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 597c425d08ecd..9daffd90c12f0 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -99,8 +99,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 5aff8ecc66cbb..90f75fa85e68b 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -91,8 +91,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index 7a6af54dd3423..d03f5853ef7bf 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -82,8 +82,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index c44fd726945a7..9e14fe5fdcde0 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -49,6 +49,7 @@ label = "power"; linux,code = ; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + wakeup-source; }; }; -- GitLab From 75fb3b1be53c85901d45ddb7cc2db6967876b99e Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 30 Nov 2021 11:01:58 +0100 Subject: [PATCH 253/965] arm64: dts: meson: p241: add vcc_5v regulator Add the VCC_5V regulator, which feeds the HDMI, USB and audio amplifier. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211130100159.214489-2-jbrunet@baylibre.com --- .../arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index eb7f5a3fefd4d..9d0684a8264bc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -84,6 +84,14 @@ regulator-max-microvolt = <3300000>; }; + vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; @@ -136,6 +144,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; }; &hdmi_tx_tmds_port { @@ -220,3 +229,7 @@ status = "okay"; dr_mode = "host"; }; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; -- GitLab From 0a62b3cc0af9322e650fe89bea0bacdedf01960a Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 30 Nov 2021 11:01:59 +0100 Subject: [PATCH 254/965] arm64: dts: meson: p241: add sound support Add the p241 sound card support. This board can play audio through HDMI and the internal DAC. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211130100159.214489-3-jbrunet@baylibre.com --- .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index 9d0684a8264bc..ff906becd2abf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "meson-gxl-s805x.dtsi" @@ -21,6 +22,13 @@ ethernet0 = ðmac; }; + au2: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&vcc_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -110,6 +118,68 @@ clocks = <&wifi32k>; clock-names = "ext_clock"; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-P241"; + audio-aux-devs = <&au2>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { -- GitLab From 8dce88fe80a858f34bb5b46470218fe478d251ee Mon Sep 17 00:00:00 2001 From: Sin Hui Kho Date: Wed, 1 Dec 2021 18:13:53 +0800 Subject: [PATCH 255/965] arm64: dts: Update NAND MTD partition for Agilex and Stratix 10 Change NAND flash MTD partition in device tree after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components. Signed-off-by: Sin Hui Kho Signed-off-by: Dinh Nguyen --- .../altera/socfpga_stratix10_socdk_nand.dts | 24 ++----------------- .../dts/intel/socfpga_agilex_socdk_nand.dts | 20 ++-------------- 2 files changed, 4 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index f9b4a39683cf4..bbc3db42d6e83 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -119,28 +119,8 @@ }; partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; + label = "root"; + reg = <0x200000 0x3fe00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index cc2dcabf34e30..57f83481f5518 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -91,24 +91,8 @@ reg = <0 0x200000>; }; partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; + label = "root"; + reg = <0x200000 0x3fe00000>; }; }; }; -- GitLab From ad1569476e7644ac5754ac9a710ce771a7b4976f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:22 +0100 Subject: [PATCH 256/965] dt-bindings: arm: apple: Add iMac (24-inch 2021) to Apple bindings This introduces compatible strings for both 2021 Apple iMac M1 devices: * apple,j456 - iMac (24-inch, 4x USB-C, M1, 2021) * apple,j457 - iMac (24-inch, 2x USB-C, M1, 2021) Reviewed-by: Mark Kettenis Signed-off-by: Janne Grunau Tested-by: Hector Martin Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 1e772c85206c0..b23c8dc5a27d4 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -12,12 +12,12 @@ maintainers: description: | ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon". - This currently includes devices based on the "M1" SoC, starting with the - three Mac models released in late 2020: + This currently includes devices based on the "M1" SoC: - Mac mini (M1, 2020) - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) + - iMac (24-inch, M1, 2021) The compatible property should follow this format: @@ -56,6 +56,8 @@ properties: - apple,j274 # Mac mini (M1, 2020) - apple,j293 # MacBook Pro (13-inch, M1, 2020) - apple,j313 # MacBook Air (M1, 2020) + - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) + - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform -- GitLab From 7c77ab91b33d2ef06c4f3eab633ceed8e7bfedcc Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:23 +0100 Subject: [PATCH 257/965] arm64: dts: apple: Add missing M1 (t8103) devices This adds support for following Apple M1 devices: - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) - iMac (24-inch 2021) Reviewed-by: Mark Kettenis Signed-off-by: Janne Grunau Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/Makefile | 4 ++ arch/arm64/boot/dts/apple/t8103-j274.dts | 29 +------------- arch/arm64/boot/dts/apple/t8103-j293.dts | 33 +++++++++++++++ arch/arm64/boot/dts/apple/t8103-j313.dts | 33 +++++++++++++++ arch/arm64/boot/dts/apple/t8103-j456.dts | 41 +++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-j457.dts | 47 ++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 49 +++++++++++++++++++++++ 7 files changed, 208 insertions(+), 28 deletions(-) create mode 100644 arch/arm64/boot/dts/apple/t8103-j293.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j313.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j456.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j457.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-jxxx.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index cbbd701ebf05b..c0510c25ca6a2 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 02c36301e9850..9e01ef70039d9 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -10,39 +10,15 @@ /dts-v1/; #include "t8103.dtsi" +#include "t8103-jxxx.dtsi" / { compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; model = "Apple Mac mini (M1, 2020)"; aliases { - serial0 = &serial0; ethernet0 = ðernet0; }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0"; - - framebuffer0: framebuffer@0 { - compatible = "apple,simple-framebuffer", "simple-framebuffer"; - reg = <0 0 0 0>; /* To be filled by loader */ - /* Format properties will be added by loader */ - status = "disabled"; - }; - }; - - memory@800000000 { - device_type = "memory"; - reg = <0x8 0 0x2 0>; /* To be filled by loader */ - }; -}; - -&serial0 { - status = "okay"; }; /* @@ -50,9 +26,6 @@ * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). */ -&port00 { - bus-range = <1 1>; -}; &port01 { bus-range = <2 2>; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts new file mode 100644 index 0000000000000..466035f00b69b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Pro (13-inch, M1, 2020) + * + * target-type: J293 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; + model = "Apple MacBook Pro (13-inch, M1, 2020)"; +}; + +/* + * Remove unused PCIe ports and disable the associated DARTs. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +&pcie0_dart_2 { + status = "disabled"; +}; + +/delete-node/ &port01; +/delete-node/ &port02; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts new file mode 100644 index 0000000000000..b0ebb45bdb6fb --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (M1, 2020) + * + * target-type: J313 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; + model = "Apple MacBook Air (M1, 2020)"; +}; + +/* + * Remove unused PCIe ports and disable the associated DARTs. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +&pcie0_dart_2 { + status = "disabled"; +}; + +/delete-node/ &port01; +/delete-node/ &port02; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts new file mode 100644 index 0000000000000..7267e069355b1 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 4x USB-C, M1, 2020) + * + * target-type: J456 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; + model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; + + aliases { + ethernet0 = ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ + +&port01 { + bus-range = <2 2>; +}; + +&port02 { + bus-range = <3 3>; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts new file mode 100644 index 0000000000000..d7c622931627c --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 2x USB-C, M1, 2020) + * + * target-type: J457 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; + model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; + + aliases { + ethernet0 = ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ + +&port02 { + bus-range = <3 3>; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; + +/* + * Remove unused PCIe port and disable the associated DART. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +/delete-node/ &port01; diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi new file mode 100644 index 0000000000000..53d22b434d76c --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021) + * + * This file contains parts common to all Apple M1 devices using the t8103. + * + * target-type: J274, J293, J313, J456, J457 + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; +}; -- GitLab From 90458f6eec42aafb7688eca0ec1d3c00adc31fb7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:24 +0100 Subject: [PATCH 258/965] arm64: dts: apple: t8103: Add i2c nodes Apple M1 has at least 5 i2c controllers. i2c0, i2c1 and i2c3 are used on all M1 Mac devices. The 2020 Mac Mini uses i2c2 and the 13-inch MacBook Pro uses i2c2 and i2c4. Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j274.dts | 4 ++ arch/arm64/boot/dts/apple/t8103-j293.dts | 8 +++ arch/arm64/boot/dts/apple/t8103.dtsi | 87 ++++++++++++++++++++++++ 3 files changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 9e01ef70039d9..2cd429efba5b9 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -39,3 +39,7 @@ local-mac-address = [00 10 18 00 00 00]; }; }; + +&i2c2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 466035f00b69b..49cdf4b560a30 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -31,3 +31,11 @@ /delete-node/ &port01; /delete-node/ &port02; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index c320c8baeb417..c62d9082c6a35 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -111,6 +111,68 @@ ranges; nonposted-mmio; + i2c0: i2c@235010000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35010000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@235014000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35014000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c2: i2c@235018000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35018000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; /* not used in all devices */ + }; + + i2c3: i2c@23501c000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x3501c000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c4: i2c@235020000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35020000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; /* only used in J293 */ + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -153,6 +215,31 @@ , ; + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + pcie_pins: pcie-pins { pinmux = , , -- GitLab From c03edf1c0fc8648ab2f3f81ce1c00fff5fe7f69b Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:25 +0100 Subject: [PATCH 259/965] arm64: dts: apple: t8103: Add cd321x nodes All M1 Mac devices have 2 SoC connected USB-C ports and use cd321x USB type C port switch and power deliver controllers. I2c bus and addresses configuration are for all devices equal. The iMac (24-inch, 2021) has a configuration with 2 additional USB-C ports (j456) using two additional cd321x controllers. Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j456.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 7267e069355b1..884fddf7d3637 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -21,6 +21,24 @@ }; }; +&i2c0 { + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm3: usb-pd@3c { + compatible = "apple,cd321x"; + reg = <0x3c>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 53d22b434d76c..876278fe0afe6 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -39,6 +39,24 @@ status = "okay"; }; +&i2c0 { + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader -- GitLab From bfc3a3f93ef7d48879c4b070bdbb6b6a80c06365 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 1 Dec 2021 22:19:39 +0100 Subject: [PATCH 260/965] MAINTAINERS: Add Florian as BCM5301X and BCM53573 maintainer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM5301X and BCM53573 commits go through Florian's stblinux.git so add him as maintainer to make sure people e-mail him when sending patches. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce85213..6a051258643c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3625,6 +3625,7 @@ F: drivers/net/ethernet/broadcom/bcm4908_enet.* F: drivers/net/ethernet/broadcom/unimac.h BROADCOM BCM5301X ARM ARCHITECTURE +M: Florian Fainelli M: Hauke Mehrtens M: Rafał Miłecki M: bcm-kernel-feedback-list@broadcom.com @@ -3636,6 +3637,7 @@ F: arch/arm/boot/dts/bcm953012* F: arch/arm/mach-bcm/bcm_5301x.c BROADCOM BCM53573 ARM ARCHITECTURE +M: Florian Fainelli M: Rafał Miłecki L: bcm-kernel-feedback-list@broadcom.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- GitLab From 6f8260557d490364c2b49872127c379de9b141ac Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:12:03 +0900 Subject: [PATCH 261/965] dt-bindings: i2c: apple,i2c: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The i2c driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 82b953181a522..47dd6c107a6d0 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -40,6 +40,9 @@ properties: used. This frequency is generated by dividing the reference clock. Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). + power-domains: + maxItems: 1 + required: - compatible - reg -- GitLab From 364609125e2ca745c698ec157615ff179b239344 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:13:15 +0900 Subject: [PATCH 262/965] dt-bindings: iommu: apple,dart: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The DART driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 94aa9e9afa596..82ad669feef70 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -41,6 +41,9 @@ properties: Has to be one. The single cell describes the stream id emitted by a master to the IOMMU. + power-domains: + maxItems: 1 + required: - compatible - reg -- GitLab From 1ed162b56baae221da049ba8641ddd4fca33c0b9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:14:12 +0900 Subject: [PATCH 263/965] dt-bindings: pinctrl: apple,pinctrl: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The pinctrl driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 07b00de797550..200d411621e7a 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -50,6 +50,9 @@ properties: '#interrupt-cells': const: 2 + power-domains: + maxItems: 1 + patternProperties: '-pins$': type: object -- GitLab From 72baffdd26fb4e5b3c7215728e98e2681a9ebc4f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:15:41 +0900 Subject: [PATCH 264/965] dt-bindings: interrupt-controller: apple,aic: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The AIC driver doesn't do runtime-pm and likely never will (since it is system-critical), but it makes sense to describe the power domain relationship the devicetree properly. Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index cf6c091a07b14..97359024709af 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -65,6 +65,9 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - '#interrupt-cells' -- GitLab From 8ff8d6936ec9134754e9a3eef1f641358dac7457 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:14 +0100 Subject: [PATCH 265/965] arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI There is another very similar device to Tanix TX6, namely Tanix TX6 mini. Because most of the board design is shared, it makes sense to have common nodes in DTSI file. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 164 +---------------- .../boot/dts/allwinner/sun50i-h6-tanix.dtsi | 173 ++++++++++++++++++ 2 files changed, 174 insertions(+), 163 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 7c37aa4c60cb9..a6e69f4b2666b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -3,175 +3,13 @@ /dts-v1/; -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include +#include "sun50i-h6-tanix.dtsi" / { model = "Tanix TX6"; compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - /* used for FD650 LED display driver */ - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ - scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ - i2c-gpio,delay-us = <5>; - }; - - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpu-gpu"; - regulator-min-microvolt = <1135000>; - regulator-max-microvolt = <1135000>; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-h6-spdif"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpu_gpu>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_vdd_cpu_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_vcc1v8>; - vcc-pd-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc1v8>; }; &r_ir { linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - status = "okay"; -}; - -&usb3phy { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi new file mode 100644 index 0000000000000..166b6a7a586ca --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Jernej Skrabec + +/dts-v1/; + +#include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" + +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + /* used for FD650 LED display driver */ + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ + scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ + i2c-gpio,delay-us = <5>; + }; + + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu-gpu"; + regulator-min-microvolt = <1135000>; + regulator-max-microvolt = <1135000>; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu_gpu>; +}; + +&de { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&gpu { + mali-supply = <®_vdd_cpu_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_vcc1v8>; + vcc-pd-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc1v8>; +}; + +&r_ir { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb3phy { + status = "okay"; +}; -- GitLab From fcad81d944e7cb8f2d0aeaec0e4109638e873036 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:15 +0100 Subject: [PATCH 266/965] dt-bindings: arm: sunxi: Add Tanix TX6 mini Tanix TX6 mini is, as its name suggest, very similar to Tanix TX6, but with less features. It misses bluetooth support, it has less RAM, wifi supports only 2.4G, it comes with different IR remote, etc. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 889128acf49a6..c8a3102c0fde7 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -808,6 +808,11 @@ properties: - const: oranth,tanix-tx6 - const: allwinner,sun50i-h6 + - description: Tanix TX6 mini + items: + - const: oranth,tanix-tx6-mini + - const: allwinner,sun50i-h6 + - description: TBS A711 Tablet items: - const: tbs-biometrics,a711 -- GitLab From fa33ec5157b08ea8bd57dd6a0bbf920dc304aca1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:16 +0100 Subject: [PATCH 267/965] arm64: dts: allwinner: h6: Add Tanix TX6 mini dts Tanix TX6 mini is less capable version of Tanix TX6 although it comes with some features not present on Tanix TX6. Basic specs: - H6 SoC - 2 GiB DDR3 RAM - HDMI - SPDIF - 2x USB - analogue audio - CVBS - SD card - IR remote - LED display - fast ethernet - XR819 wifi - 16 GiB eMMC Currently supported features doesn't differ that much from Tanix TX6, but that will change soon. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h6-tanix-tx6-mini.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index a96d9d2d8dd87..8fa5c060a4fef 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts new file mode 100644 index 0000000000000..08d84160d88f2 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Jernej Skrabec + +/dts-v1/; + +#include "sun50i-h6-tanix.dtsi" + +/ { + model = "Tanix TX6 mini"; + compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6"; +}; + +&r_ir { + linux,rc-map-name = "rc-tanix-tx3mini"; +}; -- GitLab From 0835819309540e83325ad10fb920b59c7495b419 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:17 +0100 Subject: [PATCH 268/965] arm64: dts: allwinner: h6: tanix: Add MMC1 node Both, Tanix TX6 and Tanix TX6 mini, have SDIO wifi module, albeit different. However, driver can be autoprobed via SDIO ID. Add MMC1 node, so kernel can discover wifi module and load driver for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-tanix.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi index 166b6a7a586ca..edb71e4a03047 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -75,6 +75,13 @@ #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + }; }; &cpu0 { @@ -121,6 +128,15 @@ status = "okay"; }; +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &mmc2 { vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc1v8>; -- GitLab From a8a051984a75f8123c1805fdadb5a4ec6f1a50b0 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:18 +0100 Subject: [PATCH 269/965] arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth Tanix TX6 comes either with RTL8822BS or RTL8822CS wifi+bt combo module. Wifi part is already enabled in tanix DTSI. Let's enable also bluetooth. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index a6e69f4b2666b..9a38ff9b3fc75 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -13,3 +13,17 @@ &r_ir { linux,rc-map-name = "rc-tanix-tx5max"; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ + enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + }; +}; -- GitLab From 4d3984906397581dc0ccb6a02bf16b6ff82c9192 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 26 Nov 2021 14:15:54 +0530 Subject: [PATCH 270/965] arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node Fix 'dtbs_check' in serdes_ln_ctrl (serdes-ln-ctrl@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211126084555.17797-2-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index d60ef4f7dd0b7..05a627ad6cdc4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,7 +32,7 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ -- GitLab From 3f92a5be6084b77f764a8bbb881ac0d12cb9e863 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 26 Nov 2021 14:15:55 +0530 Subject: [PATCH 271/965] arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node Fix 'dtbs_check' in serdes_ln_ctrl (mux@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211126084555.17797-3-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 08c8d1b47dcd9..e85c89eebfa31 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -42,7 +42,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - serdes_ln_ctrl: mux@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; #mux-control-cells = <1>; -- GitLab From a27a93bf70045be54b594fa8482959ffb84166d7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:35 -0600 Subject: [PATCH 272/965] arm64: dts: ti: k3-am642: Fix the L2 cache sets A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi index e2b397c884018..8a76f4821b11b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -60,6 +60,6 @@ cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; - cache-sets = <512>; + cache-sets = <256>; }; }; -- GitLab From d0c826106f3fc11ff97285102b576b65576654ae Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:38 -0600 Subject: [PATCH 273/965] arm64: dts: ti: k3-j7200: Fix the L2 cache sets A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 47567cb260c2b..a99a4d305b7ec 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -86,7 +86,7 @@ cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; -- GitLab From e9ba3a5bc6fdc2c796c69fdaf5ed6c9957cf9f9d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:39 -0600 Subject: [PATCH 274/965] arm64: dts: ti: k3-j721e: Fix the L2 cache sets A72's L2 cache[1] on J721e[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] http://www.ti.com/lit/pdf/spruil1 Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043639.4413-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index a5967ba139d7e..4a3872fce5339 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -88,7 +88,7 @@ cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; -- GitLab From a172c86931709d6663318609d71a811333bdf4b0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:26:40 -0600 Subject: [PATCH 275/965] arm64: dts: ti: k3-j7200: Correct the d-cache-sets info A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets. So, correct the d-cache-sets info. [1] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Reviewed-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index a99a4d305b7ec..64fef4e67d76a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -62,7 +62,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -76,7 +76,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; -- GitLab From 44226253e6514b8ef3ddc8710055548d22a230f0 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 2 Dec 2021 18:30:18 +0100 Subject: [PATCH 276/965] arm64: dts: ti: k3-am64-main: add timesync router node The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of multiplexers to provide selection of active CPTS time sync events for routing to CPTS capable modules. This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh Raghavendra Signed-off-by: Christian Gmeiner Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211202173114.9936-1-christian.gmeiner@gmail.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5ad638b95ffc7..e16d2ccdd8189 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -564,6 +564,14 @@ ti,cpts-ext-ts-inputs = <8>; }; + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + }; + usbss0: cdns-usb@f900000{ compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; -- GitLab From 9e4d52a00a0217857fa40dc998971a375f861a61 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Dec 2021 14:55:23 +0100 Subject: [PATCH 277/965] x86/ce4100: Replace "ti,pcf8575" by "nxp,pcf8575" The TI part is equivalent to the NXP part, and its compatible value is not documented in the DT bindings. Note that while the Linux driver DT match table does not contain the compatible value of the TI part, it could still match to this part, as i2c_device_id-based matching ignores the vendor part of the compatible value. Signed-off-by: Geert Uytterhoeven Signed-off-by: Borislav Petkov Reviewed-by: Andy Shevchenko Link: https://lkml.kernel.org/r/0c00cec971f5c405e47d04e493d854de0efc2e49.1638539629.git.geert+renesas@glider.be --- arch/x86/platform/ce4100/falconfalls.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts index 0ac3d43571361..65fa3d866226c 100644 --- a/arch/x86/platform/ce4100/falconfalls.dts +++ b/arch/x86/platform/ce4100/falconfalls.dts @@ -249,7 +249,7 @@ gpio@26 { #gpio-cells = <2>; - compatible = "ti,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; }; @@ -263,7 +263,7 @@ gpio@26 { #gpio-cells = <2>; - compatible = "ti,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; }; -- GitLab From e1cd82a339024beda8439fb2e20718363ee989a8 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Tue, 16 Nov 2021 06:13:05 +0100 Subject: [PATCH 278/965] x86/mm: Add missing dependency to In the following commit: 025768a966a3 x86/cpu: Use alternative to generate the TASK_SIZE_MAX constant ... we added the new task_size_max() inline, which uses X86_FEATURE_LA57, but doesn't include which defines the constant. Due to the way alternatives macros work currently this doesn't get reported as an immediate build error, only as a link error, if a .c file happens to include first: > ld: kernel/fork.o:(.altinstructions+0x98): undefined reference to `X86_FEATURE_LA57' In the current upstream kernel no .c file includes before including some other header that includes , which is why this dependency bug went unnoticed. Cc: Linus Torvalds Cc: Borislav Petkov Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- arch/x86/include/asm/page_64.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h index 4bde0dc66100c..e9c86299b8351 100644 --- a/arch/x86/include/asm/page_64.h +++ b/arch/x86/include/asm/page_64.h @@ -5,6 +5,7 @@ #include #ifndef __ASSEMBLY__ +#include #include /* duplicated to the one in bootmem.h */ -- GitLab From 9de4999050b5f2e847c84372c6a1aa1fe32bb269 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Thu, 2 Dec 2021 16:32:23 +0100 Subject: [PATCH 279/965] x86/realmode: Add comment for Global bit usage in trampoline_pgd Document the fact that using the trampoline_pgd will result in the creation of global TLB entries in the user range of the address space. Signed-off-by: Joerg Roedel Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211202153226.22946-2-joro@8bytes.org --- arch/x86/mm/init.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 1895986842b91..4ba024d5b63ae 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -714,6 +714,11 @@ static void __init memory_map_bottom_up(unsigned long map_start, static void __init init_trampoline(void) { #ifdef CONFIG_X86_64 + /* + * The code below will alias kernel page-tables in the user-range of the + * address space, including the Global bit. So global TLB entries will + * be created when using the trampoline page-table. + */ if (!kaslr_memory_enabled()) trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; else -- GitLab From 3e63d6a197d57f94abff0fbd71efd8f98e254e1c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:15 +0100 Subject: [PATCH 280/965] dt-bindings: vendor-prefixes: Add an entry for JOZ BV Add "joz" entry for JOZ BV: https://joz.nl/en/about-joz/ Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd7812..6414f5fdcb913 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -593,6 +593,8 @@ patternProperties: description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^joz,.*": + description: JOZ BV "^kam,.*": description: Kamstrup A/S "^karo,.*": -- GitLab From 74fb79574d26fc79a04e5a75e137317870843e7d Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:16 +0100 Subject: [PATCH 281/965] dt-bindings: arm: fsl: add JOZ Access Point Add imx6ull based JOZ Access Point. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0b595b26061f9..a0eb42595ee2a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -580,6 +580,7 @@ properties: items: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - joz,jozacp # JOZ Access Point - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules -- GitLab From 2db0624b78c42abe1bcada7dd62068ef978e1e35 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:17 +0100 Subject: [PATCH 282/965] ARM: dts: add JOZ Access Point JOZ Access Point is imx6ull based device designed for agricultural cleaning machines. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ull-jozacp.dts | 456 +++++++++++++++++++++++++++ 2 files changed, 457 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-jozacp.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..9753faf0f1aa5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -688,6 +688,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-jozacp.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/imx6ull-jozacp.dts new file mode 100644 index 0000000000000..a152eeb78e882 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-jozacp.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; + +#include +#include +#include "imx6ull.dtsi" + +/ { + model = "JOZ Access Point"; + compatible = "joz,jozacp", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + /* On board name LED_RGB1 */ + led-controller-1 { + compatible = "pwm-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + pwms = <&pwm1 0 10000000 0>; + max-brightness = <255>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + pwms = <&pwm3 0 10000000 0>; + max-brightness = <255>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + pwms = <&pwm5 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* On board name LED_RGB2 */ + led-controller-2 { + compatible = "pwm-leds"; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + pwms = <&pwm2 0 10000000 0>; + max-brightness = <255>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <4>; + pwms = <&pwm4 0 10000000 0>; + max-brightness = <255>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; + pwms = <&pwm6 0 10000000 0>; + max-brightness = <255>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v0>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vbus: regulator-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vbus>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_vbus>; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + cap-mmc-hw-reset; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sd; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW Revision */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + + /* HW ID */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 + + /* Digital inputs */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 + + /* Isolated outputs */ + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_vbus: vbus0grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_hog>; + + pinctrl_snvs_hog: snvs-hog-grp { + fsl,pins = < + /* Digital outputs */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 + + /* Digital outputs fault feedback */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 + >; + }; +}; -- GitLab From 2439d70c52c51f991b00b0ae5644e96033bd8165 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:39 +0100 Subject: [PATCH 283/965] ARM: dts: imx6qdl-tqma6: add ERR006687 hardware workaround for "a" variant The TQMa6x "a" has a workaround for ERR006687 implemented in hardware. Add the required pinmuxing and related setup to make use of this. As board DTS files based on the TQMa6x SoMs will define their own pinmuxing for the FEC ethernet controller as well, we can't apply this pin group unconditionally; instead, it is the responsibility of the board DTs derived from imx6qdl-tqma6a.dtsi to include this group. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index b679bec78e6c4..bfb67da64b960 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -4,6 +4,12 @@ * Copyright 2013-2017 Markus Niebel */ +&fec { + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -26,3 +32,17 @@ pagesize = <32>; }; }; + +&iomuxc { + /* + * This pinmuxing is required for the ERR006687 workaround. Board + * DTS files that enable the FEC controller with + * fsl,err006687-workaround-present must include this group. + */ + pinctrl_enet_fix: enetfixgrp { + fsl,pins = < + /* ENET ping patch */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; +}; -- GitLab From ef3846247b41391434c23fcd9560daa57d14bb7a Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 22 Nov 2021 12:37:40 +0100 Subject: [PATCH 284/965] ARM: dts: imx6qdl: add TQ-Systems MBa6x device trees Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 5 + arch/arm/boot/dts/imx6dl-mba6.dtsi | 22 ++ arch/arm/boot/dts/imx6dl-mba6a.dts | 21 ++ arch/arm/boot/dts/imx6dl-mba6b.dts | 21 ++ arch/arm/boot/dts/imx6q-mba6.dtsi | 44 +++ arch/arm/boot/dts/imx6q-mba6a.dts | 20 + arch/arm/boot/dts/imx6q-mba6b.dts | 20 + arch/arm/boot/dts/imx6qdl-mba6.dtsi | 526 +++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-mba6a.dtsi | 36 ++ arch/arm/boot/dts/imx6qdl-mba6b.dtsi | 52 +++ arch/arm/boot/dts/imx6qp-mba6b.dts | 18 + 11 files changed, 785 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6dl-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6q-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6qdl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6a.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6b.dtsi create mode 100644 arch/arm/boot/dts/imx6qp-mba6b.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9753faf0f1aa5..e462dbe75f6ac 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -483,6 +483,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore-rqs.dtb \ imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-mira-rdk-nand.dtb \ @@ -584,6 +586,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-kp-tpc.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ imx6q-mccmon6.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ @@ -629,6 +633,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/imx6dl-mba6.dtsi new file mode 100644 index 0000000000000..b749b424bbd6e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <0>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <300>; + txd0-skew-ps = <120>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/imx6dl-mba6a.dts new file mode 100644 index 0000000000000..df0a96b28af0c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6a.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", + "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/imx6dl-mba6b.dts new file mode 100644 index 0000000000000..610b19d2db0fc --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6b.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", + "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/imx6q-mba6.dtsi new file mode 100644 index 0000000000000..0d7be45672916 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +}; + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/imx6q-mba6a.dts new file mode 100644 index 0000000000000..349a08605a5e8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6a.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-a", "tq,mba6a", + "tq,imx6q-tqma6q-a", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/imx6q-mba6b.dts new file mode 100644 index 0000000000000..02c9f3e91b8fb --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6b.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-b", "tq,mba6b", + "tq,imx6q-tqma6q-b", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi new file mode 100644 index 0000000000000..daf76345b1798 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + /delete-property/ mmc2; + /delete-property/ mmc3; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper: gpio-beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobeeper>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button1 { + label = "s6"; + linux,code = ; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s7"; + linux,code = ; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s8"; + linux,code = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_mba6_3p3v: regulator-mba6-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "supply-pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* PCIE.PWR_EN */ + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_mba6_3p3v>; + }; + + reg_vcc3v3_audio: regulator-vcc3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-audio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba6_3p3v>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + status = "okay"; + + ssi0 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) + >; + }; + + aud3 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; + cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; +}; + +&fec { + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <100000>; + micrel,force-master; + max-speed = <1000>; + }; + }; +}; + +&i2c1 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + ldoin-supply = <®_vcc3v3_audio>; + iov-supply = <®_mba6_3p3v>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + power-active-high; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* SD card slot */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_mba6_3p3v>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* does not work on unmodified starter kit */ + /* fsl,ext-reset-output; */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ + >; + }; + + pinctrl_ecspi1_mba6: ecspimba6grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* FEC phy IRQ */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 + /* FEC phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 + /* DSE = 100, 100k up, SPEED = MED */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 + /* DSE = 111, pull 100k up */ + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 + /* DSE = 111, pull external */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 + >; + }; + + pinctrl_gpiobeeper: gpiobeepergrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 + >; + }; + + pinctrl_gpiobuttons: gpiobuttongrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 + >; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 + + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 + + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 + + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 + + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 + + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 + + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 + + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + /* Watchdog out */ + MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi new file mode 100644 index 0000000000000..a61f2705a3400 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi new file mode 100644 index 0000000000000..9f9f7037c9e40 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/imx6qp-mba6b.dts new file mode 100644 index 0000000000000..eee2e09d6e94a --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-mba6b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2015-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ +/dts-v1/; + +#include +#include "imx6qp-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6QP on MBa6x"; + compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", + "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; +}; -- GitLab From 5a759dac6503e1432f5c30a01df483608b500a54 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:38 +0100 Subject: [PATCH 285/965] dt-bindings: arm: fsl: add TQ-Systems boards based on i.MX6Q/QP/DL The TQ-Systems MBa6x mainboard can be used with TQMa6 variants with i.MX6Q/QP/DL SoCs (TQMa6Q/QP/DL). The TQMa6Q and DL exist in two variants: The newer variants "A" have a hardware workaround for Erratum ERR006687, while variants "B" are missing such a workaround, so it needs to be handled in software. The erratum was fixed in i.MX6QP, so no "A" variant of the TQMa6QP exists. Signed-off-by: Matthias Schiffer Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a0eb42595ee2a..d6a3a67e4d374 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -323,6 +323,20 @@ properties: - const: toradex,apalis_imx6q - const: fsl,imx6q + - description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x + items: + - const: tq,imx6q-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-a + - const: fsl,imx6q + + - description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x + items: + - const: tq,imx6q-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-b + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: @@ -344,6 +358,13 @@ properties: - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 - const: fsl,imx6qp + - description: TQ-Systems TQMa6QP SoM on MBa6x + items: + - const: tq,imx6qp-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6qp-tqma6qp-b + - const: fsl,imx6qp + - description: i.MX6DL based Boards items: - enum: @@ -482,6 +503,20 @@ properties: - const: dh,imx6s-dhcom-som - const: fsl,imx6dl + - description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x + items: + - const: tq,imx6dl-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-a + - const: fsl,imx6dl + + - description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x + items: + - const: tq,imx6dl-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-b + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: -- GitLab From 97164c0419fc3985921f9be4c235748a68f9095e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Mon, 22 Nov 2021 17:25:19 +0100 Subject: [PATCH 286/965] dt-bindings: arm: fsl: Add Y Soft IOTA Crux/Crux+ boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree binding for Crux/Crux+ boards from the IOTA family. These boards have the very same HW configuration as the Orion board except the usage of Quad/QuadPlus SoC. Signed-off-by: Michal Vokáč Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d6a3a67e4d374..9679e3cd946a6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -240,6 +240,7 @@ properties: - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board + - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board - zealz,imx6q-gk802 # Zealz GK802 - zii,imx6q-zii-rdu2 # ZII RDU2 Board - const: fsl,imx6q @@ -348,6 +349,7 @@ properties: - kvg,vicutp # Kverneland UT1P board - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board + - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp -- GitLab From c25b80c560b8a2bb9ca60155553abff6223c73a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 22 Nov 2021 11:22:28 +0100 Subject: [PATCH 287/965] ARM: dts: Add FSG3 system controller and LEDs This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij --- .../boot/dts/intel-ixp42x-freecom-fsg-3.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts index 598586fc08623..b740403b05a92 100644 --- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts @@ -97,6 +97,65 @@ fis-index-block = <0x1f>; }; }; + + /* Small syscon with some LEDs at CS2 */ + syscon@2,0 { + compatible = "freecom,fsg-cs2-system-controller", "syscon"; + reg = <2 0x0 0x200>; + reg-io-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <2 0x0 0x0 0x200>; + + led@0,0 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x01>; + label = "fsg:blue:wlan"; + linux,default-trigger = "wlan"; + default-state = "on"; + }; + led@0,1 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x02>; + label = "fsg:blue:wan"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,2 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:sata"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,3 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:usb"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x08>; + label = "fsg:blue:sync"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,5 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x10>; + label = "fsg:blue:ring"; + linux,default-trigger = ""; + default-state = "on"; + }; + }; }; pci@c0000000 { -- GitLab From 65248dde81528d7f6cdd091e397d2d6e0b49dae1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Jul 2021 01:34:39 +0200 Subject: [PATCH 288/965] ARM: dts: Add Goramo MultiLink device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + .../dts/intel-ixp42x-goramo-multilink.dts | 180 ++++++++++++++++++ arch/arm/boot/dts/intel-ixp4xx.dtsi | 17 ++ 3 files changed, 198 insertions(+) create mode 100644 arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..4084535c64898 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -263,6 +263,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp46x-ixdp465.dtb \ intel-ixp42x-adi-coyote.dtb \ intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ intel-ixp42x-iomega-nas100d.dtb \ intel-ixp42x-dlink-dsm-g600.dtb \ intel-ixp42x-gateworks-gw2348.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts new file mode 100644 index 0000000000000..f80388b17a9e5 --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Goramo MultiLink Router + * There are two variants: + * - MultiLink Basic (a box) + * - MultiLink Max (19" rack mount) + * This device tree supports MultiLink Basic. + * This machine is based on IXP425. + * This is one of the few devices supporting the IXP4xx High-Speed Serial + * (HSS) link for a V.35 WAN interface. + * The hardware originates in Poland. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Goramo MultiLink Router"; + compatible = "goramo,multilink-router", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* + * 64 MB of RAM according to the manual. The MultiLink + * Max has 128 MB. + */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + /* + * 74HC4094 which is used as a rudimentary GPIO expander + * FIXME: + * - Create device tree bindings for this as GPIO expander + * - Write a pure DT GPIO driver using these bindings + * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) + */ + gpio_74: gpio-74hc4094 { + compatible = "nxp,74hc4094"; + cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + /* oe-gpios is optional */ + gpio-controller; + #gpio-cells = <2>; + /* We are not cascaded */ + registers-number = <1>; + gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", + "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", + "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. + * The slots have Ethernet, Ethernet, NEC and MPCI. + * The IDSELs are 11, 12, 13, 14. + */ + interrupt-map = + /* IDSEL 11 - Ethernet A */ + <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ + <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ + <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ + <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ + /* IDSEL 12 - Ethernet B */ + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ + /* IDSEL 13 - MPCI */ + <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ + <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ + <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ + <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ + /* IDSEL 14 - NEC */ + <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ + <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ + <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ + <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ + }; + + /* HSS links */ + npe@c8006000 { + hss@0 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; + hss@1 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 10>; + intel,queue-chl-txready = <&qmgr 35>; + intel,queue-pkt-rx = <&qmgr 0>; + intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; + intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; + intel,queue-pkt-txdone = <&qmgr 9>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; + }; + }; + + /* EthB */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 32>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 33>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index 46fede0214768..51a716c596698 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -139,6 +139,23 @@ npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + /* NPE-A contains two high-speed serial links */ + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; + + hss@1 { + compatible = "intel,ixp4xx-hss"; + reg = <1>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; /* NPE-C contains a crypto accelerator */ crypto { -- GitLab From 6786e78d6b7a7236df7ded9ae0e09fa1cba950fb Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:31 +0200 Subject: [PATCH 289/965] ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X Commit 73d04ca5f4ac ("ARM: ixp4xx: Delete Intel reference design boardfiles") removes the definition of the configs MACH_IXDP465 and MACH_KIXRP435, but misses to remove the configs CPU_IXP43X and CPU_IXP46X that depend on those removed configs, and hence are dead now. Fortunately, ./scripts/checkkconfigsymbols.py warns: MACH_IXDP465 Referencing files: arch/arm/mach-ixp4xx/Kconfig MACH_KIXRP435 Referencing files: arch/arm/mach-ixp4xx/Kconfig Remove the dead configs CPU_IXP43X and CPU_IXP46X. A further quick grep for the name of those two symbols did not show any use of the two config symbols; so, there are no further clean-up activities beyond this config removal needed. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ixp4xx/Kconfig | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 365a5853d3106..4c787b4be62bb 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -39,19 +39,6 @@ config ARCH_PRPMC1100 PrPCM1100 Processor Mezanine Module. For more information on this platform, see . -# -# Certain registers and IRQs are only enabled if supporting IXP465 CPUs -# -config CPU_IXP46X - bool - depends on MACH_IXDP465 - default y - -config CPU_IXP43X - bool - depends on MACH_KIXRP435 - default y - comment "IXP4xx Options" config IXP4XX_PCI_LEGACY -- GitLab From 019cd8a9e3bcbbf6bac8036a9ae545f7858e0c08 Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Tue, 2 Nov 2021 16:02:01 -0600 Subject: [PATCH 290/965] ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h Commit b00ced38e317 ("ARM: ixp4xx: Delete Avila boardfiles") removed the last use of but left the header file in place. Nothing uses this file, delete it now. Cc: Linus Walleij Cc: Arnd Bergmann Signed-off-by: Jonathan Corbet Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- include/linux/platform_data/pata_ixp4xx_cf.h | 21 -------------------- 1 file changed, 21 deletions(-) delete mode 100644 include/linux/platform_data/pata_ixp4xx_cf.h diff --git a/include/linux/platform_data/pata_ixp4xx_cf.h b/include/linux/platform_data/pata_ixp4xx_cf.h deleted file mode 100644 index e60fa41da4a52..0000000000000 --- a/include/linux/platform_data/pata_ixp4xx_cf.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PLATFORM_DATA_PATA_IXP4XX_H -#define __PLATFORM_DATA_PATA_IXP4XX_H - -#include - -/* - * This structure provide a means for the board setup code - * to give information to th pata_ixp4xx driver. It is - * passed as platform_data. - */ -struct ixp4xx_pata_data { - volatile u32 *cs0_cfg; - volatile u32 *cs1_cfg; - unsigned long cs0_bits; - unsigned long cs1_bits; - void __iomem *cmd; - void __iomem *ctl; -}; - -#endif -- GitLab From 4172986a64dae744abe625075533ce38f6670019 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 24 Nov 2021 14:32:14 +0530 Subject: [PATCH 291/965] arm64: dts: lx2162a: Add CAN nodes for LX2162A-QDS Enable CAN support for LX2162A-QDS in board dts. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index e1defee1ad27a..67e07a8a42bd2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -167,6 +167,14 @@ }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &crypto { status = "okay"; }; -- GitLab From 474b61a7106b4b5b29eb2d98b0c2ba1e675019d5 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 27 Nov 2021 14:01:18 +0100 Subject: [PATCH 292/965] arm64: dts: imx8mq: fix the schema check errors for fsl,tmu-calibration fsl,tmu-calibration is in u32-matrix. Use matching property syntax. No functional changes. Fixes warnings as: $ make dtbs_check ... arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dt.yaml: tmu@30260000: \ fsl,tmu-calibration:0: Additional items are not allowed (1, 41, 2, 47, \ 3, 53, 4, 61, 5, 67, 6, 75, 7, 81, 8, 87, 9, 95, 10, 103, 11, 111, 65536, \ 27, 65537, 35, 65538, 43, 65539, 51, 65540, 59, 65541, 67, 65542, 75, \ 65543, 85, 65544, 93, 65545, 103, 65546, 112, 131072, 23, 131073, 35, \ 131074, 45, 131075, 55, 131076, 65, 131077, 75, 131078, 87, 131079, 99, \ 131080, 111, 196608, 21, 196609, 33, 196610, 45, 196611, 57, 196612, 69, \ 196613, 83, 196614, 95, 196615, 113 were unexpected) From schema: Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml ... Signed-off-by: David Heidelberg Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 86 +++++++++++------------ 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 95d8b95d61203..5ab9e02bd929d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -457,49 +457,49 @@ clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; little-endian; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; + fsl,tmu-calibration = <0x00000000 0x00000023>, + <0x00000001 0x00000029>, + <0x00000002 0x0000002f>, + <0x00000003 0x00000035>, + <0x00000004 0x0000003d>, + <0x00000005 0x00000043>, + <0x00000006 0x0000004b>, + <0x00000007 0x00000051>, + <0x00000008 0x00000057>, + <0x00000009 0x0000005f>, + <0x0000000a 0x00000067>, + <0x0000000b 0x0000006f>, + + <0x00010000 0x0000001b>, + <0x00010001 0x00000023>, + <0x00010002 0x0000002b>, + <0x00010003 0x00000033>, + <0x00010004 0x0000003b>, + <0x00010005 0x00000043>, + <0x00010006 0x0000004b>, + <0x00010007 0x00000055>, + <0x00010008 0x0000005d>, + <0x00010009 0x00000067>, + <0x0001000a 0x00000070>, + + <0x00020000 0x00000017>, + <0x00020001 0x00000023>, + <0x00020002 0x0000002d>, + <0x00020003 0x00000037>, + <0x00020004 0x00000041>, + <0x00020005 0x0000004b>, + <0x00020006 0x00000057>, + <0x00020007 0x00000063>, + <0x00020008 0x0000006f>, + + <0x00030000 0x00000015>, + <0x00030001 0x00000021>, + <0x00030002 0x0000002d>, + <0x00030003 0x00000039>, + <0x00030004 0x00000045>, + <0x00030005 0x00000053>, + <0x00030006 0x0000005f>, + <0x00030007 0x00000071>; #thermal-sensor-cells = <1>; }; -- GitLab From e523b7c54c05caec488cc062f0b6c497b1837ed6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:08 -0600 Subject: [PATCH 293/965] arm64: dts: imx8mm: Add CSI nodes There is a csi bridge and csis interface that tie together to allow csi2 capture. Signed-off-by: Adam Ford Reviewed-by: Laurent Pinchart Reviewed-by: Tim Harvey Tested-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 5b9c2cca9ac4b..a31cf2b9769c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1096,6 +1096,22 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + csi: csi@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; + reg = <0x32e20000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + clock-names = "mclk"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; + status = "disabled"; + + port { + csi_in: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_out>; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1123,6 +1139,41 @@ #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; -- GitLab From 9f046930657e9e231a2f9139cdcb611805b19d7c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:10 -0600 Subject: [PATCH 294/965] arm64: dts: imx8mm-beacon: Enable OV5640 Camera The baseboard has support for a TDNext 5640 Camera which uses an OV5640 connected to a 2-lane CSI2 interface. With the CSI and mipi_csi2 drivers pointing to an OV5640 camera, the media pipeline can be configured with the following: media-ctl --links "'ov5640 1-003c':0->'imx7-mipi-csis.0':0[1]" The camera and various nodes in the pipeline can be configured for UYVY: media-ctl -v -V "'ov5640 1-003c':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'csi':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../freescale/imx8mm-beacon-baseboard.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 4097a66163b2a..0da311898e01e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -54,6 +54,16 @@ enable-active-high; }; + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -78,6 +88,10 @@ }; }; +&csi { + status = "okay"; +}; + &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; @@ -101,6 +115,30 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &i2c4 { @@ -152,6 +190,18 @@ }; }; +&mipi_csi { + status = "okay"; + ports { + port@0 { + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -238,6 +288,14 @@ >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 -- GitLab From 7306251b1e99a5e765b84ca2bd3ce3a43a39a454 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:09 -0600 Subject: [PATCH 295/965] arm64: defconfig: Enable VIDEO_IMX_MEDIA To use a camera, the CSIS and CSI drivers need to be enabled with VIDEO_IMX_MEDIA. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e2b9bdd7024..bc261cf2ef5a5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -958,6 +958,7 @@ CONFIG_MFD_CROS_EC_DEV=y CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_IMX_MEDIA=m CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y -- GitLab From 8791aa1891a9b35fabde693eed597f32dbbeb963 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:11 -0600 Subject: [PATCH 296/965] arm64: defconfig: Enable OV5640 The Beacon EmbeddedWorks imx8mm development kit has a TD Next 5640 Camera. Enable the OV5640 driver to use the camera. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bc261cf2ef5a5..4c1eb9aae5e5d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -668,6 +668,7 @@ CONFIG_VIDEO_QCOM_VENUS=m CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_VIDEO_RCAR_DRIF=m CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_DRM=m -- GitLab From 8355d48fd1ec1c01b5ab1f8071562cf3e3884214 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:00 +0800 Subject: [PATCH 297/965] dt-bindings: arm: fsl: Add binding for imx8ulp evk Add the dt binding for i.MX8ULP EVK board. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng Acked-by: Rob Herring Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 9679e3cd946a6..6604aea7d6466 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -872,6 +872,12 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: i.MX8ULP based Boards + items: + - enum: + - fsl,imx8ulp-evk # i.MX8ULP EVK Board + - const: fsl,imx8ulp + - description: Freescale Vybrid Platform Device Tree Bindings -- GitLab From fe6291e963134d3609defff4547beeb2bb5bf158 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:01 +0800 Subject: [PATCH 298/965] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp Add the basic dtsi support for i.MX8ULP. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8ulp-pinfunc.h | 978 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 396 +++++++ 2 files changed, 1374 insertions(+) create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h new file mode 100755 index 0000000000000..b204ac79b4497 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 +#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 +#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 +#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 +#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 +#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 +#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 +#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 +#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 +#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 +#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 +#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 +#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 +#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 +#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 +#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 +#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 +#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 +#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 +#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 +#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 +#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 +#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 +#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 +#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 +#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 +#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 +#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 +#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 +#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 +#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 +#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 +#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 +#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 +#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 +#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 +#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 +#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 +#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 +#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 +#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 +#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 +#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 +#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 +#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 +#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 +#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 +#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 +#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 +#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 +#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 +#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 +#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 +#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 +#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 +#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 +#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 +#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 +#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 +#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 +#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 +#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 +#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 +#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 +#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 +#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 +#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 +#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 +#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 +#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 +#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 +#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 +#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 +#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 +#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 +#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 +#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 +#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 +#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 +#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 +#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 +#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 +#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 +#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 +#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 +#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 +#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 +#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 +#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 +#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 +#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 +#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 +#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 +#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 +#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 +#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 +#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 +#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 +#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 +#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 +#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 +#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 +#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 +#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 +#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 +#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 +#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 +#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 +#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 +#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 +#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 +#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 +#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 +#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 +#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 +#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 +#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 +#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 +#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 +#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 +#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 +#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 +#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 +#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 +#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 +#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 +#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 +#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 +#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 +#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 +#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 +#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 +#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 +#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 +#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 +#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 +#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 +#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 +#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 +#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 +#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 +#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 +#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 +#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 +#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 +#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 +#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 +#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 +#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 +#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 +#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 +#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 +#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 +#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 +#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 +#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 +#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 +#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 +#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 +#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 +#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 +#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 +#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 +#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 +#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 +#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 +#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 +#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 +#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 +#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 +#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 +#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 +#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 +#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 +#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 +#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 +#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 +#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 +#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 +#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 +#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 +#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 +#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 +#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 +#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 +#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 +#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 +#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 +#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 +#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 +#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 +#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 +#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 +#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 +#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 +#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 +#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 +#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 +#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 +#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 +#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 +#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 +#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 +#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 +#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 +#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 +#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 +#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 +#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 +#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 +#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 +#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 +#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 +#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 +#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 +#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 +#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 +#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 +#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 +#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 +#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 +#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 +#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 +#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 +#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 +#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 +#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 +#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 +#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 +#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 +#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 +#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 +#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 +#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 +#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 +#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 +#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 +#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 +#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 +#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 +#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 +#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 +#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 +#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 +#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 +#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 +#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 +#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 +#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 +#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 +#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 +#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 +#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 +#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 +#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 +#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 +#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 +#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 +#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 +#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 +#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 +#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 +#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 +#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 +#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 +#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 +#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 +#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 +#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 +#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 +#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 +#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 +#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 +#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 +#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 +#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 +#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 +#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 +#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 +#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 +#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 +#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 +#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 +#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 +#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 +#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 +#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 +#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 +#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 +#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 +#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 +#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 +#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 +#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 +#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 +#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 +#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 +#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 +#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 +#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 +#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 +#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 +#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 +#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 +#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 +#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 +#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 +#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 +#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 +#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 +#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 +#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 +#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 +#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 +#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 +#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 +#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 +#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 +#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 +#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 +#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 +#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 +#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 +#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 +#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 +#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 +#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 +#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 +#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 +#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 +#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 +#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 +#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 +#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 +#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 +#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 +#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 +#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 +#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 +#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 +#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 +#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 +#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 +#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 +#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 +#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 +#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 +#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 +#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 +#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 +#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 +#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 +#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 +#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 +#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 +#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 +#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 +#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 +#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 +#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 +#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 +#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 +#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 +#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 +#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 +#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 +#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 +#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 +#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 +#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 +#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 +#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 +#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 +#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 +#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 +#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 +#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 +#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 +#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 +#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 +#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 +#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 +#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 +#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 +#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 +#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 +#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 +#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 +#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 +#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 +#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 +#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 +#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 +#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 +#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 +#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 +#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 +#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 +#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 +#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 +#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 +#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 +#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 +#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 +#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 + +#endif /* __DTS_IMX8ULP_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi new file mode 100644 index 0000000000000..fb8714379026f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include +#include +#include + +#include "imx8ulp-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpiod; + gpio1 = &gpioe; + gpio2 = &gpiof; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@2d400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ + <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + frosc: clock-frosc { + compatible = "fixed-clock"; + clock-frequency = <192000000>; + clock-output-names = "frosc"; + #clock-cells = <0>; + }; + + lposc: clock-lposc { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "lposc"; + #clock-cells = <0>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + per_bridge3: bus@29000000 { + compatible = "simple-bus"; + reg = <0x29000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wdog3: watchdog@292a0000 { + compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; + reg = <0x292a0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + timeout-sec = <40>; + }; + + cgc1: clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; + clock-names = "rosc", "sosc", "frosc", "lposc"; + #clock-cells = <1>; + }; + + pcc3: clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + }; + + tpm5: tpm@29340000 { + compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; + reg = <0x29340000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_TPM5>, + <&pcc3 IMX8ULP_CLK_TPM5>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + lpi2c4: i2c@29370000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29370000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, + <&pcc3 IMX8ULP_CLK_LPI2C4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: i2c@29380000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29380000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, + <&pcc3 IMX8ULP_CLK_LPI2C5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial@29390000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29390000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpspi4: spi@293b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293b0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, + <&pcc3 IMX8ULP_CLK_LPSPI4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + + lpspi5: spi@293c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293c0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, + <&pcc3 IMX8ULP_CLK_LPSPI5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + }; + + per_bridge4: bus@29800000 { + compatible = "simple-bus"; + reg = <0x29800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcc4: clock-controller@29800000 { + compatible = "fsl,imx8ulp-pcc4"; + reg = <0x29800000 0x10000>; + #clock-cells = <1>; + }; + + lpi2c6: i2c@29840000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29840000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, + <&pcc4 IMX8ULP_CLK_LPI2C6>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: i2c@29850000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29850000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, + <&pcc4 IMX8ULP_CLK_LPI2C7>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@29860000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29860000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@29870000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29870000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc1: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + }; + + usdhc0: mmc@298d0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298d0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc1: mmc@298e0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298e0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@298f0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298f0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + + gpioe: gpio@2d000000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; + }; + + gpiof: gpio@2d010000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + per_bridge5: bus@2d800000 { + compatible = "simple-bus"; + reg = <0x2d800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cgc2: clock-controller@2da60000 { + compatible = "fsl,imx8ulp-cgc2"; + reg = <0x2da60000 0x10000>; + clocks = <&sosc>, <&frosc>; + clock-names = "sosc", "frosc"; + #clock-cells = <1>; + }; + + pcc5: clock-controller@2da70000 { + compatible = "fsl,imx8ulp-pcc5"; + reg = <0x2da70000 0x10000>; + #clock-cells = <1>; + }; + }; + + gpiod: gpio@2e200000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, + <&pcc5 IMX8ULP_CLK_RGPIOD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 24>; + }; + }; +}; -- GitLab From a6e917b7366c5d91accafa2b7b45090e6b632987 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:02 +0800 Subject: [PATCH 299/965] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Add the basic dts file for i.MX8ULP EVK board. Only the necessary devices for minimal system boot up are enabled: enet, emmc, usb, console uart. some of the devices' pin status may lost during low power mode, so additional sleep pinctrl properties are included by default. Reviewed-by: Dong Aisheng Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 64 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a14a6173b7658..c646161927945 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts new file mode 100644 index 0000000000000..33e84c4e9ed89 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; +}; -- GitLab From ee6302d90db96e1f0a49305ba9db4969b378d585 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:42 +0100 Subject: [PATCH 300/965] dt-bindings: arm: fsl: add TQMa8MxML boards TQMa8MxML is a SOM family using NXP i.MX8MM[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mm-" for the module and "tq,imx8mm--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6604aea7d6466..79789e64f673b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -792,6 +792,17 @@ properties: - const: variscite,var-som-mx8mm - const: fsl,imx8mm + - description: + TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx + - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM + - const: fsl,imx8mm + - description: i.MX8MN based Boards items: - enum: -- GitLab From 50ef92d89c12809fe8f98d0e0cab7b6765e10898 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:45 +0100 Subject: [PATCH 301/965] dt-bindings: arm: fsl: add TQMa8MxNL boards TQMa8MxNL is a SOM family using NXP i.MX8MN[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mn-" for the module and "tq,imx8mn--" for mainboards Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 79789e64f673b..a705eabe1cfc7 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -818,6 +818,17 @@ properties: - const: variscite,var-som-mx8mn - const: fsl,imx8mn + - description: + TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx + - const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM + - const: fsl,imx8mn + - description: i.MX8MP based Boards items: - enum: -- GitLab From 9aa637b5673ca100f219b13b16dbc19a0b77ef73 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:47 +0100 Subject: [PATCH 302/965] dt-bindings: arm: fsl: add TQMa8Mx boards TQMa8Mx is a SOM family using NXP i.MX8M[Q,QL, D] CPU MBa8Mx is a evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mq-" for the module and "tq,imx8mq--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a705eabe1cfc7..c35076cc551d4 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -865,6 +865,15 @@ properties: - const: purism,librem5 - const: fsl,imx8mq + - description: + TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip + variants. It is designed to be clicked on different carrier boards. + items: + - enum: + - tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx + - const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM + - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards items: - enum: -- GitLab From dfcd1b6f7620eef1f0060b64408c05419297456a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:43 +0100 Subject: [PATCH 303/965] arm64: dts: freescale: add initial device tree for TQMa8MQML with i.MX8MM This adds support for TQMa8MQML module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 253 +++++++++++++ .../boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 335 ++++++++++++++++++ arch/arm64/boot/dts/freescale/mba8mx.dtsi | 282 +++++++++++++++ 4 files changed, 871 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi create mode 100644 arch/arm64/boot/dts/freescale/mba8mx.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c646161927945..aed0d0c80a438 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts new file mode 100644 index 0000000000000..7844878788f43 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx"; + compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + extcon_usbotg1: extcon-usbotg1 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_extcon>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + extcon = <&extcon_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_hub_vbus>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander: expandergrp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usb1_extcon: usb1-extcongrp { + fsl,pins = ; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi new file mode 100644 index 0000000000000..284e62acc0b46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; + compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM / VPU */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi new file mode 100644 index 0000000000000..f27e3c8de916a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include + +/* TQ-Systems GmbH MBa8Mx baseboard */ + +/ { + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm4 0 250000 0>; + beeper-hz = <4000>; + amp-supply = <®_vcc_3v3>; + }; + + chosen { + // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobutton>; + autorepeat; + + switch1 { + label = "switch1"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + btn2: switch2 { + label = "switch2"; + linux,code = ; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch3 { + label = "switch3"; + linux,code = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2: led2 { + label = "led2"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_hub_vbus: regulator-hub-vbus { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_HUB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sn65dsi83_1v8: regulator-sn65dsi83-1v8 { + compatible = "regulator-fixed"; + regulator-name = "SN65DSI83_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&expander0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai3>; + audio-codec = <&tlv320aic3x04>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-supply = <®_vcc_3v3>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0xe>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + enet-phy-lane-no-swap; + reset-gpios = <&expander2 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <500>; + }; + }; +}; + +&i2c1 { + expander0: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + sd-mux-oe-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "SD_MUX_EN#"; + }; + + boot-cfg-oe-hog { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BOOT_CFG_OE#"; + }; + + rst-usb-hub-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "RST_USB_HUB#"; + }; + }; + + expander1: gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; + + sensor1: sensor@1f { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + eeprom3: eeprom@57 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + #sound-dai-cells = <0>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 is assigned to Cortex-M4 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; -- GitLab From 3e56e354db6d34b211fc76b3ac228fc3613663d3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:46 +0100 Subject: [PATCH 304/965] arm64: dts: freescale: add initial device tree for TQMa8MQNL with i.MX8MN This adds support for TQMa8MQNL module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 237 +++++++++++++ .../boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 322 ++++++++++++++++++ 3 files changed, 560 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index aed0d0c80a438..53b70941427b4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts new file mode 100644 index 0000000000000..3f1e49bfe38f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mn-tqma8mqnl.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx"; + compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +/* Located on TQMa8MxML-ADAP */ +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0hub_sel>; + + sel-usb-hub-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander2>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + power-active-high; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander2: expander2grp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usb0hub_sel: usb0hub-selgrp { + /* SEL_USB_HUB_B */ + fsl,pins = ; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi new file mode 100644 index 0000000000000..9ea28941068da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mn.dtsi" + +/ { + model = "TQ-Systems i.MX8MN TQMa8MxNL"; + compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; -- GitLab From b186b8b6e770570706f533dcf4c70b39e9ee31d2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:48 +0100 Subject: [PATCH 305/965] arm64: dts: freescale: add initial device tree for TQMa8Mx with i.MX8M This adds support for TQMa8Mx module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 349 +++++++++++++++++ .../boot/dts/freescale/imx8mq-tqma8mq.dtsi | 360 ++++++++++++++++++ 3 files changed, 710 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 53b70941427b4..58971bd89901e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts new file mode 100644 index 0000000000000..d7660eab68b94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mq-tqma8mq.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx"; + compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + extcon_usbotg: extcon-usbotg0 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regotgvbus>; + regulator-name = "MBA8MQ_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&btn2 { + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; +}; + +&gpio_leds { + led3 { + label = "led3"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + mpcie-rst-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "MPCIE_RST#"; + }; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&led2 { + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +}; + +&pcie0 { + reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +/* + * miniPCIe, also usable for cards with USB. Therefore configure the reset as + * static gpio hog. + */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +/* console */ +&uart3 { + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +}; + +&usb3_phy0 { + vbus-supply = <®_otg_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* we implement dual role but not full featured OTG */ + extcon = <&extcon_usbotg>; + hnp-disable; + srp-disable; + adp-disable; + /* OC not supported due to non matching active polarity */ + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander: expandergrp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_regotgvbus: reggotgvbusgrp { + /* USB1 OTG PWR as GPIO */ + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usbcon0: usb0congrp { + /* ID: floating / high: device, low: host -> use PU */ + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi new file mode 100644 index 0000000000000..8aedcddfeab87 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +#include "imx8mq.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ"; + compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_arm: regulator-vdd-arm { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-name = "TQMa8Mx_DVFS"; + regulator-type = "voltage"; + regulator-settling-time-us = <150000>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + states = <900000 0x1 1000000 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&gpu { + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + /* VDD_GPU */ + sw1a_reg: sw1ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* VDD_VPU */ + sw1c_reg: sw1c { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* NVCC_DRAM */ + sw2_reg: sw2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* VDD_DRAM */ + sw3a_reg: sw3ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */ + nvcc_1v8_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + /* not used */ + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + /* VDD_PHY_0V9 */ + vgen2_reg: vgen2 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + /* VDD_PHY_1V8 */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + /* VDDA_1V8 */ + vgen4_reg: vgen4 { + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + /* VDD_PHY_3V3 */ + vgen5_reg: vgen5 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + /* not used */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-names = "irq"; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + quartz-load-femtofarads = <7000>; + + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie0 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&pcie1 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + assigned-clocks = <&clk IMX8MQ_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +/* Attention: wdog reset forcing POR needs baseboard support */ +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_dvfs: dvfsgrp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; -- GitLab From 2ecc02a6b3f0e2a4339952c4f8b86a4d87876930 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:44 +0100 Subject: [PATCH 306/965] arm64: defconfig: enable drivers for TQ TQMa8MxML-MBa8Mx With the device tree in place, enable missing drivers as modules, if possible. PHY driver needs built-in for interrupt support. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4c1eb9aae5e5d..13207d24b564b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -363,6 +363,7 @@ CONFIG_MICROSEMI_PHY=y CONFIG_AT803X_PHY=y CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y +CONFIG_DP83867_PHY=y CONFIG_VITESSE_PHY=y CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m @@ -397,6 +398,7 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_PWM_BEEPER=m CONFIG_INPUT_PWM_VIBRA=m CONFIG_INPUT_HISI_POWERKEY=y # CONFIG_SERIO_SERPORT is not set @@ -555,6 +557,7 @@ CONFIG_BATTERY_MAX17042=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_JC42=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m @@ -793,6 +796,7 @@ CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_SIMPLE_MUX=m CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m CONFIG_SND_SOC_WCD934X=m CONFIG_SND_SOC_WM8904=m CONFIG_SND_SOC_WM8960=m @@ -908,6 +912,7 @@ CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_HYM8563=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_M41T80=m CONFIG_RTC_DRV_RX8581=m @@ -1176,6 +1181,8 @@ CONFIG_SLIM_QCOM_NGD_CTRL=m CONFIG_MUX_MMIO=y CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m +CONFIG_INTERCONNECT_IMX8MM=m +CONFIG_INTERCONNECT_IMX8MN=m CONFIG_INTERCONNECT_IMX8MQ=m CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_MSM8916=m -- GitLab From 29bf0ff5ae18ad1a6dd183569cc097e578052c57 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 23:58:19 +0200 Subject: [PATCH 307/965] ARM: dts: exynos: Rename hsi2c nodes to i2c for Exynos5260 In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204215820.17378-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 52fa211525cea..524d244050e0c 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -368,7 +368,7 @@ status = "disabled"; }; - hsi2c_0: hsi2c@12da0000 { + hsi2c_0: i2c@12da0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DA0000 0x1000>; interrupts = ; @@ -381,7 +381,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@12db0000 { + hsi2c_1: i2c@12db0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DB0000 0x1000>; interrupts = ; @@ -394,7 +394,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@12dc0000 { + hsi2c_2: i2c@12dc0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DC0000 0x1000>; interrupts = ; @@ -407,7 +407,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@12dd0000 { + hsi2c_3: i2c@12dd0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DD0000 0x1000>; interrupts = ; -- GitLab From 8858f8622e82170ec184971b66c7a455816190f8 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 23:58:20 +0200 Subject: [PATCH 308/965] arm64: dts: exynos: Rename hsi2c nodes to i2c for Exynos5433 and Exynos7 In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204215820.17378-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 +++++++++++----------- arch/arm64/boot/dts/exynos/exynos7.dtsi | 24 +++++++++++----------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 4422021cf4b23..bfe4ed8a23d62 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1585,7 +1585,7 @@ status = "disabled"; }; - hsi2c_0: hsi2c@14e40000 { + hsi2c_0: i2c@14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>; interrupts = ; @@ -1598,7 +1598,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@14e50000 { + hsi2c_1: i2c@14e50000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e50000 0x1000>; interrupts = ; @@ -1611,7 +1611,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@14e60000 { + hsi2c_2: i2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; interrupts = ; @@ -1624,7 +1624,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@14e70000 { + hsi2c_3: i2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; interrupts = ; @@ -1637,7 +1637,7 @@ status = "disabled"; }; - hsi2c_4: hsi2c@14ec0000 { + hsi2c_4: i2c@14ec0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ec0000 0x1000>; interrupts = ; @@ -1650,7 +1650,7 @@ status = "disabled"; }; - hsi2c_5: hsi2c@14ed0000 { + hsi2c_5: i2c@14ed0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ed0000 0x1000>; interrupts = ; @@ -1663,7 +1663,7 @@ status = "disabled"; }; - hsi2c_6: hsi2c@14ee0000 { + hsi2c_6: i2c@14ee0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ee0000 0x1000>; interrupts = ; @@ -1676,7 +1676,7 @@ status = "disabled"; }; - hsi2c_7: hsi2c@14ef0000 { + hsi2c_7: i2c@14ef0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ef0000 0x1000>; interrupts = ; @@ -1689,7 +1689,7 @@ status = "disabled"; }; - hsi2c_8: hsi2c@14d90000 { + hsi2c_8: i2c@14d90000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14d90000 0x1000>; interrupts = ; @@ -1702,7 +1702,7 @@ status = "disabled"; }; - hsi2c_9: hsi2c@14da0000 { + hsi2c_9: i2c@14da0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14da0000 0x1000>; interrupts = ; @@ -1715,7 +1715,7 @@ status = "disabled"; }; - hsi2c_10: hsi2c@14de0000 { + hsi2c_10: i2c@14de0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14de0000 0x1000>; interrupts = ; @@ -1728,7 +1728,7 @@ status = "disabled"; }; - hsi2c_11: hsi2c@14df0000 { + hsi2c_11: i2c@14df0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14df0000 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index c73a597ca66e3..c3efbc8add384 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -359,7 +359,7 @@ interrupts = ; }; - hsi2c_0: hsi2c@13640000 { + hsi2c_0: i2c@13640000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13640000 0x1000>; interrupts = ; @@ -372,7 +372,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@13650000 { + hsi2c_1: i2c@13650000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13650000 0x1000>; interrupts = ; @@ -385,7 +385,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@14e60000 { + hsi2c_2: i2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; interrupts = ; @@ -398,7 +398,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@14e70000 { + hsi2c_3: i2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; interrupts = ; @@ -411,7 +411,7 @@ status = "disabled"; }; - hsi2c_4: hsi2c@13660000 { + hsi2c_4: i2c@13660000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13660000 0x1000>; interrupts = ; @@ -424,7 +424,7 @@ status = "disabled"; }; - hsi2c_5: hsi2c@13670000 { + hsi2c_5: i2c@13670000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13670000 0x1000>; interrupts = ; @@ -437,7 +437,7 @@ status = "disabled"; }; - hsi2c_6: hsi2c@14e00000 { + hsi2c_6: i2c@14e00000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e00000 0x1000>; interrupts = ; @@ -450,7 +450,7 @@ status = "disabled"; }; - hsi2c_7: hsi2c@13e10000 { + hsi2c_7: i2c@13e10000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13e10000 0x1000>; interrupts = ; @@ -463,7 +463,7 @@ status = "disabled"; }; - hsi2c_8: hsi2c@14e20000 { + hsi2c_8: i2c@14e20000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e20000 0x1000>; interrupts = ; @@ -476,7 +476,7 @@ status = "disabled"; }; - hsi2c_9: hsi2c@13680000 { + hsi2c_9: i2c@13680000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13680000 0x1000>; interrupts = ; @@ -489,7 +489,7 @@ status = "disabled"; }; - hsi2c_10: hsi2c@13690000 { + hsi2c_10: i2c@13690000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13690000 0x1000>; interrupts = ; @@ -502,7 +502,7 @@ status = "disabled"; }; - hsi2c_11: hsi2c@136a0000 { + hsi2c_11: i2c@136a0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x136a0000 0x1000>; interrupts = ; -- GitLab From 856732adc1acbfdf457ec7a875a252d6fb039294 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:33 +0530 Subject: [PATCH 309/965] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ec9f1d1cd50fb..a797eaa917b7f 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -24,6 +24,91 @@ chosen { stdout-path = "serial0:115200n8"; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in_ltdc: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_ltdc>; + }; + }; }; &sdmmc1 { -- GitLab From 854b020b165fbdf040ab6872a75a6094803a6932 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:34 +0530 Subject: [PATCH 310/965] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bcaf7be3ab375..b07720ea96114 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -77,6 +77,7 @@ properties: items: - enum: - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM - const: st,stm32mp157 -- GitLab From 3ff0810ffc4793bfde454a452837484d0815aa14 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:35 +0530 Subject: [PATCH 311/965] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + ...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..641220e970e8c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1140,6 +1140,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts new file mode 100644 index 0000000000000..2a2829283456d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-stm32mp1-ctouch2-of10", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; -- GitLab From f154f290855b070cc94dd44ad253c0ef8a9337bb Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Thu, 2 Dec 2021 16:32:24 +0100 Subject: [PATCH 312/965] x86/mm/64: Flush global TLB on boot and AP bringup The AP bringup code uses the trampoline_pgd page-table which establishes global mappings in the user range of the address space. Flush the global TLB entries after the indentity mappings are removed so no stale entries remain in the TLB. Signed-off-by: Joerg Roedel Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211202153226.22946-3-joro@8bytes.org --- arch/x86/include/asm/tlbflush.h | 5 +++++ arch/x86/kernel/head64.c | 2 ++ arch/x86/kernel/head_64.S | 19 ++++++++++++++++++- arch/x86/mm/tlb.c | 8 ++------ 4 files changed, 27 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index b587a9ee9cb25..98fa0a1140742 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -261,4 +261,9 @@ extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); #endif /* !MODULE */ +static inline void __native_tlb_flush_global(unsigned long cr4) +{ + native_write_cr4(cr4 ^ X86_CR4_PGE); + native_write_cr4(cr4); +} #endif /* _ASM_X86_TLBFLUSH_H */ diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index fc5371a7e9d19..75acb6027a87a 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -483,6 +483,8 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data) /* Kill off the identity-map trampoline */ reset_early_page_tables(); + __native_tlb_flush_global(native_read_cr4()); + clear_bss(); clear_page(init_top_pgt); diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index d8b3ebd2bb85f..9c63fc5988cda 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -166,9 +166,26 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) call sev_verify_cbit popq %rsi - /* Switch to new page-table */ + /* + * Switch to new page-table + * + * For the boot CPU this switches to early_top_pgt which still has the + * indentity mappings present. The secondary CPUs will switch to the + * init_top_pgt here, away from the trampoline_pgd and unmap the + * indentity mapped ranges. + */ movq %rax, %cr3 + /* + * Do a global TLB flush after the CR3 switch to make sure the TLB + * entries from the identity mapping are flushed. + */ + movq %cr4, %rcx + movq %rcx, %rax + xorq $X86_CR4_PGE, %rcx + movq %rcx, %cr4 + movq %rax, %cr4 + /* Ensure I am executing from virtual addresses */ movq $1f, %rax ANNOTATE_RETPOLINE_SAFE diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 59ba2968af1b3..1e6513f95133a 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1148,7 +1148,7 @@ void flush_tlb_one_user(unsigned long addr) */ STATIC_NOPV void native_flush_tlb_global(void) { - unsigned long cr4, flags; + unsigned long flags; if (static_cpu_has(X86_FEATURE_INVPCID)) { /* @@ -1168,11 +1168,7 @@ STATIC_NOPV void native_flush_tlb_global(void) */ raw_local_irq_save(flags); - cr4 = this_cpu_read(cpu_tlbstate.cr4); - /* toggle PGE */ - native_write_cr4(cr4 ^ X86_CR4_PGE); - /* write old PGE again and flush TLBs */ - native_write_cr4(cr4); + __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); raw_local_irq_restore(flags); } -- GitLab From 71d5049b053876afbde6c3273250b76935494ab2 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Thu, 2 Dec 2021 16:32:25 +0100 Subject: [PATCH 313/965] x86/mm: Flush global TLB when switching to trampoline page-table Move the switching code into a function so that it can be re-used and add a global TLB flush. This makes sure that usage of memory which is not mapped in the trampoline page-table is reliably caught. Also move the clearing of CR4.PCIDE before the CR3 switch because the cr4_clear_bits() function will access data not mapped into the trampoline page-table. Signed-off-by: Joerg Roedel Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211202153226.22946-4-joro@8bytes.org --- arch/x86/include/asm/realmode.h | 1 + arch/x86/kernel/reboot.c | 12 ++---------- arch/x86/realmode/init.c | 26 ++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index 5db5d083c8732..331474b150f16 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -89,6 +89,7 @@ static inline void set_real_mode_mem(phys_addr_t mem) } void reserve_real_mode(void); +void load_trampoline_pgtable(void); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 0a40df66a40de..fa700b46588e0 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -113,17 +113,9 @@ void __noreturn machine_real_restart(unsigned int type) spin_unlock(&rtc_lock); /* - * Switch back to the initial page table. + * Switch to the trampoline page table. */ -#ifdef CONFIG_X86_32 - load_cr3(initial_page_table); -#else - write_cr3(real_mode_header->trampoline_pgd); - - /* Exiting long mode will fail if CR4.PCIDE is set. */ - if (boot_cpu_has(X86_FEATURE_PCID)) - cr4_clear_bits(X86_CR4_PCIDE); -#endif + load_trampoline_pgtable(); /* Jump to the identity-mapped low memory code */ #ifdef CONFIG_X86_32 diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 4a3da7592b99c..6d98609387ba4 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -17,6 +17,32 @@ u32 *trampoline_cr4_features; /* Hold the pgd entry used on booting additional CPUs */ pgd_t trampoline_pgd_entry; +void load_trampoline_pgtable(void) +{ +#ifdef CONFIG_X86_32 + load_cr3(initial_page_table); +#else + /* + * This function is called before exiting to real-mode and that will + * fail with CR4.PCIDE still set. + */ + if (boot_cpu_has(X86_FEATURE_PCID)) + cr4_clear_bits(X86_CR4_PCIDE); + + write_cr3(real_mode_header->trampoline_pgd); +#endif + + /* + * The CR3 write above will not flush global TLB entries. + * Stale, global entries from previous page tables may still be + * present. Flush those stale entries. + * + * This ensures that memory accessed while running with + * trampoline_pgd is *actually* mapped into trampoline_pgd. + */ + __flush_tlb_all(); +} + void __init reserve_real_mode(void) { phys_addr_t mem; -- GitLab From b087dfab4d3902681550fd1f5ff9c3e942059478 Mon Sep 17 00:00:00 2001 From: Patrick Steuer Date: Thu, 4 Nov 2021 15:58:51 +0100 Subject: [PATCH 314/965] s390/crypto: add SIMD implementation for ChaCha20 Add an implementation of the ChaCha20 stream cipher (see e.g. RFC 7539) that makes use of z13's vector instruction set extension. The original implementation is by Andy Polyakov which is adapted for kernel use. Four to six blocks are processed in parallel resulting in a performance gain for inputs >= 256 bytes. chacha20-generic 1 operation in 622 cycles (256 bytes) 1 operation in 2346 cycles (1024 bytes) chacha20-s390 1 operation in 218 cycles (256 bytes) 1 operation in 647 cycles (1024 bytes) Cc: Andy Polyakov Reviewed-by: Harald Freudenberger Signed-off-by: Patrick Steuer Signed-off-by: Heiko Carstens --- arch/s390/configs/debug_defconfig | 1 + arch/s390/configs/defconfig | 1 + arch/s390/crypto/Makefile | 2 + arch/s390/crypto/chacha-glue.c | 100 ++++ arch/s390/crypto/chacha-s390.S | 907 ++++++++++++++++++++++++++++++ arch/s390/crypto/chacha-s390.h | 14 + arch/s390/include/asm/vx-insn.h | 117 ++++ drivers/crypto/Kconfig | 12 + 8 files changed, 1154 insertions(+) create mode 100644 arch/s390/crypto/chacha-glue.c create mode 100644 arch/s390/crypto/chacha-s390.S create mode 100644 arch/s390/crypto/chacha-s390.h diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig index b626bc6e0eaf9..416257b7aad6c 100644 --- a/arch/s390/configs/debug_defconfig +++ b/arch/s390/configs/debug_defconfig @@ -768,6 +768,7 @@ CONFIG_CRYPTO_SHA3_256_S390=m CONFIG_CRYPTO_SHA3_512_S390=m CONFIG_CRYPTO_DES_S390=m CONFIG_CRYPTO_AES_S390=m +CONFIG_CRYPTO_CHACHA_S390=m CONFIG_CRYPTO_GHASH_S390=m CONFIG_CRYPTO_CRC32_S390=y CONFIG_CRYPTO_DEV_VIRTIO=m diff --git a/arch/s390/configs/defconfig b/arch/s390/configs/defconfig index 0056cab273723..03ab6081b15da 100644 --- a/arch/s390/configs/defconfig +++ b/arch/s390/configs/defconfig @@ -755,6 +755,7 @@ CONFIG_CRYPTO_SHA3_256_S390=m CONFIG_CRYPTO_SHA3_512_S390=m CONFIG_CRYPTO_DES_S390=m CONFIG_CRYPTO_AES_S390=m +CONFIG_CRYPTO_CHACHA_S390=m CONFIG_CRYPTO_GHASH_S390=m CONFIG_CRYPTO_CRC32_S390=y CONFIG_CRYPTO_DEV_VIRTIO=m diff --git a/arch/s390/crypto/Makefile b/arch/s390/crypto/Makefile index 12889d4652cca..c63abfeb6d170 100644 --- a/arch/s390/crypto/Makefile +++ b/arch/s390/crypto/Makefile @@ -11,9 +11,11 @@ obj-$(CONFIG_CRYPTO_SHA3_512_S390) += sha3_512_s390.o sha_common.o obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o obj-$(CONFIG_CRYPTO_AES_S390) += aes_s390.o obj-$(CONFIG_CRYPTO_PAES_S390) += paes_s390.o +obj-$(CONFIG_CRYPTO_CHACHA_S390) += chacha_s390.o obj-$(CONFIG_S390_PRNG) += prng.o obj-$(CONFIG_CRYPTO_GHASH_S390) += ghash_s390.o obj-$(CONFIG_CRYPTO_CRC32_S390) += crc32-vx_s390.o obj-$(CONFIG_ARCH_RANDOM) += arch_random.o crc32-vx_s390-y := crc32-vx.o crc32le-vx.o crc32be-vx.o +chacha_s390-y := chacha-glue.o chacha-s390.o diff --git a/arch/s390/crypto/chacha-glue.c b/arch/s390/crypto/chacha-glue.c new file mode 100644 index 0000000000000..ccfff73e2c936 --- /dev/null +++ b/arch/s390/crypto/chacha-glue.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * s390 ChaCha stream cipher. + * + * Copyright IBM Corp. 2021 + */ + +#define KMSG_COMPONENT "chacha_s390" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include "chacha-s390.h" + +static void chacha20_crypt_s390(u32 *state, u8 *dst, const u8 *src, + unsigned int nbytes, const u32 *key, + u32 *counter) +{ + struct kernel_fpu vxstate; + + kernel_fpu_begin(&vxstate, KERNEL_VXR); + chacha20_vx(dst, src, nbytes, key, counter); + kernel_fpu_end(&vxstate, KERNEL_VXR); + + *counter += round_up(nbytes, CHACHA_BLOCK_SIZE) / CHACHA_BLOCK_SIZE; +} + +static int chacha20_s390(struct skcipher_request *req) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm); + u32 state[CHACHA_STATE_WORDS] __aligned(16); + struct skcipher_walk walk; + unsigned int nbytes; + int rc; + + rc = skcipher_walk_virt(&walk, req, false); + chacha_init_generic(state, ctx->key, req->iv); + + while (walk.nbytes > 0) { + nbytes = walk.nbytes; + if (nbytes < walk.total) + nbytes = round_down(nbytes, walk.stride); + + if (nbytes <= CHACHA_BLOCK_SIZE) { + chacha_crypt_generic(state, walk.dst.virt.addr, + walk.src.virt.addr, nbytes, + ctx->nrounds); + } else { + chacha20_crypt_s390(state, walk.dst.virt.addr, + walk.src.virt.addr, nbytes, + &state[4], &state[12]); + } + rc = skcipher_walk_done(&walk, walk.nbytes - nbytes); + } + return rc; +} + +static struct skcipher_alg chacha_algs[] = { + { + .base.cra_name = "chacha20", + .base.cra_driver_name = "chacha20-s390", + .base.cra_priority = 900, + .base.cra_blocksize = 1, + .base.cra_ctxsize = sizeof(struct chacha_ctx), + .base.cra_module = THIS_MODULE, + + .min_keysize = CHACHA_KEY_SIZE, + .max_keysize = CHACHA_KEY_SIZE, + .ivsize = CHACHA_IV_SIZE, + .chunksize = CHACHA_BLOCK_SIZE, + .setkey = chacha20_setkey, + .encrypt = chacha20_s390, + .decrypt = chacha20_s390, + } +}; + +static int __init chacha_mod_init(void) +{ + return crypto_register_skciphers(chacha_algs, ARRAY_SIZE(chacha_algs)); +} + +static void __exit chacha_mod_fini(void) +{ + crypto_unregister_skciphers(chacha_algs, ARRAY_SIZE(chacha_algs)); +} + +module_cpu_feature_match(VXRS, chacha_mod_init); +module_exit(chacha_mod_fini); + +MODULE_DESCRIPTION("ChaCha20 stream cipher"); +MODULE_LICENSE("GPL v2"); + +MODULE_ALIAS_CRYPTO("chacha20"); diff --git a/arch/s390/crypto/chacha-s390.S b/arch/s390/crypto/chacha-s390.S new file mode 100644 index 0000000000000..9b033622191ca --- /dev/null +++ b/arch/s390/crypto/chacha-s390.S @@ -0,0 +1,907 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Original implementation written by Andy Polyakov, @dot-asm. + * This is an adaptation of the original code for kernel use. + * + * Copyright (C) 2006-2019 CRYPTOGAMS by . All Rights Reserved. + */ + +#include +#include +#include + +#define SP %r15 +#define FRAME (16 * 8 + 4 * 8) + +.data +.align 32 + +.Lsigma: +.long 0x61707865,0x3320646e,0x79622d32,0x6b206574 # endian-neutral +.long 1,0,0,0 +.long 2,0,0,0 +.long 3,0,0,0 +.long 0x03020100,0x07060504,0x0b0a0908,0x0f0e0d0c # byte swap + +.long 0,1,2,3 +.long 0x61707865,0x61707865,0x61707865,0x61707865 # smashed sigma +.long 0x3320646e,0x3320646e,0x3320646e,0x3320646e +.long 0x79622d32,0x79622d32,0x79622d32,0x79622d32 +.long 0x6b206574,0x6b206574,0x6b206574,0x6b206574 + +.previous + + GEN_BR_THUNK %r14 + +.text + +############################################################################# +# void chacha20_vx_4x(u8 *out, counst u8 *inp, size_t len, +# counst u32 *key, const u32 *counter) + +#define OUT %r2 +#define INP %r3 +#define LEN %r4 +#define KEY %r5 +#define COUNTER %r6 + +#define BEPERM %v31 +#define CTR %v26 + +#define K0 %v16 +#define K1 %v17 +#define K2 %v18 +#define K3 %v19 + +#define XA0 %v0 +#define XA1 %v1 +#define XA2 %v2 +#define XA3 %v3 + +#define XB0 %v4 +#define XB1 %v5 +#define XB2 %v6 +#define XB3 %v7 + +#define XC0 %v8 +#define XC1 %v9 +#define XC2 %v10 +#define XC3 %v11 + +#define XD0 %v12 +#define XD1 %v13 +#define XD2 %v14 +#define XD3 %v15 + +#define XT0 %v27 +#define XT1 %v28 +#define XT2 %v29 +#define XT3 %v30 + +ENTRY(chacha20_vx_4x) + stmg %r6,%r7,6*8(SP) + + larl %r7,.Lsigma + lhi %r0,10 + lhi %r1,0 + + VL K0,0,,%r7 # load sigma + VL K1,0,,KEY # load key + VL K2,16,,KEY + VL K3,0,,COUNTER # load counter + + VL BEPERM,0x40,,%r7 + VL CTR,0x50,,%r7 + + VLM XA0,XA3,0x60,%r7,4 # load [smashed] sigma + + VREPF XB0,K1,0 # smash the key + VREPF XB1,K1,1 + VREPF XB2,K1,2 + VREPF XB3,K1,3 + + VREPF XD0,K3,0 + VREPF XD1,K3,1 + VREPF XD2,K3,2 + VREPF XD3,K3,3 + VAF XD0,XD0,CTR + + VREPF XC0,K2,0 + VREPF XC1,K2,1 + VREPF XC2,K2,2 + VREPF XC3,K2,3 + +.Loop_4x: + VAF XA0,XA0,XB0 + VX XD0,XD0,XA0 + VERLLF XD0,XD0,16 + + VAF XA1,XA1,XB1 + VX XD1,XD1,XA1 + VERLLF XD1,XD1,16 + + VAF XA2,XA2,XB2 + VX XD2,XD2,XA2 + VERLLF XD2,XD2,16 + + VAF XA3,XA3,XB3 + VX XD3,XD3,XA3 + VERLLF XD3,XD3,16 + + VAF XC0,XC0,XD0 + VX XB0,XB0,XC0 + VERLLF XB0,XB0,12 + + VAF XC1,XC1,XD1 + VX XB1,XB1,XC1 + VERLLF XB1,XB1,12 + + VAF XC2,XC2,XD2 + VX XB2,XB2,XC2 + VERLLF XB2,XB2,12 + + VAF XC3,XC3,XD3 + VX XB3,XB3,XC3 + VERLLF XB3,XB3,12 + + VAF XA0,XA0,XB0 + VX XD0,XD0,XA0 + VERLLF XD0,XD0,8 + + VAF XA1,XA1,XB1 + VX XD1,XD1,XA1 + VERLLF XD1,XD1,8 + + VAF XA2,XA2,XB2 + VX XD2,XD2,XA2 + VERLLF XD2,XD2,8 + + VAF XA3,XA3,XB3 + VX XD3,XD3,XA3 + VERLLF XD3,XD3,8 + + VAF XC0,XC0,XD0 + VX XB0,XB0,XC0 + VERLLF XB0,XB0,7 + + VAF XC1,XC1,XD1 + VX XB1,XB1,XC1 + VERLLF XB1,XB1,7 + + VAF XC2,XC2,XD2 + VX XB2,XB2,XC2 + VERLLF XB2,XB2,7 + + VAF XC3,XC3,XD3 + VX XB3,XB3,XC3 + VERLLF XB3,XB3,7 + + VAF XA0,XA0,XB1 + VX XD3,XD3,XA0 + VERLLF XD3,XD3,16 + + VAF XA1,XA1,XB2 + VX XD0,XD0,XA1 + VERLLF XD0,XD0,16 + + VAF XA2,XA2,XB3 + VX XD1,XD1,XA2 + VERLLF XD1,XD1,16 + + VAF XA3,XA3,XB0 + VX XD2,XD2,XA3 + VERLLF XD2,XD2,16 + + VAF XC2,XC2,XD3 + VX XB1,XB1,XC2 + VERLLF XB1,XB1,12 + + VAF XC3,XC3,XD0 + VX XB2,XB2,XC3 + VERLLF XB2,XB2,12 + + VAF XC0,XC0,XD1 + VX XB3,XB3,XC0 + VERLLF XB3,XB3,12 + + VAF XC1,XC1,XD2 + VX XB0,XB0,XC1 + VERLLF XB0,XB0,12 + + VAF XA0,XA0,XB1 + VX XD3,XD3,XA0 + VERLLF XD3,XD3,8 + + VAF XA1,XA1,XB2 + VX XD0,XD0,XA1 + VERLLF XD0,XD0,8 + + VAF XA2,XA2,XB3 + VX XD1,XD1,XA2 + VERLLF XD1,XD1,8 + + VAF XA3,XA3,XB0 + VX XD2,XD2,XA3 + VERLLF XD2,XD2,8 + + VAF XC2,XC2,XD3 + VX XB1,XB1,XC2 + VERLLF XB1,XB1,7 + + VAF XC3,XC3,XD0 + VX XB2,XB2,XC3 + VERLLF XB2,XB2,7 + + VAF XC0,XC0,XD1 + VX XB3,XB3,XC0 + VERLLF XB3,XB3,7 + + VAF XC1,XC1,XD2 + VX XB0,XB0,XC1 + VERLLF XB0,XB0,7 + brct %r0,.Loop_4x + + VAF XD0,XD0,CTR + + VMRHF XT0,XA0,XA1 # transpose data + VMRHF XT1,XA2,XA3 + VMRLF XT2,XA0,XA1 + VMRLF XT3,XA2,XA3 + VPDI XA0,XT0,XT1,0b0000 + VPDI XA1,XT0,XT1,0b0101 + VPDI XA2,XT2,XT3,0b0000 + VPDI XA3,XT2,XT3,0b0101 + + VMRHF XT0,XB0,XB1 + VMRHF XT1,XB2,XB3 + VMRLF XT2,XB0,XB1 + VMRLF XT3,XB2,XB3 + VPDI XB0,XT0,XT1,0b0000 + VPDI XB1,XT0,XT1,0b0101 + VPDI XB2,XT2,XT3,0b0000 + VPDI XB3,XT2,XT3,0b0101 + + VMRHF XT0,XC0,XC1 + VMRHF XT1,XC2,XC3 + VMRLF XT2,XC0,XC1 + VMRLF XT3,XC2,XC3 + VPDI XC0,XT0,XT1,0b0000 + VPDI XC1,XT0,XT1,0b0101 + VPDI XC2,XT2,XT3,0b0000 + VPDI XC3,XT2,XT3,0b0101 + + VMRHF XT0,XD0,XD1 + VMRHF XT1,XD2,XD3 + VMRLF XT2,XD0,XD1 + VMRLF XT3,XD2,XD3 + VPDI XD0,XT0,XT1,0b0000 + VPDI XD1,XT0,XT1,0b0101 + VPDI XD2,XT2,XT3,0b0000 + VPDI XD3,XT2,XT3,0b0101 + + VAF XA0,XA0,K0 + VAF XB0,XB0,K1 + VAF XC0,XC0,K2 + VAF XD0,XD0,K3 + + VPERM XA0,XA0,XA0,BEPERM + VPERM XB0,XB0,XB0,BEPERM + VPERM XC0,XC0,XC0,BEPERM + VPERM XD0,XD0,XD0,BEPERM + + VLM XT0,XT3,0,INP,0 + + VX XT0,XT0,XA0 + VX XT1,XT1,XB0 + VX XT2,XT2,XC0 + VX XT3,XT3,XD0 + + VSTM XT0,XT3,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + + VAF XA0,XA1,K0 + VAF XB0,XB1,K1 + VAF XC0,XC1,K2 + VAF XD0,XD1,K3 + + VPERM XA0,XA0,XA0,BEPERM + VPERM XB0,XB0,XB0,BEPERM + VPERM XC0,XC0,XC0,BEPERM + VPERM XD0,XD0,XD0,BEPERM + + clgfi LEN,0x40 + jl .Ltail_4x + + VLM XT0,XT3,0,INP,0 + + VX XT0,XT0,XA0 + VX XT1,XT1,XB0 + VX XT2,XT2,XC0 + VX XT3,XT3,XD0 + + VSTM XT0,XT3,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_4x + + VAF XA0,XA2,K0 + VAF XB0,XB2,K1 + VAF XC0,XC2,K2 + VAF XD0,XD2,K3 + + VPERM XA0,XA0,XA0,BEPERM + VPERM XB0,XB0,XB0,BEPERM + VPERM XC0,XC0,XC0,BEPERM + VPERM XD0,XD0,XD0,BEPERM + + clgfi LEN,0x40 + jl .Ltail_4x + + VLM XT0,XT3,0,INP,0 + + VX XT0,XT0,XA0 + VX XT1,XT1,XB0 + VX XT2,XT2,XC0 + VX XT3,XT3,XD0 + + VSTM XT0,XT3,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_4x + + VAF XA0,XA3,K0 + VAF XB0,XB3,K1 + VAF XC0,XC3,K2 + VAF XD0,XD3,K3 + + VPERM XA0,XA0,XA0,BEPERM + VPERM XB0,XB0,XB0,BEPERM + VPERM XC0,XC0,XC0,BEPERM + VPERM XD0,XD0,XD0,BEPERM + + clgfi LEN,0x40 + jl .Ltail_4x + + VLM XT0,XT3,0,INP,0 + + VX XT0,XT0,XA0 + VX XT1,XT1,XB0 + VX XT2,XT2,XC0 + VX XT3,XT3,XD0 + + VSTM XT0,XT3,0,OUT,0 + +.Ldone_4x: + lmg %r6,%r7,6*8(SP) + BR_EX %r14 + +.Ltail_4x: + VLR XT0,XC0 + VLR XT1,XD0 + + VST XA0,8*8+0x00,,SP + VST XB0,8*8+0x10,,SP + VST XT0,8*8+0x20,,SP + VST XT1,8*8+0x30,,SP + + lghi %r1,0 + +.Loop_tail_4x: + llgc %r5,0(%r1,INP) + llgc %r6,8*8(%r1,SP) + xr %r6,%r5 + stc %r6,0(%r1,OUT) + la %r1,1(%r1) + brct LEN,.Loop_tail_4x + + lmg %r6,%r7,6*8(SP) + BR_EX %r14 +ENDPROC(chacha20_vx_4x) + +#undef OUT +#undef INP +#undef LEN +#undef KEY +#undef COUNTER + +#undef BEPERM + +#undef K0 +#undef K1 +#undef K2 +#undef K3 + + +############################################################################# +# void chacha20_vx(u8 *out, counst u8 *inp, size_t len, +# counst u32 *key, const u32 *counter) + +#define OUT %r2 +#define INP %r3 +#define LEN %r4 +#define KEY %r5 +#define COUNTER %r6 + +#define BEPERM %v31 + +#define K0 %v27 +#define K1 %v24 +#define K2 %v25 +#define K3 %v26 + +#define A0 %v0 +#define B0 %v1 +#define C0 %v2 +#define D0 %v3 + +#define A1 %v4 +#define B1 %v5 +#define C1 %v6 +#define D1 %v7 + +#define A2 %v8 +#define B2 %v9 +#define C2 %v10 +#define D2 %v11 + +#define A3 %v12 +#define B3 %v13 +#define C3 %v14 +#define D3 %v15 + +#define A4 %v16 +#define B4 %v17 +#define C4 %v18 +#define D4 %v19 + +#define A5 %v20 +#define B5 %v21 +#define C5 %v22 +#define D5 %v23 + +#define T0 %v27 +#define T1 %v28 +#define T2 %v29 +#define T3 %v30 + +ENTRY(chacha20_vx) + clgfi LEN,256 + jle chacha20_vx_4x + stmg %r6,%r7,6*8(SP) + + lghi %r1,-FRAME + lgr %r0,SP + la SP,0(%r1,SP) + stg %r0,0(SP) # back-chain + + larl %r7,.Lsigma + lhi %r0,10 + + VLM K1,K2,0,KEY,0 # load key + VL K3,0,,COUNTER # load counter + + VLM K0,BEPERM,0,%r7,4 # load sigma, increments, ... + +.Loop_outer_vx: + VLR A0,K0 + VLR B0,K1 + VLR A1,K0 + VLR B1,K1 + VLR A2,K0 + VLR B2,K1 + VLR A3,K0 + VLR B3,K1 + VLR A4,K0 + VLR B4,K1 + VLR A5,K0 + VLR B5,K1 + + VLR D0,K3 + VAF D1,K3,T1 # K[3]+1 + VAF D2,K3,T2 # K[3]+2 + VAF D3,K3,T3 # K[3]+3 + VAF D4,D2,T2 # K[3]+4 + VAF D5,D2,T3 # K[3]+5 + + VLR C0,K2 + VLR C1,K2 + VLR C2,K2 + VLR C3,K2 + VLR C4,K2 + VLR C5,K2 + + VLR T1,D1 + VLR T2,D2 + VLR T3,D3 + +.Loop_vx: + VAF A0,A0,B0 + VAF A1,A1,B1 + VAF A2,A2,B2 + VAF A3,A3,B3 + VAF A4,A4,B4 + VAF A5,A5,B5 + VX D0,D0,A0 + VX D1,D1,A1 + VX D2,D2,A2 + VX D3,D3,A3 + VX D4,D4,A4 + VX D5,D5,A5 + VERLLF D0,D0,16 + VERLLF D1,D1,16 + VERLLF D2,D2,16 + VERLLF D3,D3,16 + VERLLF D4,D4,16 + VERLLF D5,D5,16 + + VAF C0,C0,D0 + VAF C1,C1,D1 + VAF C2,C2,D2 + VAF C3,C3,D3 + VAF C4,C4,D4 + VAF C5,C5,D5 + VX B0,B0,C0 + VX B1,B1,C1 + VX B2,B2,C2 + VX B3,B3,C3 + VX B4,B4,C4 + VX B5,B5,C5 + VERLLF B0,B0,12 + VERLLF B1,B1,12 + VERLLF B2,B2,12 + VERLLF B3,B3,12 + VERLLF B4,B4,12 + VERLLF B5,B5,12 + + VAF A0,A0,B0 + VAF A1,A1,B1 + VAF A2,A2,B2 + VAF A3,A3,B3 + VAF A4,A4,B4 + VAF A5,A5,B5 + VX D0,D0,A0 + VX D1,D1,A1 + VX D2,D2,A2 + VX D3,D3,A3 + VX D4,D4,A4 + VX D5,D5,A5 + VERLLF D0,D0,8 + VERLLF D1,D1,8 + VERLLF D2,D2,8 + VERLLF D3,D3,8 + VERLLF D4,D4,8 + VERLLF D5,D5,8 + + VAF C0,C0,D0 + VAF C1,C1,D1 + VAF C2,C2,D2 + VAF C3,C3,D3 + VAF C4,C4,D4 + VAF C5,C5,D5 + VX B0,B0,C0 + VX B1,B1,C1 + VX B2,B2,C2 + VX B3,B3,C3 + VX B4,B4,C4 + VX B5,B5,C5 + VERLLF B0,B0,7 + VERLLF B1,B1,7 + VERLLF B2,B2,7 + VERLLF B3,B3,7 + VERLLF B4,B4,7 + VERLLF B5,B5,7 + + VSLDB C0,C0,C0,8 + VSLDB C1,C1,C1,8 + VSLDB C2,C2,C2,8 + VSLDB C3,C3,C3,8 + VSLDB C4,C4,C4,8 + VSLDB C5,C5,C5,8 + VSLDB B0,B0,B0,4 + VSLDB B1,B1,B1,4 + VSLDB B2,B2,B2,4 + VSLDB B3,B3,B3,4 + VSLDB B4,B4,B4,4 + VSLDB B5,B5,B5,4 + VSLDB D0,D0,D0,12 + VSLDB D1,D1,D1,12 + VSLDB D2,D2,D2,12 + VSLDB D3,D3,D3,12 + VSLDB D4,D4,D4,12 + VSLDB D5,D5,D5,12 + + VAF A0,A0,B0 + VAF A1,A1,B1 + VAF A2,A2,B2 + VAF A3,A3,B3 + VAF A4,A4,B4 + VAF A5,A5,B5 + VX D0,D0,A0 + VX D1,D1,A1 + VX D2,D2,A2 + VX D3,D3,A3 + VX D4,D4,A4 + VX D5,D5,A5 + VERLLF D0,D0,16 + VERLLF D1,D1,16 + VERLLF D2,D2,16 + VERLLF D3,D3,16 + VERLLF D4,D4,16 + VERLLF D5,D5,16 + + VAF C0,C0,D0 + VAF C1,C1,D1 + VAF C2,C2,D2 + VAF C3,C3,D3 + VAF C4,C4,D4 + VAF C5,C5,D5 + VX B0,B0,C0 + VX B1,B1,C1 + VX B2,B2,C2 + VX B3,B3,C3 + VX B4,B4,C4 + VX B5,B5,C5 + VERLLF B0,B0,12 + VERLLF B1,B1,12 + VERLLF B2,B2,12 + VERLLF B3,B3,12 + VERLLF B4,B4,12 + VERLLF B5,B5,12 + + VAF A0,A0,B0 + VAF A1,A1,B1 + VAF A2,A2,B2 + VAF A3,A3,B3 + VAF A4,A4,B4 + VAF A5,A5,B5 + VX D0,D0,A0 + VX D1,D1,A1 + VX D2,D2,A2 + VX D3,D3,A3 + VX D4,D4,A4 + VX D5,D5,A5 + VERLLF D0,D0,8 + VERLLF D1,D1,8 + VERLLF D2,D2,8 + VERLLF D3,D3,8 + VERLLF D4,D4,8 + VERLLF D5,D5,8 + + VAF C0,C0,D0 + VAF C1,C1,D1 + VAF C2,C2,D2 + VAF C3,C3,D3 + VAF C4,C4,D4 + VAF C5,C5,D5 + VX B0,B0,C0 + VX B1,B1,C1 + VX B2,B2,C2 + VX B3,B3,C3 + VX B4,B4,C4 + VX B5,B5,C5 + VERLLF B0,B0,7 + VERLLF B1,B1,7 + VERLLF B2,B2,7 + VERLLF B3,B3,7 + VERLLF B4,B4,7 + VERLLF B5,B5,7 + + VSLDB C0,C0,C0,8 + VSLDB C1,C1,C1,8 + VSLDB C2,C2,C2,8 + VSLDB C3,C3,C3,8 + VSLDB C4,C4,C4,8 + VSLDB C5,C5,C5,8 + VSLDB B0,B0,B0,12 + VSLDB B1,B1,B1,12 + VSLDB B2,B2,B2,12 + VSLDB B3,B3,B3,12 + VSLDB B4,B4,B4,12 + VSLDB B5,B5,B5,12 + VSLDB D0,D0,D0,4 + VSLDB D1,D1,D1,4 + VSLDB D2,D2,D2,4 + VSLDB D3,D3,D3,4 + VSLDB D4,D4,D4,4 + VSLDB D5,D5,D5,4 + brct %r0,.Loop_vx + + VAF A0,A0,K0 + VAF B0,B0,K1 + VAF C0,C0,K2 + VAF D0,D0,K3 + VAF A1,A1,K0 + VAF D1,D1,T1 # +K[3]+1 + + VPERM A0,A0,A0,BEPERM + VPERM B0,B0,B0,BEPERM + VPERM C0,C0,C0,BEPERM + VPERM D0,D0,D0,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VAF D2,D2,T2 # +K[3]+2 + VAF D3,D3,T3 # +K[3]+3 + VLM T0,T3,0,INP,0 + + VX A0,A0,T0 + VX B0,B0,T1 + VX C0,C0,T2 + VX D0,D0,T3 + + VLM K0,T3,0,%r7,4 # re-load sigma and increments + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_vx + + VAF B1,B1,K1 + VAF C1,C1,K2 + + VPERM A0,A1,A1,BEPERM + VPERM B0,B1,B1,BEPERM + VPERM C0,C1,C1,BEPERM + VPERM D0,D1,D1,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VLM A1,D1,0,INP,0 + + VX A0,A0,A1 + VX B0,B0,B1 + VX C0,C0,C1 + VX D0,D0,D1 + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_vx + + VAF A2,A2,K0 + VAF B2,B2,K1 + VAF C2,C2,K2 + + VPERM A0,A2,A2,BEPERM + VPERM B0,B2,B2,BEPERM + VPERM C0,C2,C2,BEPERM + VPERM D0,D2,D2,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VLM A1,D1,0,INP,0 + + VX A0,A0,A1 + VX B0,B0,B1 + VX C0,C0,C1 + VX D0,D0,D1 + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_vx + + VAF A3,A3,K0 + VAF B3,B3,K1 + VAF C3,C3,K2 + VAF D2,K3,T3 # K[3]+3 + + VPERM A0,A3,A3,BEPERM + VPERM B0,B3,B3,BEPERM + VPERM C0,C3,C3,BEPERM + VPERM D0,D3,D3,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VAF D3,D2,T1 # K[3]+4 + VLM A1,D1,0,INP,0 + + VX A0,A0,A1 + VX B0,B0,B1 + VX C0,C0,C1 + VX D0,D0,D1 + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_vx + + VAF A4,A4,K0 + VAF B4,B4,K1 + VAF C4,C4,K2 + VAF D4,D4,D3 # +K[3]+4 + VAF D3,D3,T1 # K[3]+5 + VAF K3,D2,T3 # K[3]+=6 + + VPERM A0,A4,A4,BEPERM + VPERM B0,B4,B4,BEPERM + VPERM C0,C4,C4,BEPERM + VPERM D0,D4,D4,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VLM A1,D1,0,INP,0 + + VX A0,A0,A1 + VX B0,B0,B1 + VX C0,C0,C1 + VX D0,D0,D1 + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + aghi LEN,-0x40 + je .Ldone_vx + + VAF A5,A5,K0 + VAF B5,B5,K1 + VAF C5,C5,K2 + VAF D5,D5,D3 # +K[3]+5 + + VPERM A0,A5,A5,BEPERM + VPERM B0,B5,B5,BEPERM + VPERM C0,C5,C5,BEPERM + VPERM D0,D5,D5,BEPERM + + clgfi LEN,0x40 + jl .Ltail_vx + + VLM A1,D1,0,INP,0 + + VX A0,A0,A1 + VX B0,B0,B1 + VX C0,C0,C1 + VX D0,D0,D1 + + VSTM A0,D0,0,OUT,0 + + la INP,0x40(INP) + la OUT,0x40(OUT) + lhi %r0,10 + aghi LEN,-0x40 + jne .Loop_outer_vx + +.Ldone_vx: + lmg %r6,%r7,FRAME+6*8(SP) + la SP,FRAME(SP) + BR_EX %r14 + +.Ltail_vx: + VSTM A0,D0,8*8,SP,3 + lghi %r1,0 + +.Loop_tail_vx: + llgc %r5,0(%r1,INP) + llgc %r6,8*8(%r1,SP) + xr %r6,%r5 + stc %r6,0(%r1,OUT) + la %r1,1(%r1) + brct LEN,.Loop_tail_vx + + lmg %r6,%r7,FRAME+6*8(SP) + la SP,FRAME(SP) + BR_EX %r14 +ENDPROC(chacha20_vx) + +.previous diff --git a/arch/s390/crypto/chacha-s390.h b/arch/s390/crypto/chacha-s390.h new file mode 100644 index 0000000000000..733744ce30f5b --- /dev/null +++ b/arch/s390/crypto/chacha-s390.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * s390 ChaCha stream cipher. + * + * Copyright IBM Corp. 2021 + */ + +#ifndef _CHACHA_S390_H +#define _CHACHA_S390_H + +void chacha20_vx(u8 *out, const u8 *inp, size_t len, const u32 *key, + const u32 *counter); + +#endif /* _CHACHA_S390_H */ diff --git a/arch/s390/include/asm/vx-insn.h b/arch/s390/include/asm/vx-insn.h index 0c05a673811ce..87e6cc2aeba4e 100644 --- a/arch/s390/include/asm/vx-insn.h +++ b/arch/s390/include/asm/vx-insn.h @@ -372,6 +372,16 @@ MRXBOPC \hint, 0x36, v1, v3 .endm +/* VECTOR STORE */ +.macro VST vr1, disp, index="%r0", base + VX_NUM v1, \vr1 + GR_NUM x2, \index + GR_NUM b2, \base /* Base register */ + .word 0xE700 | ((v1&15) << 4) | (x2&15) + .word (b2 << 12) | (\disp) + MRXBOPC 0, 0x0E, v1 +.endm + /* VECTOR STORE MULTIPLE */ .macro VSTM vfrom, vto, disp, base, hint=3 VX_NUM v1, \vfrom @@ -411,6 +421,81 @@ VUPLL \vr1, \vr2, 2 .endm +/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */ +.macro VPDI vr1, vr2, vr3, m4 + VX_NUM v1, \vr1 + VX_NUM v2, \vr2 + VX_NUM v3, \vr3 + .word 0xE700 | ((v1&15) << 4) | (v2&15) + .word ((v3&15) << 12) + MRXBOPC \m4, 0x84, v1, v2, v3 +.endm + +/* VECTOR REPLICATE */ +.macro VREP vr1, vr3, imm2, m4 + VX_NUM v1, \vr1 + VX_NUM v3, \vr3 + .word 0xE700 | ((v1&15) << 4) | (v3&15) + .word \imm2 + MRXBOPC \m4, 0x4D, v1, v3 +.endm +.macro VREPB vr1, vr3, imm2 + VREP \vr1, \vr3, \imm2, 0 +.endm +.macro VREPH vr1, vr3, imm2 + VREP \vr1, \vr3, \imm2, 1 +.endm +.macro VREPF vr1, vr3, imm2 + VREP \vr1, \vr3, \imm2, 2 +.endm +.macro VREPG vr1, vr3, imm2 + VREP \vr1, \vr3, \imm2, 3 +.endm + +/* VECTOR MERGE HIGH */ +.macro VMRH vr1, vr2, vr3, m4 + VX_NUM v1, \vr1 + VX_NUM v2, \vr2 + VX_NUM v3, \vr3 + .word 0xE700 | ((v1&15) << 4) | (v2&15) + .word ((v3&15) << 12) + MRXBOPC \m4, 0x61, v1, v2, v3 +.endm +.macro VMRHB vr1, vr2, vr3 + VMRH \vr1, \vr2, \vr3, 0 +.endm +.macro VMRHH vr1, vr2, vr3 + VMRH \vr1, \vr2, \vr3, 1 +.endm +.macro VMRHF vr1, vr2, vr3 + VMRH \vr1, \vr2, \vr3, 2 +.endm +.macro VMRHG vr1, vr2, vr3 + VMRH \vr1, \vr2, \vr3, 3 +.endm + +/* VECTOR MERGE LOW */ +.macro VMRL vr1, vr2, vr3, m4 + VX_NUM v1, \vr1 + VX_NUM v2, \vr2 + VX_NUM v3, \vr3 + .word 0xE700 | ((v1&15) << 4) | (v2&15) + .word ((v3&15) << 12) + MRXBOPC \m4, 0x60, v1, v2, v3 +.endm +.macro VMRLB vr1, vr2, vr3 + VMRL \vr1, \vr2, \vr3, 0 +.endm +.macro VMRLH vr1, vr2, vr3 + VMRL \vr1, \vr2, \vr3, 1 +.endm +.macro VMRLF vr1, vr2, vr3 + VMRL \vr1, \vr2, \vr3, 2 +.endm +.macro VMRLG vr1, vr2, vr3 + VMRL \vr1, \vr2, \vr3, 3 +.endm + /* Vector integer instructions */ @@ -557,5 +642,37 @@ VESRAV \vr1, \vr2, \vr3, 3 .endm +/* VECTOR ELEMENT ROTATE LEFT LOGICAL */ +.macro VERLL vr1, vr3, disp, base="%r0", m4 + VX_NUM v1, \vr1 + VX_NUM v3, \vr3 + GR_NUM b2, \base + .word 0xE700 | ((v1&15) << 4) | (v3&15) + .word (b2 << 12) | (\disp) + MRXBOPC \m4, 0x33, v1, v3 +.endm +.macro VERLLB vr1, vr3, disp, base="%r0" + VERLL \vr1, \vr3, \disp, \base, 0 +.endm +.macro VERLLH vr1, vr3, disp, base="%r0" + VERLL \vr1, \vr3, \disp, \base, 1 +.endm +.macro VERLLF vr1, vr3, disp, base="%r0" + VERLL \vr1, \vr3, \disp, \base, 2 +.endm +.macro VERLLG vr1, vr3, disp, base="%r0" + VERLL \vr1, \vr3, \disp, \base, 3 +.endm + +/* VECTOR SHIFT LEFT DOUBLE BY BYTE */ +.macro VSLDB vr1, vr2, vr3, imm4 + VX_NUM v1, \vr1 + VX_NUM v2, \vr2 + VX_NUM v3, \vr3 + .word 0xE700 | ((v1&15) << 4) | (v2&15) + .word ((v3&15) << 12) | (\imm4) + MRXBOPC 0, 0x77, v1, v2, v3 +.endm + #endif /* __ASSEMBLY__ */ #endif /* __ASM_S390_VX_INSN_H */ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 51690e73153ad..4f705674f94fa 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -213,6 +213,18 @@ config CRYPTO_AES_S390 key sizes and XTS mode is hardware accelerated for 256 and 512 bit keys. +config CRYPTO_CHACHA_S390 + tristate "ChaCha20 stream cipher" + depends on S390 + select CRYPTO_ALGAPI + select CRYPTO_SKCIPHER + select CRYPTO_CHACHA20 + help + This is the s390 SIMD implementation of the ChaCha20 stream + cipher (RFC 7539). + + It is available as of z13. + config S390_PRNG tristate "Pseudo random number generator device driver" depends on S390 -- GitLab From a84d1c5006b56166dac477e922643ede01cdbb92 Mon Sep 17 00:00:00 2001 From: Vineeth Vijayan Date: Tue, 29 Jun 2021 09:38:22 +0200 Subject: [PATCH 315/965] s390/cio: remove uevent suppress from cio driver commit fa1a8c23eb7d ("s390: cio: Delay uevents for subchannels") introduced suppression of uevents for a subchannel until after it is clear that the subchannel would not be unregistered again immediately. This was done to avoid uevents being generated for I/O subchannels with no valid device, which can happen on LPAR. However, this also has some drawbacks: All subchannel drivers need to manually remove the uevent suppression and generate an ADD uevent as soon as they are sure that the subchannel will stay around. This misses out on all uevents that are not the initial ADD uevent that would be generated while uevents are suppressed; for example, all subchannels were missing the BIND uevent. As uevents being generated even for I/O subchannels without an operational device turned out to be not as bad as missing uevents and complicating the code flow, let's remove uevent suppression for subchannels. Signed-off-by: Vineeth Vijayan [cohuck@redhat.com: modified changelog] Reviewed-by: Cornelia Huck Reviewed-by: Peter Oberparleiter Link: https://lore.kernel.org/r/20211122103756.352463-2-vneethv@linux.ibm.com Signed-off-by: Heiko Carstens --- drivers/s390/cio/chsc_sch.c | 5 ----- drivers/s390/cio/css.c | 19 ------------------- drivers/s390/cio/device.c | 20 +++----------------- drivers/s390/cio/eadm_sch.c | 5 ----- drivers/s390/cio/vfio_ccw_drv.c | 5 ----- 5 files changed, 3 insertions(+), 51 deletions(-) diff --git a/drivers/s390/cio/chsc_sch.c b/drivers/s390/cio/chsc_sch.c index 684348d82f085..962dfa25a3108 100644 --- a/drivers/s390/cio/chsc_sch.c +++ b/drivers/s390/cio/chsc_sch.c @@ -91,11 +91,6 @@ static int chsc_subchannel_probe(struct subchannel *sch) sch->schid.ssid, sch->schid.sch_no, ret); dev_set_drvdata(&sch->dev, NULL); kfree(private); - } else { - if (dev_get_uevent_suppress(&sch->dev)) { - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } } return ret; } diff --git a/drivers/s390/cio/css.c b/drivers/s390/cio/css.c index ce9e7517430f7..fa82933350770 100644 --- a/drivers/s390/cio/css.c +++ b/drivers/s390/cio/css.c @@ -470,16 +470,6 @@ int css_register_subchannel(struct subchannel *sch) if (sch->st == SUBCHANNEL_TYPE_IO) sch->dev.type = &io_subchannel_type; - /* - * We don't want to generate uevents for I/O subchannels that don't - * have a working ccw device behind them since they will be - * unregistered before they can be used anyway, so we delay the add - * uevent until after device recognition was successful. - * Note that we suppress the uevent for all subchannel types; - * the subchannel driver can decide itself when it wants to inform - * userspace of its existence. - */ - dev_set_uevent_suppress(&sch->dev, 1); css_update_ssd_info(sch); /* make it known to the system */ ret = css_sch_device_register(sch); @@ -488,15 +478,6 @@ int css_register_subchannel(struct subchannel *sch) sch->schid.ssid, sch->schid.sch_no, ret); return ret; } - if (!sch->driver) { - /* - * No driver matched. Generate the uevent now so that - * a fitting driver module may be loaded based on the - * modalias. - */ - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } return ret; } diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index 07a17613fab58..cd938a26b76c2 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c @@ -838,14 +838,6 @@ static void io_subchannel_register(struct ccw_device *cdev) adjust_init_count = 0; goto out; } - /* - * Now we know this subchannel will stay, we can throw - * our delayed uevent. - */ - if (dev_get_uevent_suppress(&sch->dev)) { - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } /* make it known to the system */ ret = device_add(&cdev->dev); if (ret) { @@ -1036,15 +1028,9 @@ static int io_subchannel_probe(struct subchannel *sch) "0.%x.%04x (rc=%d)\n", sch->schid.ssid, sch->schid.sch_no, rc); /* - * The console subchannel already has an associated ccw_device. - * Throw the delayed uevent for the subchannel, register - * the ccw_device and exit. - */ - if (dev_get_uevent_suppress(&sch->dev)) { - /* should always be the case for the console */ - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } + * The console subchannel already has an associated ccw_device. + * Register it and exit. + */ cdev = sch_get_cdev(sch); rc = device_add(&cdev->dev); if (rc) { diff --git a/drivers/s390/cio/eadm_sch.c b/drivers/s390/cio/eadm_sch.c index 15bdae5981ca7..8b463681a1490 100644 --- a/drivers/s390/cio/eadm_sch.c +++ b/drivers/s390/cio/eadm_sch.c @@ -243,11 +243,6 @@ static int eadm_subchannel_probe(struct subchannel *sch) spin_lock_irq(&list_lock); list_add(&private->head, &eadm_list); spin_unlock_irq(&list_lock); - - if (dev_get_uevent_suppress(&sch->dev)) { - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } out: return ret; } diff --git a/drivers/s390/cio/vfio_ccw_drv.c b/drivers/s390/cio/vfio_ccw_drv.c index 0407427770955..ee182cfb467d1 100644 --- a/drivers/s390/cio/vfio_ccw_drv.c +++ b/drivers/s390/cio/vfio_ccw_drv.c @@ -244,11 +244,6 @@ static int vfio_ccw_sch_probe(struct subchannel *sch) if (ret) goto out_disable; - if (dev_get_uevent_suppress(&sch->dev)) { - dev_set_uevent_suppress(&sch->dev, 0); - kobject_uevent(&sch->dev.kobj, KOBJ_ADD); - } - VFIO_CCW_MSG_EVENT(4, "bound to subchannel %x.%x.%04x\n", sch->schid.cssid, sch->schid.ssid, sch->schid.sch_no); -- GitLab From 764fc3187c3fae5e620a435b42c9cc0e813a903d Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 12 Nov 2021 09:15:15 +0100 Subject: [PATCH 316/965] s390/qdio: remove QDIO_SBAL_SIZE macro It's unused, and duplicates sizeof(struct qdio_buffer). Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- arch/s390/include/asm/qdio.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 4b9b14b20984e..c5a5b454f8dcb 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -18,7 +18,6 @@ #define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1) #define QDIO_BUFNR(num) ((num) & QDIO_MAX_BUFFERS_MASK) #define QDIO_MAX_ELEMENTS_PER_BUFFER 16 -#define QDIO_SBAL_SIZE 256 #define QDIO_QETH_QFMT 0 #define QDIO_ZFCP_QFMT 1 -- GitLab From bd3a025dd22c500d33960b0a1fcf92e27514332c Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Thu, 8 Jul 2021 08:49:28 +0200 Subject: [PATCH 317/965] s390/qdio: improve handling of CIWs Fetch the individual CIWs when we actually need them, rather than fetching both of them in qdio_setup_irq() and then needing to cache them inside the qdio_irq. Also deal with the error when a CIW is not available, instead of silently dropping this error condition in qdio_setup_irq()'s caller. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- drivers/s390/cio/qdio.h | 4 +--- drivers/s390/cio/qdio_main.c | 22 ++++++++++++++++++---- drivers/s390/cio/qdio_setup.c | 20 +------------------- 3 files changed, 20 insertions(+), 26 deletions(-) diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index 99c2212dc6a6b..5f43e2b0c8553 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -237,8 +237,6 @@ struct qdio_irq { int nr_output_qs; struct ccw1 ccw; - struct ciw equeue; - struct ciw aqueue; struct qdio_ssqd_desc ssqd_desc; void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); @@ -338,7 +336,7 @@ void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, struct subchannel_id *schid, struct qdio_ssqd_desc *data); -int qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data); +void qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data); void qdio_shutdown_irq(struct qdio_irq *irq); void qdio_print_subchannel_info(struct qdio_irq *irq_ptr); void qdio_free_queues(struct qdio_irq *irq_ptr); diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 45e810c6ea3ba..c42ce1933b2e0 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -972,6 +972,7 @@ int qdio_establish(struct ccw_device *cdev, { struct qdio_irq *irq_ptr = cdev->private->qdio_data; struct subchannel_id schid; + struct ciw *ciw; long timeout; int rc; @@ -996,6 +997,12 @@ int qdio_establish(struct ccw_device *cdev, if (!init_data->irq_poll) return -EINVAL; + ciw = ccw_device_get_ciw(cdev, CIW_TYPE_EQUEUE); + if (!ciw) { + DBF_ERROR("%4x NO EQ", schid.sch_no); + return -EIO; + } + mutex_lock(&irq_ptr->setup_mutex); qdio_trace_init_data(irq_ptr, init_data); qdio_setup_irq(irq_ptr, init_data); @@ -1005,9 +1012,9 @@ int qdio_establish(struct ccw_device *cdev, goto err_thinint; /* establish q */ - irq_ptr->ccw.cmd_code = irq_ptr->equeue.cmd; + irq_ptr->ccw.cmd_code = ciw->cmd; irq_ptr->ccw.flags = CCW_FLAG_SLI; - irq_ptr->ccw.count = irq_ptr->equeue.count; + irq_ptr->ccw.count = ciw->count; irq_ptr->ccw.cda = (u32) virt_to_phys(irq_ptr->qdr); spin_lock_irq(get_ccwdev_lock(cdev)); @@ -1065,6 +1072,7 @@ int qdio_activate(struct ccw_device *cdev) { struct qdio_irq *irq_ptr = cdev->private->qdio_data; struct subchannel_id schid; + struct ciw *ciw; int rc; ccw_device_get_schid(cdev, &schid); @@ -1073,15 +1081,21 @@ int qdio_activate(struct ccw_device *cdev) if (!irq_ptr) return -ENODEV; + ciw = ccw_device_get_ciw(cdev, CIW_TYPE_AQUEUE); + if (!ciw) { + DBF_ERROR("%4x NO AQ", schid.sch_no); + return -EIO; + } + mutex_lock(&irq_ptr->setup_mutex); if (irq_ptr->state == QDIO_IRQ_STATE_INACTIVE) { rc = -EBUSY; goto out; } - irq_ptr->ccw.cmd_code = irq_ptr->aqueue.cmd; + irq_ptr->ccw.cmd_code = ciw->cmd; irq_ptr->ccw.flags = CCW_FLAG_SLI; - irq_ptr->ccw.count = irq_ptr->aqueue.count; + irq_ptr->ccw.count = ciw->count; irq_ptr->ccw.cda = 0; spin_lock_irq(get_ccwdev_lock(cdev)); diff --git a/drivers/s390/cio/qdio_setup.c b/drivers/s390/cio/qdio_setup.c index efbb5e5eca05f..766f1e849fae8 100644 --- a/drivers/s390/cio/qdio_setup.c +++ b/drivers/s390/cio/qdio_setup.c @@ -351,10 +351,9 @@ static void setup_qib(struct qdio_irq *irq_ptr, sizeof(irq_ptr->qib.parm)); } -int qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data) +void qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data) { struct ccw_device *cdev = irq_ptr->cdev; - struct ciw *ciw; irq_ptr->qdioac1 = 0; memset(&irq_ptr->ccw, 0, sizeof(irq_ptr->ccw)); @@ -386,23 +385,6 @@ int qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data) irq_ptr->orig_handler = cdev->handler; cdev->handler = qdio_int_handler; spin_unlock_irq(get_ccwdev_lock(cdev)); - - /* get qdio commands */ - ciw = ccw_device_get_ciw(cdev, CIW_TYPE_EQUEUE); - if (!ciw) { - DBF_ERROR("%4x NO EQ", irq_ptr->schid.sch_no); - return -EINVAL; - } - irq_ptr->equeue = *ciw; - - ciw = ccw_device_get_ciw(cdev, CIW_TYPE_AQUEUE); - if (!ciw) { - DBF_ERROR("%4x NO AQ", irq_ptr->schid.sch_no); - return -EINVAL; - } - irq_ptr->aqueue = *ciw; - - return 0; } void qdio_shutdown_irq(struct qdio_irq *irq) -- GitLab From 718ce9e10171f70f2d00c3c89ceb7e406a892bb6 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Tue, 24 Aug 2021 09:37:06 +0300 Subject: [PATCH 318/965] s390/qdio: avoid allocating the qdio_irq with GFP_DMA The qdio_irq contains only two fields that are directly exposed to the HW (ccw and qib). And only the ccw needs to reside in 31-bit memory. So allocate it separately, and remove the GFP_DMA constraint from the qdio_irq allocation. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- drivers/s390/cio/qdio.h | 2 +- drivers/s390/cio/qdio_main.c | 34 ++++++++++++++++++++++------------ drivers/s390/cio/qdio_setup.c | 1 - 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index 5f43e2b0c8553..152c032e74d4f 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -236,7 +236,7 @@ struct qdio_irq { int nr_input_qs; int nr_output_qs; - struct ccw1 ccw; + struct ccw1 *ccw; struct qdio_ssqd_desc ssqd_desc; void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index c42ce1933b2e0..9b48573db93da 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -874,6 +875,7 @@ int qdio_free(struct ccw_device *cdev) qdio_free_queues(irq_ptr); free_page((unsigned long) irq_ptr->qdr); free_page(irq_ptr->chsc_page); + kfree(irq_ptr->ccw); free_page((unsigned long) irq_ptr); return 0; } @@ -899,11 +901,17 @@ int qdio_allocate(struct ccw_device *cdev, unsigned int no_input_qs, no_output_qs > QDIO_MAX_QUEUES_PER_IRQ) return -EINVAL; - /* irq_ptr must be in GFP_DMA since it contains ccw1.cda */ - irq_ptr = (void *) get_zeroed_page(GFP_KERNEL | GFP_DMA); + irq_ptr = (void *) get_zeroed_page(GFP_KERNEL); if (!irq_ptr) return -ENOMEM; + irq_ptr->ccw = kmalloc(sizeof(*irq_ptr->ccw), GFP_KERNEL | GFP_DMA); + if (!irq_ptr->ccw) + goto err_ccw; + + /* kmemleak doesn't scan the page-allocated irq_ptr: */ + kmemleak_not_leak(irq_ptr->ccw); + irq_ptr->cdev = cdev; mutex_init(&irq_ptr->setup_mutex); if (qdio_allocate_dbf(irq_ptr)) @@ -941,6 +949,8 @@ err_qdr: free_page(irq_ptr->chsc_page); err_chsc: err_dbf: + kfree(irq_ptr->ccw); +err_ccw: free_page((unsigned long) irq_ptr); return rc; } @@ -1012,15 +1022,15 @@ int qdio_establish(struct ccw_device *cdev, goto err_thinint; /* establish q */ - irq_ptr->ccw.cmd_code = ciw->cmd; - irq_ptr->ccw.flags = CCW_FLAG_SLI; - irq_ptr->ccw.count = ciw->count; - irq_ptr->ccw.cda = (u32) virt_to_phys(irq_ptr->qdr); + irq_ptr->ccw->cmd_code = ciw->cmd; + irq_ptr->ccw->flags = CCW_FLAG_SLI; + irq_ptr->ccw->count = ciw->count; + irq_ptr->ccw->cda = (u32) virt_to_phys(irq_ptr->qdr); spin_lock_irq(get_ccwdev_lock(cdev)); ccw_device_set_options_mask(cdev, 0); - rc = ccw_device_start(cdev, &irq_ptr->ccw, QDIO_DOING_ESTABLISH, 0, 0); + rc = ccw_device_start(cdev, irq_ptr->ccw, QDIO_DOING_ESTABLISH, 0, 0); spin_unlock_irq(get_ccwdev_lock(cdev)); if (rc) { DBF_ERROR("%4x est IO ERR", irq_ptr->schid.sch_no); @@ -1093,15 +1103,15 @@ int qdio_activate(struct ccw_device *cdev) goto out; } - irq_ptr->ccw.cmd_code = ciw->cmd; - irq_ptr->ccw.flags = CCW_FLAG_SLI; - irq_ptr->ccw.count = ciw->count; - irq_ptr->ccw.cda = 0; + irq_ptr->ccw->cmd_code = ciw->cmd; + irq_ptr->ccw->flags = CCW_FLAG_SLI; + irq_ptr->ccw->count = ciw->count; + irq_ptr->ccw->cda = 0; spin_lock_irq(get_ccwdev_lock(cdev)); ccw_device_set_options(cdev, CCWDEV_REPORT_ALL); - rc = ccw_device_start(cdev, &irq_ptr->ccw, QDIO_DOING_ACTIVATE, + rc = ccw_device_start(cdev, irq_ptr->ccw, QDIO_DOING_ACTIVATE, 0, DOIO_DENY_PREFETCH); spin_unlock_irq(get_ccwdev_lock(cdev)); if (rc) { diff --git a/drivers/s390/cio/qdio_setup.c b/drivers/s390/cio/qdio_setup.c index 766f1e849fae8..fd663922d7d59 100644 --- a/drivers/s390/cio/qdio_setup.c +++ b/drivers/s390/cio/qdio_setup.c @@ -356,7 +356,6 @@ void qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data) struct ccw_device *cdev = irq_ptr->cdev; irq_ptr->qdioac1 = 0; - memset(&irq_ptr->ccw, 0, sizeof(irq_ptr->ccw)); memset(&irq_ptr->ssqd_desc, 0, sizeof(irq_ptr->ssqd_desc)); memset(&irq_ptr->perf_stat, 0, sizeof(irq_ptr->perf_stat)); -- GitLab From 0a86cdcb4ce297f543d13d0bbd4f0c86f00626e5 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Mon, 15 Nov 2021 08:21:38 +0100 Subject: [PATCH 319/965] s390/qdio: clean up access to queue in qdio_handle_activate_check() qdio_handle_activate_check() re-uses a queue-specific handler to report that the ACTIVATE ccw has been terminated. It uses either the first input or output queue, so we can hard-code q->nr as 0. Also don't access the q->irq_ptr parent pointer, we already have a pointer to the qdio_irq. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- drivers/s390/cio/qdio_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 9b48573db93da..3e586e460f919 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -669,8 +669,8 @@ static void qdio_handle_activate_check(struct qdio_irq *irq_ptr, goto no_handler; } - q->handler(q->irq_ptr->cdev, QDIO_ERROR_ACTIVATE, - q->nr, q->first_to_check, 0, irq_ptr->int_parm); + q->handler(irq_ptr->cdev, QDIO_ERROR_ACTIVATE, 0, q->first_to_check, + 0, irq_ptr->int_parm); no_handler: qdio_set_state(irq_ptr, QDIO_IRQ_STATE_STOPPED); /* -- GitLab From 513251fe25d304d1ca628c581bd0cc0422de150a Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Mon, 15 Nov 2021 08:28:08 +0100 Subject: [PATCH 320/965] s390/qdio: clarify handler logic for qdio_handle_activate_check() qdio_handle_activate_check() tries to re-use one of the queue-specific handlers to report that the ACTIVATE ccw has been terminated. But the logic to select that handler is overly complex - in practice both qdio drivers have at least one Input Queue, so we never take the other paths. Make things more obvious by removing this unused code, and clearly spelling out that we re-use the Input Handler for generic error reporting. This also paves the way for a world without queue-specific error handlers. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- arch/s390/include/asm/qdio.h | 2 +- drivers/s390/cio/qdio.h | 1 + drivers/s390/cio/qdio_main.c | 25 +++++++++++-------------- drivers/s390/cio/qdio_setup.c | 1 + 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index c5a5b454f8dcb..97356ec27d377 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -312,7 +312,7 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, * @qib_rflags: rflags to set * @no_input_qs: number of input queues * @no_output_qs: number of output queues - * @input_handler: handler to be called for input queues + * @input_handler: handler to be called for input queues, and device-wide errors * @output_handler: handler to be called for output queues * @irq_poll: Data IRQ polling handler * @scan_threshold: # of in-use buffers that triggers scan on output queue diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index 152c032e74d4f..5ea6249d81803 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -240,6 +240,7 @@ struct qdio_irq { struct qdio_ssqd_desc ssqd_desc; void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); + qdio_handler_t (*error_handler); int perf_stat_enabled; diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 3e586e460f919..35a32240b4ce8 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -654,24 +654,18 @@ static void qdio_handle_activate_check(struct qdio_irq *irq_ptr, unsigned long intparm, int cstat, int dstat) { - struct qdio_q *q; + unsigned int first_to_check = 0; DBF_ERROR("%4x ACT CHECK", irq_ptr->schid.sch_no); DBF_ERROR("intp :%lx", intparm); DBF_ERROR("ds: %2x cs:%2x", dstat, cstat); - if (irq_ptr->nr_input_qs) { - q = irq_ptr->input_qs[0]; - } else if (irq_ptr->nr_output_qs) { - q = irq_ptr->output_qs[0]; - } else { - dump_stack(); - goto no_handler; - } + /* zfcp wants this: */ + if (irq_ptr->nr_input_qs) + first_to_check = irq_ptr->input_qs[0]->first_to_check; - q->handler(irq_ptr->cdev, QDIO_ERROR_ACTIVATE, 0, q->first_to_check, - 0, irq_ptr->int_parm); -no_handler: + irq_ptr->error_handler(irq_ptr->cdev, QDIO_ERROR_ACTIVATE, 0, + first_to_check, 0, irq_ptr->int_parm); qdio_set_state(irq_ptr, QDIO_IRQ_STATE_STOPPED); /* * In case of z/VM LGR (Live Guest Migration) QDIO recovery will happen. @@ -996,8 +990,11 @@ int qdio_establish(struct ccw_device *cdev, init_data->no_output_qs > irq_ptr->max_output_qs) return -EINVAL; - if ((init_data->no_input_qs && !init_data->input_handler) || - (init_data->no_output_qs && !init_data->output_handler)) + /* Needed as error_handler: */ + if (!init_data->input_handler) + return -EINVAL; + + if (init_data->no_output_qs && !init_data->output_handler) return -EINVAL; if (!init_data->input_sbal_addr_array || diff --git a/drivers/s390/cio/qdio_setup.c b/drivers/s390/cio/qdio_setup.c index fd663922d7d59..714878e2acc4d 100644 --- a/drivers/s390/cio/qdio_setup.c +++ b/drivers/s390/cio/qdio_setup.c @@ -362,6 +362,7 @@ void qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data) irq_ptr->debugfs_dev = NULL; irq_ptr->sch_token = irq_ptr->perf_stat_enabled = 0; irq_ptr->state = QDIO_IRQ_STATE_INACTIVE; + irq_ptr->error_handler = init_data->input_handler; irq_ptr->int_parm = init_data->int_parm; irq_ptr->nr_input_qs = init_data->no_input_qs; -- GitLab From b44995e515227e68af8a337c0538e17b05ae560f Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 23 Jul 2021 09:16:10 +0200 Subject: [PATCH 321/965] s390/qdio: split qdio_inspect_queue() The callers know what type of queue they want to inspect. Introduce type-specific variants to inspect an {Input,Output} queue, so that we can avoid one function parameter and some conditional branches in the hot paths. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- arch/s390/include/asm/qdio.h | 7 +-- drivers/s390/cio/qdio_main.c | 84 ++++++++++++++++++------------- drivers/s390/net/qeth_core_main.c | 16 +++--- drivers/s390/scsi/zfcp_qdio.c | 4 +- 4 files changed, 64 insertions(+), 47 deletions(-) diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 97356ec27d377..5eb431f59eded 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -352,9 +352,10 @@ extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, int q_nr, unsigned int bufnr, unsigned int count, struct qaob *aob); extern int qdio_start_irq(struct ccw_device *cdev); extern int qdio_stop_irq(struct ccw_device *cdev); -extern int qdio_inspect_queue(struct ccw_device *cdev, unsigned int nr, - bool is_input, unsigned int *bufnr, - unsigned int *error); +extern int qdio_inspect_input_queue(struct ccw_device *cdev, unsigned int nr, + unsigned int *bufnr, unsigned int *error); +extern int qdio_inspect_output_queue(struct ccw_device *cdev, unsigned int nr, + unsigned int *bufnr, unsigned int *error); extern int qdio_shutdown(struct ccw_device *, int); extern int qdio_free(struct ccw_device *); extern int qdio_get_ssqd_desc(struct ccw_device *, struct qdio_ssqd_desc *); diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 35a32240b4ce8..3f047faf59f00 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -500,6 +500,31 @@ static int get_inbound_buffer_frontier(struct qdio_q *q, unsigned int start, } } +int qdio_inspect_input_queue(struct ccw_device *cdev, unsigned int nr, + unsigned int *bufnr, unsigned int *error) +{ + struct qdio_irq *irq = cdev->private->qdio_data; + unsigned int start; + struct qdio_q *q; + int count; + + if (!irq) + return -ENODEV; + + q = irq->input_qs[nr]; + start = q->first_to_check; + *error = 0; + + count = get_inbound_buffer_frontier(q, start, error); + if (count == 0) + return 0; + + *bufnr = start; + q->first_to_check = add_buf(start, count); + return count; +} +EXPORT_SYMBOL_GPL(qdio_inspect_input_queue); + static inline int qdio_inbound_q_done(struct qdio_q *q, unsigned int start) { unsigned char state = 0; @@ -579,6 +604,31 @@ static int get_outbound_buffer_frontier(struct qdio_q *q, unsigned int start, } } +int qdio_inspect_output_queue(struct ccw_device *cdev, unsigned int nr, + unsigned int *bufnr, unsigned int *error) +{ + struct qdio_irq *irq = cdev->private->qdio_data; + unsigned int start; + struct qdio_q *q; + int count; + + if (!irq) + return -ENODEV; + + q = irq->output_qs[nr]; + start = q->first_to_check; + *error = 0; + + count = get_outbound_buffer_frontier(q, start, error); + if (count == 0) + return 0; + + *bufnr = start; + q->first_to_check = add_buf(start, count); + return count; +} +EXPORT_SYMBOL_GPL(qdio_inspect_output_queue); + static int qdio_kick_outbound_q(struct qdio_q *q, unsigned int count, unsigned long aob) { @@ -1284,40 +1334,6 @@ rescan: } EXPORT_SYMBOL(qdio_start_irq); -static int __qdio_inspect_queue(struct qdio_q *q, unsigned int *bufnr, - unsigned int *error) -{ - unsigned int start = q->first_to_check; - int count; - - *error = 0; - count = q->is_input_q ? get_inbound_buffer_frontier(q, start, error) : - get_outbound_buffer_frontier(q, start, error); - if (count == 0) - return 0; - - *bufnr = start; - - /* for the next time */ - q->first_to_check = add_buf(start, count); - - return count; -} - -int qdio_inspect_queue(struct ccw_device *cdev, unsigned int nr, bool is_input, - unsigned int *bufnr, unsigned int *error) -{ - struct qdio_irq *irq_ptr = cdev->private->qdio_data; - struct qdio_q *q; - - if (!irq_ptr) - return -ENODEV; - q = is_input ? irq_ptr->input_qs[nr] : irq_ptr->output_qs[nr]; - - return __qdio_inspect_queue(q, bufnr, error); -} -EXPORT_SYMBOL_GPL(qdio_inspect_queue); - /** * qdio_stop_irq - disable interrupt processing for the device * @cdev: associated ccw_device for the qdio subchannel diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 26c55f67289f0..8cfbcb6aec075 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -5850,10 +5850,10 @@ static unsigned int qeth_rx_poll(struct qeth_card *card, int budget) /* Fetch completed RX buffers: */ if (!card->rx.b_count) { card->rx.qdio_err = 0; - card->rx.b_count = qdio_inspect_queue(CARD_DDEV(card), - 0, true, - &card->rx.b_index, - &card->rx.qdio_err); + card->rx.b_count = + qdio_inspect_input_queue(CARD_DDEV(card), 0, + &card->rx.b_index, + &card->rx.qdio_err); if (card->rx.b_count <= 0) { card->rx.b_count = 0; break; @@ -5900,8 +5900,8 @@ static void qeth_cq_poll(struct qeth_card *card) unsigned int start, error; int completed; - completed = qdio_inspect_queue(CARD_DDEV(card), 1, true, &start, - &error); + completed = qdio_inspect_input_queue(CARD_DDEV(card), 1, &start, + &error); if (completed <= 0) return; @@ -6038,8 +6038,8 @@ static int qeth_tx_poll(struct napi_struct *napi, int budget) return 0; } - completed = qdio_inspect_queue(CARD_DDEV(card), queue_no, false, - &start, &error); + completed = qdio_inspect_output_queue(CARD_DDEV(card), queue_no, + &start, &error); if (completed <= 0) { /* Ensure we see TX completion for pending work: */ if (napi_complete_done(napi, 0) && diff --git a/drivers/s390/scsi/zfcp_qdio.c b/drivers/s390/scsi/zfcp_qdio.c index 6a2720105138d..728945c706214 100644 --- a/drivers/s390/scsi/zfcp_qdio.c +++ b/drivers/s390/scsi/zfcp_qdio.c @@ -79,7 +79,7 @@ static void zfcp_qdio_request_tasklet(struct tasklet_struct *tasklet) unsigned int start, error; int completed; - completed = qdio_inspect_queue(cdev, 0, false, &start, &error); + completed = qdio_inspect_output_queue(cdev, 0, &start, &error); if (completed > 0) { if (error) { zfcp_qdio_handler_error(qdio, "qdreqt1", error); @@ -169,7 +169,7 @@ static void zfcp_qdio_irq_tasklet(struct tasklet_struct *tasklet) tasklet_schedule(&qdio->request_tasklet); /* Check the Response Queue: */ - completed = qdio_inspect_queue(cdev, 0, true, &start, &error); + completed = qdio_inspect_input_queue(cdev, 0, &start, &error); if (completed < 0) return; if (completed > 0) -- GitLab From a60bffe536f90834ddedc0ed4ddf81af943eb061 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Mon, 30 Aug 2021 15:28:36 +0300 Subject: [PATCH 322/965] s390/qdio: split do_QDIO() The callers know what type of queue they want to work with. Introduce type-specific variants to add buffers on an {Input,Output} queue, so that we can avoid some function parameters and the de-muxing into type-specific hot paths. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- arch/s390/include/asm/qdio.h | 11 ++++--- drivers/s390/cio/qdio_main.c | 51 +++++++++++++++++++++++-------- drivers/s390/net/qeth_core_main.c | 20 ++++++------ drivers/s390/scsi/zfcp_qdio.c | 15 +++++---- 4 files changed, 63 insertions(+), 34 deletions(-) diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 5eb431f59eded..c65652fa2dbd1 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -336,9 +336,6 @@ struct qdio_initialize { struct qdio_buffer ***output_sbal_addr_array; }; -#define QDIO_FLAG_SYNC_INPUT 0x01 -#define QDIO_FLAG_SYNC_OUTPUT 0x02 - int qdio_alloc_buffers(struct qdio_buffer **buf, unsigned int count); void qdio_free_buffers(struct qdio_buffer **buf, unsigned int count); void qdio_reset_buffers(struct qdio_buffer **buf, unsigned int count); @@ -348,14 +345,18 @@ extern int qdio_allocate(struct ccw_device *cdev, unsigned int no_input_qs, extern int qdio_establish(struct ccw_device *cdev, struct qdio_initialize *init_data); extern int qdio_activate(struct ccw_device *); -extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, int q_nr, - unsigned int bufnr, unsigned int count, struct qaob *aob); extern int qdio_start_irq(struct ccw_device *cdev); extern int qdio_stop_irq(struct ccw_device *cdev); extern int qdio_inspect_input_queue(struct ccw_device *cdev, unsigned int nr, unsigned int *bufnr, unsigned int *error); extern int qdio_inspect_output_queue(struct ccw_device *cdev, unsigned int nr, unsigned int *bufnr, unsigned int *error); +extern int qdio_add_bufs_to_input_queue(struct ccw_device *cdev, + unsigned int q_nr, unsigned int bufnr, + unsigned int count); +extern int qdio_add_bufs_to_output_queue(struct ccw_device *cdev, + unsigned int q_nr, unsigned int bufnr, + unsigned int count, struct qaob *aob); extern int qdio_shutdown(struct ccw_device *, int); extern int qdio_free(struct ccw_device *); extern int qdio_get_ssqd_desc(struct ccw_device *, struct qdio_ssqd_desc *); diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 3f047faf59f00..82c2383b0740f 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -1214,6 +1214,35 @@ static int handle_inbound(struct qdio_q *q, int bufnr, int count) return 0; } +/** + * qdio_add_bufs_to_input_queue - process buffers on an Input Queue + * @cdev: associated ccw_device for the qdio subchannel + * @q_nr: queue number + * @bufnr: buffer number + * @count: how many buffers to process + */ +int qdio_add_bufs_to_input_queue(struct ccw_device *cdev, unsigned int q_nr, + unsigned int bufnr, unsigned int count) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + + if (bufnr >= QDIO_MAX_BUFFERS_PER_Q || count > QDIO_MAX_BUFFERS_PER_Q) + return -EINVAL; + + if (!irq_ptr) + return -ENODEV; + + DBF_DEV_EVENT(DBF_INFO, irq_ptr, "addi b:%02x c:%02x", bufnr, count); + + if (irq_ptr->state != QDIO_IRQ_STATE_ACTIVE) + return -EIO; + if (!count) + return 0; + + return handle_inbound(irq_ptr->input_qs[q_nr], bufnr, count); +} +EXPORT_SYMBOL_GPL(qdio_add_bufs_to_input_queue); + /** * handle_outbound - process filled outbound buffers * @q: queue containing the buffers @@ -1255,16 +1284,16 @@ static int handle_outbound(struct qdio_q *q, unsigned int bufnr, unsigned int co } /** - * do_QDIO - process input or output buffers + * qdio_add_bufs_to_output_queue - process buffers on an Output Queue * @cdev: associated ccw_device for the qdio subchannel - * @callflags: input or output and special flags from the program * @q_nr: queue number * @bufnr: buffer number * @count: how many buffers to process - * @aob: asynchronous operation block (outbound only) + * @aob: asynchronous operation block */ -int do_QDIO(struct ccw_device *cdev, unsigned int callflags, - int q_nr, unsigned int bufnr, unsigned int count, struct qaob *aob) +int qdio_add_bufs_to_output_queue(struct ccw_device *cdev, unsigned int q_nr, + unsigned int bufnr, unsigned int count, + struct qaob *aob) { struct qdio_irq *irq_ptr = cdev->private->qdio_data; @@ -1274,20 +1303,16 @@ int do_QDIO(struct ccw_device *cdev, unsigned int callflags, if (!irq_ptr) return -ENODEV; - DBF_DEV_EVENT(DBF_INFO, irq_ptr, - "do%02x b:%02x c:%02x", callflags, bufnr, count); + DBF_DEV_EVENT(DBF_INFO, irq_ptr, "addo b:%02x c:%02x", bufnr, count); if (irq_ptr->state != QDIO_IRQ_STATE_ACTIVE) return -EIO; if (!count) return 0; - if (callflags & QDIO_FLAG_SYNC_INPUT) - return handle_inbound(irq_ptr->input_qs[q_nr], bufnr, count); - else if (callflags & QDIO_FLAG_SYNC_OUTPUT) - return handle_outbound(irq_ptr->output_qs[q_nr], bufnr, count, aob); - return -EINVAL; + + return handle_outbound(irq_ptr->output_qs[q_nr], bufnr, count, aob); } -EXPORT_SYMBOL_GPL(do_QDIO); +EXPORT_SYMBOL_GPL(qdio_add_bufs_to_output_queue); /** * qdio_start_irq - enable interrupt processing for the device diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 8cfbcb6aec075..fe2c4c699d376 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -355,8 +355,8 @@ static int qeth_cq_init(struct qeth_card *card) qdio_reset_buffers(card->qdio.c_q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q); card->qdio.c_q->next_buf_to_init = 127; - rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 1, 0, 127, - NULL); + + rc = qdio_add_bufs_to_input_queue(CARD_DDEV(card), 1, 0, 127); if (rc) { QETH_CARD_TEXT_(card, 2, "1err%d", rc); goto out; @@ -2926,8 +2926,7 @@ static int qeth_init_qdio_queues(struct qeth_card *card) } card->qdio.in_q->next_buf_to_init = QDIO_BUFNR(rx_bufs); - rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0, rx_bufs, - NULL); + rc = qdio_add_bufs_to_input_queue(CARD_DDEV(card), 0, 0, rx_bufs); if (rc) { QETH_CARD_TEXT_(card, 2, "1err%d", rc); return rc; @@ -3415,8 +3414,9 @@ static unsigned int qeth_rx_refill_queue(struct qeth_card *card, return 0; } - rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, - queue->next_buf_to_init, count, NULL); + rc = qdio_add_bufs_to_input_queue(CARD_DDEV(card), 0, + queue->next_buf_to_init, + count); if (rc) { QETH_CARD_TEXT(card, 2, "qinberr"); } @@ -3588,8 +3588,8 @@ static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index, } QETH_TXQ_STAT_INC(queue, doorbell); - rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_OUTPUT, queue->queue_no, - index, count, aob); + rc = qdio_add_bufs_to_output_queue(CARD_DDEV(card), queue->queue_no, + index, count, aob); switch (rc) { case 0: @@ -3739,8 +3739,8 @@ static void qeth_qdio_cq_handler(struct qeth_card *card, unsigned int qdio_err, } qeth_scrub_qdio_buffer(buffer, QDIO_MAX_ELEMENTS_PER_BUFFER); } - rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue, - cq->next_buf_to_init, count, NULL); + rc = qdio_add_bufs_to_input_queue(CARD_DDEV(card), queue, + cq->next_buf_to_init, count); if (rc) { dev_warn(&card->gdev->dev, "QDIO reported an error, rc=%i\n", rc); diff --git a/drivers/s390/scsi/zfcp_qdio.c b/drivers/s390/scsi/zfcp_qdio.c index 728945c706214..f54f506b02d66 100644 --- a/drivers/s390/scsi/zfcp_qdio.c +++ b/drivers/s390/scsi/zfcp_qdio.c @@ -154,7 +154,7 @@ static void zfcp_qdio_int_resp(struct ccw_device *cdev, unsigned int qdio_err, /* * put SBALs back to response queue */ - if (do_QDIO(cdev, QDIO_FLAG_SYNC_INPUT, 0, idx, count, NULL)) + if (qdio_add_bufs_to_input_queue(cdev, 0, idx, count)) zfcp_erp_adapter_reopen(qdio->adapter, 0, "qdires2"); } @@ -326,8 +326,9 @@ int zfcp_qdio_send(struct zfcp_qdio *qdio, struct zfcp_qdio_req *q_req) atomic_sub(sbal_number, &qdio->req_q_free); - retval = do_QDIO(qdio->adapter->ccw_device, QDIO_FLAG_SYNC_OUTPUT, 0, - q_req->sbal_first, sbal_number, NULL); + retval = qdio_add_bufs_to_output_queue(qdio->adapter->ccw_device, 0, + q_req->sbal_first, sbal_number, + NULL); if (unlikely(retval)) { /* Failed to submit the IO, roll back our modifications. */ @@ -395,7 +396,10 @@ void zfcp_qdio_close(struct zfcp_qdio *qdio) if (!(atomic_read(&adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP)) return; - /* clear QDIOUP flag, thus do_QDIO is not called during qdio_shutdown */ + /* + * Clear QDIOUP flag, thus qdio_add_bufs_to_output_queue() is not called + * during qdio_shutdown(). + */ spin_lock_irq(&qdio->req_q_lock); atomic_andnot(ZFCP_STATUS_ADAPTER_QDIOUP, &adapter->status); spin_unlock_irq(&qdio->req_q_lock); @@ -498,8 +502,7 @@ int zfcp_qdio_open(struct zfcp_qdio *qdio) sbale->addr = 0; } - if (do_QDIO(cdev, QDIO_FLAG_SYNC_INPUT, 0, 0, QDIO_MAX_BUFFERS_PER_Q, - NULL)) + if (qdio_add_bufs_to_input_queue(cdev, 0, 0, QDIO_MAX_BUFFERS_PER_Q)) goto failed_qdio; /* set index of first available SBALS / number of available SBALS */ -- GitLab From 97aa7468f697383e0ed5babd1168aaed8a660dc0 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 25 Nov 2021 19:30:07 +0100 Subject: [PATCH 323/965] s390/vmcp: use page_to_virt instead of page_to_phys Fix wrong usage of page_to_phys/phys_to_page. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Acked-by: Thomas Richter Signed-off-by: Heiko Carstens --- drivers/s390/char/vmcp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/s390/char/vmcp.c b/drivers/s390/char/vmcp.c index 9e066281e2d05..4cebfaaa22b43 100644 --- a/drivers/s390/char/vmcp.c +++ b/drivers/s390/char/vmcp.c @@ -72,7 +72,7 @@ static void vmcp_response_alloc(struct vmcp_session *session) if (order > 2) page = cma_alloc(vmcp_cma, nr_pages, 0, false); if (page) { - session->response = (char *)page_to_phys(page); + session->response = (char *)page_to_virt(page); session->cma_alloc = 1; return; } @@ -89,7 +89,7 @@ static void vmcp_response_free(struct vmcp_session *session) order = get_order(session->bufsize); nr_pages = ALIGN(session->bufsize, PAGE_SIZE) >> PAGE_SHIFT; if (session->cma_alloc) { - page = phys_to_page((unsigned long)session->response); + page = virt_to_page((unsigned long)session->response); cma_release(vmcp_cma, page, nr_pages); session->cma_alloc = 0; } else { -- GitLab From 4e4dc65ab578c962ea898d475c0418ea29cc6b2f Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Thu, 25 Nov 2021 16:42:22 +0100 Subject: [PATCH 324/965] s390/pci: use phys_to_virt() for AIBVs/DIBVs The adapter and directed interrupt bit vectors need to be referenced in the FIB with their physical not their virtual address. So use virt_to_phys() as approrpiate. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reviewed-by: Pierre Morel Signed-off-by: Niklas Schnelle Signed-off-by: Heiko Carstens --- arch/s390/pci/pci_irq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/s390/pci/pci_irq.c b/arch/s390/pci/pci_irq.c index 954bb7a831241..aefd306ea71e1 100644 --- a/arch/s390/pci/pci_irq.c +++ b/arch/s390/pci/pci_irq.c @@ -45,9 +45,9 @@ static int zpci_set_airq(struct zpci_dev *zdev) fib.fmt0.isc = PCI_ISC; fib.fmt0.sum = 1; /* enable summary notifications */ fib.fmt0.noi = airq_iv_end(zdev->aibv); - fib.fmt0.aibv = (unsigned long) zdev->aibv->vector; + fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector); fib.fmt0.aibvo = 0; /* each zdev has its own interrupt vector */ - fib.fmt0.aisb = (unsigned long) zpci_sbv->vector + (zdev->aisb/64)*8; + fib.fmt0.aisb = virt_to_phys(zpci_sbv->vector) + (zdev->aisb / 64) * 8; fib.fmt0.aisbo = zdev->aisb & 63; return zpci_mod_fc(req, &fib, &status) ? -EIO : 0; @@ -422,7 +422,7 @@ static int __init zpci_directed_irq_init(void) iib.diib.isc = PCI_ISC; iib.diib.nr_cpus = num_possible_cpus(); - iib.diib.disb_addr = (u64) zpci_sbv->vector; + iib.diib.disb_addr = virt_to_phys(zpci_sbv->vector); __zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib); zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv), -- GitLab From 568de506e31749ae9140c1a804f3b1d1ab47b4c2 Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Thu, 25 Nov 2021 16:46:00 +0100 Subject: [PATCH 325/965] s390/pci: use physical addresses in DMA tables The entries in the DMA translation tables for our IOMMU must specify physical addresses of either the next level table or the final page to be mapped for DMA. Currently however the code simply passes the virtual addresses of both. On the other hand we still need to walk the tables via their virtual addresses so we need to do a phys_to_virt() when setting the entries and a virt_to_phys() when getting them. Similarly when passing the I/O translation anchor to the hardware we must also specify its physical address. As the DMA and IOMMU APIs we are implementing already use the correct phys_addr_t type for the address to be mapped let's also thread this through instead of treating it as just an unsigned long. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reviewed-by: Pierre Morel Signed-off-by: Niklas Schnelle Signed-off-by: Heiko Carstens --- arch/s390/include/asm/pci_dma.h | 29 ++++++++++++++++------------- arch/s390/pci/pci.c | 2 +- arch/s390/pci/pci_dma.c | 26 +++++++++++++------------- drivers/iommu/s390-iommu.c | 10 +++++----- 4 files changed, 35 insertions(+), 32 deletions(-) diff --git a/arch/s390/include/asm/pci_dma.h b/arch/s390/include/asm/pci_dma.h index 3b8e89d4578a8..91e63426bdc53 100644 --- a/arch/s390/include/asm/pci_dma.h +++ b/arch/s390/include/asm/pci_dma.h @@ -97,23 +97,23 @@ static inline unsigned int calc_px(dma_addr_t ptr) return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK; } -static inline void set_pt_pfaa(unsigned long *entry, void *pfaa) +static inline void set_pt_pfaa(unsigned long *entry, phys_addr_t pfaa) { *entry &= ZPCI_PTE_FLAG_MASK; - *entry |= ((unsigned long) pfaa & ZPCI_PTE_ADDR_MASK); + *entry |= (pfaa & ZPCI_PTE_ADDR_MASK); } -static inline void set_rt_sto(unsigned long *entry, void *sto) +static inline void set_rt_sto(unsigned long *entry, phys_addr_t sto) { *entry &= ZPCI_RTE_FLAG_MASK; - *entry |= ((unsigned long) sto & ZPCI_RTE_ADDR_MASK); + *entry |= (sto & ZPCI_RTE_ADDR_MASK); *entry |= ZPCI_TABLE_TYPE_RTX; } -static inline void set_st_pto(unsigned long *entry, void *pto) +static inline void set_st_pto(unsigned long *entry, phys_addr_t pto) { *entry &= ZPCI_STE_FLAG_MASK; - *entry |= ((unsigned long) pto & ZPCI_STE_ADDR_MASK); + *entry |= (pto & ZPCI_STE_ADDR_MASK); *entry |= ZPCI_TABLE_TYPE_SX; } @@ -169,16 +169,19 @@ static inline int pt_entry_isvalid(unsigned long entry) static inline unsigned long *get_rt_sto(unsigned long entry) { - return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX) - ? (unsigned long *) (entry & ZPCI_RTE_ADDR_MASK) - : NULL; + if ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX) + return phys_to_virt(entry & ZPCI_RTE_ADDR_MASK); + else + return NULL; + } static inline unsigned long *get_st_pto(unsigned long entry) { - return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX) - ? (unsigned long *) (entry & ZPCI_STE_ADDR_MASK) - : NULL; + if ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX) + return phys_to_virt(entry & ZPCI_STE_ADDR_MASK); + else + return NULL; } /* Prototypes */ @@ -186,7 +189,7 @@ void dma_free_seg_table(unsigned long); unsigned long *dma_alloc_cpu_table(void); void dma_cleanup_tables(unsigned long *); unsigned long *dma_walk_cpu_trans(unsigned long *rto, dma_addr_t dma_addr); -void dma_update_cpu_trans(unsigned long *entry, void *page_addr, int flags); +void dma_update_cpu_trans(unsigned long *entry, phys_addr_t page_addr, int flags); extern const struct dma_map_ops s390_pci_dma_ops; diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index 2f9b78fa82a54..792f8e0f21789 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -771,7 +771,7 @@ int zpci_hot_reset_device(struct zpci_dev *zdev) if (zdev->dma_table) rc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma, - (u64)zdev->dma_table); + virt_to_phys(zdev->dma_table)); else rc = zpci_dma_init_device(zdev); if (rc) { diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index 1f4540d6bd2d3..f46833a255263 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -74,7 +74,7 @@ static unsigned long *dma_get_seg_table_origin(unsigned long *entry) if (!sto) return NULL; - set_rt_sto(entry, sto); + set_rt_sto(entry, virt_to_phys(sto)); validate_rt_entry(entry); entry_clr_protected(entry); } @@ -91,7 +91,7 @@ static unsigned long *dma_get_page_table_origin(unsigned long *entry) pto = dma_alloc_page_table(); if (!pto) return NULL; - set_st_pto(entry, pto); + set_st_pto(entry, virt_to_phys(pto)); validate_st_entry(entry); entry_clr_protected(entry); } @@ -117,7 +117,7 @@ unsigned long *dma_walk_cpu_trans(unsigned long *rto, dma_addr_t dma_addr) return &pto[px]; } -void dma_update_cpu_trans(unsigned long *entry, void *page_addr, int flags) +void dma_update_cpu_trans(unsigned long *entry, phys_addr_t page_addr, int flags) { if (flags & ZPCI_PTE_INVALID) { invalidate_pt_entry(entry); @@ -132,11 +132,11 @@ void dma_update_cpu_trans(unsigned long *entry, void *page_addr, int flags) entry_clr_protected(entry); } -static int __dma_update_trans(struct zpci_dev *zdev, unsigned long pa, +static int __dma_update_trans(struct zpci_dev *zdev, phys_addr_t pa, dma_addr_t dma_addr, size_t size, int flags) { unsigned int nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; - u8 *page_addr = (u8 *) (pa & PAGE_MASK); + phys_addr_t page_addr = (pa & PAGE_MASK); unsigned long irq_flags; unsigned long *entry; int i, rc = 0; @@ -217,7 +217,7 @@ out: return ret; } -static int dma_update_trans(struct zpci_dev *zdev, unsigned long pa, +static int dma_update_trans(struct zpci_dev *zdev, phys_addr_t pa, dma_addr_t dma_addr, size_t size, int flags) { int rc; @@ -400,7 +400,7 @@ static void *s390_dma_alloc(struct device *dev, size_t size, { struct zpci_dev *zdev = to_zpci(to_pci_dev(dev)); struct page *page; - unsigned long pa; + phys_addr_t pa; dma_addr_t map; size = PAGE_ALIGN(size); @@ -411,18 +411,18 @@ static void *s390_dma_alloc(struct device *dev, size_t size, pa = page_to_phys(page); map = s390_dma_map_pages(dev, page, 0, size, DMA_BIDIRECTIONAL, 0); if (dma_mapping_error(dev, map)) { - free_pages(pa, get_order(size)); + __free_pages(page, get_order(size)); return NULL; } atomic64_add(size / PAGE_SIZE, &zdev->allocated_pages); if (dma_handle) *dma_handle = map; - return (void *) pa; + return phys_to_virt(pa); } static void s390_dma_free(struct device *dev, size_t size, - void *pa, dma_addr_t dma_handle, + void *vaddr, dma_addr_t dma_handle, unsigned long attrs) { struct zpci_dev *zdev = to_zpci(to_pci_dev(dev)); @@ -430,7 +430,7 @@ static void s390_dma_free(struct device *dev, size_t size, size = PAGE_ALIGN(size); atomic64_sub(size / PAGE_SIZE, &zdev->allocated_pages); s390_dma_unmap_pages(dev, dma_handle, size, DMA_BIDIRECTIONAL, 0); - free_pages((unsigned long) pa, get_order(size)); + free_pages((unsigned long)vaddr, get_order(size)); } /* Map a segment into a contiguous dma address area */ @@ -443,7 +443,7 @@ static int __s390_dma_map_sg(struct device *dev, struct scatterlist *sg, dma_addr_t dma_addr_base, dma_addr; int flags = ZPCI_PTE_VALID; struct scatterlist *s; - unsigned long pa = 0; + phys_addr_t pa = 0; int ret; dma_addr_base = dma_alloc_address(dev, nr_pages); @@ -598,7 +598,7 @@ int zpci_dma_init_device(struct zpci_dev *zdev) } if (zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma, - (u64)zdev->dma_table)) { + virt_to_phys(zdev->dma_table))) { rc = -EIO; goto free_bitmap; } diff --git a/drivers/iommu/s390-iommu.c b/drivers/iommu/s390-iommu.c index 83df387e70a33..50860ebdd0870 100644 --- a/drivers/iommu/s390-iommu.c +++ b/drivers/iommu/s390-iommu.c @@ -109,7 +109,7 @@ static int s390_iommu_attach_device(struct iommu_domain *domain, zdev->dma_table = s390_domain->dma_table; cc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma, - (u64) zdev->dma_table); + virt_to_phys(zdev->dma_table)); if (cc) { rc = -EIO; goto out_restore; @@ -205,11 +205,11 @@ static void s390_iommu_release_device(struct device *dev) } static int s390_iommu_update_trans(struct s390_domain *s390_domain, - unsigned long pa, dma_addr_t dma_addr, + phys_addr_t pa, dma_addr_t dma_addr, size_t size, int flags) { struct s390_domain_device *domain_device; - u8 *page_addr = (u8 *) (pa & PAGE_MASK); + phys_addr_t page_addr = pa & PAGE_MASK; dma_addr_t start_dma_addr = dma_addr; unsigned long irq_flags, nr_pages, i; unsigned long *entry; @@ -274,7 +274,7 @@ static int s390_iommu_map(struct iommu_domain *domain, unsigned long iova, if (!(prot & IOMMU_WRITE)) flags |= ZPCI_TABLE_PROTECTED; - rc = s390_iommu_update_trans(s390_domain, (unsigned long) paddr, iova, + rc = s390_iommu_update_trans(s390_domain, paddr, iova, size, flags); return rc; @@ -324,7 +324,7 @@ static size_t s390_iommu_unmap(struct iommu_domain *domain, if (!paddr) return 0; - rc = s390_iommu_update_trans(s390_domain, (unsigned long) paddr, iova, + rc = s390_iommu_update_trans(s390_domain, paddr, iova, size, flags); if (rc) return 0; -- GitLab From e628f28793033ff760c82e04a73abe415b10a66c Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 24 Nov 2021 10:16:53 +0100 Subject: [PATCH 326/965] s390/qdio: remove unneeded sanity check in qdio_do_sqbs() All callers of set_buf_states() are already making sure that 'count' is not 0. So don't check it an additional time. Note that our own code also doesn't _require_ the count to be sane (ie. we can't overrun an array or similar). So worst case HW would simply reject the SQBS operation and report an error. Signed-off-by: Julian Wiedmann Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens --- drivers/s390/cio/qdio_main.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 82c2383b0740f..9cde55730b65a 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -170,8 +170,6 @@ static int qdio_do_sqbs(struct qdio_q *q, unsigned char state, int start, int tmp_count = count, tmp_start = start; int nr = q->nr; - if (!count) - return 0; qperf_inc(q, sqbs); if (!q->is_input_q) -- GitLab From 32ddf3e124ee35b70c86e239b31d30827f993d3f Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Thu, 20 Aug 2020 15:19:42 +0300 Subject: [PATCH 327/965] s390/qdio: clarify logical vs absolute in QIB's kerneldoc qib.isliba and qib.osliba are actually logical addresses, and this is also how the relevant code sets up these fields. Fix up the documentation. Signed-off-by: Julian Wiedmann Reviewed-by: Alexandra Winter Signed-off-by: Heiko Carstens --- arch/s390/include/asm/qdio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index c65652fa2dbd1..54ae2dc65e3b2 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -91,8 +91,8 @@ struct qdr { * @pfmt: implementation dependent parameter format * @rflags: QEBSM * @ac: adapter characteristics - * @isliba: absolute address of first input SLIB - * @osliba: absolute address of first output SLIB + * @isliba: logical address of first input SLIB + * @osliba: logical address of first output SLIB * @ebcnam: adapter identifier in EBCDIC * @parm: implementation dependent parameters */ -- GitLab From 402ff5a3387dc8ec6987a80d3ce26b0c25773622 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 25 Nov 2021 19:59:16 +0100 Subject: [PATCH 328/965] s390/nmi: add missing __pa/__va address conversion of extended save area Add missing __pa/__va address conversion of machine check extended save area designation, which is an absolute address. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reported-by: Vineeth Vijayan Tested-by: Vineeth Vijayan Signed-off-by: Heiko Carstens --- arch/s390/kernel/machine_kexec.c | 2 +- arch/s390/kernel/nmi.c | 10 +++++----- arch/s390/kernel/smp.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c index 0505e55a62979..a16467b3825ec 100644 --- a/arch/s390/kernel/machine_kexec.c +++ b/arch/s390/kernel/machine_kexec.c @@ -86,7 +86,7 @@ static noinline void __machine_kdump(void *image) continue; } /* Store status of the boot CPU */ - mcesa = (struct mcesa *)(S390_lowcore.mcesad & MCESA_ORIGIN_MASK); + mcesa = __va(S390_lowcore.mcesad & MCESA_ORIGIN_MASK); if (MACHINE_HAS_VX) save_vx_regs((__vector128 *) mcesa->vector_save_area); if (MACHINE_HAS_GS) { diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 20f8e1868853f..3f18c1412eba3 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -68,7 +68,7 @@ void __init nmi_alloc_boot_cpu(struct lowcore *lc) { if (!nmi_needs_mcesa()) return; - lc->mcesad = (unsigned long) &boot_mcesa; + lc->mcesad = __pa(&boot_mcesa); if (MACHINE_HAS_GS) lc->mcesad |= ilog2(MCESA_MAX_SIZE); } @@ -94,7 +94,7 @@ static int __init nmi_init(void) __ctl_store(cr0, 0, 0); __ctl_clear_bit(0, 28); /* disable lowcore protection */ /* Replace boot_mcesa on the boot CPU */ - S390_lowcore.mcesad = origin | mcesa_origin_lc; + S390_lowcore.mcesad = __pa(origin) | mcesa_origin_lc; __ctl_load(cr0, 0, 0); return 0; } @@ -111,7 +111,7 @@ int nmi_alloc_per_cpu(struct lowcore *lc) return -ENOMEM; /* The pointer is stored with mcesa_bits ORed in */ kmemleak_not_leak((void *) origin); - lc->mcesad = origin | mcesa_origin_lc; + lc->mcesad = __pa(origin) | mcesa_origin_lc; return 0; } @@ -119,7 +119,7 @@ void nmi_free_per_cpu(struct lowcore *lc) { if (!nmi_needs_mcesa()) return; - kmem_cache_free(mcesa_cache, (void *)(lc->mcesad & MCESA_ORIGIN_MASK)); + kmem_cache_free(mcesa_cache, __va(lc->mcesad & MCESA_ORIGIN_MASK)); } static notrace void s390_handle_damage(void) @@ -246,7 +246,7 @@ static int notrace s390_validate_registers(union mci mci, int umode) : "Q" (S390_lowcore.fpt_creg_save_area)); } - mcesa = (struct mcesa *)(S390_lowcore.mcesad & MCESA_ORIGIN_MASK); + mcesa = __va(S390_lowcore.mcesad & MCESA_ORIGIN_MASK); if (!MACHINE_HAS_VX) { /* Validate floating point registers */ asm volatile( diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 78a8ea6fd582a..2e280e812dfd1 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -622,7 +622,7 @@ int smp_store_status(int cpu) return -EIO; if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) return 0; - pa = __pa(lc->mcesad & MCESA_ORIGIN_MASK); + pa = lc->mcesad & MCESA_ORIGIN_MASK; if (MACHINE_HAS_GS) pa |= lc->mcesad & MCESA_LC_MASK; if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, -- GitLab From f139862b92cf85bd25cbe7c8683d63c037e6562c Mon Sep 17 00:00:00 2001 From: Tony Krowiak Date: Wed, 27 Oct 2021 11:20:14 -0400 Subject: [PATCH 329/965] s390/vfio-ap: add status attribute to AP queue device's sysfs dir This patch adds a sysfs 'status' attribute to a queue device when it is bound to the vfio_ap device driver. The field displays a string indicating the status of the queue device: Status String: Indicates: ------------- --------- "assigned" the queue is assigned to an mdev, but is not in use by a KVM guest. "in use" the queue is assigned to an mdev and is in use by a KVM guest. "unassigned" the queue is not assigned to an mdev. The status string will be displayed by the 'lszcrypt' command if the queue device is bound to the vfio_ap device driver. Signed-off-by: Harald Freudenberger [akrowiak@linux.ibm.com: added check for queue in use by guest] Signed-off-by: Tony Krowiak Signed-off-by: Heiko Carstens --- drivers/s390/crypto/vfio_ap_drv.c | 79 +++++++++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 3 deletions(-) diff --git a/drivers/s390/crypto/vfio_ap_drv.c b/drivers/s390/crypto/vfio_ap_drv.c index 03311a476366b..e043ae236630c 100644 --- a/drivers/s390/crypto/vfio_ap_drv.c +++ b/drivers/s390/crypto/vfio_ap_drv.c @@ -17,6 +17,9 @@ #define VFIO_AP_ROOT_NAME "vfio_ap" #define VFIO_AP_DEV_NAME "matrix" +#define AP_QUEUE_ASSIGNED "assigned" +#define AP_QUEUE_UNASSIGNED "unassigned" +#define AP_QUEUE_IN_USE "in use" MODULE_AUTHOR("IBM Corporation"); MODULE_DESCRIPTION("VFIO AP device driver, Copyright IBM Corp. 2018"); @@ -41,26 +44,95 @@ static struct ap_device_id ap_queue_ids[] = { MODULE_DEVICE_TABLE(vfio_ap, ap_queue_ids); +static struct ap_matrix_mdev *vfio_ap_mdev_for_queue(struct vfio_ap_queue *q) +{ + struct ap_matrix_mdev *matrix_mdev; + unsigned long apid = AP_QID_CARD(q->apqn); + unsigned long apqi = AP_QID_QUEUE(q->apqn); + + list_for_each_entry(matrix_mdev, &matrix_dev->mdev_list, node) { + if (test_bit_inv(apid, matrix_mdev->matrix.apm) && + test_bit_inv(apqi, matrix_mdev->matrix.aqm)) + return matrix_mdev; + } + + return NULL; +} + +static ssize_t status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t nchars = 0; + struct vfio_ap_queue *q; + struct ap_matrix_mdev *matrix_mdev; + struct ap_device *apdev = to_ap_dev(dev); + + mutex_lock(&matrix_dev->lock); + q = dev_get_drvdata(&apdev->device); + matrix_mdev = vfio_ap_mdev_for_queue(q); + + if (matrix_mdev) { + if (matrix_mdev->kvm) + nchars = scnprintf(buf, PAGE_SIZE, "%s\n", + AP_QUEUE_IN_USE); + else + nchars = scnprintf(buf, PAGE_SIZE, "%s\n", + AP_QUEUE_ASSIGNED); + } else { + nchars = scnprintf(buf, PAGE_SIZE, "%s\n", + AP_QUEUE_UNASSIGNED); + } + + mutex_unlock(&matrix_dev->lock); + + return nchars; +} + +static DEVICE_ATTR_RO(status); + +static struct attribute *vfio_queue_attrs[] = { + &dev_attr_status.attr, + NULL, +}; + +static const struct attribute_group vfio_queue_attr_group = { + .attrs = vfio_queue_attrs, +}; + /** * vfio_ap_queue_dev_probe: Allocate a vfio_ap_queue structure and associate it * with the device as driver_data. * * @apdev: the AP device being probed * - * Return: returns 0 if the probe succeeded; otherwise, returns -ENOMEM if - * storage could not be allocated for a vfio_ap_queue object. + * Return: returns 0 if the probe succeeded; otherwise, returns an error if + * storage could not be allocated for a vfio_ap_queue object or the + * sysfs 'status' attribute could not be created for the queue device. */ static int vfio_ap_queue_dev_probe(struct ap_device *apdev) { + int ret; struct vfio_ap_queue *q; q = kzalloc(sizeof(*q), GFP_KERNEL); if (!q) return -ENOMEM; + + mutex_lock(&matrix_dev->lock); dev_set_drvdata(&apdev->device, q); q->apqn = to_ap_queue(&apdev->device)->qid; q->saved_isc = VFIO_AP_ISC_INVALID; - return 0; + + ret = sysfs_create_group(&apdev->device.kobj, &vfio_queue_attr_group); + if (ret) { + dev_set_drvdata(&apdev->device, NULL); + kfree(q); + } + + mutex_unlock(&matrix_dev->lock); + + return ret; } /** @@ -75,6 +147,7 @@ static void vfio_ap_queue_dev_remove(struct ap_device *apdev) struct vfio_ap_queue *q; mutex_lock(&matrix_dev->lock); + sysfs_remove_group(&apdev->device.kobj, &vfio_queue_attr_group); q = dev_get_drvdata(&apdev->device); vfio_ap_mdev_reset_queue(q, 1); dev_set_drvdata(&apdev->device, NULL); -- GitLab From d658220a1c45cb721a80a9af7d1d70b35c7b74ea Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 25 Oct 2021 17:32:32 +0100 Subject: [PATCH 330/965] arm64/kvm: Fix bitrotted comment for SVE handling in handle_exit.c The comment on the SVE trap handler in handle_exit.c says that it is a placeholder until we support SVE in guests which we now do for both VHE and nVHE cases so we really shouldn't get here in any sort of standard case. Update the comment to be less immediately incorrect, the handling of such a situation is correct. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211025163232.3502052-1-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/kvm/handle_exit.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 275a27368a04c..5abe0617f2afc 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -140,9 +140,12 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu) return 1; } +/* + * Guest access to SVE registers should be routed to this handler only + * when the system doesn't support SVE. + */ static int handle_sve(struct kvm_vcpu *vcpu) { - /* Until SVE is supported for guests: */ kvm_inject_undefined(vcpu); return 1; } -- GitLab From b6363fe7b5135bfb5aea03f414148b3c2417702e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 29 Oct 2021 09:40:55 -0500 Subject: [PATCH 331/965] arm64: Simplify checking for populated DT Use of the of_scan_flat_dt() function predates libfdt and is discouraged as libfdt provides a nicer set of APIs. Rework dt_scan_depth1_nodes to use libfdt calls directly, and rename it to dt_is_stub() to reflect exactly what it checking. Cc: Will Deacon Signed-off-by: Rob Herring Reviewed-by: Mark Rutland Link: https://lore.kernel.org/r/20211029144055.2365814-1-robh@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/kernel/acpi.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index f3851724fe356..e4dea8db6924c 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -62,29 +63,22 @@ static int __init parse_acpi(char *arg) } early_param("acpi", parse_acpi); -static int __init dt_scan_depth1_nodes(unsigned long node, - const char *uname, int depth, - void *data) +static bool __init dt_is_stub(void) { - /* - * Ignore anything not directly under the root node; we'll - * catch its parent instead. - */ - if (depth != 1) - return 0; + int node; - if (strcmp(uname, "chosen") == 0) - return 0; + fdt_for_each_subnode(node, initial_boot_params, 0) { + const char *name = fdt_get_name(initial_boot_params, node, NULL); + if (strcmp(name, "chosen") == 0) + continue; + if (strcmp(name, "hypervisor") == 0 && + of_flat_dt_is_compatible(node, "xen,xen")) + continue; - if (strcmp(uname, "hypervisor") == 0 && - of_flat_dt_is_compatible(node, "xen,xen")) - return 0; + return false; + } - /* - * This node at depth 1 is neither a chosen node nor a xen node, - * which we do not expect. - */ - return 1; + return true; } /* @@ -205,8 +199,7 @@ void __init acpi_boot_table_init(void) * and ACPI has not been [force] enabled (acpi=on|force) */ if (param_acpi_off || - (!param_acpi_on && !param_acpi_force && - of_scan_flat_dt(dt_scan_depth1_nodes, NULL))) + (!param_acpi_on && !param_acpi_force && !dt_is_stub())) goto done; /* -- GitLab From c9f5ea08a0f029fc5e0edb5f1380b9a828285439 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 18 Nov 2021 12:18:10 -0800 Subject: [PATCH 332/965] arm64: entry: Use SDEI event constants Use SDEI_EV_FAILED instead of open coding the 1 to make it clearer how SDEI_EVENT_COMPLETE vs. SDEI_EVENT_COMPLETE_AND_RESUME is selected. Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20211118201811.2974922-1-f.fainelli@gmail.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/entry.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 2f69ae43941d8..772ec2ecf4888 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -966,8 +966,10 @@ SYM_CODE_START(__sdei_asm_handler) mov sp, x1 mov x1, x0 // address to complete_and_resume - /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ - cmp x0, #1 + /* x0 = (x0 <= SDEI_EV_FAILED) ? + * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME + */ + cmp x0, #SDEI_EV_FAILED mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME csel x0, x2, x3, ls -- GitLab From fde046e07d3343a0417eafc0533b0c9675b393e5 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 19 Nov 2021 12:46:08 +0800 Subject: [PATCH 333/965] arm64: extable: remove unused ex_handler_t definition The ex_handler_t type was introduced in commit d6e2cc564775 ("arm64: extable: add `type` and `data` fields"), but has never been used, and is unnecessary. Remove it. Signed-off-by: Jisheng Zhang Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20211119124608.3f03380b@xhacker Signed-off-by: Catalin Marinas --- arch/arm64/mm/extable.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c index c3d53811a15e1..c0181e60cc98e 100644 --- a/arch/arm64/mm/extable.c +++ b/arch/arm64/mm/extable.c @@ -10,9 +10,6 @@ #include #include -typedef bool (*ex_handler_t)(const struct exception_table_entry *, - struct pt_regs *); - static inline unsigned long get_ex_fixup(const struct exception_table_entry *ex) { -- GitLab From f0616abd4e67143b45b04b565839148458857347 Mon Sep 17 00:00:00 2001 From: Reiji Watanabe Date: Sun, 5 Dec 2021 16:47:35 -0800 Subject: [PATCH 334/965] arm64: clear_page() shouldn't use DC ZVA when DCZID_EL0.DZP == 1 Currently, clear_page() uses DC ZVA instruction unconditionally. But it should make sure that DCZID_EL0.DZP, which indicates whether or not use of DC ZVA instruction is prohibited, is zero when using the instruction. Use STNP instead when DCZID_EL0.DZP == 1. Fixes: f27bb139c387 ("arm64: Miscellaneous library functions") Signed-off-by: Reiji Watanabe Reviewed-by: Robin Murphy Link: https://lore.kernel.org/r/20211206004736.1520989-2-reijiw@google.com Signed-off-by: Catalin Marinas --- arch/arm64/lib/clear_page.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/lib/clear_page.S b/arch/arm64/lib/clear_page.S index b84b179edba3a..1fd5d790ab800 100644 --- a/arch/arm64/lib/clear_page.S +++ b/arch/arm64/lib/clear_page.S @@ -16,6 +16,7 @@ */ SYM_FUNC_START_PI(clear_page) mrs x1, dczid_el0 + tbnz x1, #4, 2f /* Branch if DC ZVA is prohibited */ and w1, w1, #0xf mov x2, #4 lsl x1, x2, x1 @@ -25,5 +26,14 @@ SYM_FUNC_START_PI(clear_page) tst x0, #(PAGE_SIZE - 1) b.ne 1b ret + +2: stnp xzr, xzr, [x0] + stnp xzr, xzr, [x0, #16] + stnp xzr, xzr, [x0, #32] + stnp xzr, xzr, [x0, #48] + add x0, x0, #64 + tst x0, #(PAGE_SIZE - 1) + b.ne 2b + ret SYM_FUNC_END_PI(clear_page) EXPORT_SYMBOL(clear_page) -- GitLab From 685e2564daa1493053fcd7f1dbed38b35ee2f3cb Mon Sep 17 00:00:00 2001 From: Reiji Watanabe Date: Sun, 5 Dec 2021 16:47:36 -0800 Subject: [PATCH 335/965] arm64: mte: DC {GVA,GZVA} shouldn't be used when DCZID_EL0.DZP == 1 Currently, mte_set_mem_tag_range() and mte_zero_clear_page_tags() use DC {GVA,GZVA} unconditionally. But, they should make sure that DCZID_EL0.DZP, which indicates whether or not use of those instructions is prohibited, is zero when using those instructions. Use ST{G,ZG,Z2G} instead when DCZID_EL0.DZP == 1. Fixes: 013bb59dbb7c ("arm64: mte: handle tags zeroing at page allocation time") Fixes: 3d0cca0b02ac ("kasan: speed up mte_set_mem_tag_range") Signed-off-by: Reiji Watanabe Link: https://lore.kernel.org/r/20211206004736.1520989-3-reijiw@google.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/mte-kasan.h | 8 +++++--- arch/arm64/lib/mte.S | 8 +++++++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h index 478b9bcf69ad1..e4704a403237e 100644 --- a/arch/arm64/include/asm/mte-kasan.h +++ b/arch/arm64/include/asm/mte-kasan.h @@ -84,10 +84,12 @@ static inline void __dc_gzva(u64 p) static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag, bool init) { - u64 curr, mask, dczid_bs, end1, end2, end3; + u64 curr, mask, dczid, dczid_bs, dczid_dzp, end1, end2, end3; /* Read DC G(Z)VA block size from the system register. */ - dczid_bs = 4ul << (read_cpuid(DCZID_EL0) & 0xf); + dczid = read_cpuid(DCZID_EL0); + dczid_bs = 4ul << (dczid & 0xf); + dczid_dzp = (dczid >> 4) & 1; curr = (u64)__tag_set(addr, tag); mask = dczid_bs - 1; @@ -106,7 +108,7 @@ static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag, */ #define SET_MEMTAG_RANGE(stg_post, dc_gva) \ do { \ - if (size >= 2 * dczid_bs) { \ + if (!dczid_dzp && size >= 2 * dczid_bs) {\ do { \ curr = stg_post(curr); \ } while (curr < end1); \ diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S index e83643b3995f4..f531dcb95174a 100644 --- a/arch/arm64/lib/mte.S +++ b/arch/arm64/lib/mte.S @@ -43,17 +43,23 @@ SYM_FUNC_END(mte_clear_page_tags) * x0 - address to the beginning of the page */ SYM_FUNC_START(mte_zero_clear_page_tags) + and x0, x0, #(1 << MTE_TAG_SHIFT) - 1 // clear the tag mrs x1, dczid_el0 + tbnz x1, #4, 2f // Branch if DC GZVA is prohibited and w1, w1, #0xf mov x2, #4 lsl x1, x2, x1 - and x0, x0, #(1 << MTE_TAG_SHIFT) - 1 // clear the tag 1: dc gzva, x0 add x0, x0, x1 tst x0, #(PAGE_SIZE - 1) b.ne 1b ret + +2: stz2g x0, [x0], #(MTE_GRANULE_SIZE * 2) + tst x0, #(PAGE_SIZE - 1) + b.ne 2b + ret SYM_FUNC_END(mte_zero_clear_page_tags) /* -- GitLab From 1bf6751c8d8e2989b7b8611080b3b3b1bc0b83f4 Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:56 +0300 Subject: [PATCH 336/965] dt-bindings: vendor-prefixes: add YADRO Add vendor prefix for YADRO (https://www.yadro.com/) Signed-off-by: Andrei Kartashev Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211119120057.12118-2-a.kartashev@yadro.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd7812..f0cb7dd11698c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1350,6 +1350,8 @@ patternProperties: description: Shenzhen Xunlong Software CO.,Limited "^xylon,.*": description: Xylon + "^yadro,.*": + description: YADRO "^yamaha,.*": description: Yamaha Corporation "^yes-optoelectronics,.*": -- GitLab From 67ac01d03862b274d4ca3fa76092e96b00f478af Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:57 +0300 Subject: [PATCH 337/965] ARM: dts: aspeed: add device tree for YADRO VEGMAN BMC YADRO VEGMAN is x86 based servers family with ASPEED AST2500-based BMC. Currently there are three models: * VEGMAN N110 * VEGMAN S220/320 * VEGMAN R120/220 The dts files provides configuration for BMC system. Signed-off-by: Andrei Kartashev Link: https://lore.kernel.org/r/20211119120057.12118-3-a.kartashev@yadro.com Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts | 149 +++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts | 255 +++++++++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts | 154 +++++++++ arch/arm/boot/dts/aspeed-bmc-vegman.dtsi | 311 +++++++++++++++++++ 5 files changed, 873 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..78b71e02624c6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1519,4 +1519,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-quanta-q71l.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts new file mode 100644 index 0000000000000..24319267d5508 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN N110 BMC"; + compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", + /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", + /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", + /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts new file mode 100644 index 0000000000000..ebbb68b55559a --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Rx20 BMC"; + compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; + + leds { + compatible = "gpio-leds"; + + temp_alarm { + label = "temp:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; + }; + + temp_ok { + label = "temp:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + }; + + psu_fault { + label = "psu:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; + }; + + psu_ok { + label = "psu:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", + /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; + }; + gpio@23 { + compatible = "nxp,pcal9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", + /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; + }; + gpio@39 { + compatible = "nxp,pca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + rsra-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + }; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rsrb-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts new file mode 100644 index 0000000000000..e36ee4704994b --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Sx20 BMC"; + compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", + /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi new file mode 100644 index 0000000000000..1a5b25b2ea295 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO + +#include "aspeed-g5.dtsi" +#include + +/ { + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + ramoops@9eff0000{ + compatible = "ramoops"; + reg = <0x9eff0000 0x10000>; + record-size = <0x2000>; + console-size = <0x2000>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + identify { + label = "platform:blue:indicator"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + }; + + status_amber { + label = "platform:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "platform:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; + + power_fault { + label = "platform:red:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; + }; + + power_ok { + label = "platform:green:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&timer 5 1000000 0>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; + flash@0 { + status = "okay"; + label = "bios"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + phy-mode = "rgmii"; + phy-handle = <&phy>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + /* KSZ9131 */ + compatible = "ethernet-phy-id0022.1640"; + reg = <1>; + + micrel,led-mode = <0>; + }; + }; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + disable-wp; +}; + +&timer { + fttmr010,pwm-outputs = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_timer5_default>; + #pwm-cells = <3>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&i2c0 { + /* SMB_IPMB_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c1 { + /* SMB_CHASSENSOR_STBY_LVC3 */ + status = "okay"; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + status = "okay"; +}; + +&i2c3 { + /* SMB_HOST_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c4 { + /* BMC_PMBUS2_STBY */ + status = "okay"; +}; + +&i2c5 { + /* SMB_SMLINK0_STBY_LVC3 */ + bus-frequency = <1000000>; + multi-master; + status = "okay"; +}; + +&i2c6 { + /* SMB_TEMPSENSOR_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c7 { + /* SMB_SM_PMB1_SML1_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c9 { + /* SMB_BMC_ETH3_LVC3 */ + status = "okay"; +}; + +&i2c10 { + /* SMB_BMC_ETH2_LVC3 */ + status = "okay"; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; +}; + +&i2c12 { + /* SMB_BMC_FAULT_EXP_LVC3 */ + status = "okay"; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + status = "okay"; +}; -- GitLab From 9e9652862ac253e7b589e6c624ac6f40df5fa297 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Tue, 30 Nov 2021 17:18:08 +0100 Subject: [PATCH 338/965] dt-bindings: watchdog: Add Apple Watchdog Apple SoCs come with a simple embedded watchdog. This watchdog is also required in order to reset the SoC. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Sven Peter Reviewed-by: Guenter Roeck Signed-off-by: Hector Martin --- .../bindings/watchdog/apple,wdt.yaml | 52 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/apple,wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml new file mode 100644 index 0000000000000..e58c56a6fdf6f --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Watchdog + +allOf: + - $ref: "watchdog.yaml#" + +maintainers: + - Sven Peter + +properties: + compatible: + items: + - enum: + - apple,t8103-wdt + - apple,t6000-wdt + - const: apple,wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + wdt: watchdog@50000000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x50000000 0x4000>; + clocks = <&clk>; + interrupts = ; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce85213..1e280e6abaf70 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1750,6 +1750,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/i2c/busses/i2c-pasemi-core.c F: drivers/i2c/busses/i2c-pasemi-platform.c -- GitLab From bd4d13ed210a6d3aadaaa9c93ee7e0671579cd10 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 25 Oct 2021 23:31:16 +0900 Subject: [PATCH 339/965] MAINTAINERS: Add PMGR power state files to ARM/APPLE MACHINE This covers the PMGR power state driver and its DT bindings, as well as any other future stuff in drivers/soc/apple. Signed-off-by: Hector Martin --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1e280e6abaf70..03ffcf49f5cf4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1745,11 +1745,13 @@ B: https://github.com/AsahiLinux/linux/issues C: irc://irc.oftc.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml +F: Documentation/devicetree/bindings/arm/apple/* F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/i2c/busses/i2c-pasemi-core.c @@ -1757,6 +1759,7 @@ F: drivers/i2c/busses/i2c-pasemi-platform.c F: drivers/irqchip/irq-apple-aic.c F: drivers/mailbox/apple-mailbox.c F: drivers/pinctrl/pinctrl-apple-gpio.c +F: drivers/soc/apple/* F: include/dt-bindings/interrupt-controller/apple-aic.h F: include/dt-bindings/pinctrl/apple.h F: include/linux/apple-mailbox.h -- GitLab From e8117f85b95b932069b9db73ccb3ee973ade2fc9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:16 +0900 Subject: [PATCH 340/965] dt-bindings: power: Add apple,pmgr-pwrstate binding This syscon child node represents a single SoC device controlled by the PMGR block. This layout allows us to declare all device power state controls (power/clock gating and reset) in the device tree, including dependencies, instead of hardcoding it into the driver. The register layout is uniform. Each pmgr-pwrstate node provides genpd and reset features, to be consumed by downstream device nodes. Future SoCs are expected to use backwards compatible registers, and the "apple,pmgr-pwrstate" represents any such interfaces (possibly with additional features gated by the more specific compatible), allowing them to be bound without driver updates. If a backwards incompatible change is introduced in future SoCs, it will require a new compatible, such as "apple,pmgr-pwrstate-v2". Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../bindings/power/apple,pmgr-pwrstate.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml new file mode 100644 index 0000000000000..5056d08b82610 --- /dev/null +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC PMGR Power States + +maintainers: + - Hector Martin + +allOf: + - $ref: "power-domain.yaml#" + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This binding describes the device power + state registers, which control power states and resets. + + Each instance of a power controller within the PMGR syscon node + represents a generic power domain provider, as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. + The provider controls a single SoC block. The power hierarchy is + represented via power-domains relationships between these nodes. + + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml + for the top-level PMGR node documentation. + +properties: + compatible: + items: + - enum: + - apple,t8103-pmgr-pwrstate + - apple,t6000-pmgr-pwrstate + - const: apple,pmgr-pwrstate + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + + "#reset-cells": + const: 0 + + power-domains: + description: + Reference to parent power domains. A domain may have multiple parents, + and all will be powered up when it is powered. + minItems: 1 + maxItems: 8 # Arbitrary, should be enough + + label: + description: + Specifies the name of the SoC domain being controlled. This is used to + name the power/reset domains. + + apple,always-on: + description: + Forces this power domain to always be powered up. + type: boolean + +required: + - compatible + - reg + - "#power-domain-cells" + - "#reset-cells" + - label + +additionalProperties: false -- GitLab From c83eeec79ff64f777cbd59a8bd15d0a3fe1f92c0 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:17 +0900 Subject: [PATCH 341/965] dt-bindings: arm: apple: Add apple,pmgr binding The PMGR block in Apple Silicon SoCs is responsible for SoC power management. There are two PMGRs in T8103, with different register layouts but compatible registers. In order to support this as well as future SoC generations with backwards-compatible registers, we declare these blocks as syscons and bind to individual registers in child nodes. Each register controls one SoC device. The respective apple compatibles are defined in case device-specific quirks are necessary in the future, but currently these nodes are expected to be bound by the generic syscon driver. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../bindings/arm/apple/apple,pmgr.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml new file mode 100644 index 0000000000000..b6b5d3a912b35 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Power Manager (PMGR) + +maintainers: + - Hector Martin + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This node represents the PMGR as a syscon, + with sub-nodes representing individual features. + +properties: + $nodename: + pattern: "^power-management@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "power-controller@[0-9a-f]+$": + description: + The individual power management domains within this controller + type: object + $ref: /power/apple,pmgr-pwrstate.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + apple,always-on; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + }; + + power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0x0 0xc000>; + + ps_aop_filter: power-controller@4000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4000 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_base: power-controller@4010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4010 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_filter>; + }; + + ps_aop_shim: power-controller@4038 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4038 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_shim"; + power-domains = <&ps_aop_base>; + }; + + ps_aop_uart0: power-controller@4048 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4048 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_uart0"; + power-domains = <&ps_aop_shim>; + }; + }; + }; -- GitLab From 6df9d38f9146e83b473f0c9e57fb5fdf3fcc93e2 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:18 +0900 Subject: [PATCH 342/965] soc: apple: Add driver for Apple PMGR power state controls Implements genpd and reset providers for downstream devices. Each instance of the driver binds to a single register and represents a single SoC power domain. The driver does not currently implement all features (clockgate-only state, misc flags), but we declare the respective registers for documentation purposes. These features will be added as they become useful for downstream devices. This also creates the apple/soc tree and Kconfig submenu. Acked-by: Linus Walleij Signed-off-by: Hector Martin --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/apple/Kconfig | 22 ++ drivers/soc/apple/Makefile | 2 + drivers/soc/apple/apple-pmgr-pwrstate.c | 317 ++++++++++++++++++++++++ 5 files changed, 343 insertions(+) create mode 100644 drivers/soc/apple/Kconfig create mode 100644 drivers/soc/apple/Makefile create mode 100644 drivers/soc/apple/apple-pmgr-pwrstate.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e8a30c4c5aec5..a8562678c4370 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -3,6 +3,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" source "drivers/soc/amlogic/Kconfig" +source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index a05e9fbcd3e04..adb30c2d4feaa 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ +obj-$(CONFIG_ARCH_APPLE) += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig new file mode 100644 index 0000000000000..3eb14abf8d337 --- /dev/null +++ b/drivers/soc/apple/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_APPLE || COMPILE_TEST + +menu "Apple SoC drivers" + +config APPLE_PMGR_PWRSTATE + tristate "Apple SoC PMGR power state control" + depends on PM + select REGMAP + select MFD_SYSCON + select PM_GENERIC_DOMAINS + select RESET_CONTROLLER + default ARCH_APPLE + help + The PMGR block in Apple SoCs provides high-level power state + controls for SoC devices. This driver manages them through the + generic power domain framework, and also provides reset support. + +endmenu + +endif diff --git a/drivers/soc/apple/Makefile b/drivers/soc/apple/Makefile new file mode 100644 index 0000000000000..c114e84667e4f --- /dev/null +++ b/drivers/soc/apple/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_APPLE_PMGR_PWRSTATE) += apple-pmgr-pwrstate.o diff --git a/drivers/soc/apple/apple-pmgr-pwrstate.c b/drivers/soc/apple/apple-pmgr-pwrstate.c new file mode 100644 index 0000000000000..8ad9d5fdefbfb --- /dev/null +++ b/drivers/soc/apple/apple-pmgr-pwrstate.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple SoC PMGR device power state driver + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define APPLE_PMGR_RESET BIT(31) +#define APPLE_PMGR_AUTO_ENABLE BIT(28) +#define APPLE_PMGR_PS_AUTO GENMASK(27, 24) +#define APPLE_PMGR_PARENT_OFF BIT(11) +#define APPLE_PMGR_DEV_DISABLE BIT(10) +#define APPLE_PMGR_WAS_CLKGATED BIT(9) +#define APPLE_PMGR_WAS_PWRGATED BIT(8) +#define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4) +#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) + +#define APPLE_PMGR_FLAGS (APPLE_PMGR_WAS_CLKGATED | APPLE_PMGR_WAS_PWRGATED) + +#define APPLE_PMGR_PS_ACTIVE 0xf +#define APPLE_PMGR_PS_CLKGATE 0x4 +#define APPLE_PMGR_PS_PWRGATE 0x0 + +#define APPLE_PMGR_PS_SET_TIMEOUT 100 +#define APPLE_PMGR_RESET_TIME 1 + +struct apple_pmgr_ps { + struct device *dev; + struct generic_pm_domain genpd; + struct reset_controller_dev rcdev; + struct regmap *regmap; + u32 offset; +}; + +#define genpd_to_apple_pmgr_ps(_genpd) container_of(_genpd, struct apple_pmgr_ps, genpd) +#define rcdev_to_apple_pmgr_ps(_rcdev) container_of(_rcdev, struct apple_pmgr_ps, rcdev) + +static int apple_pmgr_ps_set(struct generic_pm_domain *genpd, u32 pstate, bool auto_enable) +{ + int ret; + struct apple_pmgr_ps *ps = genpd_to_apple_pmgr_ps(genpd); + u32 reg; + + ret = regmap_read(ps->regmap, ps->offset, ®); + if (ret < 0) + return ret; + + /* Resets are synchronous, and only work if the device is powered and clocked. */ + if (reg & APPLE_PMGR_RESET && pstate != APPLE_PMGR_PS_ACTIVE) + dev_err(ps->dev, "PS %s: powering off with RESET active\n", + genpd->name); + + reg &= ~(APPLE_PMGR_AUTO_ENABLE | APPLE_PMGR_FLAGS | APPLE_PMGR_PS_TARGET); + reg |= FIELD_PREP(APPLE_PMGR_PS_TARGET, pstate); + + dev_dbg(ps->dev, "PS %s: pwrstate = 0x%x: 0x%x\n", genpd->name, pstate, reg); + + regmap_write(ps->regmap, ps->offset, reg); + + ret = regmap_read_poll_timeout_atomic( + ps->regmap, ps->offset, reg, + (FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == pstate), 1, + APPLE_PMGR_PS_SET_TIMEOUT); + if (ret < 0) + dev_err(ps->dev, "PS %s: Failed to reach power state 0x%x (now: 0x%x)\n", + genpd->name, pstate, reg); + + if (auto_enable) { + /* Not all devices implement this; this is a no-op where not implemented. */ + reg &= ~APPLE_PMGR_FLAGS; + reg |= APPLE_PMGR_AUTO_ENABLE; + regmap_write(ps->regmap, ps->offset, reg); + } + + return ret; +} + +static bool apple_pmgr_ps_is_active(struct apple_pmgr_ps *ps) +{ + u32 reg = 0; + + regmap_read(ps->regmap, ps->offset, ®); + /* + * We consider domains as active if they are actually on, or if they have auto-PM + * enabled and the intended target is on. + */ + return (FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == APPLE_PMGR_PS_ACTIVE || + (FIELD_GET(APPLE_PMGR_PS_TARGET, reg) == APPLE_PMGR_PS_ACTIVE && + reg & APPLE_PMGR_AUTO_ENABLE)); +} + +static int apple_pmgr_ps_power_on(struct generic_pm_domain *genpd) +{ + return apple_pmgr_ps_set(genpd, APPLE_PMGR_PS_ACTIVE, true); +} + +static int apple_pmgr_ps_power_off(struct generic_pm_domain *genpd) +{ + return apple_pmgr_ps_set(genpd, APPLE_PMGR_PS_PWRGATE, false); +} + +static int apple_pmgr_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + + mutex_lock(&ps->genpd.mlock); + + if (ps->genpd.status == GENPD_STATE_OFF) + dev_err(ps->dev, "PS 0x%x: asserting RESET while powered down\n", ps->offset); + + dev_dbg(ps->dev, "PS 0x%x: assert reset\n", ps->offset); + /* Quiesce device before asserting reset */ + regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, + APPLE_PMGR_DEV_DISABLE); + regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, + APPLE_PMGR_RESET); + + mutex_unlock(&ps->genpd.mlock); + + return 0; +} + +static int apple_pmgr_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + + mutex_lock(&ps->genpd.mlock); + + dev_dbg(ps->dev, "PS 0x%x: deassert reset\n", ps->offset); + regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, 0); + regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, 0); + + if (ps->genpd.status == GENPD_STATE_OFF) + dev_err(ps->dev, "PS 0x%x: RESET was deasserted while powered down\n", ps->offset); + + mutex_unlock(&ps->genpd.mlock); + + return 0; +} + +static int apple_pmgr_reset_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + int ret; + + ret = apple_pmgr_reset_assert(rcdev, id); + if (ret) + return ret; + + usleep_range(APPLE_PMGR_RESET_TIME, 2 * APPLE_PMGR_RESET_TIME); + + return apple_pmgr_reset_deassert(rcdev, id); +} + +static int apple_pmgr_reset_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + u32 reg = 0; + + regmap_read(ps->regmap, ps->offset, ®); + + return !!(reg & APPLE_PMGR_RESET); +} + +const struct reset_control_ops apple_pmgr_reset_ops = { + .assert = apple_pmgr_reset_assert, + .deassert = apple_pmgr_reset_deassert, + .reset = apple_pmgr_reset_reset, + .status = apple_pmgr_reset_status, +}; + +static int apple_pmgr_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return 0; +} + +static int apple_pmgr_ps_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct apple_pmgr_ps *ps; + struct regmap *regmap; + struct of_phandle_iterator it; + int ret; + const char *name; + bool active; + + regmap = syscon_node_to_regmap(node->parent); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ps = devm_kzalloc(dev, sizeof(*ps), GFP_KERNEL); + if (!ps) + return -ENOMEM; + + ps->dev = dev; + ps->regmap = regmap; + + ret = of_property_read_string(node, "label", &name); + if (ret < 0) { + dev_err(dev, "missing label property\n"); + return ret; + } + + ret = of_property_read_u32(node, "reg", &ps->offset); + if (ret < 0) { + dev_err(dev, "missing reg property\n"); + return ret; + } + + ps->genpd.name = name; + ps->genpd.power_on = apple_pmgr_ps_power_on; + ps->genpd.power_off = apple_pmgr_ps_power_off; + + active = apple_pmgr_ps_is_active(ps); + if (of_property_read_bool(node, "apple,always-on")) { + ps->genpd.flags |= GENPD_FLAG_ALWAYS_ON; + if (!active) { + dev_warn(dev, "always-on domain %s is not on at boot\n", name); + /* Turn it on so pm_genpd_init does not fail */ + active = apple_pmgr_ps_power_on(&ps->genpd) == 0; + } + } + + /* Turn on auto-PM if the domain is already on */ + if (active) + regmap_update_bits(regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_AUTO_ENABLE, + APPLE_PMGR_AUTO_ENABLE); + + ret = pm_genpd_init(&ps->genpd, NULL, !active); + if (ret < 0) { + dev_err(dev, "pm_genpd_init failed\n"); + return ret; + } + + ret = of_genpd_add_provider_simple(node, &ps->genpd); + if (ret < 0) { + dev_err(dev, "of_genpd_add_provider_simple failed\n"); + return ret; + } + + of_for_each_phandle(&it, ret, node, "power-domains", "#power-domain-cells", -1) { + struct of_phandle_args parent, child; + + parent.np = it.node; + parent.args_count = of_phandle_iterator_args(&it, parent.args, MAX_PHANDLE_ARGS); + child.np = node; + child.args_count = 0; + ret = of_genpd_add_subdomain(&parent, &child); + + if (ret == -EPROBE_DEFER) { + of_node_put(parent.np); + goto err_remove; + } else if (ret < 0) { + dev_err(dev, "failed to add to parent domain: %d (%s -> %s)\n", + ret, it.node->name, node->name); + of_node_put(parent.np); + goto err_remove; + } + } + + /* + * Do not participate in regular PM; parent power domains are handled via the + * genpd hierarchy. + */ + pm_genpd_remove_device(dev); + + ps->rcdev.owner = THIS_MODULE; + ps->rcdev.nr_resets = 1; + ps->rcdev.ops = &apple_pmgr_reset_ops; + ps->rcdev.of_node = dev->of_node; + ps->rcdev.of_reset_n_cells = 0; + ps->rcdev.of_xlate = apple_pmgr_reset_xlate; + + ret = devm_reset_controller_register(dev, &ps->rcdev); + if (ret < 0) + goto err_remove; + + return 0; +err_remove: + of_genpd_del_provider(node); + pm_genpd_remove(&ps->genpd); + return ret; +} + +static const struct of_device_id apple_pmgr_ps_of_match[] = { + { .compatible = "apple,pmgr-pwrstate" }, + {} +}; + +MODULE_DEVICE_TABLE(of, apple_pmgr_ps_of_match); + +static struct platform_driver apple_pmgr_ps_driver = { + .probe = apple_pmgr_ps_probe, + .driver = { + .name = "apple-pmgr-pwrstate", + .of_match_table = apple_pmgr_ps_of_match, + }, +}; + +MODULE_AUTHOR("Hector Martin "); +MODULE_DESCRIPTION("PMGR power state driver for Apple SoCs"); +MODULE_LICENSE("GPL v2"); + +module_platform_driver(apple_pmgr_ps_driver); -- GitLab From 106ba3b48a35ddf819ec5786208cf109c81da161 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:19 +0900 Subject: [PATCH 343/965] arm64: dts: apple: t8103: Add PMGR nodes This adds the two PMGR nodes and all known power state subnodes. Since there are a large number of them, let's put them in a separate file to include. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 1136 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 29 + 2 files changed, 1165 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8103-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi new file mode 100644 index 0000000000000..1310be74df1dd --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -0,0 +1,1136 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8103 "M1" SoC + * + * Copyright The Asahi Linux Contributors + */ + + +&pmgr { + ps_sbr: power-controller@100 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@108 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@110 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + apple,always-on; /* Core device */ + }; + + ps_soc_spmi0: power-controller@118 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi0"; + }; + + ps_soc_spmi1: power-controller@120 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi1"; + }; + + ps_soc_spmi2: power-controller@128 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi2"; + }; + + ps_gpio: power-controller@130 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms_busif: power-controller@138 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_busif"; + apple,always-on; /* Core device */ + }; + + ps_pms: power-controller@140 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pms_fpwm0: power-controller@148 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm0"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm1: power-controller@150 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm1"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm2: power-controller@158 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm2"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm3: power-controller@160 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm3"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm4: power-controller@168 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm4"; + power-domains = <&ps_pms>; + }; + + ps_soc_dpe: power-controller@170 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_dpe"; + apple,always-on; /* Core device */ + }; + + ps_pmgr_soc_ocla: power-controller@178 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmgr_soc_ocla"; + }; + + ps_ispsens0: power-controller@180 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@188 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@190 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_ispsens3: power-controller@198 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens3"; + }; + + ps_pcie_ref: power-controller@1a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_aft0: power-controller@1a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aft0"; + }; + + ps_devc0_ivdmc: power-controller@1b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "devc0_ivdmc"; + }; + + ps_imx: power-controller@1b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "imx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sio_busif: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio: power-controller@1c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_busif>; + }; + + ps_sio_cpu: power-controller@1d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_cpu"; + power-domains = <&ps_sio>; + }; + + ps_fpwm0: power-controller@1d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm0"; + }; + + ps_fpwm1: power-controller@1e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm1"; + }; + + ps_fpwm2: power-controller@1e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm2"; + }; + + ps_i2c0: power-controller@1f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio>; + }; + + ps_i2c1: power-controller@1f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio>; + }; + + ps_i2c2: power-controller@200 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio>; + }; + + ps_i2c3: power-controller@208 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio>; + }; + + ps_i2c4: power-controller@210 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio>; + }; + + ps_spi_p: power-controller@218 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi_p"; + power-domains = <&ps_sio>; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_audio_p: power-controller@228 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "audio_p"; + power-domains = <&ps_sio>; + }; + + ps_sio_adma: power-controller@230 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_adma"; + power-domains = <&ps_sio>, <&ps_pms>; + }; + + ps_aes: power-controller@238 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes"; + power-domains = <&ps_sio>; + }; + + ps_spi0: power-controller@240 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi1: power-controller@248 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi2: power-controller@250 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi3: power-controller@258 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_uart_n: power-controller@268 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_n"; + power-domains = <&ps_uart_p>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@278 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@280 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@288 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@290 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@298 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@2a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_uart7: power-controller@2a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_uart_p>; + }; + + ps_uart8: power-controller@2b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_uart_p>; + }; + + ps_mca0: power-controller@2b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca1: power-controller@2c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca2: power-controller@2c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca3: power-controller@2d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca4: power-controller@2d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca5: power-controller@2e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_dpa0: power-controller@2e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa1: power-controller@2f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + power-domains = <&ps_audio_p>; + }; + + ps_mcc: power-controller@2f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory controller */ + }; + + ps_spi4: power-controller@260 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_dcs0: power-controller@300 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@310 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@308 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@318 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_smx: power-controller@340 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_apcie: power-controller@348 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie"; + power-domains = <&ps_imx>, <&ps_pcie_ref>; + }; + + ps_rmx: power-controller@350 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rmx"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_mmx: power-controller@358 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mmx"; + /* Apple Fabric, media stuff: this can power down */ + }; + + ps_disp0_fe: power-controller@360 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rmx>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_dispext_fe: power-controller@368 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_fe"; + power-domains = <&ps_rmx>; + }; + + ps_dispext_cpu0: power-controller@378 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_cpu0"; + power-domains = <&ps_dispext_fe>; + }; + + ps_jpg: power-controller@3c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_mmx>; + }; + + ps_msr: power-controller@3c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_mmx>; + }; + + ps_msr_ase_core: power-controller@3d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr_ase_core"; + }; + + ps_pmp: power-controller@3d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@3e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_apcie_gp: power-controller@3e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_gp"; + power-domains = <&ps_apcie>; + }; + + ps_ans2: power-controller@3f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + /* + * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this + * doesn't make much sense since ANS2 uses APCIE_ST. + */ + power-domains = <&ps_apcie_st>; + }; + + ps_gfx: power-controller@3f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_dcs4: power-controller@320 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@330 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@328 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs7: power-controller@338 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dispdfr_fe: power-controller@3a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_fe"; + power-domains = <&ps_rmx>; + }; + + ps_dispdfr_be: power-controller@3b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_be"; + power-domains = <&ps_dispdfr_fe>; + }; + + ps_mipi_dsi: power-controller@3b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_dispdfr_be>; + }; + + ps_isp_sys: power-controller@400 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rmx>; + }; + + ps_venc_sys: power-controller@408 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_mmx>; + }; + + ps_avd_sys: power-controller@410 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + power-domains = <&ps_mmx>; + }; + + ps_apcie_st: power-controller@418 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_st"; + power-domains = <&ps_apcie>; + }; + + ps_ane_sys: power-controller@470 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys"; + }; + + ps_atc0_common: power-controller@420 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_common"; + }; + + ps_atc0_pcie: power-controller@428 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_pcie"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@430 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio_pcie: power-controller@438 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x438 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_pcie"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@440 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_usb"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc1_common: power-controller@448 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x448 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_common"; + }; + + ps_atc1_pcie: power-controller@450 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_pcie"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@458 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x458 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio_pcie: power-controller@460 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_pcie"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@468 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x468 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_usb"; + power-domains = <&ps_atc1_cio>; + }; + + ps_sep: power-controller@c00 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_dma: power-controller@8000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; + }; + + ps_venc_me1: power-controller@8020 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; + }; + + ps_ane_sys_cpu: power-controller@c000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys_cpu"; + power-domains = <&ps_ane_sys>; + }; + + ps_disp0_cpu0: power-controller@10018 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x10018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_cpu0"; + power-domains = <&ps_disp0_fe>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; +}; + +&pmgr_mini { + ps_debug: power-controller@58 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi0: power-controller@60 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi0"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@70 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_gpio: power-controller@80 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_gpio"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_fabric: power-controller@a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_sram: power-controller@b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_debug_usb: power-controller@b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_usb"; + apple,always-on; /* Core AON device */ + power-domains = <&ps_debug>; + }; + + ps_debug_auth: power-controller@c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_auth"; + apple,always-on; /* Core AON device */ + power-domains = <&ps_debug>; + }; + + ps_nub_spmi1: power-controller@68 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi1"; + apple,always-on; /* Core AON device */ + }; + + ps_msg: power-controller@78 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msg"; + }; + + ps_atc0_usb_aon: power-controller@88 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb_aon"; + }; + + ps_atc1_usb_aon: power-controller@90 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb_aon"; + }; + + ps_atc0_usb: power-controller@98 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb"; + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb"; + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index c62d9082c6a35..1055a38ed299e 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -121,6 +121,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c0>; }; i2c1: i2c@235014000 { @@ -133,6 +134,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c1>; }; i2c2: i2c@235018000 { @@ -146,6 +148,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; status = "disabled"; /* not used in all devices */ + power-domains = <&ps_i2c2>; }; i2c3: i2c@23501c000 { @@ -158,6 +161,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c3>; }; i2c4: i2c@235020000 { @@ -170,6 +174,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c4>; status = "disabled"; /* only used in J293 */ }; @@ -185,6 +190,7 @@ */ clocks = <&clk24>, <&clk24>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -193,11 +199,20 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x2 0x3b100000 0x0 0x8000>; + power-domains = <&ps_aic>; + }; + + pmgr: power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0 0x14000>; }; pinctrl_ap: pinctrl@23c100000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3c100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -247,6 +262,13 @@ }; }; + pmgr_mini: power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0 0x4000>; + }; + pinctrl_aop: pinctrl@24a820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x4a820000 0x0 0x4000>; @@ -271,6 +293,7 @@ pinctrl_nub: pinctrl@23d1f0000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3d1f0000 0x0 0x4000>; + power-domains = <&ps_nub_gpio>; gpio-controller; #gpio-cells = <2>; @@ -316,6 +339,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0_dart_1: dart@682008000 { @@ -324,6 +348,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0_dart_2: dart@683008000 { @@ -332,6 +357,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0: pcie@690000000 { @@ -366,6 +392,7 @@ ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + power-domains = <&ps_apcie_gp>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; @@ -431,3 +458,5 @@ }; }; }; + +#include "t8103-pmgr.dtsi" -- GitLab From 2ba22cfeda44566aeb333f519ade0633e405aade Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 20 Sep 2021 02:28:20 +0900 Subject: [PATCH 344/965] arm64: dts: apple: t8103: Add UART2 This UART is connected to the debug port of the WLAN module. It is mostly useless, but makes for a good test case for runtime-pm without having to unbind the console from the main system UART. Reviewed-by: Mark Kettenis Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 5 +++++ arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 876278fe0afe6..e11d5def94b4d 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -12,6 +12,7 @@ / { aliases { serial0 = &serial0; + serial2 = &serial2; }; chosen { @@ -39,6 +40,10 @@ status = "okay"; }; +&serial2 { + status = "okay"; +}; + &i2c0 { hpm0: usb-pd@38 { compatible = "apple,cd321x"; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 1055a38ed299e..15ee8c8c5fa09 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -194,6 +194,18 @@ status = "disabled"; }; + serial2: serial@235208000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35208000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk24>, <&clk24>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart2>; + status = "disabled"; + }; + aic: interrupt-controller@23b100000 { compatible = "apple,t8103-aic", "apple,aic"; #interrupt-cells = <3>; -- GitLab From bf2c05b619ffc0bccf60d2108bfadc880ee7f5c7 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Mon, 6 Dec 2021 19:38:16 +0100 Subject: [PATCH 345/965] arm64: dts: apple: t8103: Expose PCI node for the WiFi MAC address Expose the PCI node corresponding to the WiFi device and give it a 'local-mac-address' property. The bootloader will update it (m1n1 already has the required feature). Signed-off-by: Mark Kettenis Acked-by: Marc Zyngier Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index e11d5def94b4d..fe2ae40fa9ddf 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -13,6 +13,7 @@ aliases { serial0 = &serial0; serial2 = &serial2; + wifi0 = &wifi0; }; chosen { @@ -69,4 +70,9 @@ */ &port00 { bus-range = <1 1>; + wifi0: network@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 00 00 00 00 00]; + }; }; -- GitLab From c3e4ea557ddb0a7fa431564bb1bb023ffbf823f4 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:53 +0530 Subject: [PATCH 346/965] arm64: dts: ti: k3-am65-mcu: Add Support for MCAN Add Support for two MCAN controllers present on the am65x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-2-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index c93ff1520a0e2..8d592bf41d6f1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -159,6 +159,36 @@ }; }; + m_can0: mcan@40528000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40528000 0x0 0x400>, + <0x0 0x40500000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + m_can1: mcan@40568000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40568000 0x0 0x400>, + <0x0 0x40540000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + fss: fss@47000000 { compatible = "simple-bus"; #address-cells = <2>; -- GitLab From f533bb82def8b923668df97c36c1f8fe6a3a8f1f Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:54 +0530 Subject: [PATCH 347/965] arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes AM654 base board and iot platforms do not have mcan instances pinned out. Therefore, disable all the mcan instances. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-3-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 65da226847f45..1e0112b90d9fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -646,6 +646,14 @@ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; +&m_can0 { + status = "disabled"; +}; + +&m_can1 { + status = "disabled"; +}; + &pcie1_ep { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index cfbcebfa37c1d..9043f91c9bec7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -416,6 +416,14 @@ status = "disabled"; }; +&m_can0 { + status = "disabled"; +}; + +&m_can1 { + status = "disabled"; +}; + &mailbox0_cluster0 { interrupts = <436>; -- GitLab From 4688a4fcb7a20d347a52c1f2dc9bc6fad9df1174 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:55 +0530 Subject: [PATCH 348/965] arm64: dts: ti: k3-j721e: Add support for MCAN nodes Add support for 14 MCAN controllers in main domain and 2 MCAN controllers present in mcu domain. All the MCAN controllers support classic CAN messages as well as CAN_FD messages. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 196 ++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 28 +++ 2 files changed, 224 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e85c89eebfa31..599861259a30f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1940,4 +1940,200 @@ bus_freq = <1000000>; }; }; + + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index d2dceda72fe97..b4972dfb7da81 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -390,4 +390,32 @@ ti,loczrama = <1>; }; }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; -- GitLab From 87d60c4663b6eb964cca6a03adfcf8976f374559 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:56 +0530 Subject: [PATCH 349/965] arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes Add four MCAN nodes present on the common processor board and set a maximum data rate of 5 Mbps. Disable all other nodes as they are not brought out on the common processor board. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-5-a-govindraju@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index dc2bc67f9f483..2d7596911b270 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -112,6 +112,42 @@ "cpb-codec-scki", "cpb-codec-scki-48000", "cpb-codec-scki-44100"; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_gpio_pins_default>; + standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -207,6 +243,26 @@ J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ + J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ + >; + }; + + main_mcan2_pins_default: main-mcan2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ + J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ + >; + }; + + main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ + >; + }; }; &wkup_pmx0 { @@ -252,6 +308,33 @@ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ + >; + }; }; &wkup_uart0 { @@ -773,3 +856,75 @@ &icssg1_mdio { status = "disabled"; }; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan1 { + status = "disabled"; +}; + +&main_mcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_pins_default>; + phys = <&transceiver4>; +}; + +&main_mcan3 { + status = "disabled"; +}; + +&main_mcan4 { + status = "disabled"; +}; + +&main_mcan5 { + status = "disabled"; +}; + +&main_mcan6 { + status = "disabled"; +}; + +&main_mcan7 { + status = "disabled"; +}; + +&main_mcan8 { + status = "disabled"; +}; + +&main_mcan9 { + status = "disabled"; +}; + +&main_mcan10 { + status = "disabled"; +}; + +&main_mcan11 { + status = "disabled"; +}; + +&main_mcan12 { + status = "disabled"; +}; + +&main_mcan13 { + status = "disabled"; +}; -- GitLab From 9c4441ad3da1fad75aabfd68e90558c20a2818d2 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:57 +0530 Subject: [PATCH 350/965] arm64: dts: ti: k3-am64-main: Add support for MCAN Add Support for two MCAN controllers present on the am64x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-6-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e16d2ccdd8189..012011dc619a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1261,4 +1261,32 @@ bus_freq = <1000000>; }; }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; -- GitLab From 2f474da98caf9a75d7777c5465d281240c706bc6 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:58 +0530 Subject: [PATCH 351/965] arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK AM642 EVM has two CAN connecters brought out from the two MCAN instances in the main domain through transceivers. Add device tree nodes for transceivers and set the required properties in the mcan device tree nodes, in EVM device tree file. On AM642 SK there are no connectors brought out for CAN. Therefore, disable the mcan device tree nodes in the SK device tree file. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-7-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 40 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 +++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 6726c4c7c28c9..e94ae178b1ae3 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -184,6 +184,20 @@ }; }; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -294,6 +308,20 @@ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ + >; + }; }; &main_uart0 { @@ -638,3 +666,15 @@ &icssg1_mdio { status = "disabled"; }; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 6b04745147be4..a9785bec12dfa 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -525,3 +525,11 @@ &icssg1_mdio { status = "disabled"; }; + +&main_mcan0 { + status = "disabled"; +}; + +&main_mcan1 { + status = "disabled"; +}; -- GitLab From 111659c2a570ab1d62615040249dd37f39034d68 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 7 Dec 2021 14:34:58 +0900 Subject: [PATCH 352/965] arm64: dts: apple: t8103: Remove PCIe max-link-speed properties The driver doesn't support these, they shouldn't be in the SoC include anyway, and we're now configuring this in the bootloader instead. This also solves the j274 1G/10G Ethernet variant discrepancy, since that will now be configured properly based on the dynamic ADT property. Acked-by: Marc Zyngier Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 15ee8c8c5fa09..8d1628e0b0c70 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -412,7 +412,6 @@ device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 152 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -432,7 +431,6 @@ device_type = "pci"; reg = <0x800 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 153 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -452,7 +450,6 @@ device_type = "pci"; reg = <0x1000 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 33 0>; - max-link-speed = <1>; #address-cells = <3>; #size-cells = <2>; -- GitLab From 82ce79391d0ec25ec8aaae3c0617b71048ff0836 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 4 Nov 2021 22:40:25 +0000 Subject: [PATCH 353/965] arm64: dts: renesas: Fix thermal bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding node names for the thermal zones are not successfully validated by the dt-schemas. Fix the validation by changing from sensor-thermalN or thermal-sensor-N to sensorN-thermal. Provide node labels of the form sensorN_thermal to ensure consistency with the other platform implementations. Signed-off-by: Kieran Bingham Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20211104224033.3997504-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 +++++----- 9 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 09976adf99c20..eda6a840371a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2788,7 +2788,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2803,7 +2803,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2818,7 +2818,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c504f50283806..44f79fbd75dc9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2633,7 +2633,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2648,7 +2648,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2663,7 +2663,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e4dd6ccc8b10c..e6d8610730a84 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2908,7 +2908,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2923,7 +2923,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2938,7 +2938,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 2353d3034bb5e..9265a5702792c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3379,7 +3379,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -3394,7 +3394,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -3409,7 +3409,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0f2424f125465..26f7103d11da5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2976,7 +2976,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2991,7 +2991,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -3006,7 +3006,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7468a2df1808c..ac9b587f6fc51 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2734,7 +2734,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2749,7 +2749,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2764,7 +2764,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0c44de8669963..f898aad72b9d2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2788,7 +2788,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2803,7 +2803,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2818,7 +2818,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 2a4513e7e2b5e..347c068ff2c55 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1581,7 +1581,7 @@ }; thermal-zones { - thermal-sensor-1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -1600,7 +1600,7 @@ }; }; - thermal-sensor-2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 6e83bcb0287cb..8ac1a31e4146d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2640,7 +2640,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2654,7 +2654,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2668,7 +2668,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; @@ -2682,7 +2682,7 @@ }; }; - sensor_thermal4: sensor-thermal4 { + sensor4_thermal: sensor4-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 3>; @@ -2696,7 +2696,7 @@ }; }; - sensor_thermal5: sensor-thermal5 { + sensor5_thermal: sensor5-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 4>; -- GitLab From d01986bec3887a3dbf61cbd821979f91cf0bb2dc Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:55 +0900 Subject: [PATCH 354/965] dt-bindings: arm: renesas: Document Renesas Spider boards Add device tree bindings documentation for Renesas R-Car S4-8 Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 36197f53b3109..6a9350ee690b0 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -317,6 +317,14 @@ properties: - description: R-Car S4-8 (R8A779F0) items: + - enum: + - renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S) + - const: renesas,r8a779f0 + + - items: + - enum: + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) + - const: renesas,spider-cpu - const: renesas,r8a779f0 - description: R-Car H3e (R8A779M0) -- GitLab From 500daa0e6be292edcf635ba6b090b89da80e90a8 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:56 +0900 Subject: [PATCH 355/965] dt-bindings: power: Add r8a779f0 SYSC power domain definitions Add power domain indices for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/power/r8a779f0-sysc.h | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/power/r8a779f0-sysc.h diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h new file mode 100644 index 0000000000000..0ec8ad727ed9a --- /dev/null +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779F0_PD_A1E0D0C0 0 +#define R8A779F0_PD_A1E0D0C1 1 +#define R8A779F0_PD_A1E0D1C0 2 +#define R8A779F0_PD_A1E0D1C1 3 +#define R8A779F0_PD_A1E1D0C0 4 +#define R8A779F0_PD_A1E1D0C1 5 +#define R8A779F0_PD_A1E1D1C0 6 +#define R8A779F0_PD_A1E1D1C1 7 +#define R8A779F0_PD_A2E0D0 16 +#define R8A779F0_PD_A2E0D1 17 +#define R8A779F0_PD_A2E1D0 18 +#define R8A779F0_PD_A2E1D1 19 +#define R8A779F0_PD_A3E0 20 +#define R8A779F0_PD_A3E1 21 + +/* Always-on power area */ +#define R8A779F0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/ -- GitLab From 81c1655823237eaec74b2c175ae8e13adfccdaf7 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:57 +0900 Subject: [PATCH 356/965] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 include/dt-bindings/clock/r8a779f0-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h new file mode 100644 index 0000000000000..f2ae1c6a82dd6 --- /dev/null +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ + +#include + +/* r8a779f0 CPG Core Clocks */ + +#define R8A779F0_CLK_ZX 0 +#define R8A779F0_CLK_ZS 1 +#define R8A779F0_CLK_ZT 2 +#define R8A779F0_CLK_ZTR 3 +#define R8A779F0_CLK_S0D2 4 +#define R8A779F0_CLK_S0D3 5 +#define R8A779F0_CLK_S0D4 6 +#define R8A779F0_CLK_S0D2_MM 7 +#define R8A779F0_CLK_S0D3_MM 8 +#define R8A779F0_CLK_S0D4_MM 9 +#define R8A779F0_CLK_S0D2_RT 10 +#define R8A779F0_CLK_S0D3_RT 11 +#define R8A779F0_CLK_S0D4_RT 12 +#define R8A779F0_CLK_S0D6_RT 13 +#define R8A779F0_CLK_S0D3_PER 14 +#define R8A779F0_CLK_S0D6_PER 15 +#define R8A779F0_CLK_S0D12_PER 16 +#define R8A779F0_CLK_S0D24_PER 17 +#define R8A779F0_CLK_S0D2_HSC 18 +#define R8A779F0_CLK_S0D3_HSC 19 +#define R8A779F0_CLK_S0D4_HSC 20 +#define R8A779F0_CLK_S0D6_HSC 21 +#define R8A779F0_CLK_S0D12_HSC 22 +#define R8A779F0_CLK_S0D2_CC 23 +#define R8A779F0_CLK_CL 24 +#define R8A779F0_CLK_CL16M 25 +#define R8A779F0_CLK_CL16M_MM 26 +#define R8A779F0_CLK_CL16M_RT 27 +#define R8A779F0_CLK_CL16M_PER 28 +#define R8A779F0_CLK_CL16M_HSC 29 +#define R8A779F0_CLK_Z0 30 +#define R8A779F0_CLK_Z1 31 +#define R8A779F0_CLK_ZB3 32 +#define R8A779F0_CLK_ZB3D2 33 +#define R8A779F0_CLK_ZB3D4 34 +#define R8A779F0_CLK_SD0H 35 +#define R8A779F0_CLK_SD0 36 +#define R8A779F0_CLK_RPC 37 +#define R8A779F0_CLK_RPCD2 38 +#define R8A779F0_CLK_MSO 39 +#define R8A779F0_CLK_SASYNCRT 40 +#define R8A779F0_CLK_SASYNCPERD1 41 +#define R8A779F0_CLK_SASYNCPERD2 42 +#define R8A779F0_CLK_SASYNCPERD4 43 +#define R8A779F0_CLK_DBGSOC_HSC 44 +#define R8A779F0_CLK_RSW2 45 +#define R8A779F0_CLK_OSC 46 +#define R8A779F0_CLK_ZR 47 +#define R8A779F0_CLK_CPEX 48 +#define R8A779F0_CLK_CBFUSA 49 +#define R8A779F0_CLK_R 50 + +#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ -- GitLab From e62906d6315f652b80640df0f980086462a4953b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:59 +0900 Subject: [PATCH 357/965] soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 SYSC driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-6-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 4 + drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a779a0-sysc.c | 380 +-------------------------- drivers/soc/renesas/rcar-gen4-sysc.c | 373 ++++++++++++++++++++++++++ drivers/soc/renesas/rcar-gen4-sysc.h | 42 +++ 5 files changed, 423 insertions(+), 377 deletions(-) create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.c create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index ce16ef5c939c4..2b09d6cf0d660 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -297,6 +297,9 @@ config RST_RCAR config SYSC_RCAR bool "System Controller support for R-Car" if COMPILE_TEST +config SYSC_RCAR_GEN4 + bool "System Controller support for R-Car Gen4" if COMPILE_TEST + config SYSC_R8A77995 bool "System Controller support for R-Car D3" if COMPILE_TEST select SYSC_RCAR @@ -351,6 +354,7 @@ config SYSC_R8A77970 config SYSC_R8A779A0 bool "System Controller support for R-Car V3U" if COMPILE_TEST + select SYSC_RCAR_GEN4 config SYSC_RMOBILE bool "System Controller support for R-Mobile" if COMPILE_TEST diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 9b29bed2a5979..db90f3b060072 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -32,4 +32,5 @@ endif # Family obj-$(CONFIG_RST_RCAR) += rcar-rst.o obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o +obj-$(CONFIG_SYSC_RCAR_GEN4) += rcar-gen4-sysc.o obj-$(CONFIG_SYSC_RMOBILE) += rmobile-sysc.o diff --git a/drivers/soc/renesas/r8a779a0-sysc.c b/drivers/soc/renesas/r8a779a0-sysc.c index 7410b9fa9846f..fdfc857df3349 100644 --- a/drivers/soc/renesas/r8a779a0-sysc.c +++ b/drivers/soc/renesas/r8a779a0-sysc.c @@ -21,35 +21,9 @@ #include -/* - * Power Domain flags - */ -#define PD_CPU BIT(0) /* Area contains main CPU core */ -#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ -#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ - -#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR */ -#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */ - -/* - * Description of a Power Area - */ -struct r8a779a0_sysc_area { - const char *name; - u8 pdr; /* PDRn */ - int parent; /* -1 if none */ - unsigned int flags; /* See PD_* */ -}; - -/* - * SoC-specific Power Area Description - */ -struct r8a779a0_sysc_info { - const struct r8a779a0_sysc_area *areas; - unsigned int num_areas; -}; +#include "rcar-gen4-sysc.h" -static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = { +static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = { { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, { "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU }, { "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU }, @@ -96,355 +70,7 @@ static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = { { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 }, }; -static const struct r8a779a0_sysc_info r8a779a0_sysc_info __initconst = { +const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = { .areas = r8a779a0_areas, .num_areas = ARRAY_SIZE(r8a779a0_areas), }; - -/* SYSC Common */ -#define SYSCSR 0x000 /* SYSC Status Register */ -#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */ -#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */ -#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */ -#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */ -#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */ - -/* Power Domain Registers */ -#define PDRSR(n) (0x1000 + ((n) * 0x40)) -#define PDRONCR(n) (0x1004 + ((n) * 0x40)) -#define PDROFFCR(n) (0x1008 + ((n) * 0x40)) -#define PDRESR(n) (0x100C + ((n) * 0x40)) - -/* PWRON/PWROFF */ -#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */ - -/* PDRESR */ -#define PDRESR_ERR BIT(0) - -/* PDRSR */ -#define PDRSR_OFF BIT(0) /* Power-OFF state */ -#define PDRSR_ON BIT(4) /* Power-ON state */ -#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */ -#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */ - -#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */ - -#define SYSCSR_TIMEOUT 10000 -#define SYSCSR_DELAY_US 10 - -#define PDRESR_RETRIES 1000 -#define PDRESR_DELAY_US 10 - -#define SYSCISR_TIMEOUT 10000 -#define SYSCISR_DELAY_US 10 - -#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32) - -static void __iomem *r8a779a0_sysc_base; -static DEFINE_SPINLOCK(r8a779a0_sysc_lock); /* SMP CPUs + I/O devices */ - -static int r8a779a0_sysc_pwr_on_off(u8 pdr, bool on) -{ - unsigned int reg_offs; - u32 val; - int ret; - - if (on) - reg_offs = PDRONCR(pdr); - else - reg_offs = PDROFFCR(pdr); - - /* Wait until SYSC is ready to accept a power request */ - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCSR, val, - (val & SYSCSR_BUSY) == SYSCSR_BUSY, - SYSCSR_DELAY_US, SYSCSR_TIMEOUT); - if (ret < 0) - return -EAGAIN; - - /* Submit power shutoff or power resume request */ - iowrite32(PWRON_PWROFF, r8a779a0_sysc_base + reg_offs); - - return 0; -} - -static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) -{ - u32 val; - int ret; - - iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx)); - - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), - val, !(val & isr_mask), - SYSCISR_DELAY_US, SYSCISR_TIMEOUT); - if (ret < 0) { - pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__); - return -EIO; - } - - return 0; -} - -static int r8a779a0_sysc_power(u8 pdr, bool on) -{ - unsigned int isr_mask; - unsigned int reg_idx, bit_idx; - unsigned int status; - unsigned long flags; - int ret = 0; - u32 val; - int k; - - spin_lock_irqsave(&r8a779a0_sysc_lock, flags); - - reg_idx = pdr / NUM_DOMAINS_EACH_REG; - bit_idx = pdr % NUM_DOMAINS_EACH_REG; - - isr_mask = BIT(bit_idx); - - /* - * The interrupt source needs to be enabled, but masked, to prevent the - * CPU from receiving it. - */ - iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask, - r8a779a0_sysc_base + SYSCIER(reg_idx)); - iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask, - r8a779a0_sysc_base + SYSCIMR(reg_idx)); - - ret = clear_irq_flags(reg_idx, isr_mask); - if (ret) - goto out; - - /* Submit power shutoff or resume request until it was accepted */ - for (k = 0; k < PDRESR_RETRIES; k++) { - ret = r8a779a0_sysc_pwr_on_off(pdr, on); - if (ret) - goto out; - - status = ioread32(r8a779a0_sysc_base + PDRESR(pdr)); - if (!(status & PDRESR_ERR)) - break; - - udelay(PDRESR_DELAY_US); - } - - if (k == PDRESR_RETRIES) { - ret = -EIO; - goto out; - } - - /* Wait until the power shutoff or resume request has completed * */ - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), - val, (val & isr_mask), - SYSCISR_DELAY_US, SYSCISR_TIMEOUT); - if (ret < 0) { - ret = -EIO; - goto out; - } - - /* Clear interrupt flags */ - ret = clear_irq_flags(reg_idx, isr_mask); - if (ret) - goto out; - - out: - spin_unlock_irqrestore(&r8a779a0_sysc_lock, flags); - - pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", - pdr, ioread32(r8a779a0_sysc_base + SYSCISCR(reg_idx)), ret); - return ret; -} - -static bool r8a779a0_sysc_power_is_off(u8 pdr) -{ - unsigned int st; - - st = ioread32(r8a779a0_sysc_base + PDRSR(pdr)); - - if (st & PDRSR_OFF) - return true; - - return false; -} - -struct r8a779a0_sysc_pd { - struct generic_pm_domain genpd; - u8 pdr; - unsigned int flags; - char name[]; -}; - -static inline struct r8a779a0_sysc_pd *to_r8a779a0_pd(struct generic_pm_domain *d) -{ - return container_of(d, struct r8a779a0_sysc_pd, genpd); -} - -static int r8a779a0_sysc_pd_power_off(struct generic_pm_domain *genpd) -{ - struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd); - - pr_debug("%s: %s\n", __func__, genpd->name); - return r8a779a0_sysc_power(pd->pdr, false); -} - -static int r8a779a0_sysc_pd_power_on(struct generic_pm_domain *genpd) -{ - struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd); - - pr_debug("%s: %s\n", __func__, genpd->name); - return r8a779a0_sysc_power(pd->pdr, true); -} - -static int __init r8a779a0_sysc_pd_setup(struct r8a779a0_sysc_pd *pd) -{ - struct generic_pm_domain *genpd = &pd->genpd; - const char *name = pd->genpd.name; - int error; - - if (pd->flags & PD_CPU) { - /* - * This domain contains a CPU core and therefore it should - * only be turned off if the CPU is not in use. - */ - pr_debug("PM domain %s contains %s\n", name, "CPU"); - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } else if (pd->flags & PD_SCU) { - /* - * This domain contains an SCU and cache-controller, and - * therefore it should only be turned off if the CPU cores are - * not in use. - */ - pr_debug("PM domain %s contains %s\n", name, "SCU"); - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } else if (pd->flags & PD_NO_CR) { - /* - * This domain cannot be turned off. - */ - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } - - if (!(pd->flags & (PD_CPU | PD_SCU))) { - /* Enable Clock Domain for I/O devices */ - genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; - genpd->attach_dev = cpg_mssr_attach_dev; - genpd->detach_dev = cpg_mssr_detach_dev; - } - - genpd->power_off = r8a779a0_sysc_pd_power_off; - genpd->power_on = r8a779a0_sysc_pd_power_on; - - if (pd->flags & (PD_CPU | PD_NO_CR)) { - /* Skip CPUs (handled by SMP code) and areas without control */ - pr_debug("%s: Not touching %s\n", __func__, genpd->name); - goto finalize; - } - - if (!r8a779a0_sysc_power_is_off(pd->pdr)) { - pr_debug("%s: %s is already powered\n", __func__, genpd->name); - goto finalize; - } - - r8a779a0_sysc_power(pd->pdr, true); - -finalize: - error = pm_genpd_init(genpd, &simple_qos_governor, false); - if (error) - pr_err("Failed to init PM domain %s: %d\n", name, error); - - return error; -} - -static const struct of_device_id r8a779a0_sysc_matches[] __initconst = { - { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info }, - { /* sentinel */ } -}; - -struct r8a779a0_pm_domains { - struct genpd_onecell_data onecell_data; - struct generic_pm_domain *domains[R8A779A0_PD_ALWAYS_ON + 1]; -}; - -static struct genpd_onecell_data *r8a779a0_sysc_onecell_data; - -static int __init r8a779a0_sysc_pd_init(void) -{ - const struct r8a779a0_sysc_info *info; - const struct of_device_id *match; - struct r8a779a0_pm_domains *domains; - struct device_node *np; - void __iomem *base; - unsigned int i; - int error; - - np = of_find_matching_node_and_match(NULL, r8a779a0_sysc_matches, &match); - if (!np) - return -ENODEV; - - info = match->data; - - base = of_iomap(np, 0); - if (!base) { - pr_warn("%pOF: Cannot map regs\n", np); - error = -ENOMEM; - goto out_put; - } - - r8a779a0_sysc_base = base; - - domains = kzalloc(sizeof(*domains), GFP_KERNEL); - if (!domains) { - error = -ENOMEM; - goto out_put; - } - - domains->onecell_data.domains = domains->domains; - domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); - r8a779a0_sysc_onecell_data = &domains->onecell_data; - - for (i = 0; i < info->num_areas; i++) { - const struct r8a779a0_sysc_area *area = &info->areas[i]; - struct r8a779a0_sysc_pd *pd; - size_t n; - - if (!area->name) { - /* Skip NULLified area */ - continue; - } - - n = strlen(area->name) + 1; - pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); - if (!pd) { - error = -ENOMEM; - goto out_put; - } - - memcpy(pd->name, area->name, n); - pd->genpd.name = pd->name; - pd->pdr = area->pdr; - pd->flags = area->flags; - - error = r8a779a0_sysc_pd_setup(pd); - if (error) - goto out_put; - - domains->domains[area->pdr] = &pd->genpd; - - if (area->parent < 0) - continue; - - error = pm_genpd_add_subdomain(domains->domains[area->parent], - &pd->genpd); - if (error) { - pr_warn("Failed to add PM subdomain %s to parent %u\n", - area->name, area->parent); - goto out_put; - } - } - - error = of_genpd_add_provider_onecell(np, &domains->onecell_data); - -out_put: - of_node_put(np); - return error; -} -early_initcall(r8a779a0_sysc_pd_init); diff --git a/drivers/soc/renesas/rcar-gen4-sysc.c b/drivers/soc/renesas/rcar-gen4-sysc.c new file mode 100644 index 0000000000000..d9a0929f5f1d0 --- /dev/null +++ b/drivers/soc/renesas/rcar-gen4-sysc.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen4 SYSC Power management support + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rcar-gen4-sysc.h" + +/* SYSC Common */ +#define SYSCSR 0x000 /* SYSC Status Register */ +#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */ +#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */ +#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */ +#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */ +#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */ + +/* Power Domain Registers */ +#define PDRSR(n) (0x1000 + ((n) * 0x40)) +#define PDRONCR(n) (0x1004 + ((n) * 0x40)) +#define PDROFFCR(n) (0x1008 + ((n) * 0x40)) +#define PDRESR(n) (0x100C + ((n) * 0x40)) + +/* PWRON/PWROFF */ +#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */ + +/* PDRESR */ +#define PDRESR_ERR BIT(0) + +/* PDRSR */ +#define PDRSR_OFF BIT(0) /* Power-OFF state */ +#define PDRSR_ON BIT(4) /* Power-ON state */ +#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */ +#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */ + +#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */ + +#define SYSCSR_TIMEOUT 10000 +#define SYSCSR_DELAY_US 10 + +#define PDRESR_RETRIES 1000 +#define PDRESR_DELAY_US 10 + +#define SYSCISR_TIMEOUT 10000 +#define SYSCISR_DELAY_US 10 + +#define RCAR_GEN4_PD_ALWAYS_ON 64 +#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32) + +static void __iomem *rcar_gen4_sysc_base; +static DEFINE_SPINLOCK(rcar_gen4_sysc_lock); /* SMP CPUs + I/O devices */ + +static int rcar_gen4_sysc_pwr_on_off(u8 pdr, bool on) +{ + unsigned int reg_offs; + u32 val; + int ret; + + if (on) + reg_offs = PDRONCR(pdr); + else + reg_offs = PDROFFCR(pdr); + + /* Wait until SYSC is ready to accept a power request */ + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCSR, val, + (val & SYSCSR_BUSY) == SYSCSR_BUSY, + SYSCSR_DELAY_US, SYSCSR_TIMEOUT); + if (ret < 0) + return -EAGAIN; + + /* Submit power shutoff or power resume request */ + iowrite32(PWRON_PWROFF, rcar_gen4_sysc_base + reg_offs); + + return 0; +} + +static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) +{ + u32 val; + int ret; + + iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx)); + + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), + val, !(val & isr_mask), + SYSCISR_DELAY_US, SYSCISR_TIMEOUT); + if (ret < 0) { + pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__); + return -EIO; + } + + return 0; +} + +static int rcar_gen4_sysc_power(u8 pdr, bool on) +{ + unsigned int isr_mask; + unsigned int reg_idx, bit_idx; + unsigned int status; + unsigned long flags; + int ret = 0; + u32 val; + int k; + + spin_lock_irqsave(&rcar_gen4_sysc_lock, flags); + + reg_idx = pdr / NUM_DOMAINS_EACH_REG; + bit_idx = pdr % NUM_DOMAINS_EACH_REG; + + isr_mask = BIT(bit_idx); + + /* + * The interrupt source needs to be enabled, but masked, to prevent the + * CPU from receiving it. + */ + iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask, + rcar_gen4_sysc_base + SYSCIER(reg_idx)); + iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask, + rcar_gen4_sysc_base + SYSCIMR(reg_idx)); + + ret = clear_irq_flags(reg_idx, isr_mask); + if (ret) + goto out; + + /* Submit power shutoff or resume request until it was accepted */ + for (k = 0; k < PDRESR_RETRIES; k++) { + ret = rcar_gen4_sysc_pwr_on_off(pdr, on); + if (ret) + goto out; + + status = ioread32(rcar_gen4_sysc_base + PDRESR(pdr)); + if (!(status & PDRESR_ERR)) + break; + + udelay(PDRESR_DELAY_US); + } + + if (k == PDRESR_RETRIES) { + ret = -EIO; + goto out; + } + + /* Wait until the power shutoff or resume request has completed * */ + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), + val, (val & isr_mask), + SYSCISR_DELAY_US, SYSCISR_TIMEOUT); + if (ret < 0) { + ret = -EIO; + goto out; + } + + /* Clear interrupt flags */ + ret = clear_irq_flags(reg_idx, isr_mask); + if (ret) + goto out; + + out: + spin_unlock_irqrestore(&rcar_gen4_sysc_lock, flags); + + pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", + pdr, ioread32(rcar_gen4_sysc_base + SYSCISCR(reg_idx)), ret); + return ret; +} + +static bool rcar_gen4_sysc_power_is_off(u8 pdr) +{ + unsigned int st; + + st = ioread32(rcar_gen4_sysc_base + PDRSR(pdr)); + + if (st & PDRSR_OFF) + return true; + + return false; +} + +struct rcar_gen4_sysc_pd { + struct generic_pm_domain genpd; + u8 pdr; + unsigned int flags; + char name[]; +}; + +static inline struct rcar_gen4_sysc_pd *to_rcar_gen4_pd(struct generic_pm_domain *d) +{ + return container_of(d, struct rcar_gen4_sysc_pd, genpd); +} + +static int rcar_gen4_sysc_pd_power_off(struct generic_pm_domain *genpd) +{ + struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd); + + pr_debug("%s: %s\n", __func__, genpd->name); + return rcar_gen4_sysc_power(pd->pdr, false); +} + +static int rcar_gen4_sysc_pd_power_on(struct generic_pm_domain *genpd) +{ + struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd); + + pr_debug("%s: %s\n", __func__, genpd->name); + return rcar_gen4_sysc_power(pd->pdr, true); +} + +static int __init rcar_gen4_sysc_pd_setup(struct rcar_gen4_sysc_pd *pd) +{ + struct generic_pm_domain *genpd = &pd->genpd; + const char *name = pd->genpd.name; + int error; + + if (pd->flags & PD_CPU) { + /* + * This domain contains a CPU core and therefore it should + * only be turned off if the CPU is not in use. + */ + pr_debug("PM domain %s contains %s\n", name, "CPU"); + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } else if (pd->flags & PD_SCU) { + /* + * This domain contains an SCU and cache-controller, and + * therefore it should only be turned off if the CPU cores are + * not in use. + */ + pr_debug("PM domain %s contains %s\n", name, "SCU"); + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } else if (pd->flags & PD_NO_CR) { + /* + * This domain cannot be turned off. + */ + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } + + if (!(pd->flags & (PD_CPU | PD_SCU))) { + /* Enable Clock Domain for I/O devices */ + genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev = cpg_mssr_attach_dev; + genpd->detach_dev = cpg_mssr_detach_dev; + } + + genpd->power_off = rcar_gen4_sysc_pd_power_off; + genpd->power_on = rcar_gen4_sysc_pd_power_on; + + if (pd->flags & (PD_CPU | PD_NO_CR)) { + /* Skip CPUs (handled by SMP code) and areas without control */ + pr_debug("%s: Not touching %s\n", __func__, genpd->name); + goto finalize; + } + + if (!rcar_gen4_sysc_power_is_off(pd->pdr)) { + pr_debug("%s: %s is already powered\n", __func__, genpd->name); + goto finalize; + } + + rcar_gen4_sysc_power(pd->pdr, true); + +finalize: + error = pm_genpd_init(genpd, &simple_qos_governor, false); + if (error) + pr_err("Failed to init PM domain %s: %d\n", name, error); + + return error; +} + +static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = { +#ifdef CONFIG_SYSC_R8A779A0 + { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info }, +#endif + { /* sentinel */ } +}; + +struct rcar_gen4_pm_domains { + struct genpd_onecell_data onecell_data; + struct generic_pm_domain *domains[RCAR_GEN4_PD_ALWAYS_ON + 1]; +}; + +static struct genpd_onecell_data *rcar_gen4_sysc_onecell_data; + +static int __init rcar_gen4_sysc_pd_init(void) +{ + const struct rcar_gen4_sysc_info *info; + const struct of_device_id *match; + struct rcar_gen4_pm_domains *domains; + struct device_node *np; + void __iomem *base; + unsigned int i; + int error; + + np = of_find_matching_node_and_match(NULL, rcar_gen4_sysc_matches, &match); + if (!np) + return -ENODEV; + + info = match->data; + + base = of_iomap(np, 0); + if (!base) { + pr_warn("%pOF: Cannot map regs\n", np); + error = -ENOMEM; + goto out_put; + } + + rcar_gen4_sysc_base = base; + + domains = kzalloc(sizeof(*domains), GFP_KERNEL); + if (!domains) { + error = -ENOMEM; + goto out_put; + } + + domains->onecell_data.domains = domains->domains; + domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); + rcar_gen4_sysc_onecell_data = &domains->onecell_data; + + for (i = 0; i < info->num_areas; i++) { + const struct rcar_gen4_sysc_area *area = &info->areas[i]; + struct rcar_gen4_sysc_pd *pd; + size_t n; + + if (!area->name) { + /* Skip NULLified area */ + continue; + } + + n = strlen(area->name) + 1; + pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); + if (!pd) { + error = -ENOMEM; + goto out_put; + } + + memcpy(pd->name, area->name, n); + pd->genpd.name = pd->name; + pd->pdr = area->pdr; + pd->flags = area->flags; + + error = rcar_gen4_sysc_pd_setup(pd); + if (error) + goto out_put; + + domains->domains[area->pdr] = &pd->genpd; + + if (area->parent < 0) + continue; + + error = pm_genpd_add_subdomain(domains->domains[area->parent], + &pd->genpd); + if (error) { + pr_warn("Failed to add PM subdomain %s to parent %u\n", + area->name, area->parent); + goto out_put; + } + } + + error = of_genpd_add_provider_onecell(np, &domains->onecell_data); + +out_put: + of_node_put(np); + return error; +} +early_initcall(rcar_gen4_sysc_pd_init); diff --git a/drivers/soc/renesas/rcar-gen4-sysc.h b/drivers/soc/renesas/rcar-gen4-sysc.h new file mode 100644 index 0000000000000..3470a9e2f5c77 --- /dev/null +++ b/drivers/soc/renesas/rcar-gen4-sysc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R-Car Gen4 System Controller + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __SOC_RENESAS_RCAR_GEN4_SYSC_H__ +#define __SOC_RENESAS_RCAR_GEN4_SYSC_H__ + +#include + +/* + * Power Domain flags + */ +#define PD_CPU BIT(0) /* Area contains main CPU core */ +#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ +#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ + +#define PD_CPU_NOCR (PD_CPU | PD_NO_CR) /* CPU area lacks CR */ +#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */ + +/* + * Description of a Power Area + */ +struct rcar_gen4_sysc_area { + const char *name; + u8 pdr; /* PDRn */ + int parent; /* -1 if none */ + unsigned int flags; /* See PD_* */ +}; + +/* + * SoC-specific Power Area Description + */ +struct rcar_gen4_sysc_info { + const struct rcar_gen4_sysc_area *areas; + unsigned int num_areas; +}; + +extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info; + +#endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */ -- GitLab From 654d5fdb8923994f5e79a7f0faf722958d1d759f Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:00 +0900 Subject: [PATCH 358/965] soc: renesas: r8a779f0-sysc: Add r8a779f0 support Add support for R-Car S4-8 (R8A779F0) SoC power areas and register access. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-7-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 4 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a779f0-sysc.c | 47 ++++++++++++++++++++++++++++ drivers/soc/renesas/rcar-gen4-sysc.c | 3 ++ drivers/soc/renesas/rcar-gen4-sysc.h | 1 + 5 files changed, 56 insertions(+) create mode 100644 drivers/soc/renesas/r8a779f0-sysc.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 2b09d6cf0d660..59a4106a66e98 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -340,6 +340,10 @@ config SYSC_R8A77961 bool "System Controller support for R-Car M3-W+" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A779F0 + bool "System Controller support for R-Car S4-8" if COMPILE_TEST + select SYSC_RCAR_GEN4 + config SYSC_R8A7792 bool "System Controller support for R-Car V2H" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index db90f3b060072..deeb41f84f014 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o +obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif diff --git a/drivers/soc/renesas/r8a779f0-sysc.c b/drivers/soc/renesas/r8a779f0-sysc.c new file mode 100644 index 0000000000000..5602aa6bd7ed1 --- /dev/null +++ b/drivers/soc/renesas/r8a779f0-sysc.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car S4-8 System Controller + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "rcar-gen4-sysc.h" + +static struct rcar_gen4_sysc_area r8a779f0_areas[] __initdata = { + { "always-on", R8A779F0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "a3e0", R8A779F0_PD_A3E0, R8A779F0_PD_ALWAYS_ON, PD_SCU }, + { "a3e1", R8A779F0_PD_A3E1, R8A779F0_PD_ALWAYS_ON, PD_SCU }, + { "a2e0d0", R8A779F0_PD_A2E0D0, R8A779F0_PD_A3E0, PD_SCU }, + { "a2e0d1", R8A779F0_PD_A2E0D1, R8A779F0_PD_A3E0, PD_SCU }, + { "a2e1d0", R8A779F0_PD_A2E1D0, R8A779F0_PD_A3E1, PD_SCU }, + { "a2e1d1", R8A779F0_PD_A2E1D1, R8A779F0_PD_A3E1, PD_SCU }, + { "a1e0d0c0", R8A779F0_PD_A1E0D0C0, R8A779F0_PD_A2E0D0, PD_CPU_NOCR }, + { "a1e0d0c1", R8A779F0_PD_A1E0D0C1, R8A779F0_PD_A2E0D0, PD_CPU_NOCR }, + { "a1e0d1c0", R8A779F0_PD_A1E0D1C0, R8A779F0_PD_A2E0D1, PD_CPU_NOCR }, + { "a1e0d1c1", R8A779F0_PD_A1E0D1C1, R8A779F0_PD_A2E0D1, PD_CPU_NOCR }, + { "a1e1d0c0", R8A779F0_PD_A1E1D0C0, R8A779F0_PD_A2E1D0, PD_CPU_NOCR }, + { "a1e1d0c1", R8A779F0_PD_A1E1D0C1, R8A779F0_PD_A2E1D0, PD_CPU_NOCR }, + { "a1e1d1c0", R8A779F0_PD_A1E1D1C0, R8A779F0_PD_A2E1D1, PD_CPU_NOCR }, + { "a1e1d1c1", R8A779F0_PD_A1E1D1C1, R8A779F0_PD_A2E1D1, PD_CPU_NOCR }, +}; + +const struct rcar_gen4_sysc_info r8a779f0_sysc_info __initconst = { + .areas = r8a779f0_areas, + .num_areas = ARRAY_SIZE(r8a779f0_areas), +}; diff --git a/drivers/soc/renesas/rcar-gen4-sysc.c b/drivers/soc/renesas/rcar-gen4-sysc.c index d9a0929f5f1d0..831162a57f9aa 100644 --- a/drivers/soc/renesas/rcar-gen4-sysc.c +++ b/drivers/soc/renesas/rcar-gen4-sysc.c @@ -278,6 +278,9 @@ finalize: static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = { #ifdef CONFIG_SYSC_R8A779A0 { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info }, +#endif +#ifdef CONFIG_SYSC_R8A779F0 + { .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info }, #endif { /* sentinel */ } }; diff --git a/drivers/soc/renesas/rcar-gen4-sysc.h b/drivers/soc/renesas/rcar-gen4-sysc.h index 3470a9e2f5c77..0e0bd102b1f97 100644 --- a/drivers/soc/renesas/rcar-gen4-sysc.h +++ b/drivers/soc/renesas/rcar-gen4-sysc.h @@ -38,5 +38,6 @@ struct rcar_gen4_sysc_info { }; extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info; +extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info; #endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */ -- GitLab From 9711633587f4fb4376265781c75e39c2a7b21d6f Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:01 +0900 Subject: [PATCH 359/965] soc: renesas: Identify R-Car S4-8 Add support for identifying the R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-8-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 7 +++++++ drivers/soc/renesas/renesas-soc.c | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 59a4106a66e98..2cbd03db2cc71 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -235,6 +235,13 @@ config ARCH_R8A77961 This enables support for the Renesas R-Car M3-W+ SoC. This includes different gradings like R-Car M3e and M3e-2G. +config ARCH_R8A779F0 + bool "ARM64 Platform support for R-Car S4-8" + select ARCH_RCAR_GEN3 + select SYSC_R8A779F0 + help + This enables support for the Renesas R-Car S4-8 SoC. + config ARCH_R8A77980 bool "ARM64 Platform support for R-Car V3H" select ARCH_RCAR_GEN3 diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index dff90f5049632..62540ffc581a4 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -33,6 +33,10 @@ static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = { .reg = 0xfff00044, /* PRR (Product Register) */ }; +static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = { + .name = "R-Car Gen4", +}; + static const struct renesas_family fam_rmobile __initconst __maybe_unused = { .name = "R-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -214,6 +218,11 @@ static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = { .id = 0x59, }; +static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = { + .family = &fam_rcar_gen4, + .id = 0x5a, +}; + static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { .family = &fam_shmobile, .id = 0x37, @@ -319,6 +328,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A779A0 { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, #endif +#ifdef CONFIG_ARCH_R8A779F0 + { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 }, +#endif #if defined(CONFIG_ARCH_R9A07G044) { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif -- GitLab From 363b41dd25397f553bebf87594eca9b2d6445b55 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:04 +0900 Subject: [PATCH 360/965] soc: renesas: rcar-rst: Add support for R-Car S4-8 Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. The register map of R-Car S4-8 is the same as R-Car V3U so that renames "V3U" and "r8a779a0" to "Gen4". Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-11-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/rcar-rst.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 1ad54e0c32e1c..4d293eb2d8f31 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -66,7 +66,7 @@ static const struct rst_config rcar_rst_gen3 __initconst = { .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; -static const struct rst_config rcar_rst_r8a779a0 __initconst = { +static const struct rst_config rcar_rst_gen4 __initconst = { .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ }; @@ -100,8 +100,9 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, - /* R-Car V3U */ - { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 }, + /* R-Car Gen4 */ + { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 }, + { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, { /* sentinel */ } }; -- GitLab From c62331e8222f8f21faae600effd32b972bb43850 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:06 +0900 Subject: [PATCH 361/965] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Add initial support for the Renesas R8A779F0 (R-Car S4-8) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-13-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 121 ++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi new file mode 100644 index 0000000000000..eda597766eafa --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779f0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a55_0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779f0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779f0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779f0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- GitLab From 08b8699eb369d1b416c146922edfe827b41757a4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:07 +0900 Subject: [PATCH 362/965] arm64: dts: renesas: Add Renesas Spider boards support Initial support for the Renesas Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Tested-by: Takehito Nakamura Link: https://lore.kernel.org/r/20211201073308.1003945-14-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 36 +++++++++++++++++++ .../boot/dts/renesas/r8a779f0-spider.dts | 22 ++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d1c5c21d8d146..5bc8065a78649 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -63,6 +63,8 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb +dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi new file mode 100644 index 0000000000000..156586532c844 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a779f0.dtsi" + +/ { + model = "Renesas Spider CPU board"; + compatible = "renesas,spider-cpu", "renesas,r8a779f0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts new file mode 100644 index 0000000000000..f286254b41d88 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU and BreakOut boards + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779f0-spider-cpu.dtsi" + +/ { + model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; + compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; + + aliases { + serial0 = &scif3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; -- GitLab From 44e009607444f64d173f0c884e815edabc093024 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:08 +0900 Subject: [PATCH 363/965] arm64: defconfig: Enable R-Car S4-8 Enable the Renesas R-Car S4-8 (R8A779F0) SoC in the ARM64 defconfig. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-15-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e2b9bdd7024..04db99bfbf9de 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1069,6 +1069,7 @@ CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R8A779F0=y CONFIG_ARCH_R9A07G044=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y -- GitLab From 12f332d2dd3187472f595b678246adb10d886bd0 Mon Sep 17 00:00:00 2001 From: Hari Prasath Date: Wed, 8 Dec 2021 12:05:53 +0530 Subject: [PATCH 364/965] ARM: dts: at91: update alternate function of signal PD20 The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: # v5.15+ Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com --- arch/arm/boot/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 22fe9e522a97b..4eb30445d2057 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -765,7 +765,7 @@ #define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) #define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) #define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) #define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) #define PIN_PD21 117 #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -- GitLab From 7fd890b89dea55eb5866640eb8befad26d558161 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 25 Aug 2021 17:03:10 +0200 Subject: [PATCH 365/965] soc: xilinx: move PM_INIT_FINALIZE to zynqmp_pm_domains driver PM_INIT_FINALIZE tells the PMU FW that Linux is able to handle the power management nodes that are provided by the PMU FW. Nodes that are not requested are shut down after this call. Calling PM_INIT_FINALIZE from the zynqmp_power driver is wrong. The PM node request mechanism is implemented in the zynqmp_pm_domains driver, which must also call PM_INIT_FINALIZE. Due to the behavior of the PMU FW, all devices must be powered up before PM_INIT_FINALIZE is called, because otherwise the devices might misbehave. Calling PM_INIT_FINALIZE from the sync_state device callback ensures that all users probed successfully before the PMU FW is allowed to power off unused domains. Signed-off-by: Michael Tretter Acked-by: Michal Simek Acked-by: Rajan Vaja Link: https://lore.kernel.org/r/20210825150313.4033156-2-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_pm_domains.c | 16 ++++++++++++++++ drivers/soc/xilinx/zynqmp_power.c | 1 - 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 226d343f0a6a5..81e8e10f10929 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -152,11 +152,17 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, struct device *dev) { + struct device_link *link; int ret; struct zynqmp_pm_domain *pd; pd = container_of(domain, struct zynqmp_pm_domain, gpd); + link = device_link_add(dev, &domain->dev, DL_FLAG_SYNC_STATE_ONLY); + if (!link) + dev_dbg(&domain->dev, "failed to create device link for %s\n", + dev_name(dev)); + /* If this is not the first device to attach there is nothing to do */ if (domain->device_count) return 0; @@ -299,9 +305,19 @@ static int zynqmp_gpd_remove(struct platform_device *pdev) return 0; } +static void zynqmp_gpd_sync_state(struct device *dev) +{ + int ret; + + ret = zynqmp_pm_init_finalize(); + if (ret) + dev_warn(dev, "failed to release power management to firmware\n"); +} + static struct platform_driver zynqmp_power_domain_driver = { .driver = { .name = "zynqmp_power_controller", + .sync_state = zynqmp_gpd_sync_state, }, .probe = zynqmp_gpd_probe, .remove = zynqmp_gpd_remove, diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index c556623dae024..f8c301984d4f9 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -178,7 +178,6 @@ static int zynqmp_pm_probe(struct platform_device *pdev) u32 pm_api_version; struct mbox_client *client; - zynqmp_pm_init_finalize(); zynqmp_pm_get_api_version(&pm_api_version); /* Check PM API version number */ -- GitLab From c4245100f7461e0dd1f16ef0e0fcc19bcd826de3 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 25 Aug 2021 17:03:11 +0200 Subject: [PATCH 366/965] soc: xilinx: cleanup debug and error messages Use dev_err/dev_dbg instead of pr_err/pr_debug. Add the PM node ids to supplement the (arbitrary) power domain names to include information which PM nodes are requested by the driver. Drop function names from the messages, because they can easily be added with dynamic debug. Remove comments explaining that error messages are printed on errors. Signed-off-by: Michael Tretter Acked-by: Michal Simek Acked-by: Rajan Vaja Link: https://lore.kernel.org/r/20210825150313.4033156-3-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_pm_domains.c | 45 +++++++++++++------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 81e8e10f10929..27c46c68e5cc5 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -80,12 +80,15 @@ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_BLOCKING); if (ret) { - pr_err("%s() %s set requirement for node %d failed: %d\n", - __func__, domain->name, pd->node_id, ret); + dev_err(&domain->dev, + "failed to set requirement to 0x%x for PM node id %d: %d\n", + ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id, ret); return ret; } - pr_debug("%s() Powered on %s domain\n", __func__, domain->name); + dev_dbg(&domain->dev, "set requirement to 0x%x for PM node id %d\n", + ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id); + return 0; } @@ -110,8 +113,8 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) /* If domain is already released there is nothing to be done */ if (!(pd->flags & ZYNQMP_PM_DOMAIN_REQUESTED)) { - pr_debug("%s() %s domain is already released\n", - __func__, domain->name); + dev_dbg(&domain->dev, "PM node id %d is already released\n", + pd->node_id); return 0; } @@ -128,17 +131,16 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) ret = zynqmp_pm_set_requirement(pd->node_id, capabilities, 0, ZYNQMP_PM_REQUEST_ACK_NO); - /** - * If powering down of any node inside this domain fails, - * report and return the error - */ if (ret) { - pr_err("%s() %s set requirement for node %d failed: %d\n", - __func__, domain->name, pd->node_id, ret); + dev_err(&domain->dev, + "failed to set requirement to 0x%x for PM node id %d: %d\n", + capabilities, pd->node_id, ret); return ret; } - pr_debug("%s() Powered off %s domain\n", __func__, domain->name); + dev_dbg(&domain->dev, "set requirement to 0x%x for PM node id %d\n", + capabilities, pd->node_id); + return 0; } @@ -169,17 +171,17 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, ret = zynqmp_pm_request_node(pd->node_id, 0, 0, ZYNQMP_PM_REQUEST_ACK_BLOCKING); - /* If requesting a node fails print and return the error */ if (ret) { - pr_err("%s() %s request failed for node %d: %d\n", - __func__, domain->name, pd->node_id, ret); + dev_err(&domain->dev, "%s request failed for node %d: %d\n", + domain->name, pd->node_id, ret); return ret; } pd->flags |= ZYNQMP_PM_DOMAIN_REQUESTED; - pr_debug("%s() %s attached to %s domain\n", __func__, - dev_name(dev), domain->name); + dev_dbg(&domain->dev, "%s requested PM node id %d\n", + dev_name(dev), pd->node_id); + return 0; } @@ -201,17 +203,16 @@ static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, return; ret = zynqmp_pm_release_node(pd->node_id); - /* If releasing a node fails print the error and return */ if (ret) { - pr_err("%s() %s release failed for node %d: %d\n", - __func__, domain->name, pd->node_id, ret); + dev_err(&domain->dev, "failed to release PM node id %d: %d\n", + pd->node_id, ret); return; } pd->flags &= ~ZYNQMP_PM_DOMAIN_REQUESTED; - pr_debug("%s() %s detached from %s domain\n", __func__, - dev_name(dev), domain->name); + dev_dbg(&domain->dev, "%s released PM node id %d\n", + dev_name(dev), pd->node_id); } static struct generic_pm_domain *zynqmp_gpd_xlate -- GitLab From e7a9106c32c0527735a01ae00d5d9edbdb573b40 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 25 Aug 2021 17:03:12 +0200 Subject: [PATCH 367/965] soc: xilinx: use a properly named field instead of flags Instead of defining a flags field and a single bit in this field to signal that a PM node has been requested, use a boolean field with a descriptive name. No functional change, but using a proper name instead of flags makes the code easier to read. Signed-off-by: Michael Tretter Acked-by: Michal Simek Acked-by: Rajan Vaja Link: https://lore.kernel.org/r/20210825150313.4033156-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_pm_domains.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 27c46c68e5cc5..53b0041f9fe0e 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -20,8 +20,6 @@ #include #define ZYNQMP_NUM_DOMAINS (100) -/* Flag stating if PM nodes mapped to the PM domain has been requested */ -#define ZYNQMP_PM_DOMAIN_REQUESTED BIT(0) static int min_capability; @@ -29,12 +27,12 @@ static int min_capability; * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain * @gpd: Generic power domain * @node_id: PM node ID corresponding to device inside PM domain - * @flags: ZynqMP PM domain flags + * @requested: The PM node mapped to the PM domain has been requested */ struct zynqmp_pm_domain { struct generic_pm_domain gpd; u32 node_id; - u8 flags; + bool requested; }; /** @@ -112,7 +110,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If domain is already released there is nothing to be done */ - if (!(pd->flags & ZYNQMP_PM_DOMAIN_REQUESTED)) { + if (!pd->requested) { dev_dbg(&domain->dev, "PM node id %d is already released\n", pd->node_id); return 0; @@ -177,7 +175,7 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, return ret; } - pd->flags |= ZYNQMP_PM_DOMAIN_REQUESTED; + pd->requested = true; dev_dbg(&domain->dev, "%s requested PM node id %d\n", dev_name(dev), pd->node_id); @@ -209,7 +207,7 @@ static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, return; } - pd->flags &= ~ZYNQMP_PM_DOMAIN_REQUESTED; + pd->requested = false; dev_dbg(&domain->dev, "%s released PM node id %d\n", dev_name(dev), pd->node_id); -- GitLab From 628e8ba1d331397d580e65a61c0fb4b5ae8e5ccb Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 25 Aug 2021 17:03:13 +0200 Subject: [PATCH 368/965] soc: xilinx: add a to_zynqmp_pm_domain macro Replace container_of for converting a generic_pm_domain to a zynqmp_pm_domain with a macro definition to simplify the code. Signed-off-by: Michael Tretter Acked-by: Michal Simek Acked-by: Rajan Vaja Link: https://lore.kernel.org/r/20210825150313.4033156-5-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_pm_domains.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 53b0041f9fe0e..fcce2433bd6d5 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -35,6 +35,9 @@ struct zynqmp_pm_domain { bool requested; }; +#define to_zynqmp_pm_domain(pm_domain) \ + container_of(pm_domain, struct zynqmp_pm_domain, gpd) + /** * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source * path @@ -69,10 +72,9 @@ static int zynqmp_gpd_is_active_wakeup_path(struct device *dev, void *not_used) */ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) { + struct zynqmp_pm_domain *pd = to_zynqmp_pm_domain(domain); int ret; - struct zynqmp_pm_domain *pd; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); ret = zynqmp_pm_set_requirement(pd->node_id, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, @@ -101,14 +103,12 @@ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) */ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) { + struct zynqmp_pm_domain *pd = to_zynqmp_pm_domain(domain); int ret; struct pm_domain_data *pdd, *tmp; - struct zynqmp_pm_domain *pd; u32 capabilities = min_capability; bool may_wakeup; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); - /* If domain is already released there is nothing to be done */ if (!pd->requested) { dev_dbg(&domain->dev, "PM node id %d is already released\n", @@ -152,11 +152,9 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, struct device *dev) { + struct zynqmp_pm_domain *pd = to_zynqmp_pm_domain(domain); struct device_link *link; int ret; - struct zynqmp_pm_domain *pd; - - pd = container_of(domain, struct zynqmp_pm_domain, gpd); link = device_link_add(dev, &domain->dev, DL_FLAG_SYNC_STATE_ONLY); if (!link) @@ -191,10 +189,8 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, struct device *dev) { + struct zynqmp_pm_domain *pd = to_zynqmp_pm_domain(domain); int ret; - struct zynqmp_pm_domain *pd; - - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If this is not the last device to detach there is nothing to do */ if (domain->device_count) @@ -220,7 +216,7 @@ static struct generic_pm_domain *zynqmp_gpd_xlate unsigned int i, idx = genpdspec->args[0]; struct zynqmp_pm_domain *pd; - pd = container_of(genpd_data->domains[0], struct zynqmp_pm_domain, gpd); + pd = to_zynqmp_pm_domain(genpd_data->domains[0]); if (genpdspec->args_count != 1) return ERR_PTR(-EINVAL); -- GitLab From 168e05c131cd15932f95364b103b8cb7dbf19546 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 6 Oct 2021 01:43:55 -0700 Subject: [PATCH 369/965] firmware: xilinx: check return value of zynqmp_pm_get_api_version() Currently return value of zynqmp_pm_get_api_version() is ignored. Because of that, API version is checked in case of error also. So add check for return value of zynqmp_pm_get_api_version(). Signed-off-by: Rajan Vaja Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/1633509835-31949-1-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Michal Simek --- drivers/firmware/xilinx/zynqmp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 3dd45a7420dc3..0dd117860b637 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1434,7 +1434,10 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) return ret; /* Check PM API version number */ - zynqmp_pm_get_api_version(&pm_api_version); + ret = zynqmp_pm_get_api_version(&pm_api_version); + if (ret) + return ret; + if (pm_api_version < ZYNQMP_PM_VERSION) { panic("%s Platform Management API version error. Expected: v%d.%d - Found: v%d.%d\n", __func__, -- GitLab From 6133d84228895c28d2a706176f1fa45bcf39792d Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:00 +0800 Subject: [PATCH 370/965] arm64: dts: imx8mn-evk: add hardware reset for FEC PHY Add hardware reset for FEC PHY. Signed-off-by: Joakim Zhang Reviewed-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 85e65f8719ea5..30e7c9d560901 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -97,6 +97,8 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; -- GitLab From e0aa402b40a276ac2a02c005f62a12dcd9786aca Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:01 +0800 Subject: [PATCH 371/965] arm64: dts: imx8mp-evk: add hardware reset for EQOS PHY As commit 798a1807ab13 ("arm64: dts: imx8mp-evk: Improve the Ethernet PHY description") described, add hardware reset for EQOS PHY. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7b99fad6e4d6e..a7dc0d160f794 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -97,6 +97,9 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; -- GitLab From 20b6559ecf5d49ee75ae519bf9da5ef3d2f02148 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:02 +0800 Subject: [PATCH 372/965] arm64: dts: imx8m: disable smart eee for FEC PHY As commit 390b4cad8148 ("net: phy: at803x: add support for configuring SmartEEE") described, disable PHY smart eee by default. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e033d0257b5a1..50b3bbb662d55 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -116,6 +116,7 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 30e7c9d560901..342f57e8cf61f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -99,6 +99,7 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b83df77195ece..a9e33548a2f34 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -169,6 +169,7 @@ reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; -- GitLab From 09e5ccdd866c35ac55e11a5fa3f818d6a471fe0f Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:03 +0800 Subject: [PATCH 373/965] arm64: dts: imx8m: configure FEC PHY VDDIO voltage As commit 2f664823a470 ("net: phy: at803x: add device tree binding") described, configure FEC PHY VDDIO voltage according to board design. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 50b3bbb662d55..3bac87b7e1422 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -117,6 +117,12 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 342f57e8cf61f..c3f15192b76c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -100,6 +100,12 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a9e33548a2f34..c96d23fe3010f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -170,6 +170,10 @@ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddh>; + + vddh: vddh-regulator { + }; }; }; }; -- GitLab From 311ad460c4fa3911cca36118b18feff233ae9e76 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:04 +0800 Subject: [PATCH 374/965] arm64: dts: imx8mp-evk: disable CLKOUT clock for ENET PHY According to commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock"), diable CLKOUT clock for FEC PHY to save power on i.MX8MP EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a7dc0d160f794..cf03a82f9dcda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -100,6 +100,7 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,clkout-disable; }; }; }; @@ -123,6 +124,7 @@ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,clkout-disable; }; }; }; -- GitLab From baf55c1509fec59a734a987b44e318c99610ce4f Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:05 +0800 Subject: [PATCH 375/965] arm64: dts: imx8m: remove unused "nvmem_macaddr_swap" property for FEC Remove unused "nvmem_macaddr_swap" property for FEC, there is no info in both dt-binding and driver, so it's safe to remove it. Reviewed-by: Ahmad Fatoum Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a31cf2b9769c1..c84d768604417 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1082,7 +1082,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index ba23b416b5e6c..b8d49d5f26681 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -976,7 +976,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 977783784342b..20687f9c973c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -860,7 +860,6 @@ nvmem-cells = <ð_mac1>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&gpr 0x10 3>; - nvmem_macaddr_swap; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5ab9e02bd929d..5f57deee57946 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1320,7 +1320,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; -- GitLab From 44d0dfee53ffff733de6baabea986e72af08f7bb Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:06 +0800 Subject: [PATCH 376/965] arm64: dts: imx8mp: add mac address for EQOS Add mac address in efuse, so that EQOS driver can parse it from nvmem cell. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 20687f9c973c0..6b840c05dd771 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -397,6 +397,10 @@ eth_mac1: mac-address@90 { reg = <0x90 6>; }; + + eth_mac2: mac-address@96 { + reg = <0x96 6>; + }; }; anatop: anatop@30360000 { @@ -881,6 +885,8 @@ <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_125M>; assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; intf_mode = <&gpr 0x4>; status = "disabled"; }; -- GitLab From 0de4ab81ab26f09d4dbf8142a881b4607070d01f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Mon, 22 Nov 2021 17:25:20 +0100 Subject: [PATCH 377/965] ARM: dts: imx6dl-yapp4: Add Y Soft IOTA Crux/Crux+ board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetrees for the new boards in the Y Soft IOTA family. These boards are based on Orion but use Quad/QuadPlus SoC instead of DualLite. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6q-yapp4-crux.dts | 54 ++++++++++++++++++++ arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts | 54 ++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-yapp4-crux.dts create mode 100644 arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e462dbe75f6ac..51a6dd6871918 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -632,6 +632,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ @@ -646,6 +647,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-tx6qp-8137-mb7.dtb \ imx6qp-vicutp.dtb \ imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ imx6qp-zii-rdu2.dtb \ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts new file mode 100644 index 0000000000000..15f4824a5142a --- /dev/null +++ b/arch/arm/boot/dts/imx6q-yapp4-crux.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts new file mode 100644 index 0000000000000..cea165f2161a3 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; -- GitLab From bb29e4091079dd7ef5bd488bd7625965cdfd2c12 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Thu, 14 Oct 2021 04:45:55 -0400 Subject: [PATCH 378/965] ARM: at91: pm: Add of_node_put() before goto Fix following coccicheck warning: ./arch/arm/mach-at91/pm.c:643:1-33: WARNING: Function for_each_matching_node_and_match should have of_node_put() before goto Early exits from for_each_matching_node_and_match should decrement the node reference counter. Signed-off-by: Wan Jiabing Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211014084555.21422-1-wanjiabing@vivo.com --- arch/arm/mach-at91/pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 8711d6824c1fa..dd6f4ce3f7660 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -645,6 +645,7 @@ static __init int at91_dt_ramc(bool phy_mandatory) if (!soc_pm.data.ramc[idx]) { pr_err("unable to map ramc[%d] cpu registers\n", idx); ret = -ENOMEM; + of_node_put(np); goto unmap_ramc; } @@ -670,6 +671,7 @@ static __init int at91_dt_ramc(bool phy_mandatory) if (!soc_pm.data.ramc_phy) { pr_err("unable to map ramc phy cpu registers\n"); ret = -ENOMEM; + of_node_put(np); goto unmap_ramc; } } -- GitLab From 6d4518a086b2cce1f7935eb5a88a7f03e241f640 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Tue, 26 Oct 2021 16:20:34 +0300 Subject: [PATCH 379/965] ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain Reviewed-by: Eugen Hristev Signed-off-by: Eugen Hristev Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index b1e854f658de4..9bf2ec0ba3e2f 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; non-removable; - mmc-ddr-1_8v; + mmc-ddr-3_3v; status = "okay"; }; @@ -619,10 +619,9 @@ bias-disable; }; - ck_cd_rstn_vddsel { + ck_cd_rstn { pinmux = , , - , ; bias-disable; }; -- GitLab From b3111fe15df5e420f5251bad612fcf6915392c92 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 11 Nov 2021 09:10:45 +0100 Subject: [PATCH 380/965] ARM: dts: at91: add Microchip EVB-KSZ9477 board Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU: https://www.microchip.com/en-us/development-tool/evb-ksz9477 Signed-off-by: Oleksij Rempel Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 209 ++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..f79585f6e80b7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ at91-gatwick.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts new file mode 100644 index 0000000000000..443e8b0228977 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "EVB-KSZ9477"; + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcc0_vcc>; + regulator-name = "mmc0-vcc"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_vcc_mmc0>; + vqmmc-supply = <®_3v3>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, + <&pioD 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + switch@0 { + compatible = "microchip,ksz9477"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = ; + }; + + pinctrl_mcc0_vcc: mmc0-vcc { + atmel,pins = ; + }; + + pinctrl_spi_ksz: spi-ksz { + atmel,pins = + < + /* SPI1_MISO */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + /* SPI1_MOSI */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE + /* SPI1_SPCK */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE + + /* SPI CS */ + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + /* switch IRQ */ + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH + /* switch PME_N, SoC IN */ + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP + /* switch RST */ + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH + >; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + }; +}; -- GitLab From 8260b9820f7050461b8969305bbd8cb5654f0c74 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Mon, 6 Dec 2021 16:55:03 +0300 Subject: [PATCH 381/965] x86/sev: Use CC_ATTR attribute to generalize string I/O unroll INS/OUTS are not supported in TDX guests and cause #UD. Kernel has to avoid them when running in TDX guest. To support existing usage, string I/O operations are unrolled using IN/OUT instructions. AMD SEV platform implements this support by adding unroll logic in ins#bwl()/outs#bwl() macros with SEV-specific checks. Since TDX VM guests will also need similar support, use CC_ATTR_GUEST_UNROLL_STRING_IO and generic cc_platform_has() API to implement it. String I/O helpers were the last users of sev_key_active() interface and sev_enable_key static key. Remove them. [ bp: Move comment too and do not delete it. ] Suggested-by: Tom Lendacky Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Signed-off-by: Borislav Petkov Reviewed-by: Tony Luck Reviewed-by: Tom Lendacky Tested-by: Tom Lendacky Link: https://lkml.kernel.org/r/20211206135505.75045-2-kirill.shutemov@linux.intel.com --- arch/x86/include/asm/io.h | 20 +++----------------- arch/x86/kernel/cc_platform.c | 8 ++++++++ arch/x86/mm/mem_encrypt.c | 10 ---------- include/linux/cc_platform.h | 11 +++++++++++ 4 files changed, 22 insertions(+), 27 deletions(-) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 5c6a4af0b911c..f6d91ecb80267 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -256,21 +257,6 @@ static inline void slow_down_io(void) #endif -#ifdef CONFIG_AMD_MEM_ENCRYPT -#include - -extern struct static_key_false sev_enable_key; -static inline bool sev_key_active(void) -{ - return static_branch_unlikely(&sev_enable_key); -} - -#else /* !CONFIG_AMD_MEM_ENCRYPT */ - -static inline bool sev_key_active(void) { return false; } - -#endif /* CONFIG_AMD_MEM_ENCRYPT */ - #define BUILDIO(bwl, bw, type) \ static inline void out##bwl(unsigned type value, int port) \ { \ @@ -301,7 +287,7 @@ static inline unsigned type in##bwl##_p(int port) \ \ static inline void outs##bwl(int port, const void *addr, unsigned long count) \ { \ - if (sev_key_active()) { \ + if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ unsigned type *value = (unsigned type *)addr; \ while (count) { \ out##bwl(*value, port); \ @@ -317,7 +303,7 @@ static inline void outs##bwl(int port, const void *addr, unsigned long count) \ \ static inline void ins##bwl(int port, void *addr, unsigned long count) \ { \ - if (sev_key_active()) { \ + if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ unsigned type *value = (unsigned type *)addr; \ while (count) { \ *value = in##bwl(port); \ diff --git a/arch/x86/kernel/cc_platform.c b/arch/x86/kernel/cc_platform.c index 03bb2f343ddb7..8a25b1c0d4801 100644 --- a/arch/x86/kernel/cc_platform.c +++ b/arch/x86/kernel/cc_platform.c @@ -50,6 +50,14 @@ static bool amd_cc_platform_has(enum cc_attr attr) case CC_ATTR_GUEST_STATE_ENCRYPT: return sev_status & MSR_AMD64_SEV_ES_ENABLED; + /* + * With SEV, the rep string I/O instructions need to be unrolled + * but SEV-ES supports them through the #VC handler. + */ + case CC_ATTR_GUEST_UNROLL_STRING_IO: + return (sev_status & MSR_AMD64_SEV_ENABLED) && + !(sev_status & MSR_AMD64_SEV_ES_ENABLED); + default: return false; } diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 35487305d8afe..b520021a7e7b2 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -43,8 +43,6 @@ u64 sme_me_mask __section(".data") = 0; u64 sev_status __section(".data") = 0; u64 sev_check_data __section(".data") = 0; EXPORT_SYMBOL(sme_me_mask); -DEFINE_STATIC_KEY_FALSE(sev_enable_key); -EXPORT_SYMBOL_GPL(sev_enable_key); /* Buffer used for early in-place encryption by BSP, no locking needed */ static char sme_early_buffer[PAGE_SIZE] __initdata __aligned(PAGE_SIZE); @@ -499,14 +497,6 @@ void __init mem_encrypt_init(void) /* Call into SWIOTLB to update the SWIOTLB DMA buffers */ swiotlb_update_mem_attributes(); - /* - * With SEV, we need to unroll the rep string I/O instructions, - * but SEV-ES supports them through the #VC handler. - */ - if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) && - !cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) - static_branch_enable(&sev_enable_key); - print_mem_encrypt_feature_info(); } diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index a075b70b9a70c..efd8205282da7 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -61,6 +61,17 @@ enum cc_attr { * Examples include SEV-ES. */ CC_ATTR_GUEST_STATE_ENCRYPT, + + /** + * @CC_ATTR_GUEST_UNROLL_STRING_IO: String I/O is implemented with + * IN/OUT instructions + * + * The platform/OS is running as a guest/virtual machine and uses + * IN/OUT instructions in place of string I/O. + * + * Examples include TDX guest & SEV. + */ + CC_ATTR_GUEST_UNROLL_STRING_IO, }; #ifdef CONFIG_ARCH_HAS_CC_PLATFORM -- GitLab From dbca5e1a04f8b30aea4e2c91e5045ee6e7c3ef43 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Mon, 6 Dec 2021 16:55:04 +0300 Subject: [PATCH 382/965] x86/sev: Rename mem_encrypt.c to mem_encrypt_amd.c Both Intel TDX and AMD SEV implement memory encryption features. But the bulk of the code in mem_encrypt.c is AMD-specific. Rename the file to mem_encrypt_amd.c. A subsequent patch will extract the parts that can be shared by both TDX and AMD SEV/SME into a generic file. No functional changes. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Signed-off-by: Borislav Petkov Reviewed-by: Tony Luck Reviewed-by: Tom Lendacky Tested-by: Tom Lendacky Link: https://lore.kernel.org/r/20211206135505.75045-3-kirill.shutemov@linux.intel.com --- arch/x86/mm/Makefile | 8 ++++---- arch/x86/mm/{mem_encrypt.c => mem_encrypt_amd.c} | 0 2 files changed, 4 insertions(+), 4 deletions(-) rename arch/x86/mm/{mem_encrypt.c => mem_encrypt_amd.c} (100%) diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index 5864219221ca8..c9c4806411536 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 # Kernel does not boot with instrumentation of tlb.c and mem_encrypt*.c KCOV_INSTRUMENT_tlb.o := n -KCOV_INSTRUMENT_mem_encrypt.o := n +KCOV_INSTRUMENT_mem_encrypt_amd.o := n KCOV_INSTRUMENT_mem_encrypt_identity.o := n -KASAN_SANITIZE_mem_encrypt.o := n +KASAN_SANITIZE_mem_encrypt_amd.o := n KASAN_SANITIZE_mem_encrypt_identity.o := n # Disable KCSAN entirely, because otherwise we get warnings that some functions @@ -12,7 +12,7 @@ KASAN_SANITIZE_mem_encrypt_identity.o := n KCSAN_SANITIZE := n ifdef CONFIG_FUNCTION_TRACER -CFLAGS_REMOVE_mem_encrypt.o = -pg +CFLAGS_REMOVE_mem_encrypt_amd.o = -pg CFLAGS_REMOVE_mem_encrypt_identity.o = -pg endif @@ -52,6 +52,6 @@ obj-$(CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS) += pkeys.o obj-$(CONFIG_RANDOMIZE_MEMORY) += kaslr.o obj-$(CONFIG_PAGE_TABLE_ISOLATION) += pti.o -obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt.o +obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_amd.o obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_identity.o obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_boot.o diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt_amd.c similarity index 100% rename from arch/x86/mm/mem_encrypt.c rename to arch/x86/mm/mem_encrypt_amd.c -- GitLab From 20f07a044a76aebaaa0603038857229b5c460d69 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Mon, 6 Dec 2021 16:55:05 +0300 Subject: [PATCH 383/965] x86/sev: Move common memory encryption code to mem_encrypt.c SEV and TDX both protect guest memory from host accesses. They both use guest physical address bits to communicate to the hardware which pages receive protection or not. SEV and TDX both assume that all I/O (real devices and virtio) must be performed to pages *without* protection. To add this support, AMD SEV code forces force_dma_unencrypted() to decrypt DMA pages when DMA pages were allocated for I/O. It also uses swiotlb_update_mem_attributes() to update decryption bits in SWIOTLB DMA buffers. Since TDX also uses a similar memory sharing design, all the above mentioned changes can be reused. So move force_dma_unencrypted(), SWIOTLB update code and virtio changes out of mem_encrypt_amd.c to mem_encrypt.c. Introduce a new config option X86_MEM_ENCRYPT that can be selected by platforms which use x86 memory encryption features (needed in both AMD SEV and Intel TDX guest platforms). Since the code is moved from mem_encrypt_amd.c, inherit the same make flags. This is preparation for enabling TDX memory encryption support and it has no functional changes. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Signed-off-by: Borislav Petkov Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Reviewed-by: Tom Lendacky Tested-by: Tom Lendacky Link: https://lore.kernel.org/r/20211206135505.75045-4-kirill.shutemov@linux.intel.com --- arch/x86/Kconfig | 10 +++-- arch/x86/mm/Makefile | 5 +++ arch/x86/mm/mem_encrypt.c | 84 +++++++++++++++++++++++++++++++++++ arch/x86/mm/mem_encrypt_amd.c | 69 ---------------------------- 4 files changed, 96 insertions(+), 72 deletions(-) create mode 100644 arch/x86/mm/mem_encrypt.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 95dd1ee01546a..793e9b42ace0a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1523,16 +1523,20 @@ config X86_CPA_STATISTICS helps to determine the effectiveness of preserving large and huge page mappings when mapping protections are changed. +config X86_MEM_ENCRYPT + select ARCH_HAS_FORCE_DMA_UNENCRYPTED + select DYNAMIC_PHYSICAL_MASK + select ARCH_HAS_RESTRICTED_VIRTIO_MEMORY_ACCESS + def_bool n + config AMD_MEM_ENCRYPT bool "AMD Secure Memory Encryption (SME) support" depends on X86_64 && CPU_SUP_AMD select DMA_COHERENT_POOL - select DYNAMIC_PHYSICAL_MASK select ARCH_USE_MEMREMAP_PROT - select ARCH_HAS_FORCE_DMA_UNENCRYPTED select INSTRUCTION_DECODER - select ARCH_HAS_RESTRICTED_VIRTIO_MEMORY_ACCESS select ARCH_HAS_CC_PLATFORM + select X86_MEM_ENCRYPT help Say yes to enable support for the encryption of system memory. This requires an AMD processor that supports Secure Memory diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index c9c4806411536..fe3d3061fc116 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 # Kernel does not boot with instrumentation of tlb.c and mem_encrypt*.c KCOV_INSTRUMENT_tlb.o := n +KCOV_INSTRUMENT_mem_encrypt.o := n KCOV_INSTRUMENT_mem_encrypt_amd.o := n KCOV_INSTRUMENT_mem_encrypt_identity.o := n +KASAN_SANITIZE_mem_encrypt.o := n KASAN_SANITIZE_mem_encrypt_amd.o := n KASAN_SANITIZE_mem_encrypt_identity.o := n @@ -12,6 +14,7 @@ KASAN_SANITIZE_mem_encrypt_identity.o := n KCSAN_SANITIZE := n ifdef CONFIG_FUNCTION_TRACER +CFLAGS_REMOVE_mem_encrypt.o = -pg CFLAGS_REMOVE_mem_encrypt_amd.o = -pg CFLAGS_REMOVE_mem_encrypt_identity.o = -pg endif @@ -52,6 +55,8 @@ obj-$(CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS) += pkeys.o obj-$(CONFIG_RANDOMIZE_MEMORY) += kaslr.o obj-$(CONFIG_PAGE_TABLE_ISOLATION) += pti.o +obj-$(CONFIG_X86_MEM_ENCRYPT) += mem_encrypt.o obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_amd.o + obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_identity.o obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_boot.o diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c new file mode 100644 index 0000000000000..50d209939c66c --- /dev/null +++ b/arch/x86/mm/mem_encrypt.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Memory Encryption Support Common Code + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ + +#include +#include +#include +#include +#include +#include + +/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */ +bool force_dma_unencrypted(struct device *dev) +{ + /* + * For SEV, all DMA must be to unencrypted addresses. + */ + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) + return true; + + /* + * For SME, all DMA must be to unencrypted addresses if the + * device does not support DMA to addresses that include the + * encryption mask. + */ + if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { + u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask)); + u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask, + dev->bus_dma_limit); + + if (dma_dev_mask <= dma_enc_mask) + return true; + } + + return false; +} + +static void print_mem_encrypt_feature_info(void) +{ + pr_info("AMD Memory Encryption Features active:"); + + /* Secure Memory Encryption */ + if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { + /* + * SME is mutually exclusive with any of the SEV + * features below. + */ + pr_cont(" SME\n"); + return; + } + + /* Secure Encrypted Virtualization */ + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) + pr_cont(" SEV"); + + /* Encrypted Register State */ + if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) + pr_cont(" SEV-ES"); + + pr_cont("\n"); +} + +/* Architecture __weak replacement functions */ +void __init mem_encrypt_init(void) +{ + if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT)) + return; + + /* Call into SWIOTLB to update the SWIOTLB DMA buffers */ + swiotlb_update_mem_attributes(); + + print_mem_encrypt_feature_info(); +} + +int arch_has_restricted_virtio_memory_access(void) +{ + return cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT); +} +EXPORT_SYMBOL_GPL(arch_has_restricted_virtio_memory_access); diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index b520021a7e7b2..2b2d018ea3450 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -413,32 +413,6 @@ void __init early_set_mem_enc_dec_hypercall(unsigned long vaddr, int npages, boo notify_range_enc_status_changed(vaddr, npages, enc); } -/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */ -bool force_dma_unencrypted(struct device *dev) -{ - /* - * For SEV, all DMA must be to unencrypted addresses. - */ - if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) - return true; - - /* - * For SME, all DMA must be to unencrypted addresses if the - * device does not support DMA to addresses that include the - * encryption mask. - */ - if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { - u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask)); - u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask, - dev->bus_dma_limit); - - if (dma_dev_mask <= dma_enc_mask) - return true; - } - - return false; -} - void __init mem_encrypt_free_decrypted_mem(void) { unsigned long vaddr, vaddr_end, npages; @@ -462,46 +436,3 @@ void __init mem_encrypt_free_decrypted_mem(void) free_init_pages("unused decrypted", vaddr, vaddr_end); } - -static void print_mem_encrypt_feature_info(void) -{ - pr_info("AMD Memory Encryption Features active:"); - - /* Secure Memory Encryption */ - if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { - /* - * SME is mutually exclusive with any of the SEV - * features below. - */ - pr_cont(" SME\n"); - return; - } - - /* Secure Encrypted Virtualization */ - if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) - pr_cont(" SEV"); - - /* Encrypted Register State */ - if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) - pr_cont(" SEV-ES"); - - pr_cont("\n"); -} - -/* Architecture __weak replacement functions */ -void __init mem_encrypt_init(void) -{ - if (!sme_me_mask) - return; - - /* Call into SWIOTLB to update the SWIOTLB DMA buffers */ - swiotlb_update_mem_attributes(); - - print_mem_encrypt_feature_info(); -} - -int arch_has_restricted_virtio_memory_access(void) -{ - return cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT); -} -EXPORT_SYMBOL_GPL(arch_has_restricted_virtio_memory_access); -- GitLab From 36b88b209593f6e103fdc4df369fcdedc7f2f1c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 20 Oct 2021 02:40:59 +0300 Subject: [PATCH 384/965] ARM: dts: elpida_ecb240abacn: Change Elpida compatible Vendor prefix shouldn't start with capital letter. The Elpida Memory compatible was never used in practice, hence just correct the compatible. Signed-off-by: Dmitry Osipenko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi index d87ee4794f836..9698801cbcfb6 100644 --- a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -5,7 +5,7 @@ / { elpida_ECB240ABACN: lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; density = <2048>; io-width = <32>; -- GitLab From f3499b1329c9af605874df0664ee0e245687b72b Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:19 -0700 Subject: [PATCH 385/965] ARM: dts: am335x-boneblack-common: move system-power-controller Move the rtc node system-power-controller property from am335x-boneblack-common.dtsi to am335x-bone-common.dtsi. am335x-boneblack-common.dtsi is included by am335x-boneblack.dts, am335x-boneblack-wireless.dts, am335x-sancloud-bbe.dts and am335x-sancloud-bbe-lite.dts. All of these dts files also include am335x-bone-common.dtsi and thus will retain the rtc node system-power-controller property. am335x-bone-common.dtsi is also included by am335x-bone.dts [1], am335x-bonegreen.dts [2] and am335x-bonegreen-wireless.dts [3]. These boards will now have the rtc node system-power-controller property too. This is valid as they also have PMIC_POWR_EN (ZCZ C6) connected to PWR_EN on the TPS65217B PMIC. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [4]. [1] https://beagleboard.org/static/beaglebone/BEAGLEBONE_SCHEM_A3.pdf [2] https://github.com/SeeedDocument/BeagleBone_Green/blob/master/resources/BEAGLEBONE_GREEN_V1.pdf [3] https://github.com/SeeedDocument/BeagleBone_Green_Wireless/blob/master/resources/BeagleBone_Green%20Wireless_V1.0_SCH_20160314.pdf [4] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Jason Kridner Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Reviewed-by: Johan Hovold Signed-off-by: Drew Fustini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 1 + arch/arm/boot/dts/am335x-boneblack-common.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0ccdc7cd463bc..56ae5095a5b87 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -399,6 +399,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; + system-power-controller; }; &pruss_tm { diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index 10494c4431b92..a7a8c61ef9b24 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -22,10 +22,6 @@ non-removable; }; -&rtc { - system-power-controller; -}; - / { memory@80000000 { device_type = "memory"; -- GitLab From 1e72c64eb75e99cfcd62c2678f4c465d1213170c Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:20 -0700 Subject: [PATCH 386/965] ARM: dts: am335x-icev2: Add system-power-controller to RTC node On the am335x-icev2 board [1], AM3359 PMIC_PWR_EN (ZCZ ball C6) is connected to PWRHOLD (pin 1) on the TPS65910A3 PMIC. The addition of system-power-controller to the rtc node will enable the capability of the RTC driver to poweroff the board. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [2]. [1] https://www.ti.com/tool/TMDSICE3359 [2] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Signed-off-by: Drew Fustini Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e5ce89c8f54d3..5835c0cdda50b 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -512,3 +512,7 @@ &pruss_tm { status = "okay"; }; + +&rtc { + system-power-controller; +}; -- GitLab From d2e8a6c43bbf61200e5fcb3199efc2680af32bc1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:11 +0100 Subject: [PATCH 387/965] ARM: dts: am437x-cm-t43: Use a correctly spelled DT property Back in 2014 a property got misspelled "ti,coordiante-readouts" instead of "ti,coordinate-readouts". The year after it got fixed but both are still supported, although this is not a reason to continue using this old deprecated property. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 5ce8e684e7d35..3e3354780db8f 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -399,7 +399,7 @@ tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; + ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; -- GitLab From 6c06a9f55b5fc9f48950bedfe8d5b74748a21e76 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:12 +0100 Subject: [PATCH 388/965] ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module This hardware module is close to the am33xx ADC module but instead of featuring a touchscreen it has a magnetic reader capability. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 31 ++++++++++++++++++++++++++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 7 +++++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ba58e6b0da1da..8f2268c027785 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2378,11 +2378,38 @@ }; target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x2000>; + + magadc: magadc@0 { + compatible = "ti,am4372-magadc"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&adc_mag_fck>; + clock-names = "fck"; + dmas = <&edma 54 0>, <&edma 55 0>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + mag { + compatible = "ti,am4372-mag"; + }; + + adc { + #io-channel-cells = <1>; + compatible ="ti,am4372-adc"; + }; + }; }; target-module@80000 { /* 0x48380000, ap 123 42.0 */ diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 314fc5975acbe..66e892fa3398b 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -444,6 +444,13 @@ reg = <0x422c>; }; + adc_mag_fck: adc_mag_fck@424c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; + reg = <0x424c>; + }; + l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- GitLab From 6fde719b19af7e82671c352c69981c75ca9909c2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:13 +0100 Subject: [PATCH 389/965] ARM: dts: am437x-gp-evm: enable ADC1 ADC0 and ADC1 pins are available on external connector J22. Enable ADC1 which was missing. Signed-off-by: Miquel Raynal Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index c2e4896076e7f..4416ddb559e4c 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -775,6 +775,14 @@ }; }; +&magadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + &ecap0 { status = "okay"; pinctrl-names = "default"; -- GitLab From 7ebe6e99f7702dad342486e5b30d989a0a6499af Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Dec 2021 15:10:43 +0100 Subject: [PATCH 390/965] ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value The TI wlcore DT bindings specify using a single compatible value for each variant, and the Linux kernel driver matches against the first compatible value since commit 078b30da3f074f2e ("wlcore: add wl1285 compatible") in v4.13. Signed-off-by: Geert Uytterhoeven Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index a4423ff0df392..c7a1f3ffc48ca 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -310,7 +310,7 @@ #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { - compatible = "ti,wl1285", "ti,wl1283"; + compatible = "ti,wl1285"; reg = <2>; /* gpio_100 with gpmc_wait2 pad as wakeirq */ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, -- GitLab From fa0fdb78cb5d4cde00430ec481f09fbe7c029376 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 15:48:02 +0100 Subject: [PATCH 391/965] ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. The old "ak" vendor prefix that was never officially accepted was still being used in some device trees. Convert to the correct vendor prefix (i.e. "asahi-kasei"). Signed-off-by: Thierry Reding Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 2 +- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index c6bb325ead339..147c00de37955 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -341,7 +341,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 605b2a436edf9..b2846cd220f04 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -84,7 +84,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; -- GitLab From 50468e4313355b161cac8a5155a45832995b7f25 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Tue, 16 Nov 2021 18:21:16 +0200 Subject: [PATCH 392/965] x86/sgx: Add an attribute for the amount of SGX memory in a NUMA node == Problem == The amount of SGX memory on a system is determined by the BIOS and it varies wildly between systems. It can be as small as dozens of MB's and as large as many GB's on servers. Just like how applications need to know how much regular RAM is available, enclave builders need to know how much SGX memory an enclave can consume. == Solution == Introduce a new sysfs file: /sys/devices/system/node/nodeX/x86/sgx_total_bytes to enumerate the amount of SGX memory available in each NUMA node. This serves the same function for SGX as /proc/meminfo or /sys/devices/system/node/nodeX/meminfo does for normal RAM. 'sgx_total_bytes' is needed today to help drive the SGX selftests. SGX-specific swap code is exercised by creating overcommitted enclaves which are larger than the physical SGX memory on the system. They currently use a CPUID-based approach which can diverge from the actual amount of SGX memory available. 'sgx_total_bytes' ensures that the selftests can work efficiently and do not attempt stupid things like creating a 100,000 MB enclave on a system with 128 MB of SGX memory. == Implementation Details == Introduce CONFIG_HAVE_ARCH_NODE_DEV_GROUP opt-in flag to expose an arch specific attribute group, and add an attribute for the amount of SGX memory in bytes to each NUMA node: == ABI Design Discussion == As opposed to the per-node ABI, a single, global ABI was considered. However, this would prevent enclaves from being able to size themselves so that they fit on a single NUMA node. Essentially, a single value would rule out NUMA optimizations for enclaves. Create a new "x86/" directory inside each "nodeX/" sysfs directory. 'sgx_total_bytes' is expected to be the first of at least a few sgx-specific files to be placed in the new directory. Just scanning /proc/meminfo, these are the no-brainers that we have for RAM, but we need for SGX: MemTotal: xxxx kB // sgx_total_bytes (implemented here) MemFree: yyyy kB // sgx_free_bytes SwapTotal: zzzz kB // sgx_swapped_bytes So, at *least* three. I think we will eventually end up needing something more along the lines of a dozen. A new directory (as opposed to being in the nodeX/ "root") directory avoids cluttering the root with several "sgx_*" files. Place the new file in a new "nodeX/x86/" directory because SGX is highly x86-specific. It is very unlikely that any other architecture (or even non-Intel x86 vendor) will ever implement SGX. Using "sgx/" as opposed to "x86/" was also considered. But, there is a real chance this can get used for other arch-specific purposes. [ dhansen: rewrite changelog ] Signed-off-by: Jarkko Sakkinen Signed-off-by: Dave Hansen Acked-by: Greg Kroah-Hartman Acked-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211116162116.93081-2-jarkko@kernel.org --- Documentation/ABI/stable/sysfs-devices-node | 6 ++++++ arch/Kconfig | 4 ++++ arch/x86/Kconfig | 1 + arch/x86/kernel/cpu/sgx/main.c | 20 ++++++++++++++++++++ arch/x86/kernel/cpu/sgx/sgx.h | 1 + drivers/base/node.c | 3 +++ include/linux/numa.h | 4 ++++ 7 files changed, 39 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node index 484fc04bcc254..8db67aa472f16 100644 --- a/Documentation/ABI/stable/sysfs-devices-node +++ b/Documentation/ABI/stable/sysfs-devices-node @@ -176,3 +176,9 @@ Contact: Keith Busch Description: The cache write policy: 0 for write-back, 1 for write-through, other or unknown. + +What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes +Date: November 2021 +Contact: Jarkko Sakkinen +Description: + The total amount of SGX physical memory in bytes. diff --git a/arch/Kconfig b/arch/Kconfig index 26b8ed11639da..0a9dadb00b61e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1302,6 +1302,10 @@ config ARCH_HAS_PARANOID_L1D_FLUSH config DYNAMIC_SIGFRAME bool +# Select, if arch has a named attribute group bound to NUMA device nodes. +config HAVE_ARCH_NODE_DEV_GROUP + bool + source "kernel/gcov/Kconfig" source "scripts/gcc-plugins/Kconfig" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b9281fab4e3e4..f2b699d12eb8d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -269,6 +269,7 @@ config X86 select HAVE_ARCH_KCSAN if X86_64 select X86_FEATURE_NAMES if PROC_FS select PROC_PID_ARCH_STATUS if PROC_FS + select HAVE_ARCH_NODE_DEV_GROUP if X86_SGX imply IMA_SECURE_AND_OR_TRUSTED_BOOT if EFI config INSTRUCTION_DECODER diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 6036328de255a..2857a49f23359 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -825,9 +825,11 @@ static bool __init sgx_page_cache_init(void) INIT_LIST_HEAD(&sgx_numa_nodes[nid].free_page_list); INIT_LIST_HEAD(&sgx_numa_nodes[nid].sgx_poison_page_list); node_set(nid, sgx_numa_mask); + sgx_numa_nodes[nid].size = 0; } sgx_epc_sections[i].node = &sgx_numa_nodes[nid]; + sgx_numa_nodes[nid].size += size; sgx_nr_epc_sections++; } @@ -901,6 +903,24 @@ int sgx_set_attribute(unsigned long *allowed_attributes, } EXPORT_SYMBOL_GPL(sgx_set_attribute); +#ifdef CONFIG_NUMA +static ssize_t sgx_total_bytes_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%lu\n", sgx_numa_nodes[dev->id].size); +} +static DEVICE_ATTR_RO(sgx_total_bytes); + +static struct attribute *arch_node_dev_attrs[] = { + &dev_attr_sgx_total_bytes.attr, + NULL, +}; + +const struct attribute_group arch_node_dev_group = { + .name = "x86", + .attrs = arch_node_dev_attrs, +}; +#endif /* CONFIG_NUMA */ + static int __init sgx_init(void) { int ret; diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index 9ec3136c78009..0f17def9fe6ff 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -44,6 +44,7 @@ struct sgx_epc_page { struct sgx_numa_node { struct list_head free_page_list; struct list_head sgx_poison_page_list; + unsigned long size; spinlock_t lock; }; diff --git a/drivers/base/node.c b/drivers/base/node.c index b5a4ba18f9f90..87acc47e89515 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -581,6 +581,9 @@ static const struct attribute_group node_dev_group = { static const struct attribute_group *node_dev_groups[] = { &node_dev_group, +#ifdef CONFIG_HAVE_ARCH_NODE_DEV_GROUP + &arch_node_dev_group, +#endif NULL }; diff --git a/include/linux/numa.h b/include/linux/numa.h index cb44cfe2b7255..59df211d051fa 100644 --- a/include/linux/numa.h +++ b/include/linux/numa.h @@ -58,4 +58,8 @@ static inline int phys_to_target_node(u64 start) } #endif +#ifdef CONFIG_HAVE_ARCH_NODE_DEV_GROUP +extern const struct attribute_group arch_node_dev_group; +#endif + #endif /* _LINUX_NUMA_H */ -- GitLab From df0114f1f8711dbf481324c44cf5a8349130b913 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 7 Dec 2021 22:37:35 +0000 Subject: [PATCH 393/965] x86/resctrl: Remove redundant assignment to variable chunks The variable chunks is being shifted right and re-assinged the shifted value which is then returned. Since chunks is not being read afterwards the assignment is redundant and the >>= operator can be replaced with a shift >> operator instead. Signed-off-by: Colin Ian King Signed-off-by: Dave Hansen Reviewed-by: Fenghua Yu Link: https://lkml.kernel.org/r/20211207223735.35173-1-colin.i.king@gmail.com --- arch/x86/kernel/cpu/resctrl/monitor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index c9f0f3d63f75f..eaf25a234ff5d 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -282,7 +282,7 @@ static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr, unsigned int width) u64 shift = 64 - width, chunks; chunks = (cur_msr << shift) - (prev_msr << shift); - return chunks >>= shift; + return chunks >> shift; } static u64 __mon_event_count(u32 rmid, struct rmid_read *rr) -- GitLab From 35fa745286ac44ee26ed100c2bd2553368ad193b Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Tue, 2 Nov 2021 17:52:24 +0100 Subject: [PATCH 394/965] x86/mm: Include spinlock_t definition in pgtable. This header file provides forward declartion for pgd_lock but does not include the header defining its type. This works since the definition of spinlock_t is usually included somehow via printk. By trying to avoid recursive includes on PREEMPT_RT I avoided the loop in printk and as a consequnce kernel/intel.c failed to compile due to missing type definition. Include the needed definition for spinlock_t. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Dave Hansen Link: https://lkml.kernel.org/r/20211102165224.wpz4zyhsvwccx5p3@linutronix.de --- arch/x86/include/asm/pgtable.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 448cd01eb3ecb..a34430b7af4a3 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -22,6 +22,7 @@ #define pgprot_decrypted(prot) __pgprot(__sme_clr(pgprot_val(prot))) #ifndef __ASSEMBLY__ +#include #include #include #include -- GitLab From 7afccde389dcfaca793a0d909f8cb7412e1d1dbe Mon Sep 17 00:00:00 2001 From: Rongwei Wang Date: Fri, 26 Nov 2021 01:06:00 +0800 Subject: [PATCH 395/965] arm64: kexec: reduce calls to page_address() In kexec_page_alloc(), page_address() is called twice. This patch add a new variable to help to reduce calls to page_address(). Signed-off-by: Rongwei Wang Link: https://lore.kernel.org/r/20211125170600.1608-3-rongwei.wang@linux.alibaba.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/machine_kexec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c index 1038494135c8c..7f2530bcd42eb 100644 --- a/arch/arm64/kernel/machine_kexec.c +++ b/arch/arm64/kernel/machine_kexec.c @@ -104,13 +104,15 @@ static void *kexec_page_alloc(void *arg) { struct kimage *kimage = (struct kimage *)arg; struct page *page = kimage_alloc_control_pages(kimage, 0); + void *vaddr = NULL; if (!page) return NULL; - memset(page_address(page), 0, PAGE_SIZE); + vaddr = page_address(page); + memset(vaddr, 0, PAGE_SIZE); - return page_address(page); + return vaddr; } int machine_kexec_post_load(struct kimage *kimage) -- GitLab From 1614b2b11fab29dd4ff31ebba9d266961f5af69e Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 29 Nov 2021 14:28:41 +0000 Subject: [PATCH 396/965] arch: Make ARCH_STACKWALK independent of STACKTRACE Make arch_stack_walk() available for ARCH_STACKWALK architectures without it being entangled in STACKTRACE. Link: https://lore.kernel.org/lkml/20211022152104.356586621@infradead.org/ Signed-off-by: Peter Zijlstra (Intel) [Mark: rebase, drop unnecessary arm change] Signed-off-by: Mark Rutland Cc: Albert Ou Cc: Borislav Petkov Cc: Christian Borntraeger Cc: Dave Hansen Cc: Heiko Carstens Cc: Ingo Molnar Cc: Michael Ellerman Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: Thomas Gleixner Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20211129142849.3056714-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/stacktrace.c | 4 ---- arch/powerpc/kernel/Makefile | 3 +-- arch/riscv/kernel/stacktrace.c | 4 ---- arch/s390/kernel/Makefile | 3 +-- arch/x86/kernel/Makefile | 2 +- include/linux/stacktrace.h | 35 +++++++++++++++++----------------- 6 files changed, 21 insertions(+), 30 deletions(-) diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c index 94f83cd44e507..e6ba6b000564d 100644 --- a/arch/arm64/kernel/stacktrace.c +++ b/arch/arm64/kernel/stacktrace.c @@ -221,8 +221,6 @@ void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl) barrier(); } -#ifdef CONFIG_STACKTRACE - noinline notrace void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, struct task_struct *task, struct pt_regs *regs) @@ -241,5 +239,3 @@ noinline notrace void arch_stack_walk(stack_trace_consume_fn consume_entry, walk_stackframe(task, &frame, consume_entry, cookie); } - -#endif diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 5fa68c2ef1f81..b039877c743dc 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -47,7 +47,7 @@ obj-y := cputable.o syscalls.o \ udbg.o misc.o io.o misc_$(BITS).o \ of_platform.o prom_parse.o firmware.o \ hw_breakpoint_constraints.o interrupt.o \ - kdebugfs.o + kdebugfs.o stacktrace.o obj-y += ptrace/ obj-$(CONFIG_PPC64) += setup_64.o \ paca.o nvram_64.o note.o @@ -116,7 +116,6 @@ obj-$(CONFIG_OPTPROBES) += optprobes.o optprobes_head.o obj-$(CONFIG_KPROBES_ON_FTRACE) += kprobes-ftrace.o obj-$(CONFIG_UPROBES) += uprobes.o obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o obj-$(CONFIG_ARCH_HAS_DMA_SET_MASK) += dma-mask.o diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c index 0fcdc0233faca..201ee206fb57d 100644 --- a/arch/riscv/kernel/stacktrace.c +++ b/arch/riscv/kernel/stacktrace.c @@ -139,12 +139,8 @@ unsigned long __get_wchan(struct task_struct *task) return pc; } -#ifdef CONFIG_STACKTRACE - noinline void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, struct task_struct *task, struct pt_regs *regs) { walk_stackframe(task, regs, consume_entry, cookie); } - -#endif /* CONFIG_STACKTRACE */ diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile index 80f500ffb55c3..be8007f367aab 100644 --- a/arch/s390/kernel/Makefile +++ b/arch/s390/kernel/Makefile @@ -40,7 +40,7 @@ obj-y += sysinfo.o lgr.o os_info.o machine_kexec.o obj-y += runtime_instr.o cache.o fpu.o dumpstack.o guarded_storage.o sthyi.o obj-y += entry.o reipl.o relocate_kernel.o kdebugfs.o alternative.o obj-y += nospec-branch.o ipl_vmparm.o machine_kexec_reloc.o unwind_bc.o -obj-y += smp.o text_amode31.o +obj-y += smp.o text_amode31.o stacktrace.o extra-y += head64.o vmlinux.lds @@ -55,7 +55,6 @@ compat-obj-$(CONFIG_AUDIT) += compat_audit.o obj-$(CONFIG_COMPAT) += compat_linux.o compat_signal.o obj-$(CONFIG_COMPAT) += $(compat-obj-y) obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_KPROBES) += kprobes.o obj-$(CONFIG_KPROBES) += kprobes_insn_page.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 2ff3e600f4269..6aef9ee28a394 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -84,7 +84,7 @@ obj-$(CONFIG_IA32_EMULATION) += tls.o obj-y += step.o obj-$(CONFIG_INTEL_TXT) += tboot.o obj-$(CONFIG_ISA_DMA_API) += i8237.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o +obj-y += stacktrace.o obj-y += cpu/ obj-y += acpi/ obj-y += reboot.o diff --git a/include/linux/stacktrace.h b/include/linux/stacktrace.h index bef158815e83d..97455880ac414 100644 --- a/include/linux/stacktrace.h +++ b/include/linux/stacktrace.h @@ -8,22 +8,6 @@ struct task_struct; struct pt_regs; -#ifdef CONFIG_STACKTRACE -void stack_trace_print(const unsigned long *trace, unsigned int nr_entries, - int spaces); -int stack_trace_snprint(char *buf, size_t size, const unsigned long *entries, - unsigned int nr_entries, int spaces); -unsigned int stack_trace_save(unsigned long *store, unsigned int size, - unsigned int skipnr); -unsigned int stack_trace_save_tsk(struct task_struct *task, - unsigned long *store, unsigned int size, - unsigned int skipnr); -unsigned int stack_trace_save_regs(struct pt_regs *regs, unsigned long *store, - unsigned int size, unsigned int skipnr); -unsigned int stack_trace_save_user(unsigned long *store, unsigned int size); -unsigned int filter_irq_stacks(unsigned long *entries, unsigned int nr_entries); - -/* Internal interfaces. Do not use in generic code */ #ifdef CONFIG_ARCH_STACKWALK /** @@ -76,8 +60,25 @@ int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, void *cookie, void arch_stack_walk_user(stack_trace_consume_fn consume_entry, void *cookie, const struct pt_regs *regs); +#endif /* CONFIG_ARCH_STACKWALK */ -#else /* CONFIG_ARCH_STACKWALK */ +#ifdef CONFIG_STACKTRACE +void stack_trace_print(const unsigned long *trace, unsigned int nr_entries, + int spaces); +int stack_trace_snprint(char *buf, size_t size, const unsigned long *entries, + unsigned int nr_entries, int spaces); +unsigned int stack_trace_save(unsigned long *store, unsigned int size, + unsigned int skipnr); +unsigned int stack_trace_save_tsk(struct task_struct *task, + unsigned long *store, unsigned int size, + unsigned int skipnr); +unsigned int stack_trace_save_regs(struct pt_regs *regs, unsigned long *store, + unsigned int size, unsigned int skipnr); +unsigned int stack_trace_save_user(unsigned long *store, unsigned int size); +unsigned int filter_irq_stacks(unsigned long *entries, unsigned int nr_entries); + +#ifndef CONFIG_ARCH_STACKWALK +/* Internal interfaces. Do not use in generic code */ struct stack_trace { unsigned int nr_entries, max_entries; unsigned long *entries; -- GitLab From 1e5428b2b7e8aef6a1d10a33fa15df427f087450 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 29 Nov 2021 14:28:42 +0000 Subject: [PATCH 397/965] arm64: Add comment for stack_info::kr_cur We added stack_info::kr_cur in commit: cd9bc2c9258816dc ("arm64: Recover kretprobe modified return address in stacktrace") ... but didn't add anything in the corresponding comment block. For consistency, add a corresponding comment. Signed-off-by: Mark Rutland Reviwed-by: Mark Brown Reviewed-by: Masami Hiramatsu Cc: Steven Rostedt (VMware) Cc: Will Deacon Link: https://lore.kernel.org/r/20211129142849.3056714-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/stacktrace.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/stacktrace.h b/arch/arm64/include/asm/stacktrace.h index 6564a01cc085a..1367012e05202 100644 --- a/arch/arm64/include/asm/stacktrace.h +++ b/arch/arm64/include/asm/stacktrace.h @@ -47,6 +47,10 @@ struct stack_info { * @prev_type: The type of stack this frame record was on, or a synthetic * value of STACK_TYPE_UNKNOWN. This is used to detect a * transition from one stack to another. + * + * @kr_cur: When KRETPROBES is selected, holds the kretprobe instance + * associated with the most recently encountered replacement lr + * value. */ struct stackframe { unsigned long fp; -- GitLab From 86bcbafcb726b7b11898d2d6269bd665cb27c1b9 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 29 Nov 2021 14:28:43 +0000 Subject: [PATCH 398/965] arm64: Mark __switch_to() as __sched Unlike most architectures (and only in keeping with powerpc), arm64 has a non __sched() function on the path to our cpu_switch_to() assembly function. It is expected that for a blocked task, in_sched_functions() can be used to skip all functions between the raw context switch assembly and the scheduler functions that call into __switch_to(). This is the behaviour expected by stack_trace_consume_entry_nosched(), and the behaviour we'd like to have such that we an simplify arm64's __get_wchan() implementation to use arch_stack_walk(). This patch mark's arm64's __switch_to as __sched. This *will not* change the behaviour of arm64's current __get_wchan() implementation, which always performs an initial unwind step which skips __switch_to(). This *will* change the behaviour of stack_trace_consume_entry_nosched() and stack_trace_save_tsk() to match their expected behaviour on blocked tasks, skipping all scheduler-internal functions including __switch_to(). Other than the above, there should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Madhavan T. Venkataraman Cc: Peter Zijlstra Cc: Will Deacon Reviewed-by: Mark Brown Link: https://lore.kernel.org/r/20211129142849.3056714-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/process.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index aacf2f5559a8b..980cad7292af0 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -490,7 +490,8 @@ void update_sctlr_el1(u64 sctlr) /* * Thread switching. */ -__notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, +__notrace_funcgraph __sched +struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next) { struct task_struct *last; -- GitLab From ed876d35a1dc7f9efcfc51dd06843b5b8af08ad1 Mon Sep 17 00:00:00 2001 From: "Madhavan T. Venkataraman" Date: Mon, 29 Nov 2021 14:28:44 +0000 Subject: [PATCH 399/965] arm64: Make perf_callchain_kernel() use arch_stack_walk() To enable RELIABLE_STACKTRACE and LIVEPATCH on arm64, we need to substantially rework arm64's unwinding code. As part of this, we want to minimize the set of unwind interfaces we expose, and avoid open-coding of unwind logic outside of stacktrace.c. Currently perf_callchain_kernel() walks the stack of an interrupted context by calling start_backtrace() with the context's PC and FP, and iterating unwind steps using walk_stackframe(). This is functionally equivalent to calling arch_stack_walk() with the interrupted context's pt_regs, which will start with the PC and FP from the regs. Make perf_callchain_kernel() use arch_stack_walk(). This simplifies perf_callchain_kernel(), and in future will alow us to make walk_stackframe() private to stacktrace.c. At the same time, we update the callchain_trace() callback to check the return value of perf_callchain_store(), which indicates whether there is space for any further entries. When a non-zero value is returned, further calls will be ignored, and are redundant, so we can stop the unwind at this point. We also remove the stale and confusing comment for callchain_trace. There should be no functional change as a result of this patch. Signed-off-by: Madhavan T. Venkataraman Tested-by: Mark Rutland Reviewed-by: Mark Brown Reviewed-by: Mark Rutland [Mark: elaborate commit message, remove comment, fix includes] Signed-off-by: Mark Rutland Link: https://lore.kernel.org/r/20211129142849.3056714-5-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/perf_callchain.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/perf_callchain.c b/arch/arm64/kernel/perf_callchain.c index 4a72c27273097..e9b7d99f4e3a0 100644 --- a/arch/arm64/kernel/perf_callchain.c +++ b/arch/arm64/kernel/perf_callchain.c @@ -5,10 +5,10 @@ * Copyright (C) 2015 ARM Limited */ #include +#include #include #include -#include struct frame_tail { struct frame_tail __user *fp; @@ -132,30 +132,21 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, } } -/* - * Gets called by walk_stackframe() for every stackframe. This will be called - * whist unwinding the stackframe and is like a subroutine return so we use - * the PC. - */ static bool callchain_trace(void *data, unsigned long pc) { struct perf_callchain_entry_ctx *entry = data; - perf_callchain_store(entry, pc); - return true; + return perf_callchain_store(entry, pc) == 0; } void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct stackframe frame; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } - start_backtrace(&frame, regs->regs[29], regs->pc); - walk_stackframe(current, &frame, callchain_trace, entry); + arch_stack_walk(callchain_trace, entry, current, regs); } unsigned long perf_instruction_pointer(struct pt_regs *regs) -- GitLab From 4f62bb7cb165f3e7b0a91279fe9dd5c56daf3457 Mon Sep 17 00:00:00 2001 From: "Madhavan T. Venkataraman" Date: Mon, 29 Nov 2021 14:28:45 +0000 Subject: [PATCH 400/965] arm64: Make __get_wchan() use arch_stack_walk() To enable RELIABLE_STACKTRACE and LIVEPATCH on arm64, we need to substantially rework arm64's unwinding code. As part of this, we want to minimize the set of unwind interfaces we expose, and avoid open-coding of unwind logic outside of stacktrace.c. Currently, __get_wchan() walks the stack of a blocked task by calling start_backtrace() with the task's saved PC and FP values, and iterating unwind steps using unwind_frame(). The initialization is functionally equivalent to calling arch_stack_walk() with the blocked task, which will start with the task's saved PC and FP values. Currently __get_wchan() always performs an initial unwind step, which will stkip __switch_to(), but as this is now marked as a __sched function, this no longer needs special handling and will be skipped in the same way as other sched functions. Make __get_wchan() use arch_stack_walk(). This simplifies __get_wchan(), and in future will alow us to make unwind_frame() private to stacktrace.c. At the same time, we can simplify the try_get_task_stack() check and avoid the unnecessary `stack_page` variable. The change to the skipping logic means we may terminate one frame earlier than previously where there are an excessive number of sched functions in the trace, but this isn't seen in practice, and wchan is best-effort anyway, so this should not be a problem. Other than the above, there should be no functional change as a result of this patch. Signed-off-by: Madhavan T. Venkataraman [Mark: rebase atop wchan changes, elaborate commit message, fix includes] Signed-off-by: Mark Rutland Reviewed-by: Mark Brown Link: https://lore.kernel.org/r/20211129142849.3056714-6-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/process.c | 42 ++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 980cad7292af0..836a933156cd2 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -529,30 +530,37 @@ struct task_struct *__switch_to(struct task_struct *prev, return last; } +struct wchan_info { + unsigned long pc; + int count; +}; + +static bool get_wchan_cb(void *arg, unsigned long pc) +{ + struct wchan_info *wchan_info = arg; + + if (!in_sched_functions(pc)) { + wchan_info->pc = pc; + return false; + } + return wchan_info->count++ < 16; +} + unsigned long __get_wchan(struct task_struct *p) { - struct stackframe frame; - unsigned long stack_page, ret = 0; - int count = 0; + struct wchan_info wchan_info = { + .pc = 0, + .count = 0, + }; - stack_page = (unsigned long)try_get_task_stack(p); - if (!stack_page) + if (!try_get_task_stack(p)) return 0; - start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p)); - - do { - if (unwind_frame(p, &frame)) - goto out; - if (!in_sched_functions(frame.pc)) { - ret = frame.pc; - goto out; - } - } while (count++ < 16); + arch_stack_walk(get_wchan_cb, &wchan_info, p, NULL); -out: put_task_stack(p); - return ret; + + return wchan_info.pc; } unsigned long arch_align_stack(unsigned long sp) -- GitLab From 39ef362d2d45171e941457f8cd00518bfcedfe2b Mon Sep 17 00:00:00 2001 From: "Madhavan T. Venkataraman" Date: Mon, 29 Nov 2021 14:28:46 +0000 Subject: [PATCH 401/965] arm64: Make return_address() use arch_stack_walk() To enable RELIABLE_STACKTRACE and LIVEPATCH on arm64, we need to substantially rework arm64's unwinding code. As part of this, we want to minimize the set of unwind interfaces we expose, and avoid open-coding of unwind logic outside of stacktrace.c. Currently return_address() walks the stack of the current task by calling start_backtrace() with return_address as the PC and the frame pointer of return_address() as the next frame, iterating unwind steps using walk_stackframe(). This is functionally equivalent to calling arch_stack_walk() for the current stack, which will start from its caller (i.e. return_address()) as the PC and it's caller's frame record as the next frame. Make return_address() use arch_stackwalk(). This simplifies return_address(), and in future will alow us to make walk_stackframe() private to stacktrace.c. There should be no functional change as a result of this patch. Signed-off-by: Madhavan T. Venkataraman Tested-by: Mark Rutland Reviewed-by: Mark Brown Reviewed-by: Mark Rutland [Mark: elaborate commit message, fix includes] Signed-off-by: Mark Rutland Link: https://lore.kernel.org/r/20211129142849.3056714-7-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/return_address.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/return_address.c b/arch/arm64/kernel/return_address.c index a6d18755652fa..68330017d04f9 100644 --- a/arch/arm64/kernel/return_address.c +++ b/arch/arm64/kernel/return_address.c @@ -9,9 +9,9 @@ #include #include #include +#include #include -#include struct return_address_data { unsigned int level; @@ -35,15 +35,11 @@ NOKPROBE_SYMBOL(save_return_addr); void *return_address(unsigned int level) { struct return_address_data data; - struct stackframe frame; data.level = level + 2; data.addr = NULL; - start_backtrace(&frame, - (unsigned long)__builtin_frame_address(0), - (unsigned long)return_address); - walk_stackframe(current, &frame, save_return_addr, &data); + arch_stack_walk(save_return_addr, &data, current, NULL); if (!data.level) return data.addr; -- GitLab From 22ecd975b61d3645ce8f19a95369357f04a25f0b Mon Sep 17 00:00:00 2001 From: "Madhavan T. Venkataraman" Date: Mon, 29 Nov 2021 14:28:47 +0000 Subject: [PATCH 402/965] arm64: Make profile_pc() use arch_stack_walk() To enable RELIABLE_STACKTRACE and LIVEPATCH on arm64, we need to substantially rework arm64's unwinding code. As part of this, we want to minimize the set of unwind interfaces we expose, and avoid open-coding of unwind logic outside of stacktrace.c. Currently profile_pc() walks the stack of an interrupted context by calling start_backtrace() with the context's PC and FP, and iterating unwind steps using walk_stackframe(). This is functionally equivalent to calling arch_stack_walk() with the interrupted context's pt_regs, which will start with the PC and FP from the regs. Make profile_pc() use arch_stack_walk(). This simplifies profile_pc(), and in future will alow us to make walk_stackframe() private to stacktrace.c. At the same time, we remove the early return for when regs->pc is not in lock functions, as this will be handled by the first call to the profile_pc_cb() callback. There should be no functional change as a result of this patch. Signed-off-by: Madhavan T. Venkataraman Reviewed-by: Mark Rutland [Mark: remove early return, elaborate commit message, fix includes] Signed-off-by: Mark Rutland Reviewed-by: Mark Brown Link: https://lore.kernel.org/r/20211129142849.3056714-8-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/time.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c index eebbc8d7123e0..b5855eb7435d8 100644 --- a/arch/arm64/kernel/time.c +++ b/arch/arm64/kernel/time.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -29,25 +30,25 @@ #include #include -#include #include -unsigned long profile_pc(struct pt_regs *regs) +static bool profile_pc_cb(void *arg, unsigned long pc) { - struct stackframe frame; + unsigned long *prof_pc = arg; - if (!in_lock_functions(regs->pc)) - return regs->pc; + if (in_lock_functions(pc)) + return true; + *prof_pc = pc; + return false; +} - start_backtrace(&frame, regs->regs[29], regs->pc); +unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long prof_pc = 0; - do { - int ret = unwind_frame(NULL, &frame); - if (ret < 0) - return 0; - } while (in_lock_functions(frame.pc)); + arch_stack_walk(profile_pc_cb, &prof_pc, current, regs); - return frame.pc; + return prof_pc; } EXPORT_SYMBOL(profile_pc); -- GitLab From 2dad6dc17bd0cefd03b42147c6fc9bbd81f7928a Mon Sep 17 00:00:00 2001 From: "Madhavan T. Venkataraman" Date: Mon, 29 Nov 2021 14:28:48 +0000 Subject: [PATCH 403/965] arm64: Make dump_backtrace() use arch_stack_walk() To enable RELIABLE_STACKTRACE and LIVEPATCH on arm64, we need to substantially rework arm64's unwinding code. As part of this, we want to minimize the set of unwind interfaces we expose, and avoid open-coding of unwind logic. Currently, dump_backtrace() walks the stack of the current task or a blocked task by calling stact_backtrace() and iterating unwind steps using unwind_frame(). This can be written more simply in terms of arch_stack_walk(), considering three distinct cases: 1) When unwinding a blocked task, start_backtrace() is called with the blocked task's saved PC and FP, and the unwind proceeds immediately from this point without skipping any entries. This is functionally equivalent to calling arch_stack_walk() with the blocked task, which will start with the task's saved PC and FP. There is no functional change to this case. 2) When unwinding the current task without regs, start_backtrace() is called with dump_backtrace() as the PC and __builtin_frame_address(0) as the next frame, and the unwind proceeds immediately without skipping. This is *almost* functionally equivalent to calling arch_stack_walk() for the current task, which will start with its caller (i.e. an offset into dump_backtrace()) as the PC, and the callers frame record as the next frame. The only difference being that dump_backtrace() will be reported with an offset (which is strictly more correct than currently). Otherwise there is no functional cahnge to this case. 3) When unwinding the current task with regs, start_backtrace() is called with dump_backtrace() as the PC and __builtin_frame_address(0) as the next frame, and the unwind is performed silently until the next frame is the frame pointed to by regs->fp. Reporting starts from regs->pc and continues from the frame in regs->fp. Historically, this pre-unwind was necessary to correctly record return addresses rewritten by the ftrace graph calller, but this is no longer necessary as these are now recovered using the FP since commit: c6d3cd32fd0064af ("arm64: ftrace: use HAVE_FUNCTION_GRAPH_RET_ADDR_PTR") This pre-unwind is not necessary to recover return addresses rewritten by kretprobes, which historically were not recovered, and are now recovered using the FP since commit: cd9bc2c9258816dc ("arm64: Recover kretprobe modified return address in stacktrace") Thus, this is functionally equivalent to calling arch_stack_walk() with the current task and regs, which will start with regs->pc as the PC and regs->fp as the next frame, without a pre-unwind. This patch makes dump_backtrace() use arch_stack_walk(). This simplifies dump_backtrace() and will permit subsequent changes to the unwind code. Aside from the improved reporting when unwinding current without regs, there should be no functional change as a result of this patch. Signed-off-by: Madhavan T. Venkataraman [Mark: elaborate commit message] Signed-off-by: Mark Rutland Reviewed-by: Mark Brown Link: https://lore.kernel.org/r/20211129142849.3056714-9-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/stacktrace.c | 44 +++++----------------------------- 1 file changed, 6 insertions(+), 38 deletions(-) diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c index e6ba6b000564d..9fc771a053062 100644 --- a/arch/arm64/kernel/stacktrace.c +++ b/arch/arm64/kernel/stacktrace.c @@ -156,24 +156,20 @@ void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, } NOKPROBE_SYMBOL(walk_stackframe); -static void dump_backtrace_entry(unsigned long where, const char *loglvl) +static bool dump_backtrace_entry(void *arg, unsigned long where) { + char *loglvl = arg; printk("%s %pSb\n", loglvl, (void *)where); + return true; } void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk, const char *loglvl) { - struct stackframe frame; - int skip = 0; - pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); - if (regs) { - if (user_mode(regs)) - return; - skip = 1; - } + if (regs && user_mode(regs)) + return; if (!tsk) tsk = current; @@ -181,36 +177,8 @@ void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk, if (!try_get_task_stack(tsk)) return; - if (tsk == current) { - start_backtrace(&frame, - (unsigned long)__builtin_frame_address(0), - (unsigned long)dump_backtrace); - } else { - /* - * task blocked in __switch_to - */ - start_backtrace(&frame, - thread_saved_fp(tsk), - thread_saved_pc(tsk)); - } - printk("%sCall trace:\n", loglvl); - do { - /* skip until specified stack frame */ - if (!skip) { - dump_backtrace_entry(frame.pc, loglvl); - } else if (frame.fp == regs->regs[29]) { - skip = 0; - /* - * Mostly, this is the case where this function is - * called in panic/abort. As exception handler's - * stack frame does not contain the corresponding pc - * at which an exception has taken place, use regs->pc - * instead. - */ - dump_backtrace_entry(regs->pc, loglvl); - } - } while (!unwind_frame(tsk, &frame)); + arch_stack_walk(dump_backtrace_entry, (void *)loglvl, tsk, regs); put_task_stack(tsk); } -- GitLab From d2d1d2645cfd7230fd958fddbc5e7525c34f1374 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 29 Nov 2021 14:28:49 +0000 Subject: [PATCH 404/965] arm64: Make some stacktrace functions private Now that open-coded stack unwinds have been converted to arch_stack_walk(), we no longer need to expose any of unwind_frame(), walk_stackframe(), or start_backtrace() outside of stacktrace.c. Make those functions private to stacktrace.c, removing their prototypes from and marking them static. Signed-off-by: Mark Rutland Reviewed-by: Mark Brown Cc: Madhavan T. Venkataraman Link: https://lore.kernel.org/r/20211129142849.3056714-10-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/stacktrace.h | 6 ------ arch/arm64/kernel/stacktrace.c | 12 +++++++----- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/stacktrace.h b/arch/arm64/include/asm/stacktrace.h index 1367012e05202..e77cdef9ca29b 100644 --- a/arch/arm64/include/asm/stacktrace.h +++ b/arch/arm64/include/asm/stacktrace.h @@ -63,9 +63,6 @@ struct stackframe { #endif }; -extern int unwind_frame(struct task_struct *tsk, struct stackframe *frame); -extern void walk_stackframe(struct task_struct *tsk, struct stackframe *frame, - bool (*fn)(void *, unsigned long), void *data); extern void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk, const char *loglvl); @@ -150,7 +147,4 @@ static inline bool on_accessible_stack(const struct task_struct *tsk, return false; } -void start_backtrace(struct stackframe *frame, unsigned long fp, - unsigned long pc); - #endif /* __ASM_STACKTRACE_H */ diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c index 9fc771a053062..0fb58fed54cb2 100644 --- a/arch/arm64/kernel/stacktrace.c +++ b/arch/arm64/kernel/stacktrace.c @@ -33,8 +33,8 @@ */ -void start_backtrace(struct stackframe *frame, unsigned long fp, - unsigned long pc) +static void start_backtrace(struct stackframe *frame, unsigned long fp, + unsigned long pc) { frame->fp = fp; frame->pc = pc; @@ -63,7 +63,8 @@ void start_backtrace(struct stackframe *frame, unsigned long fp, * records (e.g. a cycle), determined based on the location and fp value of A * and the location (but not the fp value) of B. */ -int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) +static int notrace unwind_frame(struct task_struct *tsk, + struct stackframe *frame) { unsigned long fp = frame->fp; struct stack_info info; @@ -141,8 +142,9 @@ int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) } NOKPROBE_SYMBOL(unwind_frame); -void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, - bool (*fn)(void *, unsigned long), void *data) +static void notrace walk_stackframe(struct task_struct *tsk, + struct stackframe *frame, + bool (*fn)(void *, unsigned long), void *data) { while (1) { int ret; -- GitLab From d2f2949ab6b60fc53134908d0ffc140ef50e5a1b Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 6 Dec 2021 18:55:21 +0100 Subject: [PATCH 405/965] s390/mm: add missing phys_to_virt translation to page table dumper The page table dumper walks page table tables without using standard page table primitives in order to also dump broken entries. However it currently does not translate physical to virtual addresses before dereferencing them. Therefore add this missing translation. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/fault.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index d30f5986fa856..6ed2886fc014b 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -115,7 +115,7 @@ static void dump_pagetable(unsigned long asce, unsigned long address) pr_cont("R1:%016lx ", *table); if (*table & _REGION_ENTRY_INVALID) goto out; - table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + table = __va(*table & _REGION_ENTRY_ORIGIN); fallthrough; case _ASCE_TYPE_REGION2: table += (address & _REGION2_INDEX) >> _REGION2_SHIFT; @@ -124,7 +124,7 @@ static void dump_pagetable(unsigned long asce, unsigned long address) pr_cont("R2:%016lx ", *table); if (*table & _REGION_ENTRY_INVALID) goto out; - table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + table = __va(*table & _REGION_ENTRY_ORIGIN); fallthrough; case _ASCE_TYPE_REGION3: table += (address & _REGION3_INDEX) >> _REGION3_SHIFT; @@ -133,7 +133,7 @@ static void dump_pagetable(unsigned long asce, unsigned long address) pr_cont("R3:%016lx ", *table); if (*table & (_REGION_ENTRY_INVALID | _REGION3_ENTRY_LARGE)) goto out; - table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + table = __va(*table & _REGION_ENTRY_ORIGIN); fallthrough; case _ASCE_TYPE_SEGMENT: table += (address & _SEGMENT_INDEX) >> _SEGMENT_SHIFT; @@ -142,7 +142,7 @@ static void dump_pagetable(unsigned long asce, unsigned long address) pr_cont("S:%016lx ", *table); if (*table & (_SEGMENT_ENTRY_INVALID | _SEGMENT_ENTRY_LARGE)) goto out; - table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN); + table = __va(*table & _SEGMENT_ENTRY_ORIGIN); } table += (address & _PAGE_INDEX) >> _PAGE_SHIFT; if (bad_address(table)) -- GitLab From 9d6305c2a116f4ea3160730df8cf83d13d629b87 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 7 Dec 2021 19:19:48 +0100 Subject: [PATCH 406/965] s390/diag: use pfn_to_phys() instead of open coding Use pfn_to_phys() instead of open coding to make it clear what the code is doing. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/include/asm/diag.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/diag.h b/arch/s390/include/asm/diag.h index b3a8cb4daed61..bdcd64f0c1d74 100644 --- a/arch/s390/include/asm/diag.h +++ b/arch/s390/include/asm/diag.h @@ -47,8 +47,8 @@ static inline void diag10_range(unsigned long start_pfn, unsigned long num_pfn) { unsigned long start_addr, end_addr; - start_addr = start_pfn << PAGE_SHIFT; - end_addr = (start_pfn + num_pfn - 1) << PAGE_SHIFT; + start_addr = pfn_to_phys(start_pfn); + end_addr = pfn_to_phys(start_pfn + num_pfn - 1); diag_stat_inc(DIAG_STAT_X010); asm volatile( -- GitLab From 69700fb4389839dae84024b39a02cab844651122 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 7 Dec 2021 19:24:00 +0100 Subject: [PATCH 407/965] s390/cmm: add missing virt_to_phys() conversion diag10_range() expects a pfn, however the current cmm code is shifting a virtual address, instead of a physical address by PAGE_SHIFT bits, which would give a wrong result in case if V!=R. Use virt_to_pfn() to fix this. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/cmm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c index 2203164b39dae..9141ed4c52e90 100644 --- a/arch/s390/mm/cmm.c +++ b/arch/s390/mm/cmm.c @@ -90,7 +90,7 @@ static long cmm_alloc_pages(long nr, long *counter, } else free_page((unsigned long) npa); } - diag10_range(addr >> PAGE_SHIFT, 1); + diag10_range(virt_to_pfn(addr), 1); pa->pages[pa->index++] = addr; (*counter)++; spin_unlock(&cmm_lock); -- GitLab From 2f882800f6ab57b50b7c23a376a452a808025f37 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 7 Dec 2021 20:06:21 +0100 Subject: [PATCH 408/965] s390/pgalloc: add virt/phys address handling to base asce functions The base asce functions create/free page tables open-coded to make sure that the returned asce and page tables do not make use of any enhanced DAT features like e.g. large pages. This is required for some I/O functions that use an asce, like e.g. some service call requests. Handling of virtual vs physical addresses is missing; therefore add that now. Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/pgalloc.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 781965f7210eb..2e33dfb38a76f 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -409,9 +409,9 @@ static int base_segment_walk(unsigned long origin, unsigned long addr, table = base_pgt_alloc(); if (!table) return -ENOMEM; - *ste = table | _SEGMENT_ENTRY; + *ste = __pa(table) | _SEGMENT_ENTRY; } - table = *ste & _SEGMENT_ENTRY_ORIGIN; + table = (unsigned long)__va(*ste & _SEGMENT_ENTRY_ORIGIN); rc = base_page_walk(table, addr, next, alloc); if (rc) return rc; @@ -438,9 +438,9 @@ static int base_region3_walk(unsigned long origin, unsigned long addr, table = base_crst_alloc(_SEGMENT_ENTRY_EMPTY); if (!table) return -ENOMEM; - *rtte = table | _REGION3_ENTRY; + *rtte = __pa(table) | _REGION3_ENTRY; } - table = *rtte & _REGION_ENTRY_ORIGIN; + table = (unsigned long)__va(*rtte & _REGION_ENTRY_ORIGIN); rc = base_segment_walk(table, addr, next, alloc); if (rc) return rc; @@ -466,9 +466,9 @@ static int base_region2_walk(unsigned long origin, unsigned long addr, table = base_crst_alloc(_REGION3_ENTRY_EMPTY); if (!table) return -ENOMEM; - *rste = table | _REGION2_ENTRY; + *rste = __pa(table) | _REGION2_ENTRY; } - table = *rste & _REGION_ENTRY_ORIGIN; + table = (unsigned long)__va(*rste & _REGION_ENTRY_ORIGIN); rc = base_region3_walk(table, addr, next, alloc); if (rc) return rc; @@ -494,9 +494,9 @@ static int base_region1_walk(unsigned long origin, unsigned long addr, table = base_crst_alloc(_REGION2_ENTRY_EMPTY); if (!table) return -ENOMEM; - *rfte = table | _REGION1_ENTRY; + *rfte = __pa(table) | _REGION1_ENTRY; } - table = *rfte & _REGION_ENTRY_ORIGIN; + table = (unsigned long)__va(*rfte & _REGION_ENTRY_ORIGIN); rc = base_region2_walk(table, addr, next, alloc); if (rc) return rc; @@ -515,7 +515,7 @@ static int base_region1_walk(unsigned long origin, unsigned long addr, */ void base_asce_free(unsigned long asce) { - unsigned long table = asce & _ASCE_ORIGIN; + unsigned long table = (unsigned long)__va(asce & _ASCE_ORIGIN); if (!asce) return; @@ -578,25 +578,25 @@ unsigned long base_asce_alloc(unsigned long addr, unsigned long num_pages) if (!table) return 0; rc = base_segment_walk(table, addr, end, 1); - asce = table | _ASCE_TYPE_SEGMENT | _ASCE_TABLE_LENGTH; + asce = __pa(table) | _ASCE_TYPE_SEGMENT | _ASCE_TABLE_LENGTH; } else if (end <= _REGION2_SIZE) { table = base_crst_alloc(_REGION3_ENTRY_EMPTY); if (!table) return 0; rc = base_region3_walk(table, addr, end, 1); - asce = table | _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH; + asce = __pa(table) | _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH; } else if (end <= _REGION1_SIZE) { table = base_crst_alloc(_REGION2_ENTRY_EMPTY); if (!table) return 0; rc = base_region2_walk(table, addr, end, 1); - asce = table | _ASCE_TYPE_REGION2 | _ASCE_TABLE_LENGTH; + asce = __pa(table) | _ASCE_TYPE_REGION2 | _ASCE_TABLE_LENGTH; } else { table = base_crst_alloc(_REGION1_ENTRY_EMPTY); if (!table) return 0; rc = base_region1_walk(table, addr, end, 1); - asce = table | _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH; + asce = __pa(table) | _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH; } if (rc) { base_asce_free(asce); -- GitLab From da001fce26bec9b5933162b32b3cc65923ad6c17 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 9 Dec 2021 12:01:25 +0100 Subject: [PATCH 409/965] s390/pgalloc: use pointers instead of unsigned long values After adding the missing __va()/__pa() calls to the base asce functions there are even more casts in the code than before. Make the code more readable by passing and using pointers to page tables, instead of using unsigned values for the same purpose. This allows to get rid of nearly all casts within the code. Suggested-by: Alexander Gordeev Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/pgalloc.c | 64 +++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 2e33dfb38a76f..82a2617362d58 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -322,34 +322,34 @@ void __tlb_remove_table(void *_table) static struct kmem_cache *base_pgt_cache; -static unsigned long base_pgt_alloc(void) +static unsigned long *base_pgt_alloc(void) { - u64 *table; + unsigned long *table; table = kmem_cache_alloc(base_pgt_cache, GFP_KERNEL); if (table) - memset64(table, _PAGE_INVALID, PTRS_PER_PTE); - return (unsigned long) table; + memset64((u64 *)table, _PAGE_INVALID, PTRS_PER_PTE); + return table; } -static void base_pgt_free(unsigned long table) +static void base_pgt_free(unsigned long *table) { - kmem_cache_free(base_pgt_cache, (void *) table); + kmem_cache_free(base_pgt_cache, table); } -static unsigned long base_crst_alloc(unsigned long val) +static unsigned long *base_crst_alloc(unsigned long val) { - unsigned long table; + unsigned long *table; - table = __get_free_pages(GFP_KERNEL, CRST_ALLOC_ORDER); + table = (unsigned long *)__get_free_pages(GFP_KERNEL, CRST_ALLOC_ORDER); if (table) - crst_table_init((unsigned long *)table, val); + crst_table_init(table, val); return table; } -static void base_crst_free(unsigned long table) +static void base_crst_free(unsigned long *table) { - free_pages(table, CRST_ALLOC_ORDER); + free_pages((unsigned long)table, CRST_ALLOC_ORDER); } #define BASE_ADDR_END_FUNC(NAME, SIZE) \ @@ -377,14 +377,14 @@ static inline unsigned long base_lra(unsigned long address) return real; } -static int base_page_walk(unsigned long origin, unsigned long addr, +static int base_page_walk(unsigned long *origin, unsigned long addr, unsigned long end, int alloc) { unsigned long *pte, next; if (!alloc) return 0; - pte = (unsigned long *) origin; + pte = origin; pte += (addr & _PAGE_INDEX) >> _PAGE_SHIFT; do { next = base_page_addr_end(addr, end); @@ -393,13 +393,13 @@ static int base_page_walk(unsigned long origin, unsigned long addr, return 0; } -static int base_segment_walk(unsigned long origin, unsigned long addr, +static int base_segment_walk(unsigned long *origin, unsigned long addr, unsigned long end, int alloc) { - unsigned long *ste, next, table; + unsigned long *ste, next, *table; int rc; - ste = (unsigned long *) origin; + ste = origin; ste += (addr & _SEGMENT_INDEX) >> _SEGMENT_SHIFT; do { next = base_segment_addr_end(addr, end); @@ -411,7 +411,7 @@ static int base_segment_walk(unsigned long origin, unsigned long addr, return -ENOMEM; *ste = __pa(table) | _SEGMENT_ENTRY; } - table = (unsigned long)__va(*ste & _SEGMENT_ENTRY_ORIGIN); + table = __va(*ste & _SEGMENT_ENTRY_ORIGIN); rc = base_page_walk(table, addr, next, alloc); if (rc) return rc; @@ -422,13 +422,13 @@ static int base_segment_walk(unsigned long origin, unsigned long addr, return 0; } -static int base_region3_walk(unsigned long origin, unsigned long addr, +static int base_region3_walk(unsigned long *origin, unsigned long addr, unsigned long end, int alloc) { - unsigned long *rtte, next, table; + unsigned long *rtte, next, *table; int rc; - rtte = (unsigned long *) origin; + rtte = origin; rtte += (addr & _REGION3_INDEX) >> _REGION3_SHIFT; do { next = base_region3_addr_end(addr, end); @@ -440,7 +440,7 @@ static int base_region3_walk(unsigned long origin, unsigned long addr, return -ENOMEM; *rtte = __pa(table) | _REGION3_ENTRY; } - table = (unsigned long)__va(*rtte & _REGION_ENTRY_ORIGIN); + table = __va(*rtte & _REGION_ENTRY_ORIGIN); rc = base_segment_walk(table, addr, next, alloc); if (rc) return rc; @@ -450,13 +450,13 @@ static int base_region3_walk(unsigned long origin, unsigned long addr, return 0; } -static int base_region2_walk(unsigned long origin, unsigned long addr, +static int base_region2_walk(unsigned long *origin, unsigned long addr, unsigned long end, int alloc) { - unsigned long *rste, next, table; + unsigned long *rste, next, *table; int rc; - rste = (unsigned long *) origin; + rste = origin; rste += (addr & _REGION2_INDEX) >> _REGION2_SHIFT; do { next = base_region2_addr_end(addr, end); @@ -468,7 +468,7 @@ static int base_region2_walk(unsigned long origin, unsigned long addr, return -ENOMEM; *rste = __pa(table) | _REGION2_ENTRY; } - table = (unsigned long)__va(*rste & _REGION_ENTRY_ORIGIN); + table = __va(*rste & _REGION_ENTRY_ORIGIN); rc = base_region3_walk(table, addr, next, alloc); if (rc) return rc; @@ -478,13 +478,13 @@ static int base_region2_walk(unsigned long origin, unsigned long addr, return 0; } -static int base_region1_walk(unsigned long origin, unsigned long addr, +static int base_region1_walk(unsigned long *origin, unsigned long addr, unsigned long end, int alloc) { - unsigned long *rfte, next, table; + unsigned long *rfte, next, *table; int rc; - rfte = (unsigned long *) origin; + rfte = origin; rfte += (addr & _REGION1_INDEX) >> _REGION1_SHIFT; do { next = base_region1_addr_end(addr, end); @@ -496,7 +496,7 @@ static int base_region1_walk(unsigned long origin, unsigned long addr, return -ENOMEM; *rfte = __pa(table) | _REGION1_ENTRY; } - table = (unsigned long)__va(*rfte & _REGION_ENTRY_ORIGIN); + table = __va(*rfte & _REGION_ENTRY_ORIGIN); rc = base_region2_walk(table, addr, next, alloc); if (rc) return rc; @@ -515,7 +515,7 @@ static int base_region1_walk(unsigned long origin, unsigned long addr, */ void base_asce_free(unsigned long asce) { - unsigned long table = (unsigned long)__va(asce & _ASCE_ORIGIN); + unsigned long *table = __va(asce & _ASCE_ORIGIN); if (!asce) return; @@ -567,7 +567,7 @@ static int base_pgt_cache_init(void) */ unsigned long base_asce_alloc(unsigned long addr, unsigned long num_pages) { - unsigned long asce, table, end; + unsigned long asce, *table, end; int rc; if (base_pgt_cache_init()) -- GitLab From 7a334a28a14bf8b8812bb2e626a6280ad0d21f4e Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 2 Dec 2021 20:58:07 +0100 Subject: [PATCH 410/965] s390/ap: add missing virt_to_phys address conversion The address of the notification-indicator byte is an absolute address. Therefore convert its virtual to a physical address before being used with PQAP(AQIC). Note: this currently doesn't fix a real bug, since virtual addresses are indentical to physical ones. Reviewed-by: Alexander Gordeev Reviewed-by: Harald Freudenberger Signed-off-by: Heiko Carstens --- arch/s390/include/asm/ap.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index 3afbee21dc1f1..c0c8a1f6c35d9 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -12,6 +12,8 @@ #ifndef _ASM_S390_AP_H_ #define _ASM_S390_AP_H_ +#include + /** * The ap_qid_t identifier of an ap queue. * If the AP facilities test (APFT) facility is available, @@ -238,7 +240,7 @@ static inline struct ap_queue_status ap_aqic(ap_qid_t qid, struct ap_qirq_ctrl qirqctrl; struct ap_queue_status status; } reg1; - void *reg2 = ind; + unsigned long reg2 = virt_to_phys(ind); reg1.qirqctrl = qirqctrl; -- GitLab From 61646ca83d3889696f2772edaff122dd96a2935e Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 8 Dec 2021 20:34:56 -0800 Subject: [PATCH 411/965] x86/uaccess: Move variable into switch case statement When building with automatic stack variable initialization, GCC 12 complains about variables defined outside of switch case statements. Move the variable into the case that uses it, which silences the warning: ./arch/x86/include/asm/uaccess.h:317:23: warning: statement will never be executed [-Wswitch-unreachable] 317 | unsigned char x_u8__; \ | ^~~~~~ Fixes: 865c50e1d279 ("x86/uaccess: utilize CONFIG_CC_HAS_ASM_GOTO_OUTPUT") Signed-off-by: Kees Cook Signed-off-by: Dave Hansen Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211209043456.1377875-1-keescook@chromium.org --- arch/x86/include/asm/uaccess.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 33a68407def3f..8ab9e79abb2b4 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -314,11 +314,12 @@ do { \ do { \ __chk_user_ptr(ptr); \ switch (size) { \ - unsigned char x_u8__; \ - case 1: \ + case 1: { \ + unsigned char x_u8__; \ __get_user_asm(x_u8__, ptr, "b", "=q", label); \ (x) = x_u8__; \ break; \ + } \ case 2: \ __get_user_asm(x, ptr, "w", "=r", label); \ break; \ -- GitLab From 20735d24adfe73c62f9482ae5b4f29cc5e00bbe8 Mon Sep 17 00:00:00 2001 From: Shaokun Zhang Date: Thu, 9 Dec 2021 09:55:50 +0800 Subject: [PATCH 412/965] x86/fpu: Remove duplicate copy_fpstate_to_sigframe() prototype The function prototype of copy_fpstate_to_sigframe() is declared twice in 0ae67cc34f76 ("x86/fpu: Remove internal.h dependency from fpu/signal.h"). Remove one of them. [ bp: Massage ] Signed-off-by: Shaokun Zhang Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211209015550.51916-1-zhangshaokun@hisilicon.com --- arch/x86/include/asm/fpu/signal.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/x86/include/asm/fpu/signal.h b/arch/x86/include/asm/fpu/signal.h index 22b0273a8bf1e..e1c9df9102a59 100644 --- a/arch/x86/include/asm/fpu/signal.h +++ b/arch/x86/include/asm/fpu/signal.h @@ -41,7 +41,4 @@ extern void fpu__clear_user_states(struct fpu *fpu); extern bool fpu__restore_sig(void __user *buf, int ia32_frame); extern void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask); - -extern bool copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); - #endif /* _ASM_X86_FPU_SIGNAL_H */ -- GitLab From a3a5b763410c7bceacf41a52071134d9dc26202a Mon Sep 17 00:00:00 2001 From: Yunfeng Ye Date: Thu, 9 Dec 2021 09:42:25 +0800 Subject: [PATCH 413/965] arm64: mm: Rename asid2idx() to ctxid2asid() The commit 0c8ea531b774 ("arm64: mm: Allocate ASIDs in pairs") introduce the asid2idx and idx2asid macro, but these macros are not really useful after the commit f88f42f853a8 ("arm64: context: Free up kernel ASIDs if KPTI is not in use"). The code "(asid & ~ASID_MASK)" can be instead by a macro, which is the same code with asid2idx(). So rename it to ctxid2asid() for a better understanding. Also we add asid2ctxid() macro, the contextid can be generated based on the asid and generation through this macro. Signed-off-by: Yunfeng Ye Reviewed-by: Kefeng Wang Link: https://lore.kernel.org/r/c31516eb-6d15-94e0-421c-305fc010ea79@huawei.com Signed-off-by: Catalin Marinas --- arch/arm64/mm/context.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index cd72576ae2b76..bbc2708fe9289 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -35,8 +35,8 @@ static unsigned long *pinned_asid_map; #define ASID_FIRST_VERSION (1UL << asid_bits) #define NUM_USER_ASIDS ASID_FIRST_VERSION -#define asid2idx(asid) ((asid) & ~ASID_MASK) -#define idx2asid(idx) asid2idx(idx) +#define ctxid2asid(asid) ((asid) & ~ASID_MASK) +#define asid2ctxid(asid, genid) ((asid) | (genid)) /* Get the ASIDBits supported by the current CPU */ static u32 get_cpu_asid_bits(void) @@ -120,7 +120,7 @@ static void flush_context(void) */ if (asid == 0) asid = per_cpu(reserved_asids, i); - __set_bit(asid2idx(asid), asid_map); + __set_bit(ctxid2asid(asid), asid_map); per_cpu(reserved_asids, i) = asid; } @@ -162,7 +162,7 @@ static u64 new_context(struct mm_struct *mm) u64 generation = atomic64_read(&asid_generation); if (asid != 0) { - u64 newasid = generation | (asid & ~ASID_MASK); + u64 newasid = asid2ctxid(ctxid2asid(asid), generation); /* * If our current ASID was active during a rollover, we @@ -183,7 +183,7 @@ static u64 new_context(struct mm_struct *mm) * We had a valid ASID in a previous life, so try to re-use * it if possible. */ - if (!__test_and_set_bit(asid2idx(asid), asid_map)) + if (!__test_and_set_bit(ctxid2asid(asid), asid_map)) return newasid; } @@ -209,7 +209,7 @@ static u64 new_context(struct mm_struct *mm) set_asid: __set_bit(asid, asid_map); cur_idx = asid; - return idx2asid(asid) | generation; + return asid2ctxid(asid, generation); } void check_and_switch_context(struct mm_struct *mm) @@ -300,13 +300,13 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) } nr_pinned_asids++; - __set_bit(asid2idx(asid), pinned_asid_map); + __set_bit(ctxid2asid(asid), pinned_asid_map); refcount_set(&mm->context.pinned, 1); out_unlock: raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); - asid &= ~ASID_MASK; + asid = ctxid2asid(asid); /* Set the equivalent of USER_ASID_BIT */ if (asid && arm64_kernel_unmapped_at_el0()) @@ -327,7 +327,7 @@ void arm64_mm_context_put(struct mm_struct *mm) raw_spin_lock_irqsave(&cpu_asid_lock, flags); if (refcount_dec_and_test(&mm->context.pinned)) { - __clear_bit(asid2idx(asid), pinned_asid_map); + __clear_bit(ctxid2asid(asid), pinned_asid_map); nr_pinned_asids--; } -- GitLab From 386a74677be13175b5626f094ef37808c45f48b8 Mon Sep 17 00:00:00 2001 From: Yunfeng Ye Date: Thu, 9 Dec 2021 09:46:03 +0800 Subject: [PATCH 414/965] arm64: mm: Use asid feature macro for cheanup The commit 95b54c3e4c92 ("KVM: arm64: Add feature register flag definitions") introduce the ID_AA64MMFR0_ASID_8 and ID_AA64MMFR0_ASID_16 macros. We can use these macros for cheanup in get_cpu_asid_bits(). No functional change. Signed-off-by: Yunfeng Ye Reviewed-by: Kefeng Wang Link: https://lore.kernel.org/r/f71c75d3-735e-b32a-8414-b3e513c77240@huawei.com Signed-off-by: Catalin Marinas --- arch/arm64/mm/context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index bbc2708fe9289..b8b4cf0bcf39b 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -50,10 +50,10 @@ static u32 get_cpu_asid_bits(void) pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", smp_processor_id(), fld); fallthrough; - case 0: + case ID_AA64MMFR0_ASID_8: asid = 8; break; - case 2: + case ID_AA64MMFR0_ASID_16: asid = 16; } -- GitLab From bc7aaf52f963674690510e6c1f3710cd0394b25e Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 19 Nov 2021 09:53:25 -0800 Subject: [PATCH 415/965] x86/boot/string: Add missing function prototypes Silence "warning: no previous prototype for ... [-Wmissing-prototypes]" warnings from string.h when building under W=1. [ bp: Clarify commit message. ] Signed-off-by: Kees Cook Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211119175325.3668419-1-keescook@chromium.org --- arch/x86/boot/string.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/boot/string.h b/arch/x86/boot/string.h index a232da487cd20..e5d2c6b8c2f1d 100644 --- a/arch/x86/boot/string.h +++ b/arch/x86/boot/string.h @@ -8,8 +8,10 @@ #undef memcmp void *memcpy(void *dst, const void *src, size_t len); +void *memmove(void *dst, const void *src, size_t len); void *memset(void *dst, int c, size_t len); int memcmp(const void *s1, const void *s2, size_t len); +int bcmp(const void *s1, const void *s2, size_t len); /* Access builtin version by default. */ #define memcpy(d,s,l) __builtin_memcpy(d,s,l) @@ -25,6 +27,7 @@ extern size_t strnlen(const char *s, size_t maxlen); extern unsigned int atou(const char *s); extern unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); +long simple_strtol(const char *cp, char **endp, unsigned int base); int kstrtoull(const char *s, unsigned int base, unsigned long long *res); int boot_kstrtoul(const char *s, unsigned int base, unsigned long *res); -- GitLab From 2e4dbcf7177e5dd1f7cb53c59cb2f394e35fd7ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Dec 2021 13:03:12 +0100 Subject: [PATCH 416/965] arm64: dts: rockchip: Change pwm pinctrl-name to "default" on rk356x The pinctrl state "active" is neither documented nor used by the PWM driver. Rename it to "default" Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20211208120312.3300390-1-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 46d9552f60284..29e8516ef0cb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -269,7 +269,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -280,7 +280,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -291,7 +291,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -302,7 +302,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -951,7 +951,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -962,7 +962,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -973,7 +973,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -984,7 +984,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -995,7 +995,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1006,7 +1006,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1017,7 +1017,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1028,7 +1028,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1039,7 +1039,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1050,7 +1050,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1061,7 +1061,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1072,7 +1072,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; -- GitLab From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:08 +0100 Subject: [PATCH 417/965] arm64: dts: rockchip: Add spi nodes on rk356x This adds the four spi nodes (spi0, spi1, spi2, spi3) to the rk356x dtsi. These are from the downstream device tree, though I have double-checked that their interrupts and DMA numbers are correct. I have also tested spi1 with an SPI device. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 29e8516ef0cb9..a68033a239750 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -39,6 +39,10 @@ serial7 = &uart7; serial8 = &uart8; serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; }; cpus { @@ -742,6 +746,66 @@ clock-names = "tclk", "pclk"; }; + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@fe650000 { compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; reg = <0x0 0xfe650000 0x0 0x100>; -- GitLab From ea1847c09c34234c2980b99b6bb732a55447c33f Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:09 +0100 Subject: [PATCH 418/965] arm64: dts: rockchip: Add spi1 pins on Quartz64 A The Quartz64 Model A has the SPI pins broken out on its pin header. The actual pins being used though are not the m0 variant, but the m1 variant, which also lacks the cs1 pin. This commit overrides pinctrl-0 accordingly for this board. spi1 is intentionally left disabled, as anyone wishing to add SPI devices needs to edit the dts anyway, and the pins are more useful as GPIOs for the rest of the users. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-4-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4d4b2a301b1a4..166399b7f13f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -509,6 +509,11 @@ status = "okay"; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; -- GitLab From d824dade33bfe464a5304f1772de8735a46eec7c Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:44:59 +0900 Subject: [PATCH 419/965] dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop A few devices (DCP/DCPEXT) need to have the minimum power state for auto-PM configured. Add a property that allows the DT to specify this value. Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 5056d08b82610..19a194980142c 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -61,6 +61,14 @@ properties: Forces this power domain to always be powered up. type: boolean + apple,min-state: + description: + Specifies the minimum power state for auto-PM. + 0 = power gated, 4 = clock gated, 15 = on. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + required: - compatible - reg -- GitLab From 34e5719e1c6bcdc585731cbe6af11497aafaa1a6 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:45:01 +0900 Subject: [PATCH 420/965] arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes This is required for DCP to boot successfully; it seems if power gating is allowed, they do not wake up properly. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index 1310be74df1dd..fc51bc8724688 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -665,6 +665,7 @@ #reset-cells = <0>; label = "dispext_cpu0"; power-domains = <&ps_dispext_fe>; + apple,min-state = <4>; }; ps_jpg: power-controller@3c0 { @@ -1005,6 +1006,7 @@ label = "disp0_cpu0"; power-domains = <&ps_disp0_fe>; apple,always-on; /* TODO: figure out if we can enable PM here */ + apple,min-state = <4>; }; }; -- GitLab From cc1fe1e54ba565aaec0006796db65b7c3b1ccd69 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:45:00 +0900 Subject: [PATCH 421/965] soc: apple: apple-pmgr-pwrstate: Add auto-PM min level support This is seemingly required for DCP/DCPEXT, without which they refuse to boot properly. They need to be set to minimum state 4 (clock gated). Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- drivers/soc/apple/apple-pmgr-pwrstate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/soc/apple/apple-pmgr-pwrstate.c b/drivers/soc/apple/apple-pmgr-pwrstate.c index 8ad9d5fdefbfb..e1122288409ab 100644 --- a/drivers/soc/apple/apple-pmgr-pwrstate.c +++ b/drivers/soc/apple/apple-pmgr-pwrstate.c @@ -20,6 +20,7 @@ #define APPLE_PMGR_RESET BIT(31) #define APPLE_PMGR_AUTO_ENABLE BIT(28) #define APPLE_PMGR_PS_AUTO GENMASK(27, 24) +#define APPLE_PMGR_PS_MIN GENMASK(19, 16) #define APPLE_PMGR_PARENT_OFF BIT(11) #define APPLE_PMGR_DEV_DISABLE BIT(10) #define APPLE_PMGR_WAS_CLKGATED BIT(9) @@ -42,6 +43,7 @@ struct apple_pmgr_ps { struct reset_controller_dev rcdev; struct regmap *regmap; u32 offset; + u32 min_state; }; #define genpd_to_apple_pmgr_ps(_genpd) container_of(_genpd, struct apple_pmgr_ps, genpd) @@ -224,6 +226,11 @@ static int apple_pmgr_ps_probe(struct platform_device *pdev) ps->genpd.power_on = apple_pmgr_ps_power_on; ps->genpd.power_off = apple_pmgr_ps_power_off; + ret = of_property_read_u32(node, "apple,min-state", &ps->min_state); + if (ret == 0 && ps->min_state <= APPLE_PMGR_PS_ACTIVE) + regmap_update_bits(regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_PS_MIN, + FIELD_PREP(APPLE_PMGR_PS_MIN, ps->min_state)); + active = apple_pmgr_ps_is_active(ps); if (of_property_read_bool(node, "apple,always-on")) { ps->genpd.flags |= GENPD_FLAG_ALWAYS_ON; -- GitLab From e15b8c8563983c134869890d7a88aada33c52885 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:58 +0900 Subject: [PATCH 422/965] dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles This adds the initial apple,t6000 platforms: - apple,j314s - MacBook Pro (14-inch, M1 Pro, 2021) - apple,j316s - MacBook Pro (16-inch, M1 Pro, 2021) And the initial apple,t6001 platforms: - apple,j314c - MacBook Pro (14-inch, M1 Max, 2021) - apple,j316c - MacBook Pro (16-inch, M1 Max, 2021) Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/arm/apple.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index b23c8dc5a27d4..8d93e8a6cc184 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -19,6 +19,13 @@ description: | - MacBook Air (M1, 2020) - iMac (24-inch, M1, 2021) + And devices based on the "M1 Pro" and "M1 Max" SoCs: + + - MacBook Pro (14-inch, M1 Pro, 2021) + - MacBook Pro (14-inch, M1 Max, 2021) + - MacBook Pro (16-inch, M1 Pro, 2021) + - MacBook Pro (16-inch, M1 Max, 2021) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -60,6 +67,20 @@ properties: - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms + items: + - enum: + - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021) + - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021) + - const: apple,t6000 + - const: apple,arm-platform + - description: Apple M1 Max SoC based platforms + items: + - enum: + - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021) + - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021) + - const: apple,t6001 + - const: apple,arm-platform additionalProperties: true -- GitLab From b66652c7517c80873258a00cccf56a2d133a5efe Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:59 +0900 Subject: [PATCH 423/965] dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible This block is compatible with t8103, so just add the new per-SoC compatible under apple,i2c. Reviewed-by: Mark Kettenis Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 47dd6c107a6d0..4ac61fec90e26 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -21,7 +21,9 @@ allOf: properties: compatible: items: - - const: apple,t8103-i2c + - enum: + - apple,t8103-i2c + - apple,t6000-i2c - const: apple,i2c reg: -- GitLab From 42c2366a9cbedc32921f0e53e14b7bef1d536514 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:00 +0900 Subject: [PATCH 424/965] dt-bindings: pci: apple,pcie: Add t6000 support This new SoC is compatible with the existing driver, but the block supports 4 downstream ports, so we need to adjust the binding to allow that. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/pci/apple,pcie.yaml | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index ef1d424ec2992..7f01e15fc81c2 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -28,19 +28,17 @@ description: | distributed over the root ports as the OS sees fit by programming the PCIe controller's port registers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/interrupt-controller/msi-controller.yaml# - properties: compatible: items: - - const: apple,t8103-pcie + - enum: + - apple,t8103-pcie + - apple,t6000-pcie - const: apple,pcie reg: minItems: 3 - maxItems: 5 + maxItems: 6 reg-names: minItems: 3 @@ -50,6 +48,7 @@ properties: - const: port0 - const: port1 - const: port2 + - const: port3 ranges: minItems: 2 @@ -59,7 +58,7 @@ properties: description: Interrupt specifiers, one for each root port. minItems: 1 - maxItems: 3 + maxItems: 4 msi-parent: true @@ -81,6 +80,21 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8103-pcie + then: + properties: + reg: + maxItems: 5 + interrupts: + maxItems: 3 + examples: - | #include -- GitLab From cba9c615bec18792c32cc95f478884e24de9d1a5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:01 +0900 Subject: [PATCH 425/965] dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible This new SoC uses the same pinctrl hardware, so just add a new per-SoC compatible. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 200d411621e7a..572923d7023e5 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: items: - - const: apple,t8103-pinctrl + - enum: + - apple,t8103-pinctrl + - apple,t6000-pinctrl - const: apple,pinctrl reg: -- GitLab From b4d11106d751a455154edf997891de0428f48a87 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Sat, 11 Dec 2021 13:40:44 +0100 Subject: [PATCH 426/965] arm64: dts: apple: t8103: Add watchdog node Add the watchdog node which also enables reboot support on the t8103. Signed-off-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8d1628e0b0c70..8203c60d4819c 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -324,6 +324,14 @@ ; }; + wdt: watchdog@23d2b0000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x2 0x3d2b0000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; -- GitLab From a39891a6e420daeb55abc99cde4278511ac861d7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:38:17 +0100 Subject: [PATCH 427/965] arm64: dts: rockchip: Add missing secondary compatible for PX30 DSI Add second DSI compatible to comply with DT schema validation comming in the second patch. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20211211233818.88482-1-david@ixit.cz Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 00f50b05d55a3..f972704dfe7ab 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1072,7 +1072,7 @@ }; dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; + compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>; interrupts = ; clocks = <&cru PCLK_MIPI_DSI>; -- GitLab From f471b1b2db0819917c54099ab68349ad6a7e9e19 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 12 Nov 2021 19:53:59 +0530 Subject: [PATCH 428/965] arm64: dts: rockchip: Fix Bluetooth on ROCK Pi 4 boards This patch fixes the Bluetooth on ROCK Pi 4 boards. ROCK Pi 4 boards has BCM4345C5 and now it is supported on Mainline Linux, brcm,bcm43438-bt still working but observed the BT Audio issues with latest test. So, use the BCM4345C5 compatible and its associated properties like clock-names as lpo and max-speed. Attach vbat and vddio supply rails as well. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20211112142359.320798-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index 81bea953c891c..cec3b7b1b9474 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -46,13 +46,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index 6c63e617063c9..cf48746a3ad81 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -34,13 +34,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 0ad7b6e22f701..793d84833921a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -46,14 +46,17 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; -- GitLab From 7b9eb6cfdb784ad713024a3f8f202620ad40ba70 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 12 Dec 2021 18:49:40 +0100 Subject: [PATCH 429/965] ARM: dts: ixp4xx: Add devicetree for Gateway 7001 This adds a device tree for the Gateway 7001 AP, based on Intel IXP422. Cc: Imre Kaloz Signed-off-by: Zoltan HERPAI Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 3 +- .../boot/dts/intel-ixp42x-gateway-7001.dts | 111 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4084535c64898..7dfda6be29166 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -269,7 +269,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-gateworks-gw2348.dtb \ intel-ixp43x-gateworks-gw2358.dtb \ intel-ixp42x-netgear-wg302v2.dtb \ - intel-ixp42x-arcom-vulcan.dtb + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts new file mode 100644 index 0000000000000..a1c03c965f17b --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Gateway 7001 AP + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Gateway 7001 AP"; + compatible = "gateway,7001", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* second UART is the primary console */ + serial0 = &uart1; + serial1 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of flash + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ + <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ + <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + }; +}; -- GitLab From e522ae91b8ff7bf89d22d9322308aba1a6326996 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 21:57:53 +0200 Subject: [PATCH 430/965] dt-bindings: soc: samsung: Add Exynos USI bindings Add constants for choosing USIv2 configuration mode in device tree. Those are further used in USI driver to figure out which value to write into SW_CONF register. Also document USIv2 IP-core bindings. Signed-off-by: Sam Protsenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211204195757.8600-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/exynos-usi.yaml | 159 ++++++++++++++++++ include/dt-bindings/soc/samsung,exynos-usi.h | 17 ++ 2 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml create mode 100644 include/dt-bindings/soc/samsung,exynos-usi.h diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml new file mode 100644 index 0000000000000..0af4821fae5e4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's Exynos USI (Universal Serial Interface) binding + +maintainers: + - Sam Protsenko + - Krzysztof Kozlowski + +description: | + USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). + USI shares almost all internal circuits within each protocol, so only one + protocol can be chosen at a time. USI is modeled as a node with zero or more + child nodes, each representing a serial sub-node device. The mode setting + selects which particular function will be used. + + Refer to next bindings documentation for information on protocol subnodes that + can exist under USI node: + + [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml + [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt + [3] Documentation/devicetree/bindings/spi/spi-samsung.txt + +properties: + $nodename: + pattern: "^usi@[0-9a-f]+$" + + compatible: + enum: + - samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9) + + reg: true + + clocks: true + + clock-names: true + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be phandle/offset pair. The phandle to System Register syscon node + (for the same domain where this USI controller resides) and the offset + of SW_CONF register for this USI controller. + + samsung,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects USI function (which serial protocol to use). Refer to + for valid USI mode values. + + samsung,clkreq-on: + type: boolean + description: + Enable this property if underlying protocol requires the clock to be + continuously provided without automatic gating. As suggested by SoC + manual, it should be set in case of SPI/I2C slave, UART Rx and I2C + multi-master mode. Usually this property is needed if USI mode is set + to "UART". + + This property is optional. + +patternProperties: + # All other properties should be child nodes + "^(serial|spi|i2c)@[0-9a-f]+$": + type: object + description: Child node describing underlying USI serial protocol + +required: + - compatible + - ranges + - "#address-cells" + - "#size-cells" + - samsung,sysreg + - samsung,mode + +if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + +then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol + + clock-names: + items: + - const: pclk + - const: ipclk + + required: + - reg + - clocks + - clock-names + +else: + properties: + reg: false + clocks: false + clock-names: false + samsung,clkreq-on: false + +additionalProperties: false + +examples: + - | + #include + #include + + usi0: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "pclk", "ipclk"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + hsi2c_0: i2c@13820000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x13820000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "hsi2c_pclk", "hsi2c"; + status = "disabled"; + }; + }; diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h new file mode 100644 index 0000000000000..a01af169d2498 --- /dev/null +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko + * + * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). + */ + +#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H +#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H + +#define USI_V2_NONE 0 +#define USI_V2_UART 1 +#define USI_V2_SPI 2 +#define USI_V2_I2C 3 + +#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ -- GitLab From 7836149e155bd3c554571f135619f95932c841fc Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 8 Dec 2021 18:18:53 +0900 Subject: [PATCH 431/965] arm64: dts: exynos: convert serial_0 to USI on ExynosAutov9 According to USI v2 driver change[1], serial_0 node should be converted to use the USI node hierarchy. syscon_peric0 will be used as a syscon node to control the USI00_USI_SW_CONF register. This also changes the serial node name from uart@ to serial@. [1]: https://lore.kernel.org/linux-samsung-soc/20211204195757.8600-2-semen.protsenko@linaro.org/ Cc: Sam Protsenko Signed-off-by: Chanho Park Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211208091853.8557-1-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynosautov9-sadk.dts | 4 +++ arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 36 ++++++++++++++----- 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index ef46d7aa6e281..57518cb5e8c46 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -54,3 +54,7 @@ vcc-supply = <&ufs_0_fixed_vcc_reg>; vcc-fixed-regulator; }; + +&usi_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 3e4727344b4ac..0fab0aa4db3fa 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -7,6 +7,7 @@ */ #include +#include / { compatible = "samsung,exynosautov9"; @@ -256,16 +257,35 @@ reg = <0x17c20000 0x1000>; }; - /* USI: UART */ - serial_0: uart@10300000 { - compatible = "samsung,exynos850-uart"; - reg = <0x10300000 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus_dual>; + syscon_peric0: syscon@10220000 { + compatible = "samsung,exynosautov9-sysreg", "syscon"; + reg = <0x10220000 0x2000>; + }; + + usi_0: usi@103000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x103000c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1000>; + samsung,mode = ; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; clocks = <&uart_clock>, <&uart_clock>; - clock-names = "uart", "clk_uart_baud0"; + clock-names = "pclk", "ipclk"; status = "disabled"; + + /* USI: UART */ + serial_0: serial@10300000 { + compatible = "samsung,exynos850-uart"; + reg = <0x10300000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus_dual>; + clocks = <&uart_clock>, <&uart_clock>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; }; ufs_0_phy: ufs0-phy@17e04000 { -- GitLab From 5e8c1bf1a0a5c728cee2b6c2162348a9dfddf1bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 30 Nov 2021 17:11:47 +0100 Subject: [PATCH 432/965] ARM: dts: bcm2711-rpi-4-b: Add gpio offsets to line name array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this helps human readers considerably to determine the line name for a given offset or vice versa. Signed-off-by: Uwe Kleine-König [ nsaenz: corrected patch title ] Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20211130161147.317653-1-u.kleine-koenig@pengutronix.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 28 +++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 631dd5baf68da..4432412044dec 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -65,12 +65,12 @@ }; &expgpio { - gpio-line-names = "BT_ON", + gpio-line-names = "BT_ON", /* 0 */ "WL_ON", "PWR_LED_OFF", "GLOBAL_RESET", "VDD_SD_IO_SEL", - "CAM_GPIO", + "CAM_GPIO", /* 5 */ "SD_PWR_ON", ""; }; @@ -84,66 +84,66 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "ID_SDA", + gpio-line-names = "ID_SDA", /* 0 */ "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", - "GPIO5", + "GPIO5", /* 5 */ "GPIO6", "SPI_CE1_N", "SPI_CE0_N", "SPI_MISO", - "SPI_MOSI", + "SPI_MOSI", /* 10 */ "SPI_SCLK", "GPIO12", "GPIO13", /* Serial port */ "TXD1", - "RXD1", + "RXD1", /* 15 */ "GPIO16", "GPIO17", "GPIO18", "GPIO19", - "GPIO20", + "GPIO20", /* 20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", - "GPIO25", + "GPIO25", /* 25 */ "GPIO26", "GPIO27", "RGMII_MDIO", "RGMIO_MDC", /* Used by BT module */ - "CTS0", + "CTS0", /* 30 */ "RTS0", "TXD0", "RXD0", /* Used by Wifi */ "SD1_CLK", - "SD1_CMD", + "SD1_CMD", /* 35 */ "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* Shared with SPI flash */ - "PWM0_MISO", + "PWM0_MISO", /* 40 */ "PWM1_MOSI", "STATUS_LED_G_CLK", "SPIFLASH_CE_N", "SDA0", - "SCL0", + "SCL0", /* 45 */ "RGMII_RXCLK", "RGMII_RXCTL", "RGMII_RXD0", "RGMII_RXD1", - "RGMII_RXD2", + "RGMII_RXD2", /* 50 */ "RGMII_RXD3", "RGMII_TXCLK", "RGMII_TXCTL", "RGMII_TXD0", - "RGMII_TXD1", + "RGMII_TXD1", /* 55 */ "RGMII_TXD2", "RGMII_TXD3"; }; -- GitLab From cf4060f1bb643495742f3630ab98a7b44fc5c0fd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 12:25:42 +0200 Subject: [PATCH 433/965] ARM: dts: at91: sama5d2: Name the qspi clock Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 801969c113d64..09c741e8ecb87 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -288,6 +288,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -299,6 +300,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- GitLab From 0081a525ceef14e950172def4af14c3f652fb4a2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:42 +0200 Subject: [PATCH 434/965] ARM: dts: at91: sama7g5: Add QSPI nodes sama7g5 embedds 2 instances of QSPI controller: 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported. 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf6788..eddcfbf4d2233 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -181,6 +181,36 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; -- GitLab From 078c2a0e8e60bb3fe78cf50b5da1620a4e13e0cd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:43 +0200 Subject: [PATCH 435/965] ARM: dts: at91: sama7g5ek: Add QSPI0 node QSPI0 comunicates with a MX66LM1G45G SPI NOR flash. Enable the controller and describe the flash. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-2-tudor.ambarus@microchip.com --- arch/arm/boot/dts/at91-sama7g5ek.dts | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0e1975c6812e2..ccf9e224da781 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -13,6 +13,7 @@ #include "sama7g5.dtsi" #include #include +#include / { model = "Microchip SAMA7G5-EK"; @@ -134,6 +135,59 @@ cpu-supply = <&vddcpu>; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + m25p,fast-read; + + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + &dma0 { status = "okay"; }; @@ -555,6 +609,25 @@ bias-disable; }; + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = , -- GitLab From 1a0ae068bf6b6f4233b1f31bf48bcbc47b111ef2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Nov 2021 11:49:56 +0100 Subject: [PATCH 436/965] m68k: defconfig: Update defconfigs for v5.16-rc1 - Drop CONFIG_MCTP=m (can no longer be modular since commit 78476d315e190533 ("mctp: Add flow extension to skb")), - Drop CONFIG_BLK_DEV_CRYPTOLOOP=m (removed in commit 47e9624616c80c98 ("block: remove support for cryptoloop and the xor transfer")). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20211115104956.2084032-1-geert@linux-m68k.org --- arch/m68k/configs/amiga_defconfig | 2 -- arch/m68k/configs/apollo_defconfig | 2 -- arch/m68k/configs/atari_defconfig | 2 -- arch/m68k/configs/bvme6000_defconfig | 2 -- arch/m68k/configs/hp300_defconfig | 2 -- arch/m68k/configs/mac_defconfig | 2 -- arch/m68k/configs/multi_defconfig | 2 -- arch/m68k/configs/mvme147_defconfig | 2 -- arch/m68k/configs/mvme16x_defconfig | 2 -- arch/m68k/configs/q40_defconfig | 2 -- arch/m68k/configs/sun3_defconfig | 2 -- arch/m68k/configs/sun3x_defconfig | 2 -- 12 files changed, 24 deletions(-) diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig index e2b14ea993423..a4b6c71084657 100644 --- a/arch/m68k/configs/amiga_defconfig +++ b/arch/m68k/configs/amiga_defconfig @@ -302,7 +302,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -317,7 +316,6 @@ CONFIG_PARPORT_1284=y CONFIG_AMIGA_FLOPPY=y CONFIG_AMIGA_Z2RAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig index 41f3f3b738b3e..2db7219655202 100644 --- a/arch/m68k/configs/apollo_defconfig +++ b/arch/m68k/configs/apollo_defconfig @@ -298,7 +298,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -307,7 +306,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig index 3fd0ea135886b..c266a704eecdc 100644 --- a/arch/m68k/configs/atari_defconfig +++ b/arch/m68k/configs/atari_defconfig @@ -305,7 +305,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -318,7 +317,6 @@ CONFIG_PARPORT_ATARI=m CONFIG_PARPORT_1284=y CONFIG_ATARI_FLOPPY=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig index 11a19f87e5864..f644f08dd6ed8 100644 --- a/arch/m68k/configs/bvme6000_defconfig +++ b/arch/m68k/configs/bvme6000_defconfig @@ -295,7 +295,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -304,7 +303,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig index ee981271476a8..e4924650b6875 100644 --- a/arch/m68k/configs/hp300_defconfig +++ b/arch/m68k/configs/hp300_defconfig @@ -297,7 +297,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -306,7 +305,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig index a48656d328dd1..24113871ea769 100644 --- a/arch/m68k/configs/mac_defconfig +++ b/arch/m68k/configs/mac_defconfig @@ -299,7 +299,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -309,7 +308,6 @@ CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_SWIM=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig index b9b7a5cc6a1e6..6a7e4be70eea9 100644 --- a/arch/m68k/configs/multi_defconfig +++ b/arch/m68k/configs/multi_defconfig @@ -319,7 +319,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -338,7 +337,6 @@ CONFIG_ATARI_FLOPPY=y CONFIG_BLK_DEV_SWIM=m CONFIG_AMIGA_Z2RAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig index 3887b1c9c5fdc..1d223247aff08 100644 --- a/arch/m68k/configs/mvme147_defconfig +++ b/arch/m68k/configs/mvme147_defconfig @@ -294,7 +294,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -303,7 +302,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig index 19e5992bba6ca..961f789f96c94 100644 --- a/arch/m68k/configs/mvme16x_defconfig +++ b/arch/m68k/configs/mvme16x_defconfig @@ -295,7 +295,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -304,7 +303,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig index af25efaa32967..ff4b5e469390b 100644 --- a/arch/m68k/configs/q40_defconfig +++ b/arch/m68k/configs/q40_defconfig @@ -296,7 +296,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -308,7 +307,6 @@ CONFIG_PARPORT=m CONFIG_PARPORT_PC=m CONFIG_PARPORT_1284=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig index 14dd96d3f5efd..5f228621d0ccb 100644 --- a/arch/m68k/configs/sun3_defconfig +++ b/arch/m68k/configs/sun3_defconfig @@ -292,7 +292,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -301,7 +300,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig index 8ac2402ac334a..a600cb9e68c25 100644 --- a/arch/m68k/configs/sun3x_defconfig +++ b/arch/m68k/configs/sun3x_defconfig @@ -292,7 +292,6 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_AF_KCM=m -CONFIG_MCTP=m # CONFIG_WIRELESS is not set CONFIG_PSAMPLE=m CONFIG_NET_IFE=m @@ -301,7 +300,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y -- GitLab From 277ee96f89d806f110e3011ea324155dd69e798f Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 17 Nov 2021 11:08:06 +0530 Subject: [PATCH 437/965] arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level Disable mcasp nodes 0-2 because several required properties are not present in the dtsi file as they are board specific. These nodes can be enabled via an overlay whenever required. Signed-off-by: Jayesh Choudhary Signed-off-by: Vignesh Raghavendra Acked-by: Jan Kiszka Link: https://lore.kernel.org/r/20211117053806.10095-1-j-choudhary@ti.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 1e0112b90d9fe..3079eaee01c06 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -739,3 +739,15 @@ &icssg2_mdio { status = "disabled"; }; + +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; -- GitLab From a34ff76a161583d24d29816a6cce85232ea7d9d0 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 3 Dec 2021 17:39:13 +0530 Subject: [PATCH 438/965] soc: ti: k3-socinfo: Add entry for J721S2 SoC family J721S2 SoC's JTAG PARTNO is 0xBB75. Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211203120913.14737-1-a-govindraju@ti.com --- drivers/soc/ti/k3-socinfo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index fd91129de6e5b..b6b2150aca4e4 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -40,7 +40,8 @@ static const struct k3_soc_id { { 0xBB5A, "AM65X" }, { 0xBB64, "J721E" }, { 0xBB6D, "J7200" }, - { 0xBB38, "AM64X" } + { 0xBB38, "AM64X" }, + { 0xBB75, "J721S2"}, }; static int -- GitLab From 5d7248e956e68f257b46cdfcee465792086e2c01 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:53 +0100 Subject: [PATCH 439/965] ARM: dts: spear3xx: Use plgpio regmap in SPEAr310 and SPEAr320 Resources used by plgpio and pinmux are conflicting on SPEAr310 and SPEAr320. Use the newly introduced regmap property in plgpio node to use pinmux resources from plgpio and so avoid the conflict. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-5-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear310.dtsi | 1 + arch/arm/boot/dts/spear320.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index 8ce751a1376dd..77570833d46b2 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -92,6 +92,7 @@ gpiopinctrl: gpio@b4000000 { compatible = "st,spear-plgpio"; reg = <0xb4000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 3bc1e93a0a550..47ac4474ed96e 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -120,6 +120,7 @@ gpiopinctrl: gpio@b3000000 { compatible = "st,spear-plgpio"; reg = <0xb3000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; -- GitLab From 7cf4cc3e8524989f9f1619ba49726576a46ee32d Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:55 +0100 Subject: [PATCH 440/965] ARM: dts: spear3xx: Add spear320s dtsi The SPEAr320s SOC is a SPEAr320 SOC variant. Mostly identical to the SPEAr320 SOC variant, it has a new interrupt routing for PL_PGIOs. Add spear320s.dtsi to handle SPEAr320s SOC Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear320s.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/spear320s.dtsi diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/spear320s.dtsi new file mode 100644 index 0000000000000..133236dc190d8 --- /dev/null +++ b/arch/arm/boot/dts/spear320s.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320s SoC + * + * Copyright 2021 Herve Codina + */ + +/include/ "spear320.dtsi" + +/ { + ahb { + apb { + gpiopinctrl: gpio@b3000000 { + /* + * The "RM0321 SPEAr320s address and map + * registers" document mentions interrupt 6 + * (NPGIO_INTR) for the PL_GPIO interrupt. + */ + interrupts = <6>; + interrupt-parent = <&shirq>; + }; + }; + }; +}; -- GitLab From bd943653b10dc9df63ad6cb69f520c10f3f21372 Mon Sep 17 00:00:00 2001 From: Julian Ribbeck Date: Tue, 16 Nov 2021 21:07:34 +0100 Subject: [PATCH 441/965] arm64: dts: qcom: Add device tree for Samsung J5 2015 (samsung-j5) Samsung J5 2015 is a MSM8916 based Smartphone. It is similar to some of the other MSM8916 devices, especially the Samsung ones. With this patch initial support for the following is added: - eMMC/SD card - Buttons - USB (although no suiting MUIC driver currently) - UART (untested for lack of equipment) - WiFi/Bluetooth (WCNSS) It is worth noting that Samsung J5 with MSM8916 exists in different generations (e.g Samsung J5 2015 and Samsung J5 2016) which each have different models (e.g. samsung-j5nlte, samsung-j5xnlte, etc). This patch is only regarding the 2015 generation, but should work with all of it's models, as far as we could test. Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Signed-off-by: Julian Ribbeck Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211116200734.73920-1-julian.ribbeck@gmx.de --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-samsung-j5.dts | 209 ++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7f26ec20d2384..693b30c51e33d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts new file mode 100644 index 0000000000000..687bea438a571 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include + +/ { + model = "Samsung Galaxy J5 (2015)"; + compatible = "samsung,j5", "qcom,msm8916"; + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home-key { + lable = "Home Key"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +/* FIXME: Replace with SM5703 MUIC when driver is available */ +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + dr_mode = "peripheral"; + extcon = <&pm8916_usbin>; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; + qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; -- GitLab From 6b1caf4dea3e0a961b7a11cff6757ff74c1c34ea Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:00 +0530 Subject: [PATCH 442/965] dt-bindings: arm: ti: Add bindings for J721s2 SoC Add binding for J721S2 SoC Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211207080904.14324-2-a-govindraju@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index cf327230fc0e2..b03c10fa2e7a0 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -53,6 +53,12 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 J721s2 SoC + items: + - enum: + - ti,j721s2-evm + - const: ti,j721s2 + additionalProperties: true ... -- GitLab From beba81faad86fc2bad567b1c029d6a000a43ca78 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:01 +0530 Subject: [PATCH 443/965] dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211207080904.14324-3-a-govindraju@ti.com --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b2839..63e038e36ca3c 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -38,4 +38,7 @@ #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- GitLab From b8545f9d3a5426a5f76814c8aaebc5cb46a3213a Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:02 +0530 Subject: [PATCH 444/965] arm64: dts: ti: Add initial support for J721S2 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 937 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 302 ++++++ arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 189 ++++ 3 files changed, 1428 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi new file mode 100644 index 0000000000000..b04db1d3ab617 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -0,0 +1,937 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family Main Domain peripherals + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x400000>; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + + tifs-sram@1f0000 { + reg = <0x1f0000 0x10000>; + }; + + l3cache-sram@200000 { + reg = <0x200000 0x200000>; + }; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>; /* GICR */ + + /* vcpumntirq: virtual CPU interface maintenance interrupt */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <148>; + ti,interrupt-ranges = <8 360 56>; + }; + + main_pmx0: pinctrl@11c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x0 0x11c000 0x0 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 146 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 350 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 351 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 352 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 353 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 354 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 355 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 356 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 357 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 358 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, <149>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 111 0>; + clock-names = "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, <158>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 112 0>; + clock-names = "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, <167>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, <176>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "gpio"; + }; + + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 214 1>; + clock-names = "fck"; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c1: i2c@2010000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 215 1>; + clock-names = "fck"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c2: i2c@2020000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 216 1>; + clock-names = "fck"; + power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c3: i2c@2030000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 217 1>; + clock-names = "fck"; + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c4: i2c@2040000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02040000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 218 1>; + clock-names = "fck"; + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c5: i2c@2050000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02050000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 219 1>; + clock-names = "fck"; + power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c6: i2c@2060000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02060000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 220 1>; + clock-names = "fck"; + power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + }; + + main_sdhci0: mmc@4f80000 { + compatible = "ti,j721e-sdhci-8bit"; + reg = <0x00 0x04f80000 0x00 0x1000>, + <0x00 0x04f88000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 98 1>; + assigned-clock-parents = <&k3_clks 98 2>; + bus-width = <8>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + dma-coherent; + }; + + main_sdhci1: mmc@4fb0000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x00 0x04fb0000 0x00 0x1000>, + <0x00 0x04fb8000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 99 1>; + assigned-clock-parents = <&k3_clks 99 2>; + bus-width = <4>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; + /* Masking support for SDR104 capability */ + sdhci-caps-mask = <0x00000003 0x00000000>; + }; + + main_navss: bus@30000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <224>; + dma-coherent; + dma-ranges; + + main_navss_intr: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x310e0000 0x00 0x4000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <227>; + ti,interrupt-ranges = <0 64 64>, + <64 448 64>, + <128 672 64>; + }; + + main_udmass_inta: msi-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x33d00000 0x00 0x100000>; + interrupt-controller; + #interrupt-cells = <0>; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&sms>; + ti,sci-dev-id = <265>; + ti,interrupt-ranges = <0 0 256>; + }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + hwspinlock: spinlock@30e00000 { + compatible = "ti,am654-hwspinlock"; + reg = <0x00 0x30e00000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster0: mailbox@31f90000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f90000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster1: mailbox@31f91000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f91000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster2: mailbox@31f92000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f92000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster3: mailbox@31f93000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f93000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster4: mailbox@31f94000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f94000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster5: mailbox@31f95000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f95000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster6: mailbox@31f96000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f96000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster7: mailbox@31f97000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f97000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster8: mailbox@31f98000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f98000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster9: mailbox@31f99000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f99000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster10: mailbox@31f9a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster11: mailbox@31f9b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <259>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x80000>, + <0x0 0x35000000 0x0 0x200000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <263>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 226 5>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; + }; + + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi new file mode 100644 index 0000000000000..7521963719ff9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu_wakeup { + sms: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x00 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x00 0x43000014 0x00 0x4>; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x100000>; + ranges = <0x00 0x00 0x41c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wkup_pmx0: pinctrl@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x178>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_gpio_intr: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <125>; + ti,interrupt-ranges = <16 928 16>; + }; + + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 359 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 149 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + }; + + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 115 0>; + clock-names = "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 116 0>; + clock-names = "gpio"; + }; + + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x42120000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 223 1>; + clock-names = "fck"; + power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b00000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 221 1>; + clock-names = "fck"; + power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_i2c1: i2c@40b10000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b10000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 222 1>; + clock-names = "fck"; + power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_navss: bus@28380000{ + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <267>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <272>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <273>; + ti,ringacc = <&mcu_ringacc>; + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 29 28>; + clock-names = "fck"; + power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 29 28>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 29 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi new file mode 100644 index 0000000000000..80d3cae03e885 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family + * + * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include +#include + +/ { + + model = "Texas Instruments K3 J721S2 SoC"; + compatible = "ti,j721s2"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart3; + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; + serial9 = &main_uart7; + serial10 = &main_uart8; + serial11 = &main_uart9; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + can0 = &main_mcan16; + can1 = &mcu_mcan0; + can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; + }; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + + }; + + pmu: pmu { + compatible = "arm,cortex-a72-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; + + cbass_main: bus@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ + <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: bus@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ + + }; + + }; +}; + +/* Now include peripherals from each bus segment */ +#include "k3-j721s2-main.dtsi" +#include "k3-j721s2-mcu-wakeup.dtsi" -- GitLab From d502f852d22af1ca33e7a2fedd7426831f6dbaef Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:03 +0530 Subject: [PATCH 445/965] arm64: dts: ti: Add initial support for J721S2 System on Module A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. SoM: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-5-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 175 +++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi new file mode 100644 index 0000000000000..76f0ceacb6d46 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SoM: https://www.ti.com/lit/zip/sprr439 + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721s2.dtsi" +#include + +/ { + memory@80000000 { + device_type = "memory"; + /* 16 GB RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x03 0x80000000>; + }; + + /* Reserving memory regions still pending */ + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mcan16_pins_default: main-mcan16-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ + >; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp_som: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", + "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", + "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", + "GPIO_LIN_EN", "CAN_STB"; + }; +}; + +&main_mcan16 { + pinctrl-0 = <&main_mcan16_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; + +&mailbox0_cluster0 { + status = "disabled"; +}; + +&mailbox0_cluster1 { + status = "disabled"; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mailbox1_cluster0 { + status = "disabled"; +}; + +&mailbox1_cluster1 { + status = "disabled"; +}; + +&mailbox1_cluster2 { + status = "disabled"; +}; + +&mailbox1_cluster3 { + status = "disabled"; +}; + +&mailbox1_cluster4 { + status = "disabled"; +}; + +&mailbox1_cluster5 { + status = "disabled"; +}; + +&mailbox1_cluster6 { + status = "disabled"; +}; + +&mailbox1_cluster7 { + status = "disabled"; +}; + +&mailbox1_cluster8 { + status = "disabled"; +}; + +&mailbox1_cluster9 { + status = "disabled"; +}; + +&mailbox1_cluster10 { + status = "disabled"; +}; + +&mailbox1_cluster11 { + status = "disabled"; +}; -- GitLab From effb32e931dd4feb8aa3cee7b5b4ddda43c8b701 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:04 +0530 Subject: [PATCH 446/965] arch: arm64: ti: Add support J721S2 Common Processor Board The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-6-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721s2-common-proc-board.dts | 421 ++++++++++++++++++ 2 files changed, 423 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 71f6097d4621d..90be511bc4d09 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -17,5 +17,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb + dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts new file mode 100644 index 0000000000000..a5a24f9f46c58 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM + */ + +/dts-v1/; + +#include "k3-j721s2-som-p0.dtsi" +#include + +/ { + compatible = "ti,j721s2-evm", "ti,j721s2"; + model = "Texas Instruments J721S2 EVM"; + + chosen { + stdout-path = "serial10:115200n8"; + bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000"; + }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-TLV71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ + J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + >; + }; +}; + +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + +&wkup_uart0 { + status = "reserved"; +}; + +&main_uart0 { + status = "disabled"; +}; + +&main_uart1 { + status = "disabled"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; + +&main_uart7 { + status = "disabled"; +}; + +&main_uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_uart9 { + status = "disabled"; +}; + +&main_i2c0 { + clock-frequency = <400000>; + + exp1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", + "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", + "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", + "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", + "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", + "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", + "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", + "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", + "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", + "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; + }; +}; + +&main_i2c1 { + status = "disabled"; +}; + +&main_i2c2 { + status = "disabled"; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&main_i2c4 { + status = "disabled"; +}; + +&main_i2c5 { + status = "disabled"; +}; + +&main_i2c6 { + status = "disabled"; +}; + +&main_sdhci0 { + /* eMMC */ + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan0 { + status = "disabled"; +}; + +&main_mcan1 { + status = "disabled"; +}; + +&main_mcan2 { + status = "disabled"; +}; + +&main_mcan3 { + status = "disabled"; +}; + +&main_mcan4 { + status = "disabled"; +}; + +&main_mcan5 { + status = "disabled"; +}; + +&main_mcan6 { + status = "disabled"; +}; + +&main_mcan7 { + status = "disabled"; +}; + +&main_mcan8 { + status = "disabled"; +}; + +&main_mcan9 { + status = "disabled"; +}; + +&main_mcan10 { + status = "disabled"; +}; + +&main_mcan11 { + status = "disabled"; +}; + +&main_mcan12 { + status = "disabled"; +}; + +&main_mcan13 { + status = "disabled"; +}; + +&main_mcan14 { + status = "disabled"; +}; + +&main_mcan15 { + status = "disabled"; +}; + +&main_mcan17 { + status = "disabled"; +}; -- GitLab From 6f6cfa5867995c03959ce8c715e54b51cd5a1528 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Tue, 7 Dec 2021 18:32:25 +0000 Subject: [PATCH 447/965] arm64: mm: use die_kernel_fault() in do_mem_abort() If we take an unhandled fault from EL1, either: a) The xFSC handler calls die_kernel_fault() directly. In this case, die_kernel_fault() calls: pr_alert(..., msg, addr); mem_abort_decode(esr); show_pte(addr); die(); bust_spinlocks(0); do_exit(SIGKILL); b) The xFSC handler returns to do_mem_abort(), indicating failure. In this case, do_mem_abort() calls: pr_alert(..., addr); mem_abort_decode(esr); show_pte(addr); arm64_notify_die() { die(); } This inconstency is unfortunatem, and in theory in case (b) registered notifiers can prevent us from terminating the faulting thread by returning NOTIFY_STOP, whereupon we'll end up returning from the fault, replaying, and almost certainly get stuck in a livelock spewing errors into dmesg. We don't expect notifers to fix things up, since we dump state to dmesg before invoking them, so it would be more sensible to consistently terminate the thread in this case. This patch has do_mem_abort() call die_kernel_fault() for unhandled faults taken from EL1. Where we would previously have logged a messafe of the form: | Unhandled fault at ${ADDR} ... we will now log a message of the form: | Unable to handle kernel ${FAULT_NAME} at virtual address ${ADDR} ... and we will consistently terminate the thread from which the fault was taken. Signed-off-by: Mark Rutland Cc: Will Deacon Tested-by: Andrey Konovalov Acked-by: Will Deacon Link: https://lore.kernel.org/r/20211207183226.834557-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/mm/fault.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 9ae24e3b72be1..b7b9caa41bc7c 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -813,11 +813,8 @@ void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs) if (!inf->fn(far, esr, regs)) return; - if (!user_mode(regs)) { - pr_alert("Unhandled fault at 0x%016lx\n", addr); - mem_abort_decode(esr); - show_pte(addr); - } + if (!user_mode(regs)) + die_kernel_fault(inf->name, addr, esr, regs); /* * At this point we have an unrecognized fault type whose tag bits may -- GitLab From 07b742a4d91260bdb61cd4cbe5ec3bba2ae7f6f9 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Tue, 7 Dec 2021 18:32:26 +0000 Subject: [PATCH 448/965] arm64: mm: log potential KASAN shadow alias When the kernel is built with KASAN_GENERIC or KASAN_SW_TAGS, shadow memory is allocated and mapped for all legitimate kernel addresses, and prior to a regular memory access instrumentation will read from the corresponding shadow address. Due to the way memory addresses are converted to shadow addresses, bogus pointers (e.g. NULL) can generate shadow addresses out of the bounds of allocated shadow memory. For example, with KASAN_GENERIC and 48-bit VAs, NULL would have a shadow address of dfff800000000000, which falls between the TTBR ranges. To make such cases easier to debug, this patch makes die_kernel_fault() dump the real memory address range for any potential KASAN shadow access using kasan_non_canonical_hook(), which results in fault information as below when KASAN is enabled: | Unable to handle kernel paging request at virtual address dfff800000000017 | KASAN: null-ptr-deref in range [0x00000000000000b8-0x00000000000000bf] | Mem abort info: | ESR = 0x96000004 | EC = 0x25: DABT (current EL), IL = 32 bits | SET = 0, FnV = 0 | EA = 0, S1PTW = 0 | FSC = 0x04: level 0 translation fault | Data abort info: | ISV = 0, ISS = 0x00000004 | CM = 0, WnR = 0 | [dfff800000000017] address between user and kernel address ranges Signed-off-by: Mark Rutland Cc: Alexander Potapenko Cc: Andrey Konovalov Cc: Andrey Ryabinin Cc: Dmitry Vyukov Cc: Will Deacon Tested-by: Andrey Konovalov Acked-by: Will Deacon Link: https://lore.kernel.org/r/20211207183226.834557-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/mm/fault.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index b7b9caa41bc7c..9a9e7675b1877 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -297,6 +297,8 @@ static void die_kernel_fault(const char *msg, unsigned long addr, pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, addr); + kasan_non_canonical_hook(addr); + mem_abort_decode(esr); show_pte(addr); -- GitLab From 5c13f042e73200b50573ace63e1a6b94e2917616 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Fri, 10 Dec 2021 16:54:30 +0000 Subject: [PATCH 449/965] arm64: cpufeature: add HWCAP for FEAT_AFP Add a new HWCAP to detect the Alternate Floating-point Behaviour feature (FEAT_AFP), introduced in Armv8.7. Also expose this to userspace in the ID_AA64MMFR1_EL1 feature register. Signed-off-by: Joey Gouly Cc: Will Deacon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20211210165432.8106-2-joey.gouly@arm.com Signed-off-by: Catalin Marinas --- Documentation/arm64/cpu-feature-registers.rst | 9 +++++++++ Documentation/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 2 ++ arch/arm64/kernel/cpuinfo.c | 1 + 7 files changed, 19 insertions(+) diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 9f9b8fd060892..1b19d20c2dbd6 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -275,6 +275,15 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ + 8) ID_AA64MMFR1_EL1 - Memory model feature register 1 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | AFP | [47-44] | y | + +------------------------------+---------+---------+ + + Appendix I: Example ------------------- diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index af106af8e1c00..247728d379118 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -251,6 +251,10 @@ HWCAP2_ECV Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. +HWCAP2_AFP + + Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index b100e0055eab6..2809df2fdd63a 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -106,6 +106,7 @@ #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI) #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) #define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) +#define KERNEL_HWCAP_AFP __khwcap2_feature(AFP) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16b3f1a1d4688..adcab9009f9de 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -889,6 +889,7 @@ #endif /* id_aa64mmfr1 */ +#define ID_AA64MMFR1_AFP_SHIFT 44 #define ID_AA64MMFR1_ETS_SHIFT 36 #define ID_AA64MMFR1_TWED_SHIFT 32 #define ID_AA64MMFR1_XNX_SHIFT 28 diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 7b23b16f21ce3..180da7396549c 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -76,5 +76,6 @@ #define HWCAP2_BTI (1 << 17) #define HWCAP2_MTE (1 << 18) #define HWCAP2_ECV (1 << 19) +#define HWCAP2_AFP (1 << 20) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6f3e677d88f15..71ff5a4afb0fc 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -325,6 +325,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), @@ -2476,6 +2477,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), + HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 6e27b759056a6..0e52014019f60 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -95,6 +95,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_BTI] = "bti", [KERNEL_HWCAP_MTE] = "mte", [KERNEL_HWCAP_ECV] = "ecv", + [KERNEL_HWCAP_AFP] = "afp", }; #ifdef CONFIG_COMPAT -- GitLab From 9e45365f1469ef2b934f9d035975dbc9ad352116 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Fri, 10 Dec 2021 16:54:31 +0000 Subject: [PATCH 450/965] arm64: add ID_AA64ISAR2_EL1 sys register This is a new ID register, introduced in 8.7. Signed-off-by: Joey Gouly Cc: Will Deacon Cc: Marc Zyngier Cc: James Morse Cc: Alexandru Elisei Cc: Suzuki K Poulose Cc: Reiji Watanabe Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++ arch/arm64/kernel/cpufeature.c | 9 +++++++++ arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kvm/sys_regs.c | 2 +- 5 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 0f6d16faa5402..a58e366f0b074 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -51,6 +51,7 @@ struct cpuinfo_arm64 { u64 reg_id_aa64dfr1; u64 reg_id_aa64isar0; u64 reg_id_aa64isar1; + u64 reg_id_aa64isar2; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; u64 reg_id_aa64mmfr2; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index adcab9009f9de..4704f5893458f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -182,6 +182,7 @@ #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) @@ -771,6 +772,20 @@ #define ID_AA64ISAR1_GPI_NI 0x0 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 +/* id_aa64isar2 */ +#define ID_AA64ISAR2_RPRES_SHIFT 4 +#define ID_AA64ISAR2_WFXT_SHIFT 0 + +#define ID_AA64ISAR2_RPRES_8BIT 0x0 +#define ID_AA64ISAR2_RPRES_12BIT 0x1 +/* + * Value 0x1 has been removed from the architecture, and is + * reserved, but has not yet been removed from the ARM ARM + * as of ARM DDI 0487G.b. + */ +#define ID_AA64ISAR2_WFXT_NI 0x0 +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 + /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 71ff5a4afb0fc..c36018310da5b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), @@ -638,6 +642,7 @@ static const struct __ftr_reg_entry { ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, &id_aa64isar1_override), + ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -934,6 +939,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); + init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); @@ -1152,6 +1158,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64isar0, boot->reg_id_aa64isar0); taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, info->reg_id_aa64isar1, boot->reg_id_aa64isar1); + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, + info->reg_id_aa64isar2, boot->reg_id_aa64isar2); /* * Differing PARange support is fine as long as all peripherals and @@ -1273,6 +1281,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64MMFR2_EL1); read_sysreg_case(SYS_ID_AA64ISAR0_EL1); read_sysreg_case(SYS_ID_AA64ISAR1_EL1); + read_sysreg_case(SYS_ID_AA64ISAR2_EL1); read_sysreg_case(SYS_CNTFRQ_EL0); read_sysreg_case(SYS_CTR_EL0); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 0e52014019f60..f2f8fe02f39c7 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -392,6 +392,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); + info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e3ec1a44f94d8..4dc2fba316fff 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1525,7 +1525,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=6 */ ID_SANITISED(ID_AA64ISAR0_EL1), ID_SANITISED(ID_AA64ISAR1_EL1), - ID_UNALLOCATED(6,2), + ID_SANITISED(ID_AA64ISAR2_EL1), ID_UNALLOCATED(6,3), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), -- GitLab From 1175011a7d0030d49dc9c10bde36f08f26d0a8ee Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Fri, 10 Dec 2021 16:54:32 +0000 Subject: [PATCH 451/965] arm64: cpufeature: add HWCAP for FEAT_RPRES Add a new HWCAP to detect the Increased precision of Reciprocal Estimate and Reciprocal Square Root Estimate feature (FEAT_RPRES), introduced in Armv8.7. Also expose this to userspace in the ID_AA64ISAR2_EL1 feature register. Signed-off-by: Joey Gouly Cc: Will Deacon Cc: Jonathan Corbet Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20211210165432.8106-4-joey.gouly@arm.com Signed-off-by: Catalin Marinas --- Documentation/arm64/cpu-feature-registers.rst | 8 ++++++++ Documentation/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 2 ++ arch/arm64/kernel/cpuinfo.c | 1 + 6 files changed, 17 insertions(+) diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 1b19d20c2dbd6..749ae970c3195 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -283,6 +283,14 @@ infrastructure: | AFP | [47-44] | y | +------------------------------+---------+---------+ + 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | RPRES | [7-4] | y | + +------------------------------+---------+---------+ + Appendix I: Example ------------------- diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 247728d379118..b72ff17d600ae 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -255,6 +255,10 @@ HWCAP2_AFP Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. +HWCAP2_RPRES + + Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 2809df2fdd63a..f68fbb2074730 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -107,6 +107,7 @@ #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) #define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) #define KERNEL_HWCAP_AFP __khwcap2_feature(AFP) +#define KERNEL_HWCAP_RPRES __khwcap2_feature(RPRES) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 180da7396549c..f03731847d9df 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -77,5 +77,6 @@ #define HWCAP2_MTE (1 << 18) #define HWCAP2_ECV (1 << 19) #define HWCAP2_AFP (1 << 20) +#define HWCAP2_RPRES (1 << 21) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c36018310da5b..a46ab3b1c4d5f 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -226,6 +226,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2487,6 +2488,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index f2f8fe02f39c7..591c18a889a56 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -96,6 +96,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_MTE] = "mte", [KERNEL_HWCAP_ECV] = "ecv", [KERNEL_HWCAP_AFP] = "afp", + [KERNEL_HWCAP_RPRES] = "rpres", }; #ifdef CONFIG_COMPAT -- GitLab From 4754eab7e5a78bdefe7a960c5c260c95ebbb5fa6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Mon, 6 Dec 2021 01:43:34 +0100 Subject: [PATCH 452/965] ARM: dts: gemini: NAS4220-B: fis-index-block with 128 KiB sectors Steven Maddox reported in the OpenWrt bugzilla, that his RaidSonic IB-NAS4220-B was no longer booting with the new OpenWrt 21.02 (uses linux 5.10's device-tree). However, it was working with the previous OpenWrt 19.07 series (uses 4.14). |[ 5.548038] No RedBoot partition table detected in 30000000.flash |[ 5.618553] Searching for RedBoot partition table in 30000000.flash at offset 0x0 |[ 5.739093] No RedBoot partition table detected in 30000000.flash |... |[ 7.039504] Waiting for root device /dev/mtdblock3... The provided bootlog shows that the RedBoot partition parser was looking for the partition table "at offset 0x0". Which is strange since the comment in the device-tree says it should be at 0xfe0000. Further digging on the internet led to a review site that took some useful PCB pictures of their review unit back in February 2009. Their picture shows a Spansion S29GL128N11TFI01 flash chip. >From Spansion's Datasheet: "S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors" Steven also provided a "cat /sys/class/mtd/mtd0/erasesize" from his unit: "131072". With the 128 KiB Sector/Erasesize in mind. This patch changes the fis-index-block property to (0xfe0000 / 0x20000) = 0x7f. Fixes: b5a923f8c739 ("ARM: dts: gemini: Switch to redboot partition parsing") Reported-by: Steven Maddox Signed-off-by: Christian Lamparter Signed-off-by: Linus Walleij Tested-by: Steven Maddox Link: https://lore.kernel.org/r/20211206004334.4169408-1-linus.walleij@linaro.org' Bugzilla: https://bugs.openwrt.org/index.php?do=details&task_id=4137 Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/gemini-nas4220b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 13112a8a5dd88..6544c730340fa 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -84,7 +84,7 @@ partitions { compatible = "redboot-fis"; /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; + fis-index-block = <0x7f>; }; }; -- GitLab From a6839c42fe7c21173eb6f5db67d944e0f076be2a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 13 Dec 2021 12:32:49 +0100 Subject: [PATCH 453/965] ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32 The DragonBoard 410c is a convenient device for testing and debugging. Since there is support for using ARM32 kernels on MSM8916 now, also build the DB410c DTB on ARM32 so it can be used for testing. ARM64 is still the main supported architecture for DB410c but it actually works great on ARM32 as well. The "apq8016-sbc.dts" is simply included as-is from ARM64 similar to the approach used for Raspberry Pi (e.g. bcm2711-rpi-4-b.dts). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213113250.4249-1-stephan@gerhold.net --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8016-sbc.dts | 2 ++ 2 files changed, 3 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8016-sbc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..bba17ee51e297 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -954,6 +954,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox810se-wd-mbwe.dtb \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom-apq8016-sbc.dts new file mode 100644 index 0000000000000..4ccd2dca74a25 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8016-sbc.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/apq8016-sbc.dts" -- GitLab From f56498fc6a9364a35dd74af791bd1251467e9cc1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:26:11 +0100 Subject: [PATCH 454/965] arm64: dts: qcom: sm6350: Fix validation errors Sort clocks and interrupts as specified in the docs and remove the stray property #power-domain-cells from aoss_qmp to solve dtbs_check validation errors. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-11-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cd55797facf69..14e1071bcca44 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -531,10 +531,10 @@ ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&xo_board>, <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&xo_board>; - clock-names = "aux", "ref", "com_aux", "cfg_ahb"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; @@ -592,11 +592,12 @@ "sleep"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -656,7 +657,6 @@ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { -- GitLab From 489be59b635ba76ea16d6f820ddf037644b3415a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:03 +0100 Subject: [PATCH 455/965] arm64: dts: qcom: sm6350: Add MPSS nodes Add the required nodes for booting the MPSS on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-4-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 14e1071bcca44..b0d70eafe148d 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -361,6 +361,32 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -473,6 +499,46 @@ #hwlock-cells = <1>; }; + mpss: remoteproc@4080000 { + compatible = "qcom,sm6350-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_CX>, + <&rpmhpd SM6350_MSS>; + power-domain-names = "cx", "mss"; + + memory-region = <&pil_modem_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; -- GitLab From efc33c969f23cd6fe983e7e7bdcd8bbb1521f1de Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:05 +0100 Subject: [PATCH 456/965] arm64: dts: qcom: sm6350: Add ADSP nodes Add the required nodes for booting the ADSP on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-6-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index b0d70eafe148d..fdd7d3b595331 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -361,6 +361,30 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -499,6 +523,73 @@ #hwlock-cells = <1>; }; + adsp: remoteproc@3000000 { + compatible = "qcom,sm6350-adsp-pas"; + reg = <0 0x03000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_LCX>, + <&rpmhpd SM6350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0>; + qcom,nsessions = <5>; + }; + }; + }; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; -- GitLab From 8eb5287e8a425aa7b27cfbb92096550046a231f8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:07 +0100 Subject: [PATCH 457/965] arm64: dts: qcom: sm6350: Add CDSP nodes Add the required nodes for booting the CDSP on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-8-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 122 +++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fdd7d3b595331..d7c9edff19f77 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -385,6 +385,30 @@ }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -630,6 +654,104 @@ }; }; + cdsp: remoteproc@8300000 { + compatible = "qcom,sm6350-cdsp-pas"; + reg = <0 0x08300000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_CX>, + <&rpmhpd SM6350_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&pil_cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1401 0x20>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1402 0x20>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1403 0x20>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1404 0x20>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1405 0x20>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1406 0x20>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1407 0x20>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1408 0x20>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; -- GitLab From bc279dc04e9ee23f6a22f6c7a6924edbd5fe0f6d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:08 +0100 Subject: [PATCH 458/965] arm64: dts: qcom: sm7225-fairphone-fp4: Enable ADSP, CDSP & MPSS Enable the remoteprocs found on the SoC and add a qcom,rmtfs-mem node. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-9-luca.weiss@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index a6937642736e7..d4af9e0dad87d 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -53,6 +53,27 @@ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; }; + + reserved-memory { + /* + * The rmtfs memory region in downstream is 'dynamically allocated' + * but given the same address every time. Hard code it as this address is + * where the modem firmware expects it to be. + */ + memory@efe01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xefe01000 0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + }; +}; + +&adsp { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/adsp.mdt"; }; &apps_rsc { @@ -269,6 +290,16 @@ }; }; +&cdsp { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; +}; + &pm6350_gpios { gpio_keys_pin: gpio-keys-pin { pins = "gpio2"; -- GitLab From ced795c2648aae44314aa8027e8e1d691ea6153f Mon Sep 17 00:00:00 2001 From: Ivan Bornyakov Date: Thu, 2 Dec 2021 08:57:24 +0300 Subject: [PATCH 459/965] dt-bindings: bus: imx-weim: add words about continuous bclk Document continuous Burst Clock option. With this option Burst Clock, if enabled, will output continuous clock, otherwise Burst Clock will output clock only when necessary. Signed-off-by: Ivan Bornyakov Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/bus/imx-weim.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 1b1d1c5c21ea1..e7f502070d77e 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -48,6 +48,11 @@ Optional properties: devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. + Without this option Burst Clock will output clock + only when necessary. This takes effect only if + "fsl,burst-clk-enable" is set. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the -- GitLab From 7b983da38417fa8c36514d6a98997b3cad11b6a9 Mon Sep 17 00:00:00 2001 From: Ivan Bornyakov Date: Thu, 2 Dec 2021 08:57:23 +0300 Subject: [PATCH 460/965] bus: imx-weim: optionally enable continuous burst clock To enable continuous burst clock, add "fsl,continuous-burst-clk" along with "fsl,burst-clk-enable" property to the weim bus's devicetree node. Example: weim: weim@21b8000 { compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; clocks = <&clks 143>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x50000000 0x08000000>; fsl,weim-cs-gpr = <&gpr>; fsl,burst-clk-enable; fsl,continuous-burst-clk; client-device@0 { ... }; }; Signed-off-by: Ivan Bornyakov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- drivers/bus/imx-weim.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 28bb65a5613fd..bccb275b65ba0 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -21,6 +21,7 @@ struct imx_weim_devtype { unsigned int cs_stride; unsigned int wcr_offset; unsigned int wcr_bcm; + unsigned int wcr_cont_bclk; }; static const struct imx_weim_devtype imx1_weim_devtype = { @@ -41,6 +42,7 @@ static const struct imx_weim_devtype imx50_weim_devtype = { .cs_stride = 0x18, .wcr_offset = 0x90, .wcr_bcm = BIT(0), + .wcr_cont_bclk = BIT(3), }; static const struct imx_weim_devtype imx51_weim_devtype = { @@ -206,8 +208,20 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) { if (devtype->wcr_bcm) { reg = readl(base + devtype->wcr_offset); - writel(reg | devtype->wcr_bcm, - base + devtype->wcr_offset); + reg |= devtype->wcr_bcm; + + if (of_property_read_bool(pdev->dev.of_node, + "fsl,continuous-burst-clk")) { + if (devtype->wcr_cont_bclk) { + reg |= devtype->wcr_cont_bclk; + } else { + dev_err(&pdev->dev, + "continuous burst clk not supported.\n"); + return -EINVAL; + } + } + + writel(reg, base + devtype->wcr_offset); } else { dev_err(&pdev->dev, "burst clk mode not supported.\n"); return -EINVAL; -- GitLab From c4cacb5b80f4f1d83b8bcd6e16672d6732982414 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:26 -0600 Subject: [PATCH 461/965] dt-bindings: soc: imx: Add binding doc for spba bus Add binding doc for fsl,spba-bus. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/bus/fsl,spba-bus.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 0000000000000..d42dbb0bbc2ea --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; -- GitLab From b357ffd8604ae45ec4bb1ebec072cd4ca4ce839c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:27 -0600 Subject: [PATCH 462/965] ARM: dts: imx: Change spba to spba-bus With the updated dt-bindings for the spba-bus, rename spba@xxxx to spba-bus@xxxx. There are no functional changes. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 2 +- arch/arm/boot/dts/imx53.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index fdcca82c9986f..83278b390c700 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -200,7 +200,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 948d2a543f8d1..2adb923c0b27b 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -166,7 +166,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a969f335b2402..a31e3694fa2b4 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -108,7 +108,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 01cfcbe5928e8..ba496fdfe8cb4 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -178,7 +178,7 @@ reg = <0x70000000 0x10000000>; ranges; - spba@70000000 { + spba-bus@70000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 2cf3909cca2f8..6082cd3471245 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -229,7 +229,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f5de5def876d8..6dc1b970bcad2 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -481,7 +481,7 @@ status = "okay"; }; - spba@203c000 { + spba-bus@203c000 { reg = <0x0203c000 0x4000>; }; }; -- GitLab From 74092acd6eab63b1f1e0c293400ef3b1bb7af6f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:01 +0200 Subject: [PATCH 463/965] ARM: dts: imx7s-warp: Drop undefined property in mipi_csi node The fsl,csis-hs-settle property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't parsed by the corresponding driver. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 569bbd84e371a..614d252f029fd 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -248,7 +248,6 @@ &mipi_csi { clock-frequency = <166000000>; - fsl,csis-hs-settle = <3>; status = "okay"; port@0 { -- GitLab From 473d06b9093ddc6b9fd2927893819f43e830bde5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:02 +0200 Subject: [PATCH 464/965] ARM: dts: imx7: Drop reset-names property for mipi_csi node The reset-names property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't used by the corresponding driver as it acquires the reset with a NULL ID. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1843fc0538709..7e6b99ece7e9c 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -819,7 +819,6 @@ power-domains = <&pgc_mipi_phy>; phy-supply = <®_1p0d>; resets = <&src IMX7_RESET_MIPI_PHY_MRST>; - reset-names = "mrst"; status = "disabled"; port@0 { -- GitLab From 3f8b6cf82088e0423b755f9a9dc79b8650bd1e25 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:03 +0200 Subject: [PATCH 465/965] ARM: dts: imx7: Group mipi_csi 'port' children in a 'ports' node The nxp,imx7-mipi-csi2.yaml binding requires ports to be grouped in a ports node, as multiple ports are present. Fix imx7s.dtsi and the only board file that references the mipi_csi ports. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 13 +++++++------ arch/arm/boot/dts/imx7s.dtsi | 21 ++++++++++++--------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 614d252f029fd..4f1edef06c922 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -250,14 +250,15 @@ clock-frequency = <166000000>; status = "okay"; - port@0 { - reg = <0>; + ports { + port@0 { + reg = <0>; - mipi_from_sensor: endpoint { - remote-endpoint = <&ov2680_to_mipi>; - data-lanes = <1>; + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; }; - }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7e6b99ece7e9c..52a9aeecdbb2c 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -809,8 +809,6 @@ mipi_csi: mipi-csi@30750000 { compatible = "fsl,imx7-mipi-csi2"; reg = <0x30750000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; interrupts = ; clocks = <&clks IMX7D_IPG_ROOT_CLK>, <&clks IMX7D_MIPI_CSI_ROOT_CLK>, @@ -821,15 +819,20 @@ resets = <&src IMX7_RESET_MIPI_PHY_MRST>; status = "disabled"; - port@0 { - reg = <0>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@1 { - reg = <1>; + port@0 { + reg = <0>; + }; - mipi_vc0_to_csi_mux: endpoint { - remote-endpoint = <&csi_mux_from_mipi_vc0>; + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; }; }; }; -- GitLab From 05be8e7472cdce0b006aa5fc995ec199f91979f5 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:23 +0100 Subject: [PATCH 466/965] ARM: dts: imx1: drop "fsl,imx-clk32" "fsl,imx-clk32" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 9b940987864c7..e312f1e74e2fe 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -55,7 +55,7 @@ clocks { clk32 { - compatible = "fsl,imx-clk32", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; -- GitLab From 9a68c8ec9ac9f097c75d6a02f12ddcd29379622d Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:24 +0100 Subject: [PATCH 467/965] ARM: dts: imx25: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 83278b390c700..fa8044c21cb8c 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -62,7 +62,7 @@ clocks { osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- GitLab From 20adb4921cd6d8db90efd466a1547af047160a0a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:25 +0100 Subject: [PATCH 468/965] ARM: dts: imx50: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a31e3694fa2b4..d61c24846eef0 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -80,7 +80,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- GitLab From c5e526a9c3d5d8be8829ab2c4530a063a9aef983 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:26 +0100 Subject: [PATCH 469/965] ARM: dts: imx50: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index d61c24846eef0..af748ea4c1a5b 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -62,7 +62,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- GitLab From c522683be5b56a2366bbe896bae2180a6d22e95e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:27 +0100 Subject: [PATCH 470/965] ARM: dts: imx50: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index af748ea4c1a5b..682880e9e485a 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -68,7 +68,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; -- GitLab From f6bc4a7c037f07bb338dde5171c64d191e65dfff Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:28 +0100 Subject: [PATCH 471/965] ARM: dts: imx50: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 682880e9e485a..be0de0fd31f95 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -74,7 +74,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- GitLab From 73cda7c63a59609fa53ab91c1167f55692140a1f Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:29 +0100 Subject: [PATCH 472/965] ARM: dts: imx51: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index ba496fdfe8cb4..090223321b3b0 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -66,7 +66,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- GitLab From 929bdb7b0afb19c6f640b96859554d0d0010c3b3 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:30 +0100 Subject: [PATCH 473/965] ARM: dts: imx51: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 090223321b3b0..7840489fcd6c3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -48,7 +48,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- GitLab From 58cd720f3f5a19c8cacff81b652018358c0105ea Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:31 +0100 Subject: [PATCH 474/965] ARM: dts: imx51: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 7840489fcd6c3..e973f3c580520 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -54,7 +54,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- GitLab From 0dee2e69efc250410f1c0d756117d6b4506f54ef Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:32 +0100 Subject: [PATCH 475/965] ARM: dts: imx51: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index e973f3c580520..56c8d87864c34 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -60,7 +60,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- GitLab From 39cd25fe2e1d10a5b319a73a6e2bf97ecba86a9c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:33 +0100 Subject: [PATCH 476/965] ARM: dts: imx53: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6082cd3471245..9e51ea3dd739d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -104,7 +104,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- GitLab From ac0894359ecfd80f260aa42b283c88bf02387e4e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:34 +0100 Subject: [PATCH 477/965] ARM: dts: imx53: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9e51ea3dd739d..dd5cf147a7a4b 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -86,7 +86,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- GitLab From 917fee9c6f7b7d4110730c2ab5f5fe8cdd7df534 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:35 +0100 Subject: [PATCH 478/965] ARM: dts: imx53: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index dd5cf147a7a4b..3efa3d6d87c53 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -92,7 +92,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; -- GitLab From 4ce956128d43527c5c917309257f2c4e927425d6 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:36 +0100 Subject: [PATCH 479/965] ARM: dts: imx53: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3efa3d6d87c53..67487f3caee1a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -98,7 +98,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- GitLab From 36b85fdaa36ac19ec6bd77ad5d44050747265c28 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:37 +0100 Subject: [PATCH 480/965] ARM: dts: imx6qdl: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dc1b970bcad2..6dcb3756597b9 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -67,7 +67,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- GitLab From 5368f930cc655d0906574e9841960ee380bf4351 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:38 +0100 Subject: [PATCH 481/965] ARM: dts: imx6qdl: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dcb3756597b9..5d4557d15d033 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -55,7 +55,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- GitLab From bca46d8e5fede9cf4491be27dba9d09721b80f71 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:39 +0100 Subject: [PATCH 482/965] ARM: dts: imx6qdl: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 5d4557d15d033..d27beb47f9a3b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -61,7 +61,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- GitLab From 97416aab15174741f7feda551ec6bfd7e7ee9323 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 7 Dec 2021 16:34:57 +0800 Subject: [PATCH 483/965] arm64: defconfig: enable drivers for booting i.MX8ULP Select i.MX8ULP CLK and PINCTRL driver to make it boot. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 13207d24b564b..cc5d3ba166b15 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -506,6 +506,7 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8ULP=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y @@ -986,6 +987,7 @@ CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MP=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y CONFIG_TI_SCI_CLK=y CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_A53PLL=y -- GitLab From e7ed6ba0239df1e2aca3f9b2d77da4de180cdbe0 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:05:43 +0100 Subject: [PATCH 484/965] ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs According to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B [1] the reset should stay asserted for at least 100uS and software should wait at least 200nS. On other DHCOM SoMs with the SMSC LAN8710Ai PHY both reset delays are 500us. This should be plenty and for consistency, the i.MX6 SoM should also use these delays. [1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002164B.pdf Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index 5d10c40313cbd..e716870611610 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -138,8 +138,8 @@ pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; reg = <0>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; + reset-assert-us = <500>; + reset-deassert-us = <500>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; smsc,disable-energy-detect; /* Make plugin detection reliable */ }; -- GitLab From cbcf2b40a7cf40da02e08e4485118a3b4fce54ce Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:07:26 +0100 Subject: [PATCH 485/965] ARM: dts: imx6qdl-dhcom: Identify the PHY by ethernet-phy-id0007.c0f0 Identify the PHY by its compatible ID value. In some cases during boot, the PHY needs to be reset to be accessible, but this is only possible if the PHY is recognized. In that case, the automatic detection of the PHY does not work and a static compatible ID value is need. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index e716870611610..b2b7daf43ede7 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -132,7 +132,8 @@ #size-cells = <0>; ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio4>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; -- GitLab From 6c5d66cb28b0611350007204da1cd079b7b4bf41 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:25 +0200 Subject: [PATCH 486/965] arm64: dts: ls1028a-rdb: sort nodes alphabetically by label In preparation for this board's device tree synchronization with U-Boot, we must find a common node ordering pattern. Alphabetical sounds about right. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1028a-rdb.dts | 84 +++++++++---------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 7719f44bcaede..a6f41aa9004a4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -102,6 +102,48 @@ }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&enetc_mdio_pf3 { + sgmii_phy0: ethernet-phy@2 { + reg = <0x2>; + }; + + /* VSC8514 QSGMII quad PHY */ + qsgmii_phy0: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy1: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy2: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy3: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +&enetc_port0 { + phy-handle = <&sgmii_phy0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50; @@ -188,48 +230,6 @@ }; }; -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - - /* VSC8514 QSGMII quad PHY */ - qsgmii_phy0: ethernet-phy@10 { - reg = <0x10>; - }; - - qsgmii_phy1: ethernet-phy@11 { - reg = <0x11>; - }; - - qsgmii_phy2: ethernet-phy@12 { - reg = <0x12>; - }; - - qsgmii_phy3: ethernet-phy@13 { - reg = <0x13>; - }; -}; - -&enetc_port0 { - phy-handle = <&sgmii_phy0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&enetc_port2 { - status = "okay"; -}; - &mscc_felix { status = "okay"; }; -- GitLab From d18c7980d4d7125b0c9fc002de301054c3667a82 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:26 +0200 Subject: [PATCH 487/965] arm64: dts: ls1028a-rdb: add an alias for the FlexSPI controller This is used by U-Boot and is required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index a6f41aa9004a4..7e3faa78c7062 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -22,6 +22,7 @@ mmc0 = &esdhc; mmc1 = &esdhc1; rtc1 = &ftm_alarm0; + spi0 = &fspi; }; chosen { -- GitLab From 96ad273759e0176b5e00c7c7266421c26a7f4811 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:27 +0200 Subject: [PATCH 488/965] arm64: dts: ls1028a-rdb: add aliases for the Ethernet ports These are used by U-Boot, and are required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 7e3faa78c7062..79d7e7cf54036 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -23,6 +23,12 @@ mmc1 = &esdhc1; rtc1 = &ftm_alarm0; spi0 = &fspi; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port2; + ethernet2 = &mscc_felix_port0; + ethernet3 = &mscc_felix_port1; + ethernet4 = &mscc_felix_port2; + ethernet5 = &mscc_felix_port3; }; chosen { -- GitLab From bd8a9cd624c6189c6ad6e0d08513e089775303a4 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:28 +0200 Subject: [PATCH 489/965] arm64: dts: ls1028a-rdb: update copyright Company policy requires that copyright is updated when a file is touched. Keeping the copyright change separate to reduce the noise in other patches. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 79d7e7cf54036..639f40740d563 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A RDB Board. * - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * * Harninder Rai * -- GitLab From 22e9e261bfe85539d2a3ce8e2f8f5b8187082028 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 3 Dec 2021 19:15:36 -0600 Subject: [PATCH 490/965] arm64: dts: ls1088a: Add reboot nodes ls1088a has a separate reset register block. Define it in dts and use it for reboot. Signed-off-by: Ashish Kumar Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f891ef6a3754c..1eda080b497cc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -206,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -226,6 +233,11 @@ little-endian; }; + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; -- GitLab From a3d5b4e2af448afd0c8c843178380a8efbbaf8df Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 3 Dec 2021 19:15:37 -0600 Subject: [PATCH 491/965] arm64: dts: ls1088a: add snps incr burst type adjustment for usb1 This property could fix the defect that external usb device always prints this error log --- 'reset SuperSpeed USB device number n using xhci_hcd' when system power on. Signed-off-by: Pengbo Mu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 1eda080b497cc..3ed1f2c51cadf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -497,6 +497,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; -- GitLab From 1a42daaa3c7e0749f212c6bf9a8176d59833da71 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 5 Dec 2021 15:01:43 -0600 Subject: [PATCH 492/965] arm64: dts: imx8mq-evk: link regulator to VPU domain The SW1C regulator powers the VPU and the state isn't guaranteed to always be on. Link the VPU power-domain to the regulator to ensure it is turned on before using the power domain. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index c96d23fe3010f..a1b7582f3ecff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -331,6 +331,10 @@ power-supply = <&sw1a_reg>; }; +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + &qspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; -- GitLab From 057ccd9db760fc2c336b1138dab345bc2d3cdd35 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:53 +0800 Subject: [PATCH 493/965] dt-bindings: power: imx8ulp: add power domain header file Add i.MX8ULP power domain header file Acked-by: Rob Herring Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8ulp-power.h | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/power/imx8ulp-power.h diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h new file mode 100644 index 0000000000000..a556b2e96df16 --- /dev/null +++ b/include/dt-bindings/power/imx8ulp-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ +#define __DT_BINDINGS_IMX8ULP_POWER_H__ + +#define IMX8ULP_PD_DMA1 0 +#define IMX8ULP_PD_FLEXSPI2 1 +#define IMX8ULP_PD_USB0 2 +#define IMX8ULP_PD_USDHC0 3 +#define IMX8ULP_PD_USDHC1 4 +#define IMX8ULP_PD_USDHC2_USB1 5 +#define IMX8ULP_PD_DCNANO 6 +#define IMX8ULP_PD_EPDC 7 +#define IMX8ULP_PD_DMA2 8 +#define IMX8ULP_PD_GPU2D 9 +#define IMX8ULP_PD_GPU3D 10 +#define IMX8ULP_PD_HIFI4 11 +#define IMX8ULP_PD_ISI 12 +#define IMX8ULP_PD_MIPI_CSI 13 +#define IMX8ULP_PD_MIPI_DSI 14 +#define IMX8ULP_PD_PXP 15 + +#endif -- GitLab From a38771d7a49baf682fffd5cb8e1c6aea45ae5d26 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:54 +0800 Subject: [PATCH 494/965] arm64: dts: imx8ulp: add scmi firmware node i.MX8ULP use scmi firmware based power domain and sensor support. So add the firmware node and the sram it uses. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index fb8714379026f..8ee040e3cbae4 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include "imx8ulp-pinfunc.h" @@ -102,6 +103,40 @@ #clock-cells = <0>; }; + sram@2201f000 { + compatible = "mmio-sram"; + reg = <0x0 0x2201f000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2201f000 0x1000>; + + scmi_buf: scmi-buf@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x400>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; -- GitLab From 03eb813dac25d478151892e959055a80b9eb7dbe Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:55 +0800 Subject: [PATCH 495/965] arm64: dts: imx8ulp: add power domain entry for usdhc Add power domain for USDHC node. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 8ee040e3cbae4..a987ff7156bd6 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -329,6 +329,7 @@ <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -343,6 +344,7 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -357,6 +359,7 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; -- GitLab From aafac22d6b232a2a4f496f7ac3f98a32ff1fb29f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Dec 2021 16:52:45 -0300 Subject: [PATCH 496/965] arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property The 'pm-ignore-notify' property is not a valid property and there is no documentation for it. Drop such invalid property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts | 1 - arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 1 - arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 40f5e7a3b0644..cf07987ccc10b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -263,7 +263,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts index 5389d6f2beba9..502745402847e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts index a4a2ada148353..ddac8bc7ae651 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 3b2d627a03428..1133cded9be2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -274,7 +274,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; -- GitLab From 63aca69c224fd2a38e02598a8ce48b984c7e9c76 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:15 -0300 Subject: [PATCH 497/965] dt-bindings: Add vendor prefix for BSH Hausgeraete GmbH Document vendor prefix for BSH Hausgeraete GmbH ('BSH Home Appliances', B/S/H/) manufacturer. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6414f5fdcb913..b491666ba6201 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -187,6 +187,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^brcm,.*": description: Broadcom Corporation + "^bsh,.*": + description: BSH Hausgeraete GmbH "^buffalo,.*": description: Buffalo, Inc. "^bur,.*": -- GitLab From 50cee5eb406b9557f30a2824691b26d2a74f1a8a Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:16 -0300 Subject: [PATCH 498/965] dt-bindings: arm: fsl: Add iMX8MN BSH SMM S2 boards Add bindings for BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c35076cc551d4..d065721d65e9f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -807,6 +807,8 @@ properties: items: - enum: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit + - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 + - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board -- GitLab From 8802266a103343da81fc99f7977273713e0e1980 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:18 -0300 Subject: [PATCH 499/965] dt-bindings: arm: fsl: Add BSH SMM-M2 IMX6ULZ SystemMaster board Add bindings for BSH SystemMaster (SMM) M2 IMX6ULZ board. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d065721d65e9f..97f6eebad76af 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -670,6 +670,7 @@ properties: - description: i.MX6ULZ based Boards items: - enum: + - bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board - const: fsl,imx6ull # This seems odd. Should be last? - const: fsl,imx6ulz -- GitLab From bd4372f056a2cf1a8b47afafc565b1fa7eb54323 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:17 -0300 Subject: [PATCH 500/965] arm64: dts: imx8mn-bsh-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Add support for iMX8MN BSH SMM S2 board: - 256 MiB DDR3 RAM - 512 MiB NAND - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Add support for iMX8MN BSH SMM S2 PRO board: - 512 MiB DDR3 RAM - 8 GiB eMMC - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 426 ++++++++++++++++++ .../boot/dts/freescale/imx8mn-bsh-smm-s2.dts | 48 ++ .../dts/freescale/imx8mn-bsh-smm-s2pro.dts | 80 ++++ 4 files changed, 556 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 58971bd89901e..5018b8b1e5f23 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -48,6 +48,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi new file mode 100644 index 0000000000000..c11895d9d5828 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + chosen { + stdout-path = &uart4; + }; + + fec_supply: fec-supply-en { + compatible = "regulator-fixed"; + vin-supply = <&buck4_reg>; + regulator-name = "tja1101_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <&fec_supply>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + bd71847: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + buck1_reg: BUCK1 { + /* PMIC_BUCK1 - VDD_SOC */ + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + /* PMIC_BUCK2 - VDD_ARM */ + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */ + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + /* PMIC_BUCK6 - VDD_3V3 */ + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + /* PMIC_BUCK7 - VDD_1V8 */ + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + /* PMIC_BUCK8 - NVCC_DRAM */ + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + /* PMIC_LDO1 - NVCC_SNVS_1V8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + /* PMIC_LDO2 - VDD_SNVS_0V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + /* PMIC_LDO3 - VDDA_1V8 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + /* PMIC_LDO4 - VDD_MIPI_0V9 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* PMIC_LDO6 - VDD_MIPI_1V2 */ + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bluetooth>; + shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + mmc-pwrseq = <&usdhc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */ + MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */ + MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090 + MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016 + MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090 + MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */ + MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040 + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6 + >; + }; + + pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts new file mode 100644 index 0000000000000..33f98582eace2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2"; + compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x10000000>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts new file mode 100644 index 0000000000000..c6a8ed6745c11 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2 PRO"; + compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096 + >; + }; +}; -- GitLab From b2db714bc9a6dcf3636d2c5b1053cf43c0a700d9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Nov 2021 16:43:10 +0000 Subject: [PATCH 501/965] arm64: dts: renesas: r8a779a0: Add DSI encoders Provide the two MIPI DSI encoders on the V3U and connect them to the DU accordingly. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211130164311.2909616-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8ac1a31e4146d..f89bcc6984206 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2290,12 +2290,14 @@ port@0 { reg = <0>; du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; }; }; }; @@ -2633,6 +2635,62 @@ }; }; + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- GitLab From 5a6bca1ff7a50d2613c3074f00d2768af1aff120 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Nov 2021 16:43:11 +0000 Subject: [PATCH 502/965] arm64: dts: renesas: falcon-cpu: Add DSI display output Provide the display output using the sn65dsi86 MIPI DSI bridge. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211130164311.2909616-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index cd2f0d60f21a1..6af3f4f4f2682 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -98,6 +98,27 @@ reg = <0x7 0x00000000 0x0 0x80000000>; }; + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -115,6 +136,29 @@ regulator-boot-on; regulator-always-on; }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; }; &extal_clk { @@ -146,6 +190,41 @@ status = "okay"; clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; }; &i2c6 { -- GitLab From 844dd4378453ad8234498ebc330887209e8ad346 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 14:27:28 +0000 Subject: [PATCH 503/965] arm64: dts: renesas: r9a07g044: Add TSU node Add TSU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 439870930fb3f..ea528580f3063 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -539,6 +539,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g044-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; + resets = <&cpg R9A07G044_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g044-rpc-if", "renesas,rzg2l-rpc-if"; @@ -902,6 +912,22 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -- GitLab From 88404c56fde05eb741552a33fdfe6d7d20c1c986 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 14:27:29 +0000 Subject: [PATCH 504/965] arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham and others for r8a77990 SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index ea528580f3063..2639fd383010a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -88,6 +88,7 @@ compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; @@ -917,6 +918,15 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; trips { sensor_crit: sensor-crit { @@ -924,6 +934,12 @@ hysteresis = <1000>; type = "critical"; }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; }; -- GitLab From 369461ce8fb6c8156206c7110d7da48e9fbc41bb Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Dec 2021 14:11:20 -0600 Subject: [PATCH 505/965] x86: perf: Move RDPMC event flag to a common definition In preparation to enable user counter access on arm64 and to move some of the user access handling to perf core, create a common event flag for user counter access and convert x86 to use it. Since the architecture specific flags start at the LSB, starting at the MSB for common flags. Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Kan Liang Cc: Thomas Gleixner Cc: Borislav Petkov Cc: x86@kernel.org Cc: "H. Peter Anvin" Cc: linux-perf-users@vger.kernel.org Reviewed-by: Mark Rutland Reviewed-by: Thomas Gleixner Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211208201124.310740-2-robh@kernel.org Signed-off-by: Will Deacon --- arch/x86/events/core.c | 10 +++++----- arch/x86/events/perf_event.h | 2 +- include/linux/perf_event.h | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 38b2c779146f1..68dea7ce6a222 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2476,7 +2476,7 @@ static int x86_pmu_event_init(struct perf_event *event) if (READ_ONCE(x86_pmu.attr_rdpmc) && !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) - event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; return err; } @@ -2510,7 +2510,7 @@ void perf_clear_dirty_counters(void) static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) { - if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) + if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT)) return; /* @@ -2531,7 +2531,7 @@ static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) { - if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) + if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT)) return; if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) @@ -2542,7 +2542,7 @@ static int x86_pmu_event_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; - if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED)) + if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) return 0; if (is_metric_idx(hwc->idx)) @@ -2725,7 +2725,7 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->cap_user_time = 0; userpg->cap_user_time_zero = 0; userpg->cap_user_rdpmc = - !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); + !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; if (!using_native_sched_clock() || !sched_clock_stable()) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 5480db242083a..9d376e528dfcd 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -74,7 +74,7 @@ static inline bool constraint_match(struct event_constraint *c, u64 ecode) #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ -#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ + #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 0dcfd265beed5..ba9467972c091 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -129,6 +129,15 @@ struct hw_perf_event_extra { int idx; /* index in shared_regs->regs[] */ }; +/** + * hw_perf_event::flag values + * + * PERF_EVENT_FLAG_ARCH bits are reserved for architecture-specific + * usage. + */ +#define PERF_EVENT_FLAG_ARCH 0x0000ffff +#define PERF_EVENT_FLAG_USER_READ_CNT 0x80000000 + /** * struct hw_perf_event - performance event hardware details: */ -- GitLab From 82ff0c022d19c2ad69a472692bb7ee01ac07a40b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Dec 2021 14:11:21 -0600 Subject: [PATCH 506/965] perf: Add a counter for number of user access events in context On arm64, user space counter access will be controlled differently compared to x86. On x86, access in the strictest mode is enabled for all tasks in an MM when any event is mmap'ed. For arm64, access is explicitly requested for an event and only enabled when the event's context is active. This avoids hooks into the arch context switch code and gives better control of when access is enabled. In order to configure user space access when the PMU is enabled, it is necessary to know if any event (currently active or not) in the current context has user space accessed enabled. Add a counter similar to other counters in the context to avoid walking the event list every time. Reviewed-by: Mark Rutland Reviewed-by: Thomas Gleixner Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211208201124.310740-3-robh@kernel.org Signed-off-by: Will Deacon --- include/linux/perf_event.h | 1 + kernel/events/core.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index ba9467972c091..411e34210fbf4 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -831,6 +831,7 @@ struct perf_event_context { int nr_events; int nr_active; + int nr_user; int is_active; int nr_stat; int nr_freq; diff --git a/kernel/events/core.c b/kernel/events/core.c index 30d94f68c5bdb..1362b9b770d8c 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1808,6 +1808,8 @@ list_add_event(struct perf_event *event, struct perf_event_context *ctx) list_add_rcu(&event->event_entry, &ctx->event_list); ctx->nr_events++; + if (event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT) + ctx->nr_user++; if (event->attr.inherit_stat) ctx->nr_stat++; @@ -1999,6 +2001,8 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx) event->attach_state &= ~PERF_ATTACH_CONTEXT; ctx->nr_events--; + if (event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT) + ctx->nr_user--; if (event->attr.inherit_stat) ctx->nr_stat--; -- GitLab From e2012600810c9ded81f6f63a8d04781be3c300ad Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Dec 2021 14:11:22 -0600 Subject: [PATCH 507/965] arm64: perf: Add userspace counter access disable switch Like x86, some users may want to disable userspace PMU counter altogether. Add a sysctl 'perf_user_access' file to control userspace counter access. The default is '0' which is disabled. Writing '1' enables access. Note that x86 supports globally enabling user access by writing '2' to /sys/bus/event_source/devices/cpu/rdpmc. As there's not existing userspace support to worry about, this shouldn't be necessary for Arm. It could be added later if the need arises. Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Catalin Marinas Cc: linux-perf-users@vger.kernel.org Acked-by: Will Deacon Reviewed-by: Mark Rutland Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211208201124.310740-4-robh@kernel.org Signed-off-by: Will Deacon --- Documentation/admin-guide/sysctl/kernel.rst | 11 +++++++++++ arch/arm64/kernel/perf_event.c | 17 +++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index 0e486f41185ef..d359bcfadd39a 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -905,6 +905,17 @@ enabled, otherwise writing to this file will return ``-EBUSY``. The default value is 8. +perf_user_access (arm64 only) +================================= + +Controls user space access for reading perf event counters. When set to 1, +user space can read performance monitor counter registers directly. + +The default value is 0 (access disabled). + +See Documentation/arm64/perf.rst for more information. + + pid_max ======= diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index b4044469527e0..6ae20c4217af6 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -286,6 +286,8 @@ static const struct attribute_group armv8_pmuv3_events_attr_group = { PMU_FORMAT_ATTR(event, "config:0-15"); PMU_FORMAT_ATTR(long, "config1:0"); +static int sysctl_perf_user_access __read_mostly; + static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { return event->attr.config1 & 0x1; @@ -1104,6 +1106,19 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) return probe.present ? 0 : -ENODEV; } +static struct ctl_table armv8_pmu_sysctl_table[] = { + { + .procname = "perf_user_access", + .data = &sysctl_perf_user_access, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, + }, + { } +}; + static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, int (*map_event)(struct perf_event *event), const struct attribute_group *events, @@ -1136,6 +1151,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ? caps : &armv8_pmuv3_caps_attr_group; + register_sysctl("kernel", armv8_pmu_sysctl_table); + return 0; } -- GitLab From 83a7a4d643d33a8b74a42229346b7ed7139fcef9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Dec 2021 14:11:23 -0600 Subject: [PATCH 508/965] arm64: perf: Enable PMU counter userspace access for perf event Arm PMUs can support direct userspace access of counters which allows for low overhead (i.e. no syscall) self-monitoring of tasks. The same feature exists on x86 called 'rdpmc'. Unlike x86, userspace access will only be enabled for thread bound events. This could be extended if needed, but simplifies the implementation and reduces the chances for any information leaks (which the x86 implementation suffers from). PMU EL0 access will be enabled when an event with userspace access is part of the thread's context. This includes when the event is not scheduled on the PMU. There's some additional overhead clearing dirty counters when access is enabled in order to prevent leaking disabled counter data from other tasks. Unlike x86, enabling of userspace access must be requested with a new attr bit: config1:1. If the user requests userspace access with 64-bit counters, then the event open will fail if the h/w doesn't support 64-bit counters. Chaining is not supported with userspace access. The modes for config1 are as follows: config1 = 0 : user access disabled and always 32-bit config1 = 1 : user access disabled and always 64-bit (using chaining if needed) config1 = 2 : user access enabled and always 32-bit config1 = 3 : user access enabled and always 64-bit Based on work by Raphael Gault , but has been completely re-written. Cc: Will Deacon Cc: Mark Rutland Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org Cc: linux-perf-users@vger.kernel.org Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211208201124.310740-5-robh@kernel.org [will: Made armv8pmu_proc_user_access_handler() static] Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 119 +++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 6ae20c4217af6..81cc9f0e718ab 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -285,6 +285,7 @@ static const struct attribute_group armv8_pmuv3_events_attr_group = { PMU_FORMAT_ATTR(event, "config:0-15"); PMU_FORMAT_ATTR(long, "config1:0"); +PMU_FORMAT_ATTR(rdpmc, "config1:1"); static int sysctl_perf_user_access __read_mostly; @@ -293,9 +294,15 @@ static inline bool armv8pmu_event_is_64bit(struct perf_event *event) return event->attr.config1 & 0x1; } +static inline bool armv8pmu_event_want_user_access(struct perf_event *event) +{ + return event->attr.config1 & 0x2; +} + static struct attribute *armv8_pmuv3_format_attrs[] = { &format_attr_event.attr, &format_attr_long.attr, + &format_attr_rdpmc.attr, NULL, }; @@ -364,7 +371,7 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { */ #define ARMV8_IDX_CYCLE_COUNTER 0 #define ARMV8_IDX_COUNTER0 1 - +#define ARMV8_IDX_CYCLE_COUNTER_USER 32 /* * We unconditionally enable ARMv8.5-PMU long event counter support @@ -376,18 +383,22 @@ static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5); } +static inline bool armv8pmu_event_has_user_read(struct perf_event *event) +{ + return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; +} + /* * We must chain two programmable counters for 64 bit events, * except when we have allocated the 64bit cycle counter (for CPU - * cycles event). This must be called only when the event has - * a counter allocated. + * cycles event) or when user space counter access is enabled. */ static inline bool armv8pmu_event_is_chained(struct perf_event *event) { int idx = event->hw.idx; struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - return !WARN_ON(idx < 0) && + return !armv8pmu_event_has_user_read(event) && armv8pmu_event_is_64bit(event) && !armv8pmu_has_long_event(cpu_pmu) && (idx != ARMV8_IDX_CYCLE_COUNTER); @@ -720,6 +731,28 @@ static inline u32 armv8pmu_getreset_flags(void) return value; } +static void armv8pmu_disable_user_access(void) +{ + write_sysreg(0, pmuserenr_el0); +} + +static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) +{ + int i; + struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); + + /* Clear any unused counters to avoid leaking their contents */ + for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) { + if (i == ARMV8_IDX_CYCLE_COUNTER) + write_sysreg(0, pmccntr_el0); + else + armv8pmu_write_evcntr(i, 0); + } + + write_sysreg(0, pmuserenr_el0); + write_sysreg(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR, pmuserenr_el0); +} + static void armv8pmu_enable_event(struct perf_event *event) { /* @@ -763,6 +796,14 @@ static void armv8pmu_disable_event(struct perf_event *event) static void armv8pmu_start(struct arm_pmu *cpu_pmu) { + struct perf_event_context *task_ctx = + this_cpu_ptr(cpu_pmu->pmu.pmu_cpu_context)->task_ctx; + + if (sysctl_perf_user_access && task_ctx && task_ctx->nr_user) + armv8pmu_enable_user_access(cpu_pmu); + else + armv8pmu_disable_user_access(); + /* Enable all counters */ armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); } @@ -880,13 +921,16 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) return ARMV8_IDX_CYCLE_COUNTER; + else if (armv8pmu_event_is_64bit(event) && + armv8pmu_event_want_user_access(event) && + !armv8pmu_has_long_event(cpu_pmu)) + return -EAGAIN; } /* * Otherwise use events counters */ - if (armv8pmu_event_is_64bit(event) && - !armv8pmu_has_long_event(cpu_pmu)) + if (armv8pmu_event_is_chained(event)) return armv8pmu_get_chain_idx(cpuc, cpu_pmu); else return armv8pmu_get_single_idx(cpuc, cpu_pmu); @@ -902,6 +946,22 @@ static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, clear_bit(idx - 1, cpuc->used_mask); } +static int armv8pmu_user_event_idx(struct perf_event *event) +{ + if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) + return 0; + + /* + * We remap the cycle counter index to 32 to + * match the offset applied to the rest of + * the counter indices. + */ + if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) + return ARMV8_IDX_CYCLE_COUNTER_USER; + + return event->hw.idx; +} + /* * Add an event filter to a given event. */ @@ -998,6 +1058,25 @@ static int __armv8_pmuv3_map_event(struct perf_event *event, if (armv8pmu_event_is_64bit(event)) event->hw.flags |= ARMPMU_EVT_64BIT; + /* + * User events must be allocated into a single counter, and so + * must not be chained. + * + * Most 64-bit events require long counter support, but 64-bit + * CPU_CYCLES events can be placed into the dedicated cycle + * counter when this is free. + */ + if (armv8pmu_event_want_user_access(event)) { + if (!(event->attach_state & PERF_ATTACH_TASK)) + return -EINVAL; + if (armv8pmu_event_is_64bit(event) && + (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && + !armv8pmu_has_long_event(armpmu)) + return -EOPNOTSUPP; + + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; + } + /* Only expose micro/arch events supported by this PMU */ if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { @@ -1106,13 +1185,29 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) return probe.present ? 0 : -ENODEV; } +static void armv8pmu_disable_user_access_ipi(void *unused) +{ + armv8pmu_disable_user_access(); +} + +static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); + if (ret || !write || sysctl_perf_user_access) + return ret; + + on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1); + return 0; +} + static struct ctl_table armv8_pmu_sysctl_table[] = { { .procname = "perf_user_access", .data = &sysctl_perf_user_access, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = proc_dointvec_minmax, + .proc_handler = armv8pmu_proc_user_access_handler, .extra1 = SYSCTL_ZERO, .extra2 = SYSCTL_ONE, }, @@ -1142,6 +1237,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->set_event_filter = armv8pmu_set_event_filter; cpu_pmu->filter_match = armv8pmu_filter_match; + cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx; + cpu_pmu->name = name; cpu_pmu->map_event = map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? @@ -1318,6 +1415,14 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->cap_user_time = 0; userpg->cap_user_time_zero = 0; userpg->cap_user_time_short = 0; + userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event); + + if (userpg->cap_user_rdpmc) { + if (event->hw.flags & ARMPMU_EVT_64BIT) + userpg->pmc_width = 64; + else + userpg->pmc_width = 32; + } do { rd = sched_clock_read_begin(&seq); -- GitLab From aa1005d15d2aee10e5b93a25db076c47e05c4efa Mon Sep 17 00:00:00 2001 From: Raphael Gault Date: Wed, 8 Dec 2021 14:11:24 -0600 Subject: [PATCH 509/965] Documentation: arm64: Document PMU counters access from userspace Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211208201124.310740-6-robh@kernel.org Signed-off-by: Will Deacon --- Documentation/arm64/perf.rst | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d3858..1f87b57c23324 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,76 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counters, the global sysctl +kernel/perf_user_access must first be enabled: + +.. code-block:: sh + + echo 1 > /proc/sys/kernel/perf_user_access + +It is necessary to open the event using the perf tool interface with config1:1 +attr bit set: the sys_perf_event_open syscall returns a fd which can +subsequently be used with the mmap syscall in order to retrieve a page of memory +containing information about the event. The PMU driver uses this page to expose +to the user the hardware counter's index and other necessary data. Using this +index enables the user to access the PMU registers using the `mrs` instruction. +Access to the PMU registers is only valid while the sequence lock is unchanged. +In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is +changed. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and counter sizes +-------------------------------------- +The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) +counter along with userspace access. The sys_perf_event_open syscall will fail +if a 64-bit counter is requested and the hardware doesn't support 64-bit +counters. Chained events are not supported in conjunction with userspace counter +access. If a 32-bit counter is requested on hardware with 64-bit counters, then +userspace must treat the upper 32-bits read from the counter as UNKNOWN. The +'pmc_width' field in the user page will indicate the valid width of the counter +and should be used to mask the upper bits as needed. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- GitLab From 56c7c6eaf3eb8ac1ec40d56096c0f2b27250da5f Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:50 +0000 Subject: [PATCH 510/965] perf/arm-cmn: Fix CPU hotplug unregistration Attempting to migrate the PMU context after we've unregistered the PMU device, or especially if we never successfully registered it in the first place, is a woefully bad idea. It's also fundamentally pointless anyway. Make sure to unregister an instance from the hotplug handler *without* invoking the teardown callback. Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver") Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/2c221d745544774e4b07583b65b5d4d94f7e0fe4.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index bc3cba5f8c5dc..400eb7f579dce 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1561,7 +1561,8 @@ static int arm_cmn_probe(struct platform_device *pdev) err = perf_pmu_register(&cmn->pmu, name, -1); if (err) - cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node); + cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); + return err; } @@ -1572,7 +1573,7 @@ static int arm_cmn_remove(struct platform_device *pdev) writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); perf_pmu_unregister(&cmn->pmu); - cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node); + cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); return 0; } -- GitLab From 6190741c294d1cad15198d5d2f912868434fa492 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:51 +0000 Subject: [PATCH 511/965] perf/arm-cmn: Account for NUMA affinity On a system with multiple CMN meshes, ideally we'd want to access each PMU from within its own mesh, rather than with a long CML round-trip, wherever feasible. Since such a system is likely to be presented as multiple NUMA nodes, let's also hope a proximity domain is specified for each CMN programming interface, and use that to guide our choice of IRQ affinity to favour a node-local CPU where possible. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/32438b0d016e0649d882d47d30ac2000484287b9.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 51 +++++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 400eb7f579dce..02b898dbba91b 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1147,23 +1147,47 @@ static int arm_cmn_commit_txn(struct pmu *pmu) return 0; } -static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) +{ + unsigned int i; + + perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); + for (i = 0; i < cmn->num_dtcs; i++) + irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); + cmn->cpu = cpu; +} + +static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) { struct arm_cmn *cmn; - unsigned int i, target; + int node; - cmn = hlist_entry_safe(node, struct arm_cmn, cpuhp_node); - if (cpu != cmn->cpu) - return 0; + cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); + node = dev_to_node(cmn->dev); + if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) + arm_cmn_migrate(cmn, cpu); + return 0; +} + +static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) +{ + struct arm_cmn *cmn; + unsigned int target; + int node; + cpumask_t mask; - target = cpumask_any_but(cpu_online_mask, cpu); - if (target >= nr_cpu_ids) + cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); + if (cpu != cmn->cpu) return 0; - perf_pmu_migrate_context(&cmn->pmu, cpu, target); - for (i = 0; i < cmn->num_dtcs; i++) - irq_set_affinity(cmn->dtc[i].irq, cpumask_of(target)); - cmn->cpu = target; + node = dev_to_node(cmn->dev); + if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && + cpumask_andnot(&mask, &mask, cpumask_of(cpu))) + target = cpumask_any(&mask); + else + target = cpumask_any_but(cpu_online_mask, cpu); + if (target < nr_cpu_ids) + arm_cmn_migrate(cmn, target); return 0; } @@ -1532,7 +1556,7 @@ static int arm_cmn_probe(struct platform_device *pdev) if (err) return err; - cmn->cpu = raw_smp_processor_id(); + cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); cmn->pmu = (struct pmu) { .module = THIS_MODULE, .attr_groups = arm_cmn_attr_groups, @@ -1608,7 +1632,8 @@ static int __init arm_cmn_init(void) int ret; ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, - "perf/arm/cmn:online", NULL, + "perf/arm/cmn:online", + arm_cmn_pmu_online_cpu, arm_cmn_pmu_offline_cpu); if (ret < 0) return ret; -- GitLab From 82d8ea4b450074e81748830929bbd94eebbaffea Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:52 +0000 Subject: [PATCH 512/965] perf/arm-cmn: Drop compile-test restriction Although CMN is currently (and overwhelmingly likely to remain) deployed in arm64-only (modulo userspace) systems, the 64-bit "dependency" for compile-testing was just laziness due to heavy reliance on readq/writeq accessors. Since we only need one extra include for robustness in that regard, let's pull that in, widen the compile-test coverage, and fix up the smattering of type laziness that that brings to light. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/baee9ee0d0bdad8aaeb70f5a4b98d8fd4b1f5786.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/Kconfig | 2 +- drivers/perf/arm-cmn.c | 25 +++++++++++++------------ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 4374af292e6d0..1070515d340cb 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -43,7 +43,7 @@ config ARM_CCN config ARM_CMN tristate "Arm CMN-600 PMU support" - depends on ARM64 || (COMPILE_TEST && 64BIT) + depends on ARM64 || COMPILE_TEST help Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh Network interconnect. diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 02b898dbba91b..1d52fcfe3a0db 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -122,11 +123,11 @@ /* Event attributes */ -#define CMN_CONFIG_TYPE GENMASK(15, 0) -#define CMN_CONFIG_EVENTID GENMASK(23, 16) -#define CMN_CONFIG_OCCUPID GENMASK(27, 24) -#define CMN_CONFIG_BYNODEID BIT(31) -#define CMN_CONFIG_NODEID GENMASK(47, 32) +#define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) +#define CMN_CONFIG_EVENTID GENMASK_ULL(23, 16) +#define CMN_CONFIG_OCCUPID GENMASK_ULL(27, 24) +#define CMN_CONFIG_BYNODEID BIT_ULL(31) +#define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) @@ -134,13 +135,13 @@ #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) -#define CMN_CONFIG_WP_COMBINE GENMASK(27, 24) -#define CMN_CONFIG_WP_DEV_SEL BIT(48) -#define CMN_CONFIG_WP_CHN_SEL GENMASK(50, 49) -#define CMN_CONFIG_WP_GRP BIT(52) -#define CMN_CONFIG_WP_EXCLUSIVE BIT(53) -#define CMN_CONFIG1_WP_VAL GENMASK(63, 0) -#define CMN_CONFIG2_WP_MASK GENMASK(63, 0) +#define CMN_CONFIG_WP_COMBINE GENMASK_ULL(27, 24) +#define CMN_CONFIG_WP_DEV_SEL BIT_ULL(48) +#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(50, 49) +#define CMN_CONFIG_WP_GRP BIT_ULL(52) +#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(53) +#define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) +#define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) -- GitLab From 5f167eab83f153c2c6f80cfe419e269d5f481b09 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:53 +0000 Subject: [PATCH 513/965] perf/arm-cmn: Refactor node ID handling Add a bit more abstraction for the places where we decompose node IDs. This will help keep things nice and manageable when we come to add yet more variables which affect the node ID format. Also use the opportunity to move the rest of the low-level node management helpers back up to the logical place they were meant to be - how they ended up buried right in the middle of the event-related definitions is somewhat of a mystery... Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/a2242a8c3c96056c13a04ae87bf2047e5e64d2d9.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 94 +++++++++++++++++++++++++----------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 1d52fcfe3a0db..adf50d6137345 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -255,6 +255,58 @@ struct arm_cmn { static int arm_cmn_hp_state; +struct arm_cmn_nodeid { + u8 x; + u8 y; + u8 port; + u8 dev; +}; + +static int arm_cmn_xyidbits(const struct arm_cmn *cmn) +{ + int dim = max(cmn->mesh_x, cmn->mesh_y); + + return dim > 4 ? 3 : 2; +} + +static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id) +{ + struct arm_cmn_nodeid nid; + int bits = arm_cmn_xyidbits(cmn); + + nid.x = CMN_NODEID_X(id, bits); + nid.y = CMN_NODEID_Y(id, bits); + nid.port = CMN_NODEID_PID(id); + nid.dev = CMN_NODEID_DEVID(id); + + return nid; +} + +static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn, + struct arm_cmn_node *dn) +{ + struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); + int xp_idx = cmn->mesh_x * nid.y + nid.x; + + dn->to_xp = (cmn->xps + xp_idx) - dn; +} + +static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn) +{ + return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp; +} + +static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, + enum cmn_node_type type) +{ + int i; + + for (i = 0; i < cmn->num_dns; i++) + if (cmn->dns[i].type == type) + return &cmn->dns[i]; + return NULL; +} + struct arm_cmn_hw_event { struct arm_cmn_node *dn; u64 dtm_idx[2]; @@ -295,38 +347,6 @@ struct arm_cmn_format_attr { int config; }; -static int arm_cmn_xyidbits(const struct arm_cmn *cmn) -{ - return cmn->mesh_x > 4 || cmn->mesh_y > 4 ? 3 : 2; -} - -static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn, - struct arm_cmn_node *dn) -{ - int bits = arm_cmn_xyidbits(cmn); - int x = CMN_NODEID_X(dn->id, bits); - int y = CMN_NODEID_Y(dn->id, bits); - int xp_idx = cmn->mesh_x * y + x; - - dn->to_xp = (cmn->xps + xp_idx) - dn; -} - -static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn) -{ - return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp; -} - -static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, - enum cmn_node_type type) -{ - int i; - - for (i = 0; i < cmn->num_dns; i++) - if (cmn->dns[i].type == type) - return &cmn->dns[i]; - return NULL; -} - #define CMN_EVENT_ATTR(_name, _type, _eventid, _occupid) \ (&((struct arm_cmn_event_attr[]) {{ \ .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ @@ -966,11 +986,10 @@ static int arm_cmn_event_init(struct perf_event *event) } if (!hw->num_dns) { - int bits = arm_cmn_xyidbits(cmn); + struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid); dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n", - nodeid, CMN_NODEID_X(nodeid, bits), CMN_NODEID_Y(nodeid, bits), - CMN_NODEID_PID(nodeid), CMN_NODEID_DEVID(nodeid), type); + nodeid, nid.x, nid.y, nid.port, nid.dev, type); return -EINVAL; } /* @@ -1068,11 +1087,10 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) dn->wp_event[wp_idx] = dtc_idx; writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx)); } else { - unsigned int port = CMN_NODEID_PID(dn->id); - unsigned int dev = CMN_NODEID_DEVID(dn->id); + struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + - (port << 4) + (dev << 2); + (nid.port << 4) + (nid.dev << 2); if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) { int occupid = CMN_EVENT_OCCUPID(event); -- GitLab From da5f7d2c8019c9dd053e2d94fdc1b3e7c03c35a5 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:54 +0000 Subject: [PATCH 514/965] perf/arm-cmn: Streamline node iteration Refactor the places where we scan through the set of nodes to switch from explicit array indexing to pointer-based iteration. This leads to slightly simpler object code, but also makes the source less dense and more pleasant for further development. It also unearths an almost-bug in arm_cmn_event_init() where we've been depending on the "array index" of NULL relative to cmn->dns being a sufficiently large number, yuck. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/ee0c9eda9a643f46001ac43aadf3f0b1fd5660dd.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index adf50d6137345..da7bf779fec2b 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -299,11 +299,11 @@ static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn) static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, enum cmn_node_type type) { - int i; + struct arm_cmn_node *dn; - for (i = 0; i < cmn->num_dns; i++) - if (cmn->dns[i].type == type) - return &cmn->dns[i]; + for (dn = cmn->dns; dn->type; dn++) + if (dn->type == type) + return dn; return NULL; } @@ -941,8 +941,8 @@ static int arm_cmn_event_init(struct perf_event *event) { struct arm_cmn *cmn = to_cmn(event->pmu); struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_node *dn; enum cmn_node_type type; - unsigned int i; bool bynodeid; u16 nodeid, eventid; @@ -974,10 +974,12 @@ static int arm_cmn_event_init(struct perf_event *event) nodeid = CMN_EVENT_NODEID(event); hw->dn = arm_cmn_node(cmn, type); - for (i = hw->dn - cmn->dns; i < cmn->num_dns && cmn->dns[i].type == type; i++) { + if (!hw->dn) + return -EINVAL; + for (dn = hw->dn; dn->type == type; dn++) { if (!bynodeid) { hw->num_dns++; - } else if (cmn->dns[i].id != nodeid) { + } else if (dn->id != nodeid) { hw->dn++; } else { hw->num_dns = 1; @@ -1332,7 +1334,7 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); - for (dn = cmn->dns; dn < cmn->dns + cmn->num_dns; dn++) { + for (dn = cmn->dns; dn->type; dn++) { if (dn->type != CMN_TYPE_XP) arm_cmn_init_node_to_xp(cmn, dn); else if (cmn->num_dtcs == 1) @@ -1382,6 +1384,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) u32 xp_offset[CMN_MAX_XPS]; u64 reg; int i, j; + size_t sz; cfg_region = cmn->base + rgn_offset; reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); @@ -1408,14 +1411,13 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); } - /* Cheeky +1 to help terminate pointer-based iteration */ - cmn->dns = devm_kcalloc(cmn->dev, cmn->num_dns + 1, - sizeof(*cmn->dns), GFP_KERNEL); - if (!cmn->dns) + /* Cheeky +1 to help terminate pointer-based iteration later */ + dn = devm_kcalloc(cmn->dev, cmn->num_dns + 1, sizeof(*dn), GFP_KERNEL); + if (!dn) return -ENOMEM; /* Pass 2: now we can actually populate the nodes */ - dn = cmn->dns; + cmn->dns = dn; for (i = 0; i < cmn->num_xps; i++) { void __iomem *xp_region = cmn->base + xp_offset[i]; struct arm_cmn_node *xp = dn++; @@ -1484,6 +1486,11 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) /* Correct for any nodes we skipped */ cmn->num_dns = dn - cmn->dns; + sz = (void *)(dn + 1) - (void *)cmn->dns; + dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); + if (dn) + cmn->dns = dn; + /* * If mesh_x wasn't set during discovery then we never saw * an XP at (0,1), thus we must have an Nx1 configuration. -- GitLab From 0947c80aba23972987a88e620812d17a7af27297 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:55 +0000 Subject: [PATCH 515/965] perf/arm-cmn: Refactor DTM handling Untangle DTMs from XPs into a dedicated abstraction. This helps make things a little more obvious and robust, but primarily paves the way for further development where new IPs can grow extra DTMs per XP. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/9cca18b1b98f482df7f1aaf3d3213e7f39500423.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 169 +++++++++++++++++++++-------------------- 1 file changed, 87 insertions(+), 82 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index da7bf779fec2b..8b98ca9666d01 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -35,14 +35,9 @@ #define CMN_CHILD_NODE_ADDR GENMASK(27, 0) #define CMN_CHILD_NODE_EXTERNAL BIT(31) -#define CMN_ADDR_NODE_PTR GENMASK(27, 14) - -#define CMN_NODE_PTR_DEVID(ptr) (((ptr) >> 2) & 3) -#define CMN_NODE_PTR_PID(ptr) ((ptr) & 1) -#define CMN_NODE_PTR_X(ptr, bits) ((ptr) >> (6 + (bits))) -#define CMN_NODE_PTR_Y(ptr, bits) (((ptr) >> 6) & ((1U << (bits)) - 1)) - -#define CMN_MAX_XPS (8 * 8) +#define CMN_MAX_DIMENSION 8 +#define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) +#define CMN_MAX_DTMS CMN_MAX_XPS /* The CFG node has one other useful purpose */ #define CMN_CFGM_PERIPH_ID_2 0x0010 @@ -190,32 +185,32 @@ struct arm_cmn_node { u16 id, logid; enum cmn_node_type type; + int dtm; union { - /* Device node */ + /* DN/HN-F/CXHA */ struct { - int to_xp; - /* DN/HN-F/CXHA */ - unsigned int occupid_val; - unsigned int occupid_count; + u8 occupid_val; + u8 occupid_count; }; /* XP */ - struct { - int dtc; - u32 pmu_config_low; - union { - u8 input_sel[4]; - __le32 pmu_config_high; - }; - s8 wp_event[4]; - }; + int dtc; }; - union { u8 event[4]; __le32 event_sel; }; }; +struct arm_cmn_dtm { + void __iomem *base; + u32 pmu_config_low; + union { + u8 input_sel[4]; + __le32 pmu_config_high; + }; + s8 wp_event[4]; +}; + struct arm_cmn_dtc { void __iomem *base; int irq; @@ -241,6 +236,7 @@ struct arm_cmn { struct arm_cmn_node *xps; struct arm_cmn_node *dns; + struct arm_cmn_dtm *dtms; struct arm_cmn_dtc *dtc; unsigned int num_dtcs; @@ -282,20 +278,14 @@ static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id) return nid; } -static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn, - struct arm_cmn_node *dn) +static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, + const struct arm_cmn_node *dn) { struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); int xp_idx = cmn->mesh_x * nid.y + nid.x; - dn->to_xp = (cmn->xps + xp_idx) - dn; -} - -static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn) -{ - return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp; + return cmn->xps + xp_idx; } - static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, enum cmn_node_type type) { @@ -706,9 +696,9 @@ static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; for_each_hw_dn(hw, dn, i) { - struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn); + struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm]; int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); - u64 reg = readq_relaxed(xp->pmu_base + offset); + u64 reg = readq_relaxed(dtm->base + offset); u16 dtm_count = reg >> (dtm_idx * 16); count += dtm_count; @@ -835,9 +825,9 @@ static void arm_cmn_event_stop(struct perf_event *event, int flags) } struct arm_cmn_val { - u8 dtm_count[CMN_MAX_XPS]; - u8 occupid[CMN_MAX_XPS]; - u8 wp[CMN_MAX_XPS][4]; + u8 dtm_count[CMN_MAX_DTMS]; + u8 occupid[CMN_MAX_DTMS]; + u8 wp[CMN_MAX_DTMS][4]; int dtc_count; bool cycles; }; @@ -866,16 +856,16 @@ static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *ev occupid = 0; for_each_hw_dn(hw, dn, i) { - int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid; + int wp_idx, dtm = dn->dtm; - val->dtm_count[xp]++; - val->occupid[xp] = occupid; + val->dtm_count[dtm]++; + val->occupid[dtm] = occupid; if (type != CMN_TYPE_WP) continue; wp_idx = arm_cmn_wp_idx(event); - val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; + val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; } } @@ -914,22 +904,22 @@ static int arm_cmn_validate_group(struct perf_event *event) occupid = 0; for_each_hw_dn(hw, dn, i) { - int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid; + int wp_idx, wp_cmb, dtm = dn->dtm; - if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS) + if (val.dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) return -EINVAL; - if (occupid && val.occupid[xp] && occupid != val.occupid[xp]) + if (occupid && val.occupid[dtm] && occupid != val.occupid[dtm]) return -EINVAL; if (type != CMN_TYPE_WP) continue; wp_idx = arm_cmn_wp_idx(event); - if (val.wp[xp][wp_idx]) + if (val.wp[dtm][wp_idx]) return -EINVAL; - wp_cmb = val.wp[xp][wp_idx ^ 1]; + wp_cmb = val.wp[dtm][wp_idx ^ 1]; if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) return -EINVAL; } @@ -1010,17 +1000,17 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, enum cmn_node_type type = CMN_EVENT_TYPE(event); while (i--) { - struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i); + struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm]; unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); if (type == CMN_TYPE_WP) - hw->dn[i].wp_event[arm_cmn_wp_idx(event)] = -1; + dtm->wp_event[arm_cmn_wp_idx(event)] = -1; if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) hw->dn[i].occupid_count--; - xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); - writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG); + dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); + writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); } memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); @@ -1062,12 +1052,12 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) /* ...then the local counters to feed it. */ for_each_hw_dn(hw, dn, i) { - struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn); + struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm]; unsigned int dtm_idx, shift; u64 reg; dtm_idx = 0; - while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) + while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) if (++dtm_idx == CMN_DTM_NUM_COUNTERS) goto free_dtms; @@ -1077,17 +1067,17 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) int tmp, wp_idx = arm_cmn_wp_idx(event); u32 cfg = arm_cmn_wp_config(event); - if (dn->wp_event[wp_idx] >= 0) + if (dtm->wp_event[wp_idx] >= 0) goto free_dtms; - tmp = dn->wp_event[wp_idx ^ 1]; + tmp = dtm->wp_event[wp_idx ^ 1]; if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != CMN_EVENT_WP_COMBINE(dtc->counters[tmp])) goto free_dtms; input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; - dn->wp_event[wp_idx] = dtc_idx; - writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx)); + dtm->wp_event[wp_idx] = dtc_idx; + writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); } else { struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); @@ -1095,7 +1085,7 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) (nid.port << 4) + (nid.dev << 2); if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) { - int occupid = CMN_EVENT_OCCUPID(event); + u8 occupid = CMN_EVENT_OCCUPID(event); if (dn->occupid_count == 0) { dn->occupid_val = occupid; @@ -1110,13 +1100,13 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); - xp->input_sel[dtm_idx] = input_sel; + dtm->input_sel[dtm_idx] = input_sel; shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); - xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); - xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift; - xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); - reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low; - writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG); + dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); + dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift; + dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); + reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; + writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); } /* Go go go! */ @@ -1276,23 +1266,22 @@ static int arm_cmn_init_irqs(struct arm_cmn *cmn) return 0; } -static void arm_cmn_init_dtm(struct arm_cmn_node *xp) +static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp) { int i; + dtm->base = xp->pmu_base; + dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; for (i = 0; i < 4; i++) { - xp->wp_event[i] = -1; - writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i)); - writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i)); + dtm->wp_event[i] = -1; + writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); + writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); } - xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; - xp->dtc = -1; } static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) { struct arm_cmn_dtc *dtc = cmn->dtc + idx; - struct arm_cmn_node *xp; dtc->base = dn->pmu_base - CMN_PMU_OFFSET; dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); @@ -1303,10 +1292,6 @@ static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int id writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); writel_relaxed(CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR); - /* We do at least know that a DTC's XP must be in that DTC's domain */ - xp = arm_cmn_node_to_xp(dn); - xp->dtc = idx; - return 0; } @@ -1323,7 +1308,7 @@ static int arm_cmn_node_cmp(const void *a, const void *b) static int arm_cmn_init_dtcs(struct arm_cmn *cmn) { - struct arm_cmn_node *dn; + struct arm_cmn_node *dn, *xp; int dtc_idx = 0; cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); @@ -1335,13 +1320,24 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); for (dn = cmn->dns; dn->type; dn++) { - if (dn->type != CMN_TYPE_XP) - arm_cmn_init_node_to_xp(cmn, dn); - else if (cmn->num_dtcs == 1) - dn->dtc = 0; + if (dn->type == CMN_TYPE_XP) { + if (dn->dtc < 0 && cmn->num_dtcs == 1) + dn->dtc = 0; + continue; + } - if (dn->type == CMN_TYPE_DTC) - arm_cmn_init_dtc(cmn, dn, dtc_idx++); + xp = arm_cmn_node_to_xp(cmn, dn); + dn->dtm = xp->dtm; + + if (dn->type == CMN_TYPE_DTC) { + int err; + /* We do at least know that a DTC's XP must be in that DTC's domain */ + if (xp->dtc < 0) + xp->dtc = dtc_idx; + err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); + if (err) + return err; + } /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ if (dn->type == CMN_TYPE_RND) @@ -1380,6 +1376,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) { void __iomem *cfg_region; struct arm_cmn_node cfg, *dn; + struct arm_cmn_dtm *dtm; u16 child_count, child_poff; u32 xp_offset[CMN_MAX_XPS]; u64 reg; @@ -1416,14 +1413,18 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (!dn) return -ENOMEM; + dtm = devm_kcalloc(cmn->dev, cmn->num_xps, sizeof(*dtm), GFP_KERNEL); + if (!dtm) + return -ENOMEM; + /* Pass 2: now we can actually populate the nodes */ cmn->dns = dn; + cmn->dtms = dtm; for (i = 0; i < cmn->num_xps; i++) { void __iomem *xp_region = cmn->base + xp_offset[i]; struct arm_cmn_node *xp = dn++; arm_cmn_init_node_info(cmn, xp_offset[i], xp); - arm_cmn_init_dtm(xp); /* * Thanks to the order in which XP logical IDs seem to be * assigned, we can handily infer the mesh X dimension by @@ -1433,6 +1434,10 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (xp->id == (1 << 3)) cmn->mesh_x = xp->logid; + xp->dtc = -1; + xp->dtm = dtm - cmn->dtms; + arm_cmn_init_dtm(dtm++, xp); + reg = readq_relaxed(xp_region + CMN_CHILD_INFO); child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); -- GitLab From 847eef94e6327dd7690bfac0bd3a81a7ba6aa1ee Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:56 +0000 Subject: [PATCH 516/965] perf/arm-cmn: Optimise DTM counter reads When multiple nodes of the same type are connected to the same XP (particularly in CAL configurations), it seems that they are likely to be consecutive in logical ID. Therefore, we're likely to gain a small benefit from an easy tweak to optimise out consecutive reads of the same set of DTM counters for an aggregated event. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/7777d77c2df17693cd3dabb6e268906e15238d82.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 8b98ca9666d01..005a0d83bcac4 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -690,18 +690,19 @@ static void arm_cmn_pmu_disable(struct pmu *pmu) static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, bool snapshot) { + struct arm_cmn_dtm *dtm = NULL; struct arm_cmn_node *dn; - unsigned int i, offset; - u64 count = 0; + unsigned int i, offset, dtm_idx; + u64 reg, count = 0; offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; for_each_hw_dn(hw, dn, i) { - struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm]; - int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); - u64 reg = readq_relaxed(dtm->base + offset); - u16 dtm_count = reg >> (dtm_idx * 16); - - count += dtm_count; + if (dtm != &cmn->dtms[dn->dtm]) { + dtm = &cmn->dtms[dn->dtm]; + reg = readq_relaxed(dtm->base + offset); + } + dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); + count += (u16)(reg >> (dtm_idx * 16)); } return count; } -- GitLab From 4f2c3872dde55090bf39e1f12a8517a32b6cd048 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:57 +0000 Subject: [PATCH 517/965] perf/arm-cmn: Optimise DTC counter accesses In cases where we do know which DTC domain a node belongs to, we can skip initialising or reading the global count in DTCs where we know it won't change. The machinery to achieve that is mostly in place already, so finish hooking it up by converting the vestigial domain tracking to propagate suitable bitmaps all the way through to events. Note that this does not allow allocating such an unused counter to a different event on that DTC, because that is a flippin' nightmare. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/51d930fd945ef51c81f5889ccca055c302b0a1d0.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 005a0d83bcac4..acff8683af2c2 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -193,7 +193,7 @@ struct arm_cmn_node { u8 occupid_count; }; /* XP */ - int dtc; + u8 dtc; }; union { u8 event[4]; @@ -968,14 +968,14 @@ static int arm_cmn_event_init(struct perf_event *event) if (!hw->dn) return -EINVAL; for (dn = hw->dn; dn->type == type; dn++) { - if (!bynodeid) { - hw->num_dns++; - } else if (dn->id != nodeid) { + if (bynodeid && dn->id != nodeid) { hw->dn++; - } else { - hw->num_dns = 1; - break; + continue; } + hw->dtcs_used |= arm_cmn_node_to_xp(cmn, dn)->dtc; + hw->num_dns++; + if (bynodeid) + break; } if (!hw->num_dns) { @@ -985,11 +985,6 @@ static int arm_cmn_event_init(struct perf_event *event) nodeid, nid.x, nid.y, nid.port, nid.dev, type); return -EINVAL; } - /* - * By assuming events count in all DTC domains, we cunningly avoid - * needing to know anything about how XPs are assigned to domains. - */ - hw->dtcs_used = (1U << cmn->num_dtcs) - 1; return arm_cmn_validate_group(event); } @@ -1311,6 +1306,7 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) { struct arm_cmn_node *dn, *xp; int dtc_idx = 0; + u8 dtcs_present = (1 << cmn->num_dtcs) - 1; cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); if (!cmn->dtc) @@ -1322,8 +1318,7 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) for (dn = cmn->dns; dn->type; dn++) { if (dn->type == CMN_TYPE_XP) { - if (dn->dtc < 0 && cmn->num_dtcs == 1) - dn->dtc = 0; + dn->dtc &= dtcs_present; continue; } @@ -1333,8 +1328,8 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) if (dn->type == CMN_TYPE_DTC) { int err; /* We do at least know that a DTC's XP must be in that DTC's domain */ - if (xp->dtc < 0) - xp->dtc = dtc_idx; + if (xp->dtc == 0xf) + xp->dtc = 1 << dtc_idx; err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); if (err) return err; @@ -1435,7 +1430,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (xp->id == (1 << 3)) cmn->mesh_x = xp->logid; - xp->dtc = -1; + xp->dtc = 0xf; xp->dtm = dtm - cmn->dtms; arm_cmn_init_dtm(dtm++, xp); -- GitLab From 558a07807038017255005a4820f600da643d8a5f Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:58 +0000 Subject: [PATCH 518/965] perf/arm-cmn: Move group validation data off-stack With the value of CMN_MAX_DTMS increasing significantly, our validation data structure is set to get quite big. Technically we could pack it at least twice as densely, since we only need around 19 bits of information per DTM, but that makes the code even more mind-bogglingly impenetrable, and even half of "quite big" may still be uncomfortably large for a stack frame (~1KB). Just move it to an off-stack allocation instead. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/0cabff2e5839ddc0979e757c55515966f65359e4.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 43 ++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index acff8683af2c2..d2dd02f040b8c 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -876,8 +876,8 @@ static int arm_cmn_validate_group(struct perf_event *event) struct arm_cmn_node *dn; struct perf_event *sibling, *leader = event->group_leader; enum cmn_node_type type; - struct arm_cmn_val val; - int i; + struct arm_cmn_val *val; + int i, ret = -EINVAL; u8 occupid; if (leader == event) @@ -886,18 +886,22 @@ static int arm_cmn_validate_group(struct perf_event *event) if (event->pmu != leader->pmu && !is_software_event(leader)) return -EINVAL; - memset(&val, 0, sizeof(val)); + val = kzalloc(sizeof(*val), GFP_KERNEL); + if (!val) + return -ENOMEM; - arm_cmn_val_add_event(&val, leader); + arm_cmn_val_add_event(val, leader); for_each_sibling_event(sibling, leader) - arm_cmn_val_add_event(&val, sibling); + arm_cmn_val_add_event(val, sibling); type = CMN_EVENT_TYPE(event); - if (type == CMN_TYPE_DTC) - return val.cycles ? -EINVAL : 0; + if (type == CMN_TYPE_DTC) { + ret = val->cycles ? -EINVAL : 0; + goto done; + } - if (val.dtc_count == CMN_DT_NUM_COUNTERS) - return -EINVAL; + if (val->dtc_count == CMN_DT_NUM_COUNTERS) + goto done; if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) occupid = CMN_EVENT_OCCUPID(event) + 1; @@ -907,25 +911,28 @@ static int arm_cmn_validate_group(struct perf_event *event) for_each_hw_dn(hw, dn, i) { int wp_idx, wp_cmb, dtm = dn->dtm; - if (val.dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) - return -EINVAL; + if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) + goto done; - if (occupid && val.occupid[dtm] && occupid != val.occupid[dtm]) - return -EINVAL; + if (occupid && val->occupid[dtm] && occupid != val->occupid[dtm]) + goto done; if (type != CMN_TYPE_WP) continue; wp_idx = arm_cmn_wp_idx(event); - if (val.wp[dtm][wp_idx]) - return -EINVAL; + if (val->wp[dtm][wp_idx]) + goto done; - wp_cmb = val.wp[dtm][wp_idx ^ 1]; + wp_cmb = val->wp[dtm][wp_idx ^ 1]; if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) - return -EINVAL; + goto done; } - return 0; + ret = 0; +done: + kfree(val); + return ret; } static int arm_cmn_event_init(struct perf_event *event) -- GitLab From 61ec1d875812046ff9d473183d53e19dcd6b2ada Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:44:59 +0000 Subject: [PATCH 519/965] perf/arm-cmn: Demarcate CMN-600 specifics In preparation for supporting newer CMN products, let's introduce a means to differentiate the features and events which are specific to a particular IP from those which remain common to the whole family. The newer designs have also smoothed off some of the rough edges in terms of discoverability, so separate out the parts of the flow which have effectively now become CMN-600 quirks. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/9f6368cdca4c821d801138939508a5bba54ccabb.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 313 +++++++++++++++++++++-------------------- 1 file changed, 162 insertions(+), 151 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index d2dd02f040b8c..ce94f923a6079 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -151,7 +151,12 @@ #define CMN_WP_DOWN 2 -/* r0px probably don't exist in silicon, thankfully */ +enum cmn_model { + CMN_ANY = -1, + CMN600 = 1, +}; + +/* CMN-600 r0px shouldn't exist in silicon, thankfully */ enum cmn_revision { CMN600_R1P0, CMN600_R1P1, @@ -159,6 +164,7 @@ enum cmn_revision { CMN600_R1P3, CMN600_R2P0, CMN600_R3P0, + CMN600_R3P1, }; enum cmn_node_type { @@ -229,6 +235,7 @@ struct arm_cmn { void __iomem *base; enum cmn_revision rev; + enum cmn_model model; u8 mesh_x; u8 mesh_y; u16 num_xps; @@ -326,6 +333,7 @@ static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) struct arm_cmn_event_attr { struct device_attribute attr; + enum cmn_model model; enum cmn_node_type type; u8 eventid; u8 occupid; @@ -337,9 +345,10 @@ struct arm_cmn_format_attr { int config; }; -#define CMN_EVENT_ATTR(_name, _type, _eventid, _occupid) \ +#define CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid) \ (&((struct arm_cmn_event_attr[]) {{ \ .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ + .model = _model, \ .type = _type, \ .eventid = _eventid, \ .occupid = _occupid, \ @@ -386,12 +395,15 @@ static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, eattr = container_of(attr, typeof(*eattr), attr.attr); type = eattr->type; + if (!(eattr->model & cmn->model)) + return 0; + /* Watchpoints aren't nodes */ if (type == CMN_TYPE_WP) type = CMN_TYPE_XP; /* Revision-specific differences */ - if (cmn->rev < CMN600_R1P2) { + if (cmn->model == CMN600 && cmn->rev < CMN600_R1P2) { if (type == CMN_TYPE_HNF && eattr->eventid == 0x1b) return 0; } @@ -402,25 +414,27 @@ static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, return attr->mode; } -#define _CMN_EVENT_DVM(_name, _event, _occup) \ - CMN_EVENT_ATTR(dn_##_name, CMN_TYPE_DVM, _event, _occup) +#define _CMN_EVENT_DVM(_model, _name, _event, _occup) \ + CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup) #define CMN_EVENT_DTC(_name) \ - CMN_EVENT_ATTR(dtc_##_name, CMN_TYPE_DTC, 0, 0) -#define _CMN_EVENT_HNF(_name, _event, _occup) \ - CMN_EVENT_ATTR(hnf_##_name, CMN_TYPE_HNF, _event, _occup) + CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0, 0) +#define _CMN_EVENT_HNF(_model, _name, _event, _occup) \ + CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event, _occup) #define CMN_EVENT_HNI(_name, _event) \ - CMN_EVENT_ATTR(hni_##_name, CMN_TYPE_HNI, _event, 0) + CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event, 0) #define __CMN_EVENT_XP(_name, _event) \ - CMN_EVENT_ATTR(mxp_##_name, CMN_TYPE_XP, _event, 0) -#define CMN_EVENT_SBSX(_name, _event) \ - CMN_EVENT_ATTR(sbsx_##_name, CMN_TYPE_SBSX, _event, 0) -#define CMN_EVENT_RNID(_name, _event) \ - CMN_EVENT_ATTR(rnid_##_name, CMN_TYPE_RNI, _event, 0) - -#define CMN_EVENT_DVM(_name, _event) \ - _CMN_EVENT_DVM(_name, _event, 0) -#define CMN_EVENT_HNF(_name, _event) \ - _CMN_EVENT_HNF(_name, _event, 0) + CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event, 0) +#define CMN_EVENT_SBSX(_model, _name, _event) \ + CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event, 0) +#define CMN_EVENT_RNID(_model, _name, _event) \ + CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event, 0) +#define CMN_EVENT_MTSX(_name, _event) \ + CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event, 0) + +#define CMN_EVENT_DVM(_model, _name, _event) \ + _CMN_EVENT_DVM(_model, _name, _event, 0) +#define CMN_EVENT_HNF(_model, _name, _event) \ + _CMN_EVENT_HNF(_model, _name, _event, 0) #define _CMN_EVENT_XP(_name, _event) \ __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ @@ -445,115 +459,115 @@ static struct attribute *arm_cmn_event_attrs[] = { * slot, but our lazy short-cut of using the DTM counter index for * the PMU index as well happens to avoid that by construction. */ - CMN_EVENT_DVM(rxreq_dvmop, 0x01), - CMN_EVENT_DVM(rxreq_dvmsync, 0x02), - CMN_EVENT_DVM(rxreq_dvmop_vmid_filtered, 0x03), - CMN_EVENT_DVM(rxreq_retried, 0x04), - _CMN_EVENT_DVM(rxreq_trk_occupancy_all, 0x05, 0), - _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmop, 0x05, 1), - _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmsync, 0x05, 2), - - CMN_EVENT_HNF(cache_miss, 0x01), - CMN_EVENT_HNF(slc_sf_cache_access, 0x02), - CMN_EVENT_HNF(cache_fill, 0x03), - CMN_EVENT_HNF(pocq_retry, 0x04), - CMN_EVENT_HNF(pocq_reqs_recvd, 0x05), - CMN_EVENT_HNF(sf_hit, 0x06), - CMN_EVENT_HNF(sf_evictions, 0x07), - CMN_EVENT_HNF(dir_snoops_sent, 0x08), - CMN_EVENT_HNF(brd_snoops_sent, 0x09), - CMN_EVENT_HNF(slc_eviction, 0x0a), - CMN_EVENT_HNF(slc_fill_invalid_way, 0x0b), - CMN_EVENT_HNF(mc_retries, 0x0c), - CMN_EVENT_HNF(mc_reqs, 0x0d), - CMN_EVENT_HNF(qos_hh_retry, 0x0e), - _CMN_EVENT_HNF(qos_pocq_occupancy_all, 0x0f, 0), - _CMN_EVENT_HNF(qos_pocq_occupancy_read, 0x0f, 1), - _CMN_EVENT_HNF(qos_pocq_occupancy_write, 0x0f, 2), - _CMN_EVENT_HNF(qos_pocq_occupancy_atomic, 0x0f, 3), - _CMN_EVENT_HNF(qos_pocq_occupancy_stash, 0x0f, 4), - CMN_EVENT_HNF(pocq_addrhaz, 0x10), - CMN_EVENT_HNF(pocq_atomic_addrhaz, 0x11), - CMN_EVENT_HNF(ld_st_swp_adq_full, 0x12), - CMN_EVENT_HNF(cmp_adq_full, 0x13), - CMN_EVENT_HNF(txdat_stall, 0x14), - CMN_EVENT_HNF(txrsp_stall, 0x15), - CMN_EVENT_HNF(seq_full, 0x16), - CMN_EVENT_HNF(seq_hit, 0x17), - CMN_EVENT_HNF(snp_sent, 0x18), - CMN_EVENT_HNF(sfbi_dir_snp_sent, 0x19), - CMN_EVENT_HNF(sfbi_brd_snp_sent, 0x1a), - CMN_EVENT_HNF(snp_sent_untrk, 0x1b), - CMN_EVENT_HNF(intv_dirty, 0x1c), - CMN_EVENT_HNF(stash_snp_sent, 0x1d), - CMN_EVENT_HNF(stash_data_pull, 0x1e), - CMN_EVENT_HNF(snp_fwded, 0x1f), - - CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), - CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), - CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), - CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), - CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), - CMN_EVENT_HNI(rrt_rd_alloc, 0x25), - CMN_EVENT_HNI(rrt_wr_alloc, 0x26), - CMN_EVENT_HNI(rdt_rd_alloc, 0x27), - CMN_EVENT_HNI(rdt_wr_alloc, 0x28), - CMN_EVENT_HNI(wdb_alloc, 0x29), - CMN_EVENT_HNI(txrsp_retryack, 0x2a), - CMN_EVENT_HNI(arvalid_no_arready, 0x2b), - CMN_EVENT_HNI(arready_no_arvalid, 0x2c), - CMN_EVENT_HNI(awvalid_no_awready, 0x2d), - CMN_EVENT_HNI(awready_no_awvalid, 0x2e), - CMN_EVENT_HNI(wvalid_no_wready, 0x2f), - CMN_EVENT_HNI(txdat_stall, 0x30), - CMN_EVENT_HNI(nonpcie_serialization, 0x31), - CMN_EVENT_HNI(pcie_serialization, 0x32), - - CMN_EVENT_XP(txflit_valid, 0x01), - CMN_EVENT_XP(txflit_stall, 0x02), - CMN_EVENT_XP(partial_dat_flit, 0x03), + CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), + CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), + CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), + CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), + _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_all, 0x05, 0), + _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_dvmop, 0x05, 1), + _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_dvmsync, 0x05, 2), + + CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), + CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), + CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), + CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), + CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), + CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), + CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), + CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), + CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), + CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), + CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), + CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), + CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), + CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), + _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_all, 0x0f, 0), + _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_read, 0x0f, 1), + _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_write, 0x0f, 2), + _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_atomic, 0x0f, 3), + _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_stash, 0x0f, 4), + CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), + CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), + CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), + CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), + CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), + CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), + CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), + CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), + CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), + CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), + CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), + CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), + CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), + CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), + CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), + CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), + + CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), + CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), + CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), + CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), + CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), + CMN_EVENT_HNI(rrt_rd_alloc, 0x25), + CMN_EVENT_HNI(rrt_wr_alloc, 0x26), + CMN_EVENT_HNI(rdt_rd_alloc, 0x27), + CMN_EVENT_HNI(rdt_wr_alloc, 0x28), + CMN_EVENT_HNI(wdb_alloc, 0x29), + CMN_EVENT_HNI(txrsp_retryack, 0x2a), + CMN_EVENT_HNI(arvalid_no_arready, 0x2b), + CMN_EVENT_HNI(arready_no_arvalid, 0x2c), + CMN_EVENT_HNI(awvalid_no_awready, 0x2d), + CMN_EVENT_HNI(awready_no_awvalid, 0x2e), + CMN_EVENT_HNI(wvalid_no_wready, 0x2f), + CMN_EVENT_HNI(txdat_stall, 0x30), + CMN_EVENT_HNI(nonpcie_serialization, 0x31), + CMN_EVENT_HNI(pcie_serialization, 0x32), + + CMN_EVENT_XP(txflit_valid, 0x01), + CMN_EVENT_XP(txflit_stall, 0x02), + CMN_EVENT_XP(partial_dat_flit, 0x03), /* We treat watchpoints as a special made-up class of XP events */ - CMN_EVENT_ATTR(watchpoint_up, CMN_TYPE_WP, 0, 0), - CMN_EVENT_ATTR(watchpoint_down, CMN_TYPE_WP, 2, 0), - - CMN_EVENT_SBSX(rd_req, 0x01), - CMN_EVENT_SBSX(wr_req, 0x02), - CMN_EVENT_SBSX(cmo_req, 0x03), - CMN_EVENT_SBSX(txrsp_retryack, 0x04), - CMN_EVENT_SBSX(txdat_flitv, 0x05), - CMN_EVENT_SBSX(txrsp_flitv, 0x06), - CMN_EVENT_SBSX(rd_req_trkr_occ_cnt_ovfl, 0x11), - CMN_EVENT_SBSX(wr_req_trkr_occ_cnt_ovfl, 0x12), - CMN_EVENT_SBSX(cmo_req_trkr_occ_cnt_ovfl, 0x13), - CMN_EVENT_SBSX(wdb_occ_cnt_ovfl, 0x14), - CMN_EVENT_SBSX(rd_axi_trkr_occ_cnt_ovfl, 0x15), - CMN_EVENT_SBSX(cmo_axi_trkr_occ_cnt_ovfl, 0x16), - CMN_EVENT_SBSX(arvalid_no_arready, 0x21), - CMN_EVENT_SBSX(awvalid_no_awready, 0x22), - CMN_EVENT_SBSX(wvalid_no_wready, 0x23), - CMN_EVENT_SBSX(txdat_stall, 0x24), - CMN_EVENT_SBSX(txrsp_stall, 0x25), - - CMN_EVENT_RNID(s0_rdata_beats, 0x01), - CMN_EVENT_RNID(s1_rdata_beats, 0x02), - CMN_EVENT_RNID(s2_rdata_beats, 0x03), - CMN_EVENT_RNID(rxdat_flits, 0x04), - CMN_EVENT_RNID(txdat_flits, 0x05), - CMN_EVENT_RNID(txreq_flits_total, 0x06), - CMN_EVENT_RNID(txreq_flits_retried, 0x07), - CMN_EVENT_RNID(rrt_occ_ovfl, 0x08), - CMN_EVENT_RNID(wrt_occ_ovfl, 0x09), - CMN_EVENT_RNID(txreq_flits_replayed, 0x0a), - CMN_EVENT_RNID(wrcancel_sent, 0x0b), - CMN_EVENT_RNID(s0_wdata_beats, 0x0c), - CMN_EVENT_RNID(s1_wdata_beats, 0x0d), - CMN_EVENT_RNID(s2_wdata_beats, 0x0e), - CMN_EVENT_RNID(rrt_alloc, 0x0f), - CMN_EVENT_RNID(wrt_alloc, 0x10), - CMN_EVENT_RNID(rdb_unord, 0x11), - CMN_EVENT_RNID(rdb_replay, 0x12), - CMN_EVENT_RNID(rdb_hybrid, 0x13), - CMN_EVENT_RNID(rdb_ord, 0x14), + CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP, 0), + CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN, 0), + + CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), + CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), + CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), + CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), + CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), + CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), + CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), + CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), + CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), + CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), + CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), + CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), + CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), + CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), + CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), + CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), + CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), + + CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), + CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), + CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), + CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), + CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), + CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), + CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), + CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), + CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), + CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), + CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), + CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), + CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), + CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), + CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), + CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), + CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), + CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), + CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), + CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), NULL }; @@ -1386,15 +1400,14 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) int i, j; size_t sz; - cfg_region = cmn->base + rgn_offset; - reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); - cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); - dev_dbg(cmn->dev, "periph_id_2 revision: %d\n", cmn->rev); - arm_cmn_init_node_info(cmn, rgn_offset, &cfg); if (cfg.type != CMN_TYPE_CFG) return -ENODEV; + cfg_region = cmn->base + rgn_offset; + reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); + cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); + reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); @@ -1507,13 +1520,14 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) cmn->mesh_x = cmn->num_xps; cmn->mesh_y = cmn->num_xps / cmn->mesh_x; + dev_dbg(cmn->dev, "model %d, periph_id_2 revision %d\n", cmn->model, cmn->rev); dev_dbg(cmn->dev, "mesh %dx%d, ID width %d\n", cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn)); return 0; } -static int arm_cmn_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) +static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) { struct resource *cfg, *root; @@ -1540,21 +1554,11 @@ static int arm_cmn_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) return root->start - cfg->start; } -static int arm_cmn_of_probe(struct platform_device *pdev, struct arm_cmn *cmn) +static int arm_cmn600_of_probe(struct device_node *np) { - struct device_node *np = pdev->dev.of_node; u32 rootnode; - int ret; - cmn->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(cmn->base)) - return PTR_ERR(cmn->base); - - ret = of_property_read_u32(np, "arm,root-node", &rootnode); - if (ret) - return ret; - - return rootnode; + return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; } static int arm_cmn_probe(struct platform_device *pdev) @@ -1569,12 +1573,19 @@ static int arm_cmn_probe(struct platform_device *pdev) return -ENOMEM; cmn->dev = &pdev->dev; + cmn->model = (unsigned long)device_get_match_data(cmn->dev); platform_set_drvdata(pdev, cmn); - if (has_acpi_companion(cmn->dev)) - rootnode = arm_cmn_acpi_probe(pdev, cmn); - else - rootnode = arm_cmn_of_probe(pdev, cmn); + if (cmn->model == CMN600 && has_acpi_companion(cmn->dev)) { + rootnode = arm_cmn600_acpi_probe(pdev, cmn); + } else { + rootnode = 0; + cmn->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cmn->base)) + return PTR_ERR(cmn->base); + if (cmn->model == CMN600) + rootnode = arm_cmn600_of_probe(pdev->dev.of_node); + } if (rootnode < 0) return rootnode; @@ -1637,7 +1648,7 @@ static int arm_cmn_remove(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id arm_cmn_of_match[] = { - { .compatible = "arm,cmn-600", }, + { .compatible = "arm,cmn-600", .data = (void *)CMN600 }, {} }; MODULE_DEVICE_TABLE(of, arm_cmn_of_match); @@ -1645,7 +1656,7 @@ MODULE_DEVICE_TABLE(of, arm_cmn_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id arm_cmn_acpi_match[] = { - { "ARMHC600", }, + { "ARMHC600", CMN600 }, {} }; MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); -- GitLab From 60d1504070c22c059a1e11bc3fd444953da988c1 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:45:00 +0000 Subject: [PATCH 520/965] perf/arm-cmn: Support new IP features The second generation of CMN IPs add new node types and significantly expand the configuration space with options for extra device ports on edge XPs, either plumbed into the regular DTM or with extra dedicated DTMs to monitor them, plus larger (and smaller) mesh sizes. Add basic support for pulling this new information out of the hardware, piping it around as necessary, and handling (most of) the new choices. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/e58b495bcc7deec3882be4bac910ed0bf6979674.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 218 ++++++++++++++++++++++++++++++++--------- 1 file changed, 171 insertions(+), 47 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index ce94f923a6079..0a3f33a83c01f 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -24,7 +24,10 @@ #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) #define CMN_NODEID_DEVID(reg) ((reg) & 3) +#define CMN_NODEID_EXT_DEVID(reg) ((reg) & 1) #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1) +#define CMN_NODEID_EXT_PID(reg) (((reg) >> 1) & 3) +#define CMN_NODEID_1x1_PID(reg) (((reg) >> 2) & 7) #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits))) #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1)) @@ -37,13 +40,26 @@ #define CMN_MAX_DIMENSION 8 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) -#define CMN_MAX_DTMS CMN_MAX_XPS +#define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) -/* The CFG node has one other useful purpose */ +/* The CFG node has various info besides the discovery tree */ #define CMN_CFGM_PERIPH_ID_2 0x0010 #define CMN_CFGM_PID2_REVISION GENMASK(7, 4) -/* PMU registers occupy the 3rd 4KB page of each node's 16KB space */ +#define CMN_CFGM_INFO_GLOBAL 0x900 +#define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) +#define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) +#define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) + +/* XPs also have some local topology info which has uses too */ +#define CMN_MXP__CONNECT_INFO_P0 0x0008 +#define CMN_MXP__CONNECT_INFO_P1 0x0010 +#define CMN_MXP__CONNECT_INFO_P2 0x0028 +#define CMN_MXP__CONNECT_INFO_P3 0x0030 +#define CMN_MXP__CONNECT_INFO_P4 0x0038 +#define CMN_MXP__CONNECT_INFO_P5 0x0040 + +/* PMU registers occupy the 3rd 4KB page of each node's region */ #define CMN_PMU_OFFSET 0x2000 /* For most nodes, this is all there is */ @@ -53,6 +69,7 @@ /* DTMs live in the PMU space of XP registers */ #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) +#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18,17) #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(6) #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(5) #define CMN_DTM_WPn_CONFIG_WP_GRP BIT(4) @@ -77,7 +94,11 @@ #define CMN_DTM_PMEVCNTSR 0x240 +#define CMN_DTM_UNIT_INFO 0x0910 + #define CMN_DTM_NUM_COUNTERS 4 +/* Want more local counters? Why not replicate the whole DTM! Ugh... */ +#define CMN_DTM_OFFSET(n) ((n) * 0x200) /* The DTC node is where the magic happens */ #define CMN_DT_DTC_CTL 0x0a00 @@ -131,10 +152,10 @@ #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(27, 24) -#define CMN_CONFIG_WP_DEV_SEL BIT_ULL(48) -#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(50, 49) -#define CMN_CONFIG_WP_GRP BIT_ULL(52) -#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(53) +#define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) +#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) +#define CMN_CONFIG_WP_GRP BIT_ULL(56) +#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57) #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) @@ -176,9 +197,12 @@ enum cmn_node_type { CMN_TYPE_HNF, CMN_TYPE_XP, CMN_TYPE_SBSX, - CMN_TYPE_RNI = 0xa, + CMN_TYPE_MPAM_S, + CMN_TYPE_MPAM_NS, + CMN_TYPE_RNI, CMN_TYPE_RND = 0xd, CMN_TYPE_RNSAM = 0xf, + CMN_TYPE_MTSX, CMN_TYPE_CXRA = 0x100, CMN_TYPE_CXHA = 0x101, CMN_TYPE_CXLA = 0x102, @@ -233,6 +257,7 @@ struct arm_cmn_dtc { struct arm_cmn { struct device *dev; void __iomem *base; + unsigned int state; enum cmn_revision rev; enum cmn_model model; @@ -240,6 +265,13 @@ struct arm_cmn { u8 mesh_y; u16 num_xps; u16 num_dns; + bool multi_dtm; + u8 ports_used; + struct { + unsigned int rsp_vc_num : 2; + unsigned int dat_vc_num : 2; + }; + struct arm_cmn_node *xps; struct arm_cmn_node *dns; @@ -250,7 +282,6 @@ struct arm_cmn { int cpu; struct hlist_node cpuhp_node; - unsigned int state; struct pmu pmu; }; @@ -275,13 +306,25 @@ static int arm_cmn_xyidbits(const struct arm_cmn *cmn) static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id) { struct arm_cmn_nodeid nid; - int bits = arm_cmn_xyidbits(cmn); - nid.x = CMN_NODEID_X(id, bits); - nid.y = CMN_NODEID_Y(id, bits); - nid.port = CMN_NODEID_PID(id); - nid.dev = CMN_NODEID_DEVID(id); + if (cmn->num_xps == 1) { + nid.x = 0; + nid.y = 0; + nid.port = CMN_NODEID_1x1_PID(id); + nid.dev = CMN_NODEID_DEVID(id); + } else { + int bits = arm_cmn_xyidbits(cmn); + nid.x = CMN_NODEID_X(id, bits); + nid.y = CMN_NODEID_Y(id, bits); + if (cmn->ports_used & 0xc) { + nid.port = CMN_NODEID_EXT_PID(id); + nid.dev = CMN_NODEID_EXT_DEVID(id); + } else { + nid.port = CMN_NODEID_PID(id); + nid.dev = CMN_NODEID_DEVID(id); + } + } return nid; } @@ -310,6 +353,7 @@ struct arm_cmn_hw_event { unsigned int dtc_idx; u8 dtcs_used; u8 num_dns; + u8 dtm_offset; }; #define for_each_hw_dn(hw, dn, i) \ @@ -354,7 +398,8 @@ struct arm_cmn_format_attr { .occupid = _occupid, \ }})[0].attr.attr) -static bool arm_cmn_is_occup_event(enum cmn_node_type type, unsigned int id) +static bool arm_cmn_is_occup_event(enum cmn_model model, + enum cmn_node_type type, unsigned int id) { return (type == CMN_TYPE_DVM && id == 0x05) || (type == CMN_TYPE_HNF && id == 0x0f); @@ -375,7 +420,7 @@ static ssize_t arm_cmn_event_show(struct device *dev, "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", eattr->type, eattr->eventid); - if (arm_cmn_is_occup_event(eattr->type, eattr->eventid)) + if (arm_cmn_is_occup_event(eattr->model, eattr->type, eattr->eventid)) return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n", eattr->type, eattr->eventid, eattr->occupid); @@ -390,25 +435,36 @@ static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, struct device *dev = kobj_to_dev(kobj); struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); struct arm_cmn_event_attr *eattr; - enum cmn_node_type type; eattr = container_of(attr, typeof(*eattr), attr.attr); - type = eattr->type; if (!(eattr->model & cmn->model)) return 0; - /* Watchpoints aren't nodes */ - if (type == CMN_TYPE_WP) - type = CMN_TYPE_XP; + /* Watchpoints aren't nodes, so avoid confusion */ + if (eattr->type == CMN_TYPE_WP) + return attr->mode; + + /* Hide XP events for unused interfaces/channels */ + if (eattr->type == CMN_TYPE_XP) { + unsigned int intf = (eattr->eventid >> 2) & 7; + unsigned int chan = eattr->eventid >> 5; + + if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) + return 0; + + if ((chan == 5 && cmn->rsp_vc_num < 2) || + (chan == 6 && cmn->dat_vc_num < 2)) + return 0; + } /* Revision-specific differences */ if (cmn->model == CMN600 && cmn->rev < CMN600_R1P2) { - if (type == CMN_TYPE_HNF && eattr->eventid == 0x1b) + if (eattr->type == CMN_TYPE_HNF && eattr->eventid == 0x1b) return 0; } - if (!arm_cmn_node(cmn, type)) + if (!arm_cmn_node(cmn, eattr->type)) return 0; return attr->mode; @@ -669,7 +725,8 @@ static u32 arm_cmn_wp_config(struct perf_event *event) config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | - FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc); + FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc) | + FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); if (combine && !grp) config |= CMN_DTM_WPn_CONFIG_WP_COMBINE; @@ -712,7 +769,7 @@ static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; for_each_hw_dn(hw, dn, i) { if (dtm != &cmn->dtms[dn->dtm]) { - dtm = &cmn->dtms[dn->dtm]; + dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; reg = readq_relaxed(dtm->base + offset); } dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); @@ -800,8 +857,10 @@ static void arm_cmn_event_start(struct perf_event *event, int flags) u64 mask = CMN_EVENT_WP_MASK(event); for_each_hw_dn(hw, dn, i) { - writeq_relaxed(val, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); - writeq_relaxed(mask, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); + void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); + + writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); + writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); } } else for_each_hw_dn(hw, dn, i) { int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); @@ -826,8 +885,10 @@ static void arm_cmn_event_stop(struct perf_event *event, int flags) int wp_idx = arm_cmn_wp_idx(event); for_each_hw_dn(hw, dn, i) { - writeq_relaxed(0, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); - writeq_relaxed(~0ULL, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); + void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); + + writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); + writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); } } else for_each_hw_dn(hw, dn, i) { int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); @@ -847,7 +908,8 @@ struct arm_cmn_val { bool cycles; }; -static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *event) +static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, + struct perf_event *event) { struct arm_cmn_hw_event *hw = to_cmn_hw(event); struct arm_cmn_node *dn; @@ -865,7 +927,7 @@ static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *ev } val->dtc_count++; - if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + if (arm_cmn_is_occup_event(cmn->model, type, CMN_EVENT_EVENTID(event))) occupid = CMN_EVENT_OCCUPID(event) + 1; else occupid = 0; @@ -884,7 +946,7 @@ static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *ev } } -static int arm_cmn_validate_group(struct perf_event *event) +static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) { struct arm_cmn_hw_event *hw = to_cmn_hw(event); struct arm_cmn_node *dn; @@ -904,9 +966,9 @@ static int arm_cmn_validate_group(struct perf_event *event) if (!val) return -ENOMEM; - arm_cmn_val_add_event(val, leader); + arm_cmn_val_add_event(cmn, val, leader); for_each_sibling_event(sibling, leader) - arm_cmn_val_add_event(val, sibling); + arm_cmn_val_add_event(cmn, val, sibling); type = CMN_EVENT_TYPE(event); if (type == CMN_TYPE_DTC) { @@ -917,7 +979,7 @@ static int arm_cmn_validate_group(struct perf_event *event) if (val->dtc_count == CMN_DT_NUM_COUNTERS) goto done; - if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + if (arm_cmn_is_occup_event(cmn->model, type, CMN_EVENT_EVENTID(event))) occupid = CMN_EVENT_OCCUPID(event) + 1; else occupid = 0; @@ -980,6 +1042,9 @@ static int arm_cmn_event_init(struct perf_event *event) eventid = CMN_EVENT_EVENTID(event); if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) return -EINVAL; + /* ...but the DTM may depend on which port we're watching */ + if (cmn->multi_dtm) + hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; } bynodeid = CMN_EVENT_BYNODEID(event); @@ -1007,7 +1072,7 @@ static int arm_cmn_event_init(struct perf_event *event) return -EINVAL; } - return arm_cmn_validate_group(event); + return arm_cmn_validate_group(cmn, event); } static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, @@ -1017,13 +1082,13 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, enum cmn_node_type type = CMN_EVENT_TYPE(event); while (i--) { - struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm]; + struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); if (type == CMN_TYPE_WP) dtm->wp_event[arm_cmn_wp_idx(event)] = -1; - if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + if (arm_cmn_is_occup_event(cmn->model, type, CMN_EVENT_EVENTID(event))) hw->dn[i].occupid_count--; dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); @@ -1069,7 +1134,7 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) /* ...then the local counters to feed it. */ for_each_hw_dn(hw, dn, i) { - struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm]; + struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; unsigned int dtm_idx, shift; u64 reg; @@ -1098,10 +1163,13 @@ static int arm_cmn_event_add(struct perf_event *event, int flags) } else { struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); + if (cmn->multi_dtm) + nid.port %= 2; + input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + (nid.port << 4) + (nid.dev << 2); - if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) { + if (arm_cmn_is_occup_event(cmn->model, type, CMN_EVENT_EVENTID(event))) { u8 occupid = CMN_EVENT_OCCUPID(event); if (dn->occupid_count == 0) { @@ -1283,11 +1351,11 @@ static int arm_cmn_init_irqs(struct arm_cmn *cmn) return 0; } -static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp) +static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) { int i; - dtm->base = xp->pmu_base; + dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; for (i = 0; i < 4; i++) { dtm->wp_event[i] = -1; @@ -1345,6 +1413,8 @@ static int arm_cmn_init_dtcs(struct arm_cmn *cmn) xp = arm_cmn_node_to_xp(cmn, dn); dn->dtm = xp->dtm; + if (cmn->multi_dtm) + dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2; if (dn->type == CMN_TYPE_DTC) { int err; @@ -1408,6 +1478,11 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); + reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); + cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; + cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); + cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); + reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); @@ -1429,7 +1504,11 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (!dn) return -ENOMEM; - dtm = devm_kcalloc(cmn->dev, cmn->num_xps, sizeof(*dtm), GFP_KERNEL); + /* Initial safe upper bound on DTMs for any possible mesh layout */ + i = cmn->num_xps; + if (cmn->multi_dtm) + i += cmn->num_xps + 1; + dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); if (!dtm) return -ENOMEM; @@ -1439,6 +1518,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) for (i = 0; i < cmn->num_xps; i++) { void __iomem *xp_region = cmn->base + xp_offset[i]; struct arm_cmn_node *xp = dn++; + unsigned int xp_ports = 0; arm_cmn_init_node_info(cmn, xp_offset[i], xp); /* @@ -1450,9 +1530,39 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (xp->id == (1 << 3)) cmn->mesh_x = xp->logid; - xp->dtc = 0xf; + if (cmn->model == CMN600) + xp->dtc = 0xf; + else + xp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO); + xp->dtm = dtm - cmn->dtms; - arm_cmn_init_dtm(dtm++, xp); + arm_cmn_init_dtm(dtm++, xp, 0); + /* + * Keeping track of connected ports will let us filter out + * unnecessary XP events easily. We can also reliably infer the + * "extra device ports" configuration for the node ID format + * from this, since in that case we will see at least one XP + * with port 2 connected, for the HN-D. + */ + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P0)) + xp_ports |= BIT(0); + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P1)) + xp_ports |= BIT(1); + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P2)) + xp_ports |= BIT(2); + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P3)) + xp_ports |= BIT(3); + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P4)) + xp_ports |= BIT(4); + if (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P5)) + xp_ports |= BIT(5); + + if (cmn->multi_dtm && (xp_ports & 0xc)) + arm_cmn_init_dtm(dtm++, xp, 1); + if (cmn->multi_dtm && (xp_ports & 0x30)) + arm_cmn_init_dtm(dtm++, xp, 2); + + cmn->ports_used |= xp_ports; reg = readq_relaxed(xp_region + CMN_CHILD_INFO); child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); @@ -1488,11 +1598,14 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) case CMN_TYPE_SBSX: case CMN_TYPE_RNI: case CMN_TYPE_RND: + case CMN_TYPE_MTSX: case CMN_TYPE_CXRA: case CMN_TYPE_CXHA: dn++; break; /* Nothing to see here */ + case CMN_TYPE_MPAM_S: + case CMN_TYPE_MPAM_NS: case CMN_TYPE_RNSAM: case CMN_TYPE_CXLA: break; @@ -1512,6 +1625,11 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) if (dn) cmn->dns = dn; + sz = (void *)dtm - (void *)cmn->dtms; + dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); + if (dtm) + cmn->dtms = dtm; + /* * If mesh_x wasn't set during discovery then we never saw * an XP at (0,1), thus we must have an Nx1 configuration. @@ -1520,9 +1638,15 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) cmn->mesh_x = cmn->num_xps; cmn->mesh_y = cmn->num_xps / cmn->mesh_x; + /* 1x1 config plays havoc with XP event encodings */ + if (cmn->num_xps == 1) + dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); + dev_dbg(cmn->dev, "model %d, periph_id_2 revision %d\n", cmn->model, cmn->rev); - dev_dbg(cmn->dev, "mesh %dx%d, ID width %d\n", - cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn)); + reg = cmn->ports_used; + dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", + cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, + cmn->multi_dtm ? ", multi-DTM" : ""); return 0; } -- GitLab From e310644724e195b79cf8114ca5297e4cdb36c955 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:45:01 +0000 Subject: [PATCH 521/965] dt-bindings: perf: arm-cmn: Add CI-700 CI-700 is a new client-level coherent interconnect derived from the enterprise-level CMN family, and shares the same PMU design. CC: devicetree@vger.kernel.org Signed-off-by: Robin Murphy Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/5f0b372f808f1468e6d9500cedafbecd10254674.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- .../devicetree/bindings/perf/arm,cmn.yaml | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/perf/arm,cmn.yaml b/Documentation/devicetree/bindings/perf/arm,cmn.yaml index 42424ccbdd0c6..2d4219ec7eda6 100644 --- a/Documentation/devicetree/bindings/perf/arm,cmn.yaml +++ b/Documentation/devicetree/bindings/perf/arm,cmn.yaml @@ -12,12 +12,14 @@ maintainers: properties: compatible: - const: arm,cmn-600 + enum: + - arm,cmn-600 + - arm,ci-700 reg: items: - description: Physical address of the base (PERIPHBASE) and - size (up to 64MB) of the configuration address space. + size of the configuration address space. interrupts: minItems: 1 @@ -31,14 +33,23 @@ properties: arm,root-node: $ref: /schemas/types.yaml#/definitions/uint32 - description: Offset from PERIPHBASE of the configuration - discovery node (see TRM definition of ROOTNODEBASE). + description: Offset from PERIPHBASE of CMN-600's configuration + discovery node (see TRM definition of ROOTNODEBASE). Not + relevant for newer CMN/CI products. required: - compatible - reg - interrupts - - arm,root-node + +if: + properties: + compatible: + contains: + const: arm,cmn-600 +then: + required: + - arm,root-node additionalProperties: false -- GitLab From b2fea780c9282dbaf77ef081e6d97a3f2c0dfc6a Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:45:02 +0000 Subject: [PATCH 522/965] perf/arm-cmn: Add CI-700 Support Add the identifiers and events for the CI-700 coherent interconnect. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/28f566ab23a83733c6c9ef9414c010b760b4549c.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 57 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 0a3f33a83c01f..28ab87a6cde44 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -175,6 +175,7 @@ enum cmn_model { CMN_ANY = -1, CMN600 = 1, + CI700 = 2, }; /* CMN-600 r0px shouldn't exist in silicon, thankfully */ @@ -186,6 +187,9 @@ enum cmn_revision { CMN600_R2P0, CMN600_R3P0, CMN600_R3P1, + CI700_R0P0 = 0, + CI700_R1P0, + CI700_R2P0, }; enum cmn_node_type { @@ -401,8 +405,10 @@ struct arm_cmn_format_attr { static bool arm_cmn_is_occup_event(enum cmn_model model, enum cmn_node_type type, unsigned int id) { - return (type == CMN_TYPE_DVM && id == 0x05) || - (type == CMN_TYPE_HNF && id == 0x0f); + if (type == CMN_TYPE_DVM) + return (model == CMN600 && id == 0x05) || + (model == CI700 && id == 0x0c); + return type == CMN_TYPE_HNF && id == 0x0f; } static ssize_t arm_cmn_event_show(struct device *dev, @@ -497,14 +503,19 @@ static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \ __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ - __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)) + __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ + __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ + __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) /* Good thing there are only 3 fundamental XP events... */ #define CMN_EVENT_XP(_name, _event) \ _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ - _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)) + _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ + _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ + _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ + _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)) static struct attribute *arm_cmn_event_attrs[] = { @@ -522,6 +533,20 @@ static struct attribute *arm_cmn_event_attrs[] = { _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_all, 0x05, 0), _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_dvmop, 0x05, 1), _CMN_EVENT_DVM(CMN600, rxreq_trk_occupancy_dvmsync, 0x05, 2), + CMN_EVENT_DVM(CI700, dvmop_tlbi, 0x01), + CMN_EVENT_DVM(CI700, dvmop_bpi, 0x02), + CMN_EVENT_DVM(CI700, dvmop_pici, 0x03), + CMN_EVENT_DVM(CI700, dvmop_vici, 0x04), + CMN_EVENT_DVM(CI700, dvmsync, 0x05), + CMN_EVENT_DVM(CI700, vmid_filtered, 0x06), + CMN_EVENT_DVM(CI700, rndop_filtered, 0x07), + CMN_EVENT_DVM(CI700, retry, 0x08), + CMN_EVENT_DVM(CI700, txsnp_flitv, 0x09), + CMN_EVENT_DVM(CI700, txsnp_stall, 0x0a), + CMN_EVENT_DVM(CI700, trkfull, 0x0b), + _CMN_EVENT_DVM(CI700, trk_occupancy_all, 0x0c, 0), + _CMN_EVENT_DVM(CI700, trk_occupancy_dvmop, 0x0c, 1), + _CMN_EVENT_DVM(CI700, trk_occupancy_dvmsync, 0x0c, 2), CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), @@ -558,6 +583,9 @@ static struct attribute *arm_cmn_event_attrs[] = { CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), + CMN_EVENT_HNF(CI700, atomic_fwd, 0x20), + CMN_EVENT_HNF(CI700, mpam_hardlim, 0x21), + CMN_EVENT_HNF(CI700, mpam_softlim, 0x22), CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), @@ -598,6 +626,7 @@ static struct attribute *arm_cmn_event_attrs[] = { CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), + CMN_EVENT_SBSX(CI700, rdb_occ_cnt_ovfl, 0x17), CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), @@ -624,6 +653,25 @@ static struct attribute *arm_cmn_event_attrs[] = { CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), + CMN_EVENT_RNID(CI700, padb_occ_ovfl, 0x11), + CMN_EVENT_RNID(CI700, rpdb_occ_ovfl, 0x12), + CMN_EVENT_RNID(CI700, rrt_occup_ovfl_slice1, 0x13), + CMN_EVENT_RNID(CI700, rrt_occup_ovfl_slice2, 0x14), + CMN_EVENT_RNID(CI700, rrt_occup_ovfl_slice3, 0x15), + CMN_EVENT_RNID(CI700, wrt_throttled, 0x16), + + CMN_EVENT_MTSX(tc_lookup, 0x01), + CMN_EVENT_MTSX(tc_fill, 0x02), + CMN_EVENT_MTSX(tc_miss, 0x03), + CMN_EVENT_MTSX(tdb_forward, 0x04), + CMN_EVENT_MTSX(tcq_hazard, 0x05), + CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), + CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), + CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), + CMN_EVENT_MTSX(axi_rd_req, 0x09), + CMN_EVENT_MTSX(axi_wr_req, 0x0a), + CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), + CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), NULL }; @@ -1773,6 +1821,7 @@ static int arm_cmn_remove(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id arm_cmn_of_match[] = { { .compatible = "arm,cmn-600", .data = (void *)CMN600 }, + { .compatible = "arm,ci-700", .data = (void *)CI700 }, {} }; MODULE_DEVICE_TABLE(of, arm_cmn_of_match); -- GitLab From a88fa6c28b867a387e3af202d6dbbb754d3aa2f1 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 3 Dec 2021 11:45:03 +0000 Subject: [PATCH 523/965] perf/arm-cmn: Add debugfs topology info In general, detailed performance analysis will require knoweldge of the the SoC beyond the CMN itself - e.g. which actual CPUs/peripherals/etc. are connected to each node. However for certain development and bringup tasks it can be useful to have a quick overview of the CMN internal topology to hand too. Add a debugfs file to map this out. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/159fd4d7e19fb3c8801a8cb64ee73ec50f55903c.1638530442.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- drivers/perf/arm-cmn.c | 151 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 148 insertions(+), 3 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 28ab87a6cde44..0e48adce57ef3 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -287,6 +288,7 @@ struct arm_cmn { struct hlist_node cpuhp_node; struct pmu pmu; + struct dentry *debug; }; #define to_cmn(p) container_of(p, struct arm_cmn, pmu) @@ -351,6 +353,140 @@ static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, return NULL; } +struct dentry *arm_cmn_debugfs; + +#ifdef CONFIG_DEBUG_FS +static const char *arm_cmn_device_type(u8 type) +{ + switch(type) { + case 0x01: return " RN-I |"; + case 0x02: return " RN-D |"; + case 0x04: return " RN-F_B |"; + case 0x05: return "RN-F_B_E|"; + case 0x06: return " RN-F_A |"; + case 0x07: return "RN-F_A_E|"; + case 0x08: return " HN-T |"; + case 0x09: return " HN-I |"; + case 0x0a: return " HN-D |"; + case 0x0c: return " SN-F |"; + case 0x0d: return " SBSX |"; + case 0x0e: return " HN-F |"; + case 0x0f: return " SN-F_E |"; + case 0x10: return " SN-F_D |"; + case 0x11: return " CXHA |"; + case 0x12: return " CXRA |"; + case 0x13: return " CXRH |"; + case 0x14: return " RN-F_D |"; + case 0x15: return "RN-F_D_E|"; + case 0x16: return " RN-F_C |"; + case 0x17: return "RN-F_C_E|"; + case 0x1c: return " MTSX |"; + default: return " |"; + } +} + +static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d) +{ + struct arm_cmn *cmn = s->private; + struct arm_cmn_node *dn; + + for (dn = cmn->dns; dn->type; dn++) { + struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); + + if (dn->type == CMN_TYPE_XP) + continue; + /* Ignore the extra components that will overlap on some ports */ + if (dn->type < CMN_TYPE_HNI) + continue; + + if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d) + continue; + + seq_printf(s, " #%-2d |", dn->logid); + return; + } + seq_puts(s, " |"); +} + +static int arm_cmn_map_show(struct seq_file *s, void *data) +{ + struct arm_cmn *cmn = s->private; + int x, y, p, pmax = fls(cmn->ports_used); + + seq_puts(s, " X"); + for (x = 0; x < cmn->mesh_x; x++) + seq_printf(s, " %d ", x); + seq_puts(s, "\nY P D+"); + y = cmn->mesh_y; + while (y--) { + int xp_base = cmn->mesh_x * y; + u8 port[6][CMN_MAX_DIMENSION]; + + for (x = 0; x < cmn->mesh_x; x++) + seq_puts(s, "--------+"); + + seq_printf(s, "\n%d |", y); + for (x = 0; x < cmn->mesh_x; x++) { + struct arm_cmn_node *xp = cmn->xps + xp_base + x; + void __iomem *base = xp->pmu_base - CMN_PMU_OFFSET; + + port[0][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P0); + port[1][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P1); + port[2][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P2); + port[3][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P3); + port[4][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P4); + port[5][x] = readl_relaxed(base + CMN_MXP__CONNECT_INFO_P5); + seq_printf(s, " XP #%-2d |", xp_base + x); + } + + seq_puts(s, "\n |"); + for (x = 0; x < cmn->mesh_x; x++) { + u8 dtc = cmn->xps[xp_base + x].dtc; + + if (dtc & (dtc - 1)) + seq_puts(s, " DTC ?? |"); + else + seq_printf(s, " DTC %ld |", __ffs(dtc)); + } + seq_puts(s, "\n |"); + for (x = 0; x < cmn->mesh_x; x++) + seq_puts(s, "........|"); + + for (p = 0; p < pmax; p++) { + seq_printf(s, "\n %d |", p); + for (x = 0; x < cmn->mesh_x; x++) + seq_puts(s, arm_cmn_device_type(port[p][x])); + seq_puts(s, "\n 0|"); + for (x = 0; x < cmn->mesh_x; x++) + arm_cmn_show_logid(s, x, y, p, 0); + seq_puts(s, "\n 1|"); + for (x = 0; x < cmn->mesh_x; x++) + arm_cmn_show_logid(s, x, y, p, 1); + } + seq_puts(s, "\n-----+"); + } + for (x = 0; x < cmn->mesh_x; x++) + seq_puts(s, "--------+"); + seq_puts(s, "\n"); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); + +static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) +{ + const char *name = "map"; + + if (id > 0) + name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); + if (!name) + return; + + cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); +} +#else +static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} +#endif + struct arm_cmn_hw_event { struct arm_cmn_node *dn; u64 dtm_idx[2]; @@ -1738,7 +1874,7 @@ static int arm_cmn_probe(struct platform_device *pdev) struct arm_cmn *cmn; const char *name; static atomic_t id; - int err, rootnode; + int err, rootnode, this_id; cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); if (!cmn) @@ -1792,7 +1928,8 @@ static int arm_cmn_probe(struct platform_device *pdev) .cancel_txn = arm_cmn_end_txn, }; - name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", atomic_fetch_inc(&id)); + this_id = atomic_fetch_inc(&id); + name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); if (!name) return -ENOMEM; @@ -1803,6 +1940,8 @@ static int arm_cmn_probe(struct platform_device *pdev) err = perf_pmu_register(&cmn->pmu, name, -1); if (err) cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); + else + arm_cmn_debugfs_init(cmn, this_id); return err; } @@ -1815,6 +1954,7 @@ static int arm_cmn_remove(struct platform_device *pdev) perf_pmu_unregister(&cmn->pmu); cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); + debugfs_remove(cmn->debug); return 0; } @@ -1857,9 +1997,13 @@ static int __init arm_cmn_init(void) return ret; arm_cmn_hp_state = ret; + arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); + ret = platform_driver_register(&arm_cmn_driver); - if (ret) + if (ret) { cpuhp_remove_multi_state(arm_cmn_hp_state); + debugfs_remove(arm_cmn_debugfs); + } return ret; } @@ -1867,6 +2011,7 @@ static void __exit arm_cmn_exit(void) { platform_driver_unregister(&arm_cmn_driver); cpuhp_remove_multi_state(arm_cmn_hp_state); + debugfs_remove(arm_cmn_debugfs); } module_init(arm_cmn_init); -- GitLab From 2704e7594383c0275dcb65e05408260ad34f3e15 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Wed, 17 Nov 2021 14:48:43 +0000 Subject: [PATCH 524/965] dt-bindings: Add Arm SMMUv3 PMCG binding Add binding for the Arm SMMUv3 PMU. Each node represents a PMCG, and is placed as a sibling node of the SMMU. Although the PMCGs registers may be within the SMMU MMIO region, they are separate devices, and there can be multiple PMCG devices for each SMMU (for example one for the TCU and one for each TBU). Signed-off-by: Jean-Philippe Brucker Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/20211117144844.241072-2-jean-philippe@linaro.org Signed-off-by: Will Deacon --- .../bindings/perf/arm,smmu-v3-pmcg.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml diff --git a/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml b/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml new file mode 100644 index 0000000000000..a4b53a6a1ebf5 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm SMMUv3 Performance Monitor Counter Group + +maintainers: + - Will Deacon + - Robin Murphy + +description: | + An SMMUv3 may have several Performance Monitor Counter Group (PMCG). + They are standalone performance monitoring units that support both + architected and IMPLEMENTATION DEFINED event counters. + +properties: + $nodename: + pattern: "^pmu@[0-9a-f]*" + compatible: + oneOf: + - items: + - const: arm,mmu-600-pmcg + - const: arm,smmu-v3-pmcg + - const: arm,smmu-v3-pmcg + + reg: + items: + - description: Register page 0 + - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1 + minItems: 1 + + interrupts: + maxItems: 1 + + msi-parent: true + +required: + - compatible + - reg + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + #include + #include + + pmu@2b420000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x2b420000 0x1000>, + <0x2b430000 0x1000>; + interrupts = ; + msi-parent = <&its 0xff0000>; + }; + + pmu@2b440000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x2b440000 0x1000>, + <0x2b450000 0x1000>; + interrupts = ; + msi-parent = <&its 0xff0000>; + }; -- GitLab From 3f7be43561766b7ad91661580376913c997613d6 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Wed, 17 Nov 2021 14:48:44 +0000 Subject: [PATCH 525/965] perf/smmuv3: Add devicetree support Add device-tree support to the SMMUv3 PMCG driver. Signed-off-by: Jay Chen Signed-off-by: Jean-Philippe Brucker Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/20211117144844.241072-3-jean-philippe@linaro.org Signed-off-by: Will Deacon --- drivers/perf/arm_smmuv3_pmu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 226348822ab39..19697617153a0 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -834,7 +835,8 @@ static int smmu_pmu_probe(struct platform_device *pdev) return -EINVAL; } - smmu_pmu_get_acpi_options(smmu_pmu); + if (!dev->of_node) + smmu_pmu_get_acpi_options(smmu_pmu); /* Pick one CPU to be the preferred one to use */ smmu_pmu->on_cpu = raw_smp_processor_id(); @@ -884,9 +886,16 @@ static void smmu_pmu_shutdown(struct platform_device *pdev) smmu_pmu_disable(&smmu_pmu->pmu); } +static const struct of_device_id smmu_pmu_of_match[] = { + { .compatible = "arm,smmu-v3-pmcg" }, + {} +}; +MODULE_DEVICE_TABLE(of, smmu_pmu_of_match); + static struct platform_driver smmu_pmu_driver = { .driver = { .name = "arm-smmu-v3-pmcg", + .of_match_table = of_match_ptr(smmu_pmu_of_match), .suppress_bind_attrs = true, }, .probe = smmu_pmu_probe, -- GitLab From df457ca973fee9e66d0d688afa6605d053034cd2 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 17 Nov 2021 14:48:45 +0000 Subject: [PATCH 526/965] perf/smmuv3: Synthesize IIDR from CoreSight ID registers The SMMU_PMCG_IIDR register was not present in older revisions of the Arm SMMUv3 spec. On Arm Ltd. implementations, the IIDR value consists of fields from several PIDR registers, allowing us to present a standardized identifier to userspace. Signed-off-by: Robin Murphy Signed-off-by: Jean-Philippe Brucker Link: https://lore.kernel.org/r/20211117144844.241072-4-jean-philippe@linaro.org Signed-off-by: Will Deacon --- drivers/perf/arm_smmuv3_pmu.c | 55 ++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 19697617153a0..598d6978280d8 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -76,6 +76,10 @@ #define SMMU_PMCG_CR 0xE04 #define SMMU_PMCG_CR_ENABLE BIT(0) #define SMMU_PMCG_IIDR 0xE08 +#define SMMU_PMCG_IIDR_PRODUCTID GENMASK(31, 20) +#define SMMU_PMCG_IIDR_VARIANT GENMASK(19, 16) +#define SMMU_PMCG_IIDR_REVISION GENMASK(15, 12) +#define SMMU_PMCG_IIDR_IMPLEMENTER GENMASK(11, 0) #define SMMU_PMCG_CEID0 0xE20 #define SMMU_PMCG_CEID1 0xE28 #define SMMU_PMCG_IRQ_CTRL 0xE50 @@ -84,6 +88,20 @@ #define SMMU_PMCG_IRQ_CFG1 0xE60 #define SMMU_PMCG_IRQ_CFG2 0xE64 +/* IMP-DEF ID registers */ +#define SMMU_PMCG_PIDR0 0xFE0 +#define SMMU_PMCG_PIDR0_PART_0 GENMASK(7, 0) +#define SMMU_PMCG_PIDR1 0xFE4 +#define SMMU_PMCG_PIDR1_DES_0 GENMASK(7, 4) +#define SMMU_PMCG_PIDR1_PART_1 GENMASK(3, 0) +#define SMMU_PMCG_PIDR2 0xFE8 +#define SMMU_PMCG_PIDR2_REVISION GENMASK(7, 4) +#define SMMU_PMCG_PIDR2_DES_1 GENMASK(2, 0) +#define SMMU_PMCG_PIDR3 0xFEC +#define SMMU_PMCG_PIDR3_REVAND GENMASK(7, 4) +#define SMMU_PMCG_PIDR4 0xFD0 +#define SMMU_PMCG_PIDR4_DES_2 GENMASK(3, 0) + /* MSI config fields */ #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) #define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 @@ -755,6 +773,41 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu) dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options); } +static bool smmu_pmu_coresight_id_regs(struct smmu_pmu *smmu_pmu) +{ + return of_device_is_compatible(smmu_pmu->dev->of_node, + "arm,mmu-600-pmcg"); +} + +static void smmu_pmu_get_iidr(struct smmu_pmu *smmu_pmu) +{ + u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR); + + if (!iidr && smmu_pmu_coresight_id_regs(smmu_pmu)) { + u32 pidr0 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR0); + u32 pidr1 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR1); + u32 pidr2 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR2); + u32 pidr3 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR3); + u32 pidr4 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR4); + + u32 productid = FIELD_GET(SMMU_PMCG_PIDR0_PART_0, pidr0) | + (FIELD_GET(SMMU_PMCG_PIDR1_PART_1, pidr1) << 8); + u32 variant = FIELD_GET(SMMU_PMCG_PIDR2_REVISION, pidr2); + u32 revision = FIELD_GET(SMMU_PMCG_PIDR3_REVAND, pidr3); + u32 implementer = + FIELD_GET(SMMU_PMCG_PIDR1_DES_0, pidr1) | + (FIELD_GET(SMMU_PMCG_PIDR2_DES_1, pidr2) << 4) | + (FIELD_GET(SMMU_PMCG_PIDR4_DES_2, pidr4) << 8); + + iidr = FIELD_PREP(SMMU_PMCG_IIDR_PRODUCTID, productid) | + FIELD_PREP(SMMU_PMCG_IIDR_VARIANT, variant) | + FIELD_PREP(SMMU_PMCG_IIDR_REVISION, revision) | + FIELD_PREP(SMMU_PMCG_IIDR_IMPLEMENTER, implementer); + } + + smmu_pmu->iidr = iidr; +} + static int smmu_pmu_probe(struct platform_device *pdev) { struct smmu_pmu *smmu_pmu; @@ -826,7 +879,7 @@ static int smmu_pmu_probe(struct platform_device *pdev) return err; } - smmu_pmu->iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR); + smmu_pmu_get_iidr(smmu_pmu); name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx", (res_0->start) >> SMMU_PMCG_PA_SHIFT); -- GitLab From 2c54b423cf85baed5ad9f9546f6c8ea741774a06 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Dec 2021 15:02:52 +0100 Subject: [PATCH 527/965] arm64/xor: use EOR3 instructions when available Use the EOR3 instruction to implement xor_blocks() if the instruction is available, which is the case if the CPU implements the SHA-3 extension. This is about 20% faster on Apple M1 when using the 5-way version. Signed-off-by: Ard Biesheuvel Link: https://lore.kernel.org/r/20211213140252.2856053-1-ardb@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/Kconfig | 6 ++ arch/arm64/Makefile | 5 ++ arch/arm64/lib/xor-neon.c | 147 +++++++++++++++++++++++++++++++++++++- 3 files changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c4207cf9bb17f..63d41ba4e716b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1545,6 +1545,12 @@ endmenu menu "ARMv8.2 architectural features" +config AS_HAS_ARMV8_2 + def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) + +config AS_HAS_SHA3 + def_bool $(as-instr,.arch armv8.2-a+sha3) + config ARM64_PMEM bool "Enable support for persistent memory" select ARCH_HAS_PMEM_API diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index e8cfc5868aa8e..2f1de88651e6d 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -58,6 +58,11 @@ stack_protector_prepare: prepare0 include/generated/asm-offsets.h)) endif +ifeq ($(CONFIG_AS_HAS_ARMV8_2), y) +# make sure to pass the newest target architecture to -march. +asm-arch := armv8.2-a +endif + # Ensure that if the compiler supports branch protection we default it # off, this will be overridden if we are using branch protection. branch-prot-flags-y += $(call cc-option,-mbranch-protection=none) diff --git a/arch/arm64/lib/xor-neon.c b/arch/arm64/lib/xor-neon.c index 11bf4f8aca686..d189cf4e70ea6 100644 --- a/arch/arm64/lib/xor-neon.c +++ b/arch/arm64/lib/xor-neon.c @@ -167,7 +167,7 @@ void xor_arm64_neon_5(unsigned long bytes, unsigned long *p1, } while (--lines > 0); } -struct xor_block_template const xor_block_inner_neon = { +struct xor_block_template xor_block_inner_neon __ro_after_init = { .name = "__inner_neon__", .do_2 = xor_arm64_neon_2, .do_3 = xor_arm64_neon_3, @@ -176,6 +176,151 @@ struct xor_block_template const xor_block_inner_neon = { }; EXPORT_SYMBOL(xor_block_inner_neon); +static inline uint64x2_t eor3(uint64x2_t p, uint64x2_t q, uint64x2_t r) +{ + uint64x2_t res; + + asm(ARM64_ASM_PREAMBLE ".arch_extension sha3\n" + "eor3 %0.16b, %1.16b, %2.16b, %3.16b" + : "=w"(res) : "w"(p), "w"(q), "w"(r)); + return res; +} + +static void xor_arm64_eor3_3(unsigned long bytes, unsigned long *p1, + unsigned long *p2, unsigned long *p3) +{ + uint64_t *dp1 = (uint64_t *)p1; + uint64_t *dp2 = (uint64_t *)p2; + uint64_t *dp3 = (uint64_t *)p3; + + register uint64x2_t v0, v1, v2, v3; + long lines = bytes / (sizeof(uint64x2_t) * 4); + + do { + /* p1 ^= p2 ^ p3 */ + v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0), + vld1q_u64(dp3 + 0)); + v1 = eor3(vld1q_u64(dp1 + 2), vld1q_u64(dp2 + 2), + vld1q_u64(dp3 + 2)); + v2 = eor3(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4), + vld1q_u64(dp3 + 4)); + v3 = eor3(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6), + vld1q_u64(dp3 + 6)); + + /* store */ + vst1q_u64(dp1 + 0, v0); + vst1q_u64(dp1 + 2, v1); + vst1q_u64(dp1 + 4, v2); + vst1q_u64(dp1 + 6, v3); + + dp1 += 8; + dp2 += 8; + dp3 += 8; + } while (--lines > 0); +} + +static void xor_arm64_eor3_4(unsigned long bytes, unsigned long *p1, + unsigned long *p2, unsigned long *p3, + unsigned long *p4) +{ + uint64_t *dp1 = (uint64_t *)p1; + uint64_t *dp2 = (uint64_t *)p2; + uint64_t *dp3 = (uint64_t *)p3; + uint64_t *dp4 = (uint64_t *)p4; + + register uint64x2_t v0, v1, v2, v3; + long lines = bytes / (sizeof(uint64x2_t) * 4); + + do { + /* p1 ^= p2 ^ p3 */ + v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0), + vld1q_u64(dp3 + 0)); + v1 = eor3(vld1q_u64(dp1 + 2), vld1q_u64(dp2 + 2), + vld1q_u64(dp3 + 2)); + v2 = eor3(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4), + vld1q_u64(dp3 + 4)); + v3 = eor3(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6), + vld1q_u64(dp3 + 6)); + + /* p1 ^= p4 */ + v0 = veorq_u64(v0, vld1q_u64(dp4 + 0)); + v1 = veorq_u64(v1, vld1q_u64(dp4 + 2)); + v2 = veorq_u64(v2, vld1q_u64(dp4 + 4)); + v3 = veorq_u64(v3, vld1q_u64(dp4 + 6)); + + /* store */ + vst1q_u64(dp1 + 0, v0); + vst1q_u64(dp1 + 2, v1); + vst1q_u64(dp1 + 4, v2); + vst1q_u64(dp1 + 6, v3); + + dp1 += 8; + dp2 += 8; + dp3 += 8; + dp4 += 8; + } while (--lines > 0); +} + +static void xor_arm64_eor3_5(unsigned long bytes, unsigned long *p1, + unsigned long *p2, unsigned long *p3, + unsigned long *p4, unsigned long *p5) +{ + uint64_t *dp1 = (uint64_t *)p1; + uint64_t *dp2 = (uint64_t *)p2; + uint64_t *dp3 = (uint64_t *)p3; + uint64_t *dp4 = (uint64_t *)p4; + uint64_t *dp5 = (uint64_t *)p5; + + register uint64x2_t v0, v1, v2, v3; + long lines = bytes / (sizeof(uint64x2_t) * 4); + + do { + /* p1 ^= p2 ^ p3 */ + v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0), + vld1q_u64(dp3 + 0)); + v1 = eor3(vld1q_u64(dp1 + 2), vld1q_u64(dp2 + 2), + vld1q_u64(dp3 + 2)); + v2 = eor3(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4), + vld1q_u64(dp3 + 4)); + v3 = eor3(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6), + vld1q_u64(dp3 + 6)); + + /* p1 ^= p4 ^ p5 */ + v0 = eor3(v0, vld1q_u64(dp4 + 0), vld1q_u64(dp5 + 0)); + v1 = eor3(v1, vld1q_u64(dp4 + 2), vld1q_u64(dp5 + 2)); + v2 = eor3(v2, vld1q_u64(dp4 + 4), vld1q_u64(dp5 + 4)); + v3 = eor3(v3, vld1q_u64(dp4 + 6), vld1q_u64(dp5 + 6)); + + /* store */ + vst1q_u64(dp1 + 0, v0); + vst1q_u64(dp1 + 2, v1); + vst1q_u64(dp1 + 4, v2); + vst1q_u64(dp1 + 6, v3); + + dp1 += 8; + dp2 += 8; + dp3 += 8; + dp4 += 8; + dp5 += 8; + } while (--lines > 0); +} + +static int __init xor_neon_init(void) +{ + if (IS_ENABLED(CONFIG_AS_HAS_SHA3) && cpu_have_named_feature(SHA3)) { + xor_block_inner_neon.do_3 = xor_arm64_eor3_3; + xor_block_inner_neon.do_4 = xor_arm64_eor3_4; + xor_block_inner_neon.do_5 = xor_arm64_eor3_5; + } + return 0; +} +module_init(xor_neon_init); + +static void __exit xor_neon_exit(void) +{ +} +module_exit(xor_neon_exit); + MODULE_AUTHOR("Jackie Liu "); MODULE_DESCRIPTION("ARMv8 XOR Extensions"); MODULE_LICENSE("GPL"); -- GitLab From 036a7584bede317d0df6b854e4f531b7a2dd8b33 Mon Sep 17 00:00:00 2001 From: Bhaskara Budiredla Date: Mon, 15 Nov 2021 10:05:05 +0530 Subject: [PATCH 528/965] drivers: perf: Add LLC-TAD perf counter support This driver adds support for Last-level cache tag-and-data unit (LLC-TAD) PMU that is featured in some of the Marvell's CN10K infrastructure silicons. The LLC is divided into 2N slices distributed across N Mesh tiles in a single-socket configuration. The driver always configures the same counter for all of the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of an application run. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The event counters are zeroed to start event counting to avoid any rollover issues. TAD perf counters are 64-bit, so it's not currently possible to overflow event counters at current mesh and core frequencies. To measure tad pmu events use perf tool stat command. For instance: perf stat -e tad_dat_msh_in_dss,tad_req_msh_out_any perf stat -e tad_alloc_any,tad_hit_any,tad_tag_rd Signed-off-by: Bhaskara Budiredla Link: https://lore.kernel.org/r/20211115043506.6679-2-bbudiredla@marvell.com Signed-off-by: Will Deacon --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/marvell_cn10k_tad_pmu.c | 429 +++++++++++++++++++++++++++ 3 files changed, 437 insertions(+) create mode 100644 drivers/perf/marvell_cn10k_tad_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 4374af292e6d0..8fe825dd0d084 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -139,6 +139,13 @@ config ARM_DMC620_PMU Support for PMU events monitoring on the ARM DMC-620 memory controller. +config MARVELL_CN10K_TAD_PMU + tristate "Marvell CN10K LLC-TAD PMU" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) + performance monitors on CN10K family silicons. + source "drivers/perf/hisilicon/Kconfig" endmenu diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 5260b116c7dad..2db5418d5b0aa 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o +obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c new file mode 100644 index 0000000000000..250dd4c52d705 --- /dev/null +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell CN10K LLC-TAD perf driver + * + * Copyright (C) 2021 Marvell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "tad_pmu: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#define TAD_PFC_OFFSET 0x0 +#define TAD_PFC(counter) (TAD_PFC_OFFSET | (counter << 3)) +#define TAD_PRF_OFFSET 0x100 +#define TAD_PRF(counter) (TAD_PRF_OFFSET | (counter << 3)) +#define TAD_PRF_CNTSEL_MASK 0xFF +#define TAD_MAX_COUNTERS 8 + +#define to_tad_pmu(p) (container_of(p, struct tad_pmu, pmu)) + +struct tad_region { + void __iomem *base; +}; + +struct tad_pmu { + struct pmu pmu; + struct tad_region *regions; + u32 region_cnt; + unsigned int cpu; + struct hlist_node node; + struct perf_event *events[TAD_MAX_COUNTERS]; + DECLARE_BITMAP(counters_map, TAD_MAX_COUNTERS); +}; + +static int tad_pmu_cpuhp_state; + +static void tad_pmu_event_counter_read(struct perf_event *event) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u32 counter_idx = hwc->idx; + u64 prev, new; + int i; + + do { + prev = local64_read(&hwc->prev_count); + for (i = 0, new = 0; i < tad_pmu->region_cnt; i++) + new += readq(tad_pmu->regions[i].base + + TAD_PFC(counter_idx)); + } while (local64_cmpxchg(&hwc->prev_count, prev, new) != prev); + + local64_add(new - prev, &event->count); +} + +static void tad_pmu_event_counter_stop(struct perf_event *event, int flags) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u32 counter_idx = hwc->idx; + int i; + + /* TAD()_PFC() stop counting on the write + * which sets TAD()_PRF()[CNTSEL] == 0 + */ + for (i = 0; i < tad_pmu->region_cnt; i++) { + writeq_relaxed(0, tad_pmu->regions[i].base + + TAD_PRF(counter_idx)); + } + + tad_pmu_event_counter_read(event); + hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static void tad_pmu_event_counter_start(struct perf_event *event, int flags) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u32 event_idx = event->attr.config; + u32 counter_idx = hwc->idx; + u64 reg_val; + int i; + + hwc->state = 0; + + /* Typically TAD_PFC() are zeroed to start counting */ + for (i = 0; i < tad_pmu->region_cnt; i++) + writeq_relaxed(0, tad_pmu->regions[i].base + + TAD_PFC(counter_idx)); + + /* TAD()_PFC() start counting on the write + * which sets TAD()_PRF()[CNTSEL] != 0 + */ + for (i = 0; i < tad_pmu->region_cnt; i++) { + reg_val = readq_relaxed(tad_pmu->regions[i].base + + TAD_PRF(counter_idx)); + reg_val |= (event_idx & 0xFF); + writeq_relaxed(reg_val, tad_pmu->regions[i].base + + TAD_PRF(counter_idx)); + } +} + +static void tad_pmu_event_counter_del(struct perf_event *event, int flags) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + tad_pmu_event_counter_stop(event, flags | PERF_EF_UPDATE); + tad_pmu->events[idx] = NULL; + clear_bit(idx, tad_pmu->counters_map); +} + +static int tad_pmu_event_counter_add(struct perf_event *event, int flags) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx; + + /* Get a free counter for this event */ + idx = find_first_zero_bit(tad_pmu->counters_map, TAD_MAX_COUNTERS); + if (idx == TAD_MAX_COUNTERS) + return -EAGAIN; + + set_bit(idx, tad_pmu->counters_map); + + hwc->idx = idx; + hwc->state = PERF_HES_STOPPED; + tad_pmu->events[idx] = event; + + if (flags & PERF_EF_START) + tad_pmu_event_counter_start(event, flags); + + return 0; +} + +static int tad_pmu_event_init(struct perf_event *event) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); + + if (!event->attr.disabled) + return -EINVAL; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (event->state != PERF_EVENT_STATE_OFF) + return -EINVAL; + + event->cpu = tad_pmu->cpu; + event->hw.idx = -1; + event->hw.config_base = event->attr.config; + + return 0; +} + +static ssize_t tad_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); + return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); +} + +#define TAD_PMU_EVENT_ATTR(name, config) \ + PMU_EVENT_ATTR_ID(name, tad_pmu_event_show, config) + +static struct attribute *tad_pmu_event_attrs[] = { + TAD_PMU_EVENT_ATTR(tad_none, 0x0), + TAD_PMU_EVENT_ATTR(tad_req_msh_in_any, 0x1), + TAD_PMU_EVENT_ATTR(tad_req_msh_in_mn, 0x2), + TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_any, 0x4), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_mn, 0x5), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_exlmn, 0x6), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_dss, 0x7), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_retry_dss, 0x8), + TAD_PMU_EVENT_ATTR(tad_dat_msh_in_any, 0x9), + TAD_PMU_EVENT_ATTR(tad_dat_msh_in_dss, 0xa), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_any, 0xb), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_rd, 0xc), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_wr, 0xd), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_evict, 0xe), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_any, 0xf), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_retry_exlmn, 0x10), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_retry_mn, 0x11), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_exlmn, 0x12), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_mn, 0x13), + TAD_PMU_EVENT_ATTR(tad_snp_msh_out_any, 0x14), + TAD_PMU_EVENT_ATTR(tad_snp_msh_out_mn, 0x15), + TAD_PMU_EVENT_ATTR(tad_snp_msh_out_exlmn, 0x16), + TAD_PMU_EVENT_ATTR(tad_dat_msh_out_any, 0x17), + TAD_PMU_EVENT_ATTR(tad_dat_msh_out_fill, 0x18), + TAD_PMU_EVENT_ATTR(tad_dat_msh_out_dss, 0x19), + TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a), + TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b), + TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c), + TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d), + TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e), + TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f), + TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20), + TAD_PMU_EVENT_ATTR(tad_dat_rd, 0x21), + TAD_PMU_EVENT_ATTR(tad_dat_rd_byp, 0x22), + TAD_PMU_EVENT_ATTR(tad_ifb_occ, 0x23), + TAD_PMU_EVENT_ATTR(tad_req_occ, 0x24), + NULL +}; + +static const struct attribute_group tad_pmu_events_attr_group = { + .name = "events", + .attrs = tad_pmu_event_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-7"); + +static struct attribute *tad_pmu_format_attrs[] = { + &format_attr_event.attr, + NULL +}; + +static struct attribute_group tad_pmu_format_attr_group = { + .name = "format", + .attrs = tad_pmu_format_attrs, +}; + +static ssize_t tad_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tad_pmu *tad_pmu = to_tad_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(tad_pmu->cpu)); +} + +static DEVICE_ATTR(cpumask, 0444, tad_pmu_cpumask_show, NULL); + +static struct attribute *tad_pmu_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL +}; + +static struct attribute_group tad_pmu_cpumask_attr_group = { + .attrs = tad_pmu_cpumask_attrs, +}; + +static const struct attribute_group *tad_pmu_attr_groups[] = { + &tad_pmu_events_attr_group, + &tad_pmu_format_attr_group, + &tad_pmu_cpumask_attr_group, + NULL +}; + +static int tad_pmu_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct tad_region *regions; + struct tad_pmu *tad_pmu; + struct resource *res; + u32 tad_pmu_page_size; + u32 tad_page_size; + u32 tad_cnt; + int i, ret; + char *name; + + tad_pmu = devm_kzalloc(&pdev->dev, sizeof(*tad_pmu), GFP_KERNEL); + if (!tad_pmu) + return -ENOMEM; + + platform_set_drvdata(pdev, tad_pmu); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Mem resource not found\n"); + return -ENODEV; + } + + ret = of_property_read_u32(node, "marvell,tad-page-size", + &tad_page_size); + if (ret) { + dev_err(&pdev->dev, "Can't find tad-page-size property\n"); + return ret; + } + + ret = of_property_read_u32(node, "marvell,tad-pmu-page-size", + &tad_pmu_page_size); + if (ret) { + dev_err(&pdev->dev, "Can't find tad-pmu-page-size property\n"); + return ret; + } + + ret = of_property_read_u32(node, "marvell,tad-cnt", &tad_cnt); + if (ret) { + dev_err(&pdev->dev, "Can't find tad-cnt property\n"); + return ret; + } + + regions = devm_kcalloc(&pdev->dev, tad_cnt, + sizeof(*regions), GFP_KERNEL); + if (!regions) + return -ENOMEM; + + /* ioremap the distributed TAD pmu regions */ + for (i = 0; i < tad_cnt && res->start < res->end; i++) { + regions[i].base = devm_ioremap(&pdev->dev, + res->start, + tad_pmu_page_size); + if (IS_ERR(regions[i].base)) { + dev_err(&pdev->dev, "TAD%d ioremap fail\n", i); + return -ENOMEM; + } + res->start += tad_page_size; + } + + tad_pmu->regions = regions; + tad_pmu->region_cnt = tad_cnt; + + tad_pmu->pmu = (struct pmu) { + + .module = THIS_MODULE, + .attr_groups = tad_pmu_attr_groups, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE | + PERF_PMU_CAP_NO_INTERRUPT, + .task_ctx_nr = perf_invalid_context, + + .event_init = tad_pmu_event_init, + .add = tad_pmu_event_counter_add, + .del = tad_pmu_event_counter_del, + .start = tad_pmu_event_counter_start, + .stop = tad_pmu_event_counter_stop, + .read = tad_pmu_event_counter_read, + }; + + tad_pmu->cpu = raw_smp_processor_id(); + + /* Register pmu instance for cpu hotplug */ + ret = cpuhp_state_add_instance_nocalls(tad_pmu_cpuhp_state, + &tad_pmu->node); + if (ret) { + dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); + return ret; + } + + name = "tad"; + ret = perf_pmu_register(&tad_pmu->pmu, name, -1); + if (ret) + cpuhp_state_remove_instance_nocalls(tad_pmu_cpuhp_state, + &tad_pmu->node); + + return ret; +} + +static int tad_pmu_remove(struct platform_device *pdev) +{ + struct tad_pmu *pmu = platform_get_drvdata(pdev); + + cpuhp_state_remove_instance_nocalls(tad_pmu_cpuhp_state, + &pmu->node); + perf_pmu_unregister(&pmu->pmu); + + return 0; +} + +static const struct of_device_id tad_pmu_of_match[] = { + { .compatible = "marvell,cn10k-tad-pmu", }, + {}, +}; + +static struct platform_driver tad_pmu_driver = { + .driver = { + .name = "cn10k_tad_pmu", + .of_match_table = of_match_ptr(tad_pmu_of_match), + .suppress_bind_attrs = true, + }, + .probe = tad_pmu_probe, + .remove = tad_pmu_remove, +}; + +static int tad_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct tad_pmu *pmu = hlist_entry_safe(node, struct tad_pmu, node); + unsigned int target; + + if (cpu != pmu->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&pmu->pmu, cpu, target); + pmu->cpu = target; + + return 0; +} + +static int __init tad_pmu_init(void) +{ + int ret; + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/cn10k/tadpmu:online", + NULL, + tad_pmu_offline_cpu); + if (ret < 0) + return ret; + tad_pmu_cpuhp_state = ret; + return platform_driver_register(&tad_pmu_driver); +} + +static void __exit tad_pmu_exit(void) +{ + platform_driver_unregister(&tad_pmu_driver); + cpuhp_remove_multi_state(tad_pmu_cpuhp_state); +} + +module_init(tad_pmu_init); +module_exit(tad_pmu_exit); + +MODULE_DESCRIPTION("Marvell CN10K LLC-TAD Perf driver"); +MODULE_AUTHOR("Bhaskara Budiredla "); +MODULE_LICENSE("GPL v2"); -- GitLab From 4cbf47728f8d9d18e7e43863c0b623351267f203 Mon Sep 17 00:00:00 2001 From: Bhaskara Budiredla Date: Mon, 15 Nov 2021 10:05:06 +0530 Subject: [PATCH 529/965] dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings Add device tree bindings for Last-level-cache Tag-and-data (LLC-TAD) unit PMU for Marvell CN10K SoCs. Signed-off-by: Bhaskara Budiredla Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211115043506.6679-3-bbudiredla@marvell.com Signed-off-by: Will Deacon --- .../bindings/perf/marvell-cn10k-tad.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml new file mode 100644 index 0000000000000..3621422526677 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell CN10K LLC-TAD performance monitor + +maintainers: + - Bhaskara Budiredla + +description: | + The Tag-and-Data units (TADs) maintain coherence and contain CN10K + shared on-chip last level cache (LLC). The tad pmu measures the + performance of last-level cache. Each tad pmu supports up to eight + counters. + + The DT setup comprises of number of tad blocks, the sizes of pmu + regions, tad blocks and overall base address of the HW. + +properties: + compatible: + const: marvell,cn10k-tad-pmu + + reg: + maxItems: 1 + + marvell,tad-cnt: + description: specifies the number of tads on the soc + $ref: /schemas/types.yaml#/definitions/uint32 + + marvell,tad-page-size: + description: specifies the size of each tad page + $ref: /schemas/types.yaml#/definitions/uint32 + + marvell,tad-pmu-page-size: + description: specifies the size of page that the pmu uses + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - marvell,tad-cnt + - marvell,tad-page-size + - marvell,tad-pmu-page-size + +additionalProperties: false + +examples: + - | + + tad { + #address-cells = <2>; + #size-cells = <2>; + + tad_pmu@80000000 { + compatible = "marvell,cn10k-tad-pmu"; + reg = <0x87e2 0x80000000 0x0 0x1000>; + marvell,tad-cnt = <1>; + marvell,tad-page-size = <0x1000>; + marvell,tad-pmu-page-size = <0x1000>; + }; + }; -- GitLab From c8602008e247f5603317c16f076565a96715e1ba Mon Sep 17 00:00:00 2001 From: Qi Liu Date: Thu, 2 Dec 2021 16:06:32 +0800 Subject: [PATCH 530/965] docs: perf: Add description for HiSilicon PCIe PMU driver PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported on HiSilicon HIP09 platform. Document it to provide guidance on how to use it. Reviewed-by: John Garry Signed-off-by: Qi Liu Reviewed-by: Shaokun Zhang Link: https://lore.kernel.org/r/20211202080633.2919-2-liuqi115@huawei.com Signed-off-by: Will Deacon --- .../admin-guide/perf/hisi-pcie-pmu.rst | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/admin-guide/perf/hisi-pcie-pmu.rst diff --git a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst new file mode 100644 index 0000000000000..294ebbdb22af8 --- /dev/null +++ b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst @@ -0,0 +1,106 @@ +================================================ +HiSilicon PCIe Performance Monitoring Unit (PMU) +================================================ + +On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor +bandwidth, latency, bus utilization and buffer occupancy data of PCIe. + +Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and +all Endpoints downstream these Root Ports. + + +HiSilicon PCIe PMU driver +========================= + +The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe +Core id.:: + + /sys/bus/event_source/hisi_pcie_ + +PMU driver provides description of available events and filter options in sysfs, +see /sys/bus/event_source/devices/hisi_pcie_. + +The "format" directory describes all formats of the config (events) and config1 +(filter options) fields of the perf_event_attr structure. The "events" directory +describes all documented events shown in perf list. + +The "identifier" sysfs file allows users to identify the version of the +PMU hardware device. + +The "bus" sysfs file allows users to get the bus number of Root Ports +monitored by PMU. + +Example usage of perf:: + + $# perf list + hisi_pcie0_0/rx_mwr_latency/ [kernel PMU event] + hisi_pcie0_0/rx_mwr_cnt/ [kernel PMU event] + ------------------------------------------ + + $# perf stat -e hisi_pcie0_0/rx_mwr_latency/ + $# perf stat -e hisi_pcie0_0/rx_mwr_cnt/ + $# perf stat -g -e hisi_pcie0_0/rx_mwr_latency/ -e hisi_pcie0_0/rx_mwr_cnt/ + +The current driver does not support sampling. So "perf record" is unsupported. +Also attach to a task is unsupported for PCIe PMU. + +Filter options +-------------- + +1. Target filter +PMU could only monitor the performance of traffic downstream target Root Ports +or downstream target Endpoint. PCIe PMU driver support "port" and "bdf" +interfaces for users, and these two interfaces aren't supported at the same +time. + +-port +"port" filter can be used in all PCIe PMU events, target Root Port can be +selected by configuring the 16-bits-bitmap "port". Multi ports can be selected +for AP-layer-events, and only one port can be selected for TL/DL-layer-events. + +For example, if target Root Port is 0000:00:00.0 (x8 lanes), bit0 of bitmap +should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4 lanes), +bit8 is set, port=0x100; if these two Root Ports are both monitored, port=0x101. + +Example usage of perf:: + + $# perf stat -e hisi_pcie0_0/rx_mwr_latency,port=0x1/ sleep 5 + +-bdf + +"bdf" filter can only be used in bandwidth events, target Endpoint is selected +by configuring BDF to "bdf". Counter only counts the bandwidth of message +requested by target Endpoint. + +For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0. + +Example usage of perf:: + + $# perf stat -e hisi_pcie0_0/rx_mrd_flux,bdf=0x3900/ sleep 5 + +2. Trigger filter +Event statistics start when the first time TLP length is greater/smaller +than trigger condition. You can set the trigger condition by writing "trig_len", +and set the trigger mode by writing "trig_mode". This filter can only be used +in bandwidth events. + +For example, "trig_len=4" means trigger condition is 2^4 DW, "trig_mode=0" +means statistics start when TLP length > trigger condition, "trig_mode=1" +means start when TLP length < condition. + +Example usage of perf:: + + $# perf stat -e hisi_pcie0_0/rx_mrd_flux,trig_len=0x4,trig_mode=1/ sleep 5 + +3. Threshold filter +Counter counts when TLP length within the specified range. You can set the +threshold by writing "thr_len", and set the threshold mode by writing +"thr_mode". This filter can only be used in bandwidth events. + +For example, "thr_len=4" means threshold is 2^4 DW, "thr_mode=0" means +counter counts when TLP length >= threshold, and "thr_mode=1" means counts +when TLP length < threshold. + +Example usage of perf:: + + $# perf stat -e hisi_pcie0_0/rx_mrd_flux,thr_len=0x4,thr_mode=1/ sleep 5 -- GitLab From 8404b0fbc7fbd42e5c5d28cdedd450e70829c77a Mon Sep 17 00:00:00 2001 From: Qi Liu Date: Thu, 2 Dec 2021 16:06:33 +0800 Subject: [PATCH 531/965] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported to sample bandwidth, latency, buffer occupation etc. Each PMU RCiEP device monitors multiple Root Ports, and each RCiEP is registered as a PMU in /sys/bus/event_source/devices, so users can select target PMU, and use filter to do further sets. Filtering options contains: event - select the event. port - select target Root Ports. Information of Root Ports are shown under sysfs. bdf - select requester_id of target EP device. trig_len - set trigger condition for starting event statistics. trig_mode - set trigger mode. 0 means starting to statistic when bigger than trigger condition, and 1 means smaller. thr_len - set threshold for statistics. thr_mode - set threshold mode. 0 means count when bigger than threshold, and 1 means smaller. Acked-by: Krzysztof Wilczyński Reviewed-by: John Garry Signed-off-by: Qi Liu Reviewed-by: Shaokun Zhang Link: https://lore.kernel.org/r/20211202080633.2919-3-liuqi115@huawei.com Signed-off-by: Will Deacon --- MAINTAINERS | 2 + drivers/perf/hisilicon/Kconfig | 9 + drivers/perf/hisilicon/Makefile | 2 + drivers/perf/hisilicon/hisi_pcie_pmu.c | 948 +++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 5 files changed, 962 insertions(+) create mode 100644 drivers/perf/hisilicon/hisi_pcie_pmu.c diff --git a/MAINTAINERS b/MAINTAINERS index 360e9aa0205d6..90a7d7b21982c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8607,8 +8607,10 @@ F: drivers/misc/hisi_hikey_usb.c HISILICON PMU DRIVER M: Shaokun Zhang +M: Qi Liu S: Supported W: http://www.hisilicon.com +F: Documentation/admin-guide/perf/hisi-pcie-pmu.rst F: Documentation/admin-guide/perf/hisi-pmu.rst F: drivers/perf/hisilicon diff --git a/drivers/perf/hisilicon/Kconfig b/drivers/perf/hisilicon/Kconfig index c5d1b7019fffd..5546218b5598d 100644 --- a/drivers/perf/hisilicon/Kconfig +++ b/drivers/perf/hisilicon/Kconfig @@ -5,3 +5,12 @@ config HISI_PMU help Support for HiSilicon SoC L3 Cache performance monitor, Hydra Home Agent performance monitor and DDR Controller performance monitor. + +config HISI_PCIE_PMU + tristate "HiSilicon PCIE PERF PMU" + depends on PCI && ARM64 + help + Provide support for HiSilicon PCIe performance monitoring unit (PMU) + RCiEP devices. + Adds the PCIe PMU into perf events system for monitoring latency, + bandwidth etc. diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile index 7643c9f93e367..506ed39e32664 100644 --- a/drivers/perf/hisilicon/Makefile +++ b/drivers/perf/hisilicon/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \ hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_sllc_pmu.o \ hisi_uncore_pa_pmu.o + +obj-$(CONFIG_HISI_PCIE_PMU) += hisi_pcie_pmu.o diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c new file mode 100644 index 0000000000000..21771708597db --- /dev/null +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver adds support for PCIe PMU RCiEP device. Related + * perf events are bandwidth, latency etc. + * + * Copyright (C) 2021 HiSilicon Limited + * Author: Qi Liu + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "hisi_pcie_pmu" +/* Define registers */ +#define HISI_PCIE_GLOBAL_CTRL 0x00 +#define HISI_PCIE_EVENT_CTRL 0x010 +#define HISI_PCIE_CNT 0x090 +#define HISI_PCIE_EXT_CNT 0x110 +#define HISI_PCIE_INT_STAT 0x150 +#define HISI_PCIE_INT_MASK 0x154 +#define HISI_PCIE_REG_BDF 0xfe0 +#define HISI_PCIE_REG_VERSION 0xfe4 +#define HISI_PCIE_REG_INFO 0xfe8 + +/* Define command in HISI_PCIE_GLOBAL_CTRL */ +#define HISI_PCIE_GLOBAL_EN 0x01 +#define HISI_PCIE_GLOBAL_NONE 0 + +/* Define command in HISI_PCIE_EVENT_CTRL */ +#define HISI_PCIE_EVENT_EN BIT_ULL(20) +#define HISI_PCIE_RESET_CNT BIT_ULL(22) +#define HISI_PCIE_INIT_SET BIT_ULL(34) +#define HISI_PCIE_THR_EN BIT_ULL(26) +#define HISI_PCIE_TARGET_EN BIT_ULL(32) +#define HISI_PCIE_TRIG_EN BIT_ULL(52) + +/* Define offsets in HISI_PCIE_EVENT_CTRL */ +#define HISI_PCIE_EVENT_M GENMASK_ULL(15, 0) +#define HISI_PCIE_THR_MODE_M GENMASK_ULL(27, 27) +#define HISI_PCIE_THR_M GENMASK_ULL(31, 28) +#define HISI_PCIE_TARGET_M GENMASK_ULL(52, 36) +#define HISI_PCIE_TRIG_MODE_M GENMASK_ULL(53, 53) +#define HISI_PCIE_TRIG_M GENMASK_ULL(59, 56) + +#define HISI_PCIE_MAX_COUNTERS 8 +#define HISI_PCIE_REG_STEP 8 +#define HISI_PCIE_THR_MAX_VAL 10 +#define HISI_PCIE_TRIG_MAX_VAL 10 +#define HISI_PCIE_MAX_PERIOD (GENMASK_ULL(63, 0)) +#define HISI_PCIE_INIT_VAL BIT_ULL(63) + +struct hisi_pcie_pmu { + struct perf_event *hw_events[HISI_PCIE_MAX_COUNTERS]; + struct hlist_node node; + struct pci_dev *pdev; + struct pmu pmu; + void __iomem *base; + int irq; + u32 identifier; + /* Minimum and maximum BDF of root ports monitored by PMU */ + u16 bdf_min; + u16 bdf_max; + int on_cpu; +}; + +struct hisi_pcie_reg_pair { + u16 lo; + u16 hi; +}; + +#define to_pcie_pmu(p) (container_of((p), struct hisi_pcie_pmu, pmu)) +#define GET_PCI_DEVFN(bdf) ((bdf) & 0xff) + +#define HISI_PCIE_PMU_FILTER_ATTR(_name, _config, _hi, _lo) \ + static u64 hisi_pcie_get_##_name(struct perf_event *event) \ + { \ + return FIELD_GET(GENMASK(_hi, _lo), event->attr._config); \ + } \ + +HISI_PCIE_PMU_FILTER_ATTR(event, config, 16, 0); +HISI_PCIE_PMU_FILTER_ATTR(thr_len, config1, 3, 0); +HISI_PCIE_PMU_FILTER_ATTR(thr_mode, config1, 4, 4); +HISI_PCIE_PMU_FILTER_ATTR(trig_len, config1, 8, 5); +HISI_PCIE_PMU_FILTER_ATTR(trig_mode, config1, 9, 9); +HISI_PCIE_PMU_FILTER_ATTR(port, config2, 15, 0); +HISI_PCIE_PMU_FILTER_ATTR(bdf, config2, 31, 16); + +static ssize_t hisi_pcie_format_sysfs_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *eattr; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + + return sysfs_emit(buf, "%s\n", (char *)eattr->var); +} + +static ssize_t hisi_pcie_event_sysfs_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct perf_pmu_events_attr *pmu_attr = + container_of(attr, struct perf_pmu_events_attr, attr); + + return sysfs_emit(buf, "config=0x%llx\n", pmu_attr->id); +} + +#define HISI_PCIE_PMU_FORMAT_ATTR(_name, _format) \ + (&((struct dev_ext_attribute[]){ \ + { .attr = __ATTR(_name, 0444, hisi_pcie_format_sysfs_show, \ + NULL), \ + .var = (void *)_format } \ + })[0].attr.attr) + +#define HISI_PCIE_PMU_EVENT_ATTR(_name, _id) \ + PMU_EVENT_ATTR_ID(_name, hisi_pcie_event_sysfs_show, _id) + +static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->on_cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static ssize_t identifier_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(dev_get_drvdata(dev)); + + return sysfs_emit(buf, "%#x\n", pcie_pmu->identifier); +} +static DEVICE_ATTR_RO(identifier); + +static ssize_t bus_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(dev_get_drvdata(dev)); + + return sysfs_emit(buf, "%#04x\n", PCI_BUS_NUM(pcie_pmu->bdf_min)); +} +static DEVICE_ATTR_RO(bus); + +static struct hisi_pcie_reg_pair +hisi_pcie_parse_reg_value(struct hisi_pcie_pmu *pcie_pmu, u32 reg_off) +{ + u32 val = readl_relaxed(pcie_pmu->base + reg_off); + struct hisi_pcie_reg_pair regs = { + .lo = val, + .hi = val >> 16, + }; + + return regs; +} + +/* + * Hardware counter and ext_counter work together for bandwidth, latency, bus + * utilization and buffer occupancy events. For example, RX memory write latency + * events(index = 0x0010), counter counts total delay cycles and ext_counter + * counts RX memory write PCIe packets number. + * + * As we don't want PMU driver to process these two data, "delay cycles" can + * be treated as an independent event(index = 0x0010), "RX memory write packets + * number" as another(index = 0x10010). BIT 16 is used to distinguish and 0-15 + * bits are "real" event index, which can be used to set HISI_PCIE_EVENT_CTRL. + */ +#define EXT_COUNTER_IS_USED(idx) ((idx) & BIT(16)) + +static u32 hisi_pcie_get_real_event(struct perf_event *event) +{ + return hisi_pcie_get_event(event) & GENMASK(15, 0); +} + +static u32 hisi_pcie_pmu_get_offset(u32 offset, u32 idx) +{ + return offset + HISI_PCIE_REG_STEP * idx; +} + +static u32 hisi_pcie_pmu_readl(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, + u32 idx) +{ + u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx); + + return readl_relaxed(pcie_pmu->base + offset); +} + +static void hisi_pcie_pmu_writel(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u32 val) +{ + u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx); + + writel_relaxed(val, pcie_pmu->base + offset); +} + +static u64 hisi_pcie_pmu_readq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx) +{ + u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx); + + return readq_relaxed(pcie_pmu->base + offset); +} + +static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u64 val) +{ + u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx); + + writeq_relaxed(val, pcie_pmu->base + offset); +} + +static void hisi_pcie_pmu_config_filter(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 reg = HISI_PCIE_INIT_SET; + u64 port, trig_len, thr_len; + + /* Config HISI_PCIE_EVENT_CTRL according to event. */ + reg |= FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event)); + + /* Config HISI_PCIE_EVENT_CTRL according to root port or EP device. */ + port = hisi_pcie_get_port(event); + if (port) + reg |= FIELD_PREP(HISI_PCIE_TARGET_M, port); + else + reg |= HISI_PCIE_TARGET_EN | + FIELD_PREP(HISI_PCIE_TARGET_M, hisi_pcie_get_bdf(event)); + + /* Config HISI_PCIE_EVENT_CTRL according to trigger condition. */ + trig_len = hisi_pcie_get_trig_len(event); + if (trig_len) { + reg |= FIELD_PREP(HISI_PCIE_TRIG_M, trig_len); + reg |= FIELD_PREP(HISI_PCIE_TRIG_MODE_M, hisi_pcie_get_trig_mode(event)); + reg |= HISI_PCIE_TRIG_EN; + } + + /* Config HISI_PCIE_EVENT_CTRL according to threshold condition. */ + thr_len = hisi_pcie_get_thr_len(event); + if (thr_len) { + reg |= FIELD_PREP(HISI_PCIE_THR_M, thr_len); + reg |= FIELD_PREP(HISI_PCIE_THR_MODE_M, hisi_pcie_get_thr_mode(event)); + reg |= HISI_PCIE_THR_EN; + } + + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); +} + +static void hisi_pcie_pmu_clear_filter(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, HISI_PCIE_INIT_SET); +} + +static bool hisi_pcie_pmu_valid_requester_id(struct hisi_pcie_pmu *pcie_pmu, u32 bdf) +{ + struct pci_dev *root_port, *pdev; + u16 rp_bdf; + + pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pcie_pmu->pdev->bus), PCI_BUS_NUM(bdf), + GET_PCI_DEVFN(bdf)); + if (!pdev) + return false; + + root_port = pcie_find_root_port(pdev); + if (!root_port) { + pci_dev_put(pdev); + return false; + } + + pci_dev_put(pdev); + rp_bdf = pci_dev_id(root_port); + return rp_bdf >= pcie_pmu->bdf_min && rp_bdf <= pcie_pmu->bdf_max; +} + +static bool hisi_pcie_pmu_valid_filter(struct perf_event *event, + struct hisi_pcie_pmu *pcie_pmu) +{ + u32 requester_id = hisi_pcie_get_bdf(event); + + if (hisi_pcie_get_thr_len(event) > HISI_PCIE_THR_MAX_VAL) + return false; + + if (hisi_pcie_get_trig_len(event) > HISI_PCIE_TRIG_MAX_VAL) + return false; + + if (requester_id) { + if (!hisi_pcie_pmu_valid_requester_id(pcie_pmu, requester_id)) + return false; + } + + return true; +} + +static bool hisi_pcie_pmu_cmp_event(struct perf_event *target, + struct perf_event *event) +{ + return hisi_pcie_get_real_event(target) == hisi_pcie_get_real_event(event); +} + +static bool hisi_pcie_pmu_validate_event_group(struct perf_event *event) +{ + struct perf_event *sibling, *leader = event->group_leader; + struct perf_event *event_group[HISI_PCIE_MAX_COUNTERS]; + int counters = 1; + int num; + + event_group[0] = leader; + if (!is_software_event(leader)) { + if (leader->pmu != event->pmu) + return false; + + if (leader != event && !hisi_pcie_pmu_cmp_event(leader, event)) + event_group[counters++] = event; + } + + for_each_sibling_event(sibling, event->group_leader) { + if (is_software_event(sibling)) + continue; + + if (sibling->pmu != event->pmu) + return false; + + for (num = 0; num < counters; num++) { + if (hisi_pcie_pmu_cmp_event(event_group[num], sibling)) + break; + } + + if (num == counters) + event_group[counters++] = sibling; + } + + return counters <= HISI_PCIE_MAX_COUNTERS; +} + +static int hisi_pcie_pmu_event_init(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + event->cpu = pcie_pmu->on_cpu; + + if (EXT_COUNTER_IS_USED(hisi_pcie_get_event(event))) + hwc->event_base = HISI_PCIE_EXT_CNT; + else + hwc->event_base = HISI_PCIE_CNT; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* Sampling is not supported. */ + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EOPNOTSUPP; + + if (!hisi_pcie_pmu_valid_filter(event, pcie_pmu)) + return -EINVAL; + + if (!hisi_pcie_pmu_validate_event_group(event)) + return -EINVAL; + + return 0; +} + +static u64 hisi_pcie_pmu_read_counter(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + u32 idx = event->hw.idx; + + return hisi_pcie_pmu_readq(pcie_pmu, event->hw.event_base, idx); +} + +static int hisi_pcie_pmu_find_related_event(struct hisi_pcie_pmu *pcie_pmu, + struct perf_event *event) +{ + struct perf_event *sibling; + int idx; + + for (idx = 0; idx < HISI_PCIE_MAX_COUNTERS; idx++) { + sibling = pcie_pmu->hw_events[idx]; + if (!sibling) + continue; + + if (!hisi_pcie_pmu_cmp_event(sibling, event)) + continue; + + /* Related events must be used in group */ + if (sibling->group_leader == event->group_leader) + return idx; + else + return -EINVAL; + } + + return idx; +} + +static int hisi_pcie_pmu_get_event_idx(struct hisi_pcie_pmu *pcie_pmu) +{ + int idx; + + for (idx = 0; idx < HISI_PCIE_MAX_COUNTERS; idx++) { + if (!pcie_pmu->hw_events[idx]) + return idx; + } + + return -EINVAL; +} + +static void hisi_pcie_pmu_event_update(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + u64 new_cnt, prev_cnt, delta; + + do { + prev_cnt = local64_read(&hwc->prev_count); + new_cnt = hisi_pcie_pmu_read_counter(event); + } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, + new_cnt) != prev_cnt); + + delta = (new_cnt - prev_cnt) & HISI_PCIE_MAX_PERIOD; + local64_add(delta, &event->count); +} + +static void hisi_pcie_pmu_read(struct perf_event *event) +{ + hisi_pcie_pmu_event_update(event); +} + +static void hisi_pcie_pmu_set_period(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + local64_set(&hwc->prev_count, HISI_PCIE_INIT_VAL); + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_CNT, idx, HISI_PCIE_INIT_VAL); + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EXT_CNT, idx, HISI_PCIE_INIT_VAL); +} + +static void hisi_pcie_pmu_enable_counter(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc) +{ + u32 idx = hwc->idx; + u64 val; + + val = hisi_pcie_pmu_readq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx); + val |= HISI_PCIE_EVENT_EN; + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, val); +} + +static void hisi_pcie_pmu_disable_counter(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc) +{ + u32 idx = hwc->idx; + u64 val; + + val = hisi_pcie_pmu_readq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx); + val &= ~HISI_PCIE_EVENT_EN; + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, val); +} + +static void hisi_pcie_pmu_enable_int(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc) +{ + u32 idx = hwc->idx; + + hisi_pcie_pmu_writel(pcie_pmu, HISI_PCIE_INT_MASK, idx, 0); +} + +static void hisi_pcie_pmu_disable_int(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc) +{ + u32 idx = hwc->idx; + + hisi_pcie_pmu_writel(pcie_pmu, HISI_PCIE_INT_MASK, idx, 1); +} + +static void hisi_pcie_pmu_reset_counter(struct hisi_pcie_pmu *pcie_pmu, int idx) +{ + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, HISI_PCIE_RESET_CNT); + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, HISI_PCIE_INIT_SET); +} + +static void hisi_pcie_pmu_start(struct perf_event *event, int flags) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + u64 prev_cnt; + + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) + return; + + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); + hwc->state = 0; + + hisi_pcie_pmu_config_filter(event); + hisi_pcie_pmu_enable_counter(pcie_pmu, hwc); + hisi_pcie_pmu_enable_int(pcie_pmu, hwc); + hisi_pcie_pmu_set_period(event); + + if (flags & PERF_EF_RELOAD) { + prev_cnt = local64_read(&hwc->prev_count); + hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt); + } + + perf_event_update_userpage(event); +} + +static void hisi_pcie_pmu_stop(struct perf_event *event, int flags) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + hisi_pcie_pmu_event_update(event); + hisi_pcie_pmu_disable_int(pcie_pmu, hwc); + hisi_pcie_pmu_disable_counter(pcie_pmu, hwc); + hisi_pcie_pmu_clear_filter(event); + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); + hwc->state |= PERF_HES_STOPPED; + + if (hwc->state & PERF_HES_UPTODATE) + return; + + hwc->state |= PERF_HES_UPTODATE; +} + +static int hisi_pcie_pmu_add(struct perf_event *event, int flags) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx; + + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + + /* Check all working events to find a related event. */ + idx = hisi_pcie_pmu_find_related_event(pcie_pmu, event); + if (idx < 0) + return idx; + + /* Current event shares an enabled counter with the related event */ + if (idx < HISI_PCIE_MAX_COUNTERS) { + hwc->idx = idx; + goto start_count; + } + + idx = hisi_pcie_pmu_get_event_idx(pcie_pmu); + if (idx < 0) + return idx; + + hwc->idx = idx; + pcie_pmu->hw_events[idx] = event; + /* Reset Counter to avoid previous statistic interference. */ + hisi_pcie_pmu_reset_counter(pcie_pmu, idx); + +start_count: + if (flags & PERF_EF_START) + hisi_pcie_pmu_start(event, PERF_EF_RELOAD); + + return 0; +} + +static void hisi_pcie_pmu_del(struct perf_event *event, int flags) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + hisi_pcie_pmu_stop(event, PERF_EF_UPDATE); + pcie_pmu->hw_events[hwc->idx] = NULL; + perf_event_update_userpage(event); +} + +static void hisi_pcie_pmu_enable(struct pmu *pmu) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(pmu); + int num; + + for (num = 0; num < HISI_PCIE_MAX_COUNTERS; num++) { + if (pcie_pmu->hw_events[num]) + break; + } + + if (num == HISI_PCIE_MAX_COUNTERS) + return; + + writel(HISI_PCIE_GLOBAL_EN, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL); +} + +static void hisi_pcie_pmu_disable(struct pmu *pmu) +{ + struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(pmu); + + writel(HISI_PCIE_GLOBAL_NONE, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL); +} + +static irqreturn_t hisi_pcie_pmu_irq(int irq, void *data) +{ + struct hisi_pcie_pmu *pcie_pmu = data; + irqreturn_t ret = IRQ_NONE; + struct perf_event *event; + u32 overflown; + int idx; + + for (idx = 0; idx < HISI_PCIE_MAX_COUNTERS; idx++) { + overflown = hisi_pcie_pmu_readl(pcie_pmu, HISI_PCIE_INT_STAT, idx); + if (!overflown) + continue; + + /* Clear status of interrupt. */ + hisi_pcie_pmu_writel(pcie_pmu, HISI_PCIE_INT_STAT, idx, 1); + event = pcie_pmu->hw_events[idx]; + if (!event) + continue; + + hisi_pcie_pmu_event_update(event); + hisi_pcie_pmu_set_period(event); + ret = IRQ_HANDLED; + } + + return ret; +} + +static int hisi_pcie_pmu_irq_register(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu) +{ + int irq, ret; + + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); + if (ret < 0) { + pci_err(pdev, "Failed to enable MSI vectors: %d\n", ret); + return ret; + } + + irq = pci_irq_vector(pdev, 0); + ret = request_irq(irq, hisi_pcie_pmu_irq, IRQF_NOBALANCING | IRQF_NO_THREAD, DRV_NAME, + pcie_pmu); + if (ret) { + pci_err(pdev, "Failed to register IRQ: %d\n", ret); + pci_free_irq_vectors(pdev); + return ret; + } + + pcie_pmu->irq = irq; + + return 0; +} + +static void hisi_pcie_pmu_irq_unregister(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu) +{ + free_irq(pcie_pmu->irq, pcie_pmu); + pci_free_irq_vectors(pdev); +} + +static int hisi_pcie_pmu_online_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct hisi_pcie_pmu *pcie_pmu = hlist_entry_safe(node, struct hisi_pcie_pmu, node); + + if (pcie_pmu->on_cpu == -1) { + pcie_pmu->on_cpu = cpu; + WARN_ON(irq_set_affinity(pcie_pmu->irq, cpumask_of(cpu))); + } + + return 0; +} + +static int hisi_pcie_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct hisi_pcie_pmu *pcie_pmu = hlist_entry_safe(node, struct hisi_pcie_pmu, node); + unsigned int target; + + /* Nothing to do if this CPU doesn't own the PMU */ + if (pcie_pmu->on_cpu != cpu) + return 0; + + pcie_pmu->on_cpu = -1; + /* Choose a new CPU from all online cpus. */ + target = cpumask_first(cpu_online_mask); + if (target >= nr_cpu_ids) { + pci_err(pcie_pmu->pdev, "There is no CPU to set\n"); + return 0; + } + + perf_pmu_migrate_context(&pcie_pmu->pmu, cpu, target); + /* Use this CPU for event counting */ + pcie_pmu->on_cpu = target; + WARN_ON(irq_set_affinity(pcie_pmu->irq, cpumask_of(target))); + + return 0; +} + +static struct attribute *hisi_pcie_pmu_events_attr[] = { + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_latency, 0x0010), + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_cnt, 0x10010), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_latency, 0x0210), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x1005), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x11005), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x2004), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x12004), + NULL +}; + +static struct attribute_group hisi_pcie_pmu_events_group = { + .name = "events", + .attrs = hisi_pcie_pmu_events_attr, +}; + +static struct attribute *hisi_pcie_pmu_format_attr[] = { + HISI_PCIE_PMU_FORMAT_ATTR(event, "config:0-16"), + HISI_PCIE_PMU_FORMAT_ATTR(thr_len, "config1:0-3"), + HISI_PCIE_PMU_FORMAT_ATTR(thr_mode, "config1:4"), + HISI_PCIE_PMU_FORMAT_ATTR(trig_len, "config1:5-8"), + HISI_PCIE_PMU_FORMAT_ATTR(trig_mode, "config1:9"), + HISI_PCIE_PMU_FORMAT_ATTR(port, "config2:0-15"), + HISI_PCIE_PMU_FORMAT_ATTR(bdf, "config2:16-31"), + NULL +}; + +static const struct attribute_group hisi_pcie_pmu_format_group = { + .name = "format", + .attrs = hisi_pcie_pmu_format_attr, +}; + +static struct attribute *hisi_pcie_pmu_bus_attrs[] = { + &dev_attr_bus.attr, + NULL +}; + +static const struct attribute_group hisi_pcie_pmu_bus_attr_group = { + .attrs = hisi_pcie_pmu_bus_attrs, +}; + +static struct attribute *hisi_pcie_pmu_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL +}; + +static const struct attribute_group hisi_pcie_pmu_cpumask_attr_group = { + .attrs = hisi_pcie_pmu_cpumask_attrs, +}; + +static struct attribute *hisi_pcie_pmu_identifier_attrs[] = { + &dev_attr_identifier.attr, + NULL +}; + +static const struct attribute_group hisi_pcie_pmu_identifier_attr_group = { + .attrs = hisi_pcie_pmu_identifier_attrs, +}; + +static const struct attribute_group *hisi_pcie_pmu_attr_groups[] = { + &hisi_pcie_pmu_events_group, + &hisi_pcie_pmu_format_group, + &hisi_pcie_pmu_bus_attr_group, + &hisi_pcie_pmu_cpumask_attr_group, + &hisi_pcie_pmu_identifier_attr_group, + NULL +}; + +static int hisi_pcie_alloc_pmu(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu) +{ + struct hisi_pcie_reg_pair regs; + u16 sicl_id, core_id; + char *name; + + regs = hisi_pcie_parse_reg_value(pcie_pmu, HISI_PCIE_REG_BDF); + pcie_pmu->bdf_min = regs.lo; + pcie_pmu->bdf_max = regs.hi; + + regs = hisi_pcie_parse_reg_value(pcie_pmu, HISI_PCIE_REG_INFO); + sicl_id = regs.hi; + core_id = regs.lo; + + name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_pcie%u_core%u", sicl_id, core_id); + if (!name) + return -ENOMEM; + + pcie_pmu->pdev = pdev; + pcie_pmu->on_cpu = -1; + pcie_pmu->identifier = readl(pcie_pmu->base + HISI_PCIE_REG_VERSION); + pcie_pmu->pmu = (struct pmu) { + .name = name, + .module = THIS_MODULE, + .event_init = hisi_pcie_pmu_event_init, + .pmu_enable = hisi_pcie_pmu_enable, + .pmu_disable = hisi_pcie_pmu_disable, + .add = hisi_pcie_pmu_add, + .del = hisi_pcie_pmu_del, + .start = hisi_pcie_pmu_start, + .stop = hisi_pcie_pmu_stop, + .read = hisi_pcie_pmu_read, + .task_ctx_nr = perf_invalid_context, + .attr_groups = hisi_pcie_pmu_attr_groups, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, + }; + + return 0; +} + +static int hisi_pcie_init_pmu(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu) +{ + int ret; + + pcie_pmu->base = pci_ioremap_bar(pdev, 2); + if (!pcie_pmu->base) { + pci_err(pdev, "Ioremap failed for pcie_pmu resource\n"); + return -ENOMEM; + } + + ret = hisi_pcie_alloc_pmu(pdev, pcie_pmu); + if (ret) + goto err_iounmap; + + ret = hisi_pcie_pmu_irq_register(pdev, pcie_pmu); + if (ret) + goto err_iounmap; + + ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, &pcie_pmu->node); + if (ret) { + pci_err(pdev, "Failed to register hotplug: %d\n", ret); + goto err_irq_unregister; + } + + ret = perf_pmu_register(&pcie_pmu->pmu, pcie_pmu->pmu.name, -1); + if (ret) { + pci_err(pdev, "Failed to register PCIe PMU: %d\n", ret); + goto err_hotplug_unregister; + } + + return ret; + +err_hotplug_unregister: + cpuhp_state_remove_instance_nocalls( + CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, &pcie_pmu->node); + +err_irq_unregister: + hisi_pcie_pmu_irq_unregister(pdev, pcie_pmu); + +err_iounmap: + iounmap(pcie_pmu->base); + + return ret; +} + +static void hisi_pcie_uninit_pmu(struct pci_dev *pdev) +{ + struct hisi_pcie_pmu *pcie_pmu = pci_get_drvdata(pdev); + + perf_pmu_unregister(&pcie_pmu->pmu); + cpuhp_state_remove_instance_nocalls( + CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, &pcie_pmu->node); + hisi_pcie_pmu_irq_unregister(pdev, pcie_pmu); + iounmap(pcie_pmu->base); +} + +static int hisi_pcie_init_dev(struct pci_dev *pdev) +{ + int ret; + + ret = pcim_enable_device(pdev); + if (ret) { + pci_err(pdev, "Failed to enable PCI device: %d\n", ret); + return ret; + } + + ret = pcim_iomap_regions(pdev, BIT(2), DRV_NAME); + if (ret < 0) { + pci_err(pdev, "Failed to request PCI mem regions: %d\n", ret); + return ret; + } + + pci_set_master(pdev); + + return 0; +} + +static int hisi_pcie_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct hisi_pcie_pmu *pcie_pmu; + int ret; + + pcie_pmu = devm_kzalloc(&pdev->dev, sizeof(*pcie_pmu), GFP_KERNEL); + if (!pcie_pmu) + return -ENOMEM; + + ret = hisi_pcie_init_dev(pdev); + if (ret) + return ret; + + ret = hisi_pcie_init_pmu(pdev, pcie_pmu); + if (ret) + return ret; + + pci_set_drvdata(pdev, pcie_pmu); + + return ret; +} + +static void hisi_pcie_pmu_remove(struct pci_dev *pdev) +{ + hisi_pcie_uninit_pmu(pdev); + pci_set_drvdata(pdev, NULL); +} + +static const struct pci_device_id hisi_pcie_pmu_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa12d) }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, hisi_pcie_pmu_ids); + +static struct pci_driver hisi_pcie_pmu_driver = { + .name = DRV_NAME, + .id_table = hisi_pcie_pmu_ids, + .probe = hisi_pcie_pmu_probe, + .remove = hisi_pcie_pmu_remove, +}; + +static int __init hisi_pcie_module_init(void) +{ + int ret; + + ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, + "AP_PERF_ARM_HISI_PCIE_PMU_ONLINE", + hisi_pcie_pmu_online_cpu, + hisi_pcie_pmu_offline_cpu); + if (ret) { + pr_err("Failed to setup PCIe PMU hotplug: %d\n", ret); + return ret; + } + + ret = pci_register_driver(&hisi_pcie_pmu_driver); + if (ret) + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE); + + return ret; +} +module_init(hisi_pcie_module_init); + +static void __exit hisi_pcie_module_exit(void) +{ + pci_unregister_driver(&hisi_pcie_pmu_driver); + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE); +} +module_exit(hisi_pcie_module_exit); + +MODULE_DESCRIPTION("HiSilicon PCIe PMU driver"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Qi Liu "); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 773c83730906d..411a428ace4d4 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -225,6 +225,7 @@ enum cpuhp_state { CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE, + CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, CPUHP_AP_PERF_ARM_L2X0_ONLINE, CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE, CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, -- GitLab From 8e6082e94aac6d0338883b5953631b662a5a9188 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 10 Dec 2021 15:14:06 +0000 Subject: [PATCH 532/965] arm64: atomics: format whitespace consistently The code for the atomic ops is formatted inconsistently, and while this is not a functional problem it is rather distracting when working on them. Some have ops have consistent indentation, e.g. | #define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \ | static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \ | { \ | u32 tmp; \ | \ | asm volatile( \ | __LSE_PREAMBLE \ | " ldadd" #mb " %w[i], %w[tmp], %[v]\n" \ | " add %w[i], %w[i], %w[tmp]" \ | : [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ | : "r" (v) \ | : cl); \ | \ | return i; \ | } While others have negative indentation for some lines, and/or have misaligned trailing backslashes, e.g. | static inline void __lse_atomic_##op(int i, atomic_t *v) \ | { \ | asm volatile( \ | __LSE_PREAMBLE \ | " " #asm_op " %w[i], %[v]\n" \ | : [i] "+r" (i), [v] "+Q" (v->counter) \ | : "r" (v)); \ | } This patch makes the indentation consistent and also aligns the trailing backslashes. This makes the code easier to read for those (like myself) who are easily distracted by these inconsistencies. This is intended as a cleanup. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Acked-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20211210151410.2782645-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/atomic_ll_sc.h | 86 +++++++++++++-------------- arch/arm64/include/asm/atomic_lse.h | 14 ++--- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h index 13869b76b58cd..fe0db8d416fb2 100644 --- a/arch/arm64/include/asm/atomic_ll_sc.h +++ b/arch/arm64/include/asm/atomic_ll_sc.h @@ -44,11 +44,11 @@ __ll_sc_atomic_##op(int i, atomic_t *v) \ \ asm volatile("// atomic_" #op "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %2\n" \ -"1: ldxr %w0, %2\n" \ -" " #asm_op " %w0, %w0, %w3\n" \ -" stxr %w1, %w0, %2\n" \ -" cbnz %w1, 1b\n") \ + " prfm pstl1strm, %2\n" \ + "1: ldxr %w0, %2\n" \ + " " #asm_op " %w0, %w0, %w3\n" \ + " stxr %w1, %w0, %2\n" \ + " cbnz %w1, 1b\n") \ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i)); \ } @@ -62,12 +62,12 @@ __ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \ \ asm volatile("// atomic_" #op "_return" #name "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %2\n" \ -"1: ld" #acq "xr %w0, %2\n" \ -" " #asm_op " %w0, %w0, %w3\n" \ -" st" #rel "xr %w1, %w0, %2\n" \ -" cbnz %w1, 1b\n" \ -" " #mb ) \ + " prfm pstl1strm, %2\n" \ + "1: ld" #acq "xr %w0, %2\n" \ + " " #asm_op " %w0, %w0, %w3\n" \ + " st" #rel "xr %w1, %w0, %2\n" \ + " cbnz %w1, 1b\n" \ + " " #mb ) \ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i) \ : cl); \ @@ -84,12 +84,12 @@ __ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \ \ asm volatile("// atomic_fetch_" #op #name "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %3\n" \ -"1: ld" #acq "xr %w0, %3\n" \ -" " #asm_op " %w1, %w0, %w4\n" \ -" st" #rel "xr %w2, %w1, %3\n" \ -" cbnz %w2, 1b\n" \ -" " #mb ) \ + " prfm pstl1strm, %3\n" \ + "1: ld" #acq "xr %w0, %3\n" \ + " " #asm_op " %w1, %w0, %w4\n" \ + " st" #rel "xr %w2, %w1, %3\n" \ + " cbnz %w2, 1b\n" \ + " " #mb ) \ : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i) \ : cl); \ @@ -143,11 +143,11 @@ __ll_sc_atomic64_##op(s64 i, atomic64_t *v) \ \ asm volatile("// atomic64_" #op "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %2\n" \ -"1: ldxr %0, %2\n" \ -" " #asm_op " %0, %0, %3\n" \ -" stxr %w1, %0, %2\n" \ -" cbnz %w1, 1b") \ + " prfm pstl1strm, %2\n" \ + "1: ldxr %0, %2\n" \ + " " #asm_op " %0, %0, %3\n" \ + " stxr %w1, %0, %2\n" \ + " cbnz %w1, 1b") \ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i)); \ } @@ -161,12 +161,12 @@ __ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \ \ asm volatile("// atomic64_" #op "_return" #name "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %2\n" \ -"1: ld" #acq "xr %0, %2\n" \ -" " #asm_op " %0, %0, %3\n" \ -" st" #rel "xr %w1, %0, %2\n" \ -" cbnz %w1, 1b\n" \ -" " #mb ) \ + " prfm pstl1strm, %2\n" \ + "1: ld" #acq "xr %0, %2\n" \ + " " #asm_op " %0, %0, %3\n" \ + " st" #rel "xr %w1, %0, %2\n" \ + " cbnz %w1, 1b\n" \ + " " #mb ) \ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i) \ : cl); \ @@ -176,19 +176,19 @@ __ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \ #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\ static inline long \ -__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \ +__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \ { \ s64 result, val; \ unsigned long tmp; \ \ asm volatile("// atomic64_fetch_" #op #name "\n" \ __LL_SC_FALLBACK( \ -" prfm pstl1strm, %3\n" \ -"1: ld" #acq "xr %0, %3\n" \ -" " #asm_op " %1, %0, %4\n" \ -" st" #rel "xr %w2, %1, %3\n" \ -" cbnz %w2, 1b\n" \ -" " #mb ) \ + " prfm pstl1strm, %3\n" \ + "1: ld" #acq "xr %0, %3\n" \ + " " #asm_op " %1, %0, %4\n" \ + " st" #rel "xr %w2, %1, %3\n" \ + " cbnz %w2, 1b\n" \ + " " #mb ) \ : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \ : __stringify(constraint) "r" (i) \ : cl); \ @@ -241,14 +241,14 @@ __ll_sc_atomic64_dec_if_positive(atomic64_t *v) asm volatile("// atomic64_dec_if_positive\n" __LL_SC_FALLBACK( -" prfm pstl1strm, %2\n" -"1: ldxr %0, %2\n" -" subs %0, %0, #1\n" -" b.lt 2f\n" -" stlxr %w1, %0, %2\n" -" cbnz %w1, 1b\n" -" dmb ish\n" -"2:") + " prfm pstl1strm, %2\n" + "1: ldxr %0, %2\n" + " subs %0, %0, #1\n" + " b.lt 2f\n" + " stlxr %w1, %0, %2\n" + " cbnz %w1, 1b\n" + " dmb ish\n" + "2:") : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) : : "cc", "memory"); diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index da3280f639cd7..ab661375835e3 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -11,11 +11,11 @@ #define __ASM_ATOMIC_LSE_H #define ATOMIC_OP(op, asm_op) \ -static inline void __lse_atomic_##op(int i, atomic_t *v) \ +static inline void __lse_atomic_##op(int i, atomic_t *v) \ { \ asm volatile( \ __LSE_PREAMBLE \ -" " #asm_op " %w[i], %[v]\n" \ + " " #asm_op " %w[i], %[v]\n" \ : [i] "+r" (i), [v] "+Q" (v->counter) \ : "r" (v)); \ } @@ -32,7 +32,7 @@ static inline int __lse_atomic_fetch_##op##name(int i, atomic_t *v) \ { \ asm volatile( \ __LSE_PREAMBLE \ -" " #asm_op #mb " %w[i], %w[i], %[v]" \ + " " #asm_op #mb " %w[i], %w[i], %[v]" \ : [i] "+r" (i), [v] "+Q" (v->counter) \ : "r" (v) \ : cl); \ @@ -130,7 +130,7 @@ static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \ " add %w[i], %w[i], %w[tmp]" \ : [i] "+&r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ : "r" (v) \ - : cl); \ + : cl); \ \ return i; \ } @@ -168,7 +168,7 @@ static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \ { \ asm volatile( \ __LSE_PREAMBLE \ -" " #asm_op " %[i], %[v]\n" \ + " " #asm_op " %[i], %[v]\n" \ : [i] "+r" (i), [v] "+Q" (v->counter) \ : "r" (v)); \ } @@ -185,7 +185,7 @@ static inline long __lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v)\ { \ asm volatile( \ __LSE_PREAMBLE \ -" " #asm_op #mb " %[i], %[i], %[v]" \ + " " #asm_op #mb " %[i], %[i], %[v]" \ : [i] "+r" (i), [v] "+Q" (v->counter) \ : "r" (v) \ : cl); \ @@ -272,7 +272,7 @@ static inline void __lse_atomic64_sub(s64 i, atomic64_t *v) } #define ATOMIC64_OP_SUB_RETURN(name, mb, cl...) \ -static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v) \ +static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v)\ { \ unsigned long tmp; \ \ -- GitLab From ef53245060989d1cbe4b72ba56e94f217f4fd1ee Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 10 Dec 2021 15:14:07 +0000 Subject: [PATCH 533/965] arm64: atomics lse: define SUBs in terms of ADDs The FEAT_LSE atomic instructions include atomic ADD instructions (`stadd*` and `ldadd*`), but do not include atomic SUB instructions, so we must build all of the SUB operations using the ADD instructions. We open-code these today, with each SUB op implemented as a copy of the corresponding ADD op with a leading `neg` instruction in the inline assembly to negate the `i` argument. As the compiler has no visibility of the `neg`, this leads to less than optimal code generation when generating `i` into a register. For example, __les_atomic_fetch_sub(1, v) can be compiled to: mov w1, #0x1 neg w1, w1 ldaddal w1, w1, [x2] This patch improves this by replacing the `neg` with negation in C before the inline assembly block, e.g. i = -i; This allows the compiler to generate `i` into a register more optimally, e.g. mov w1, #0xffffffff ldaddal w1, w1, [x2] With this change the assembly for each SUB op is identical to the corresponding ADD op (including barriers and clobbers), so I've removed the inline assembly and rewritten each SUB op in terms of the corresponding ADD op, e.g. | static inline void __lse_atomic_sub(int i, atomic_t *v) | { | __lse_atomic_add(-i, v); | } For clarity I've moved the definition of each SUB op immediately after the corresponding ADD op, and used a single macro to create the RETURN forms of both ops. This is intended as an optimization and cleanup. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Acked-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20211210151410.2782645-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/atomic_lse.h | 180 +++++++++------------------- 1 file changed, 58 insertions(+), 122 deletions(-) diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index ab661375835e3..7454febb6d778 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -25,6 +25,11 @@ ATOMIC_OP(or, stset) ATOMIC_OP(xor, steor) ATOMIC_OP(add, stadd) +static inline void __lse_atomic_sub(int i, atomic_t *v) +{ + __lse_atomic_add(-i, v); +} + #undef ATOMIC_OP #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \ @@ -54,7 +59,20 @@ ATOMIC_FETCH_OPS(add, ldadd) #undef ATOMIC_FETCH_OP #undef ATOMIC_FETCH_OPS -#define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \ +#define ATOMIC_FETCH_OP_SUB(name) \ +static inline int __lse_atomic_fetch_sub##name(int i, atomic_t *v) \ +{ \ + return __lse_atomic_fetch_add##name(-i, v); \ +} + +ATOMIC_FETCH_OP_SUB(_relaxed) +ATOMIC_FETCH_OP_SUB(_acquire) +ATOMIC_FETCH_OP_SUB(_release) +ATOMIC_FETCH_OP_SUB( ) + +#undef ATOMIC_FETCH_OP_SUB + +#define ATOMIC_OP_ADD_SUB_RETURN(name, mb, cl...) \ static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \ { \ u32 tmp; \ @@ -68,14 +86,19 @@ static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \ : cl); \ \ return i; \ +} \ + \ +static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \ +{ \ + return __lse_atomic_add_return##name(-i, v); \ } -ATOMIC_OP_ADD_RETURN(_relaxed, ) -ATOMIC_OP_ADD_RETURN(_acquire, a, "memory") -ATOMIC_OP_ADD_RETURN(_release, l, "memory") -ATOMIC_OP_ADD_RETURN( , al, "memory") +ATOMIC_OP_ADD_SUB_RETURN(_relaxed, ) +ATOMIC_OP_ADD_SUB_RETURN(_acquire, a, "memory") +ATOMIC_OP_ADD_SUB_RETURN(_release, l, "memory") +ATOMIC_OP_ADD_SUB_RETURN( , al, "memory") -#undef ATOMIC_OP_ADD_RETURN +#undef ATOMIC_OP_ADD_SUB_RETURN static inline void __lse_atomic_and(int i, atomic_t *v) { @@ -108,61 +131,6 @@ ATOMIC_FETCH_OP_AND( , al, "memory") #undef ATOMIC_FETCH_OP_AND -static inline void __lse_atomic_sub(int i, atomic_t *v) -{ - asm volatile( - __LSE_PREAMBLE - " neg %w[i], %w[i]\n" - " stadd %w[i], %[v]" - : [i] "+&r" (i), [v] "+Q" (v->counter) - : "r" (v)); -} - -#define ATOMIC_OP_SUB_RETURN(name, mb, cl...) \ -static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \ -{ \ - u32 tmp; \ - \ - asm volatile( \ - __LSE_PREAMBLE \ - " neg %w[i], %w[i]\n" \ - " ldadd" #mb " %w[i], %w[tmp], %[v]\n" \ - " add %w[i], %w[i], %w[tmp]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ - : "r" (v) \ - : cl); \ - \ - return i; \ -} - -ATOMIC_OP_SUB_RETURN(_relaxed, ) -ATOMIC_OP_SUB_RETURN(_acquire, a, "memory") -ATOMIC_OP_SUB_RETURN(_release, l, "memory") -ATOMIC_OP_SUB_RETURN( , al, "memory") - -#undef ATOMIC_OP_SUB_RETURN - -#define ATOMIC_FETCH_OP_SUB(name, mb, cl...) \ -static inline int __lse_atomic_fetch_sub##name(int i, atomic_t *v) \ -{ \ - asm volatile( \ - __LSE_PREAMBLE \ - " neg %w[i], %w[i]\n" \ - " ldadd" #mb " %w[i], %w[i], %[v]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ - : cl); \ - \ - return i; \ -} - -ATOMIC_FETCH_OP_SUB(_relaxed, ) -ATOMIC_FETCH_OP_SUB(_acquire, a, "memory") -ATOMIC_FETCH_OP_SUB(_release, l, "memory") -ATOMIC_FETCH_OP_SUB( , al, "memory") - -#undef ATOMIC_FETCH_OP_SUB - #define ATOMIC64_OP(op, asm_op) \ static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \ { \ @@ -178,6 +146,11 @@ ATOMIC64_OP(or, stset) ATOMIC64_OP(xor, steor) ATOMIC64_OP(add, stadd) +static inline void __lse_atomic64_sub(s64 i, atomic64_t *v) +{ + __lse_atomic64_add(-i, v); +} + #undef ATOMIC64_OP #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \ @@ -207,7 +180,20 @@ ATOMIC64_FETCH_OPS(add, ldadd) #undef ATOMIC64_FETCH_OP #undef ATOMIC64_FETCH_OPS -#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...) \ +#define ATOMIC64_FETCH_OP_SUB(name) \ +static inline long __lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \ +{ \ + return __lse_atomic64_fetch_add##name(-i, v); \ +} + +ATOMIC64_FETCH_OP_SUB(_relaxed) +ATOMIC64_FETCH_OP_SUB(_acquire) +ATOMIC64_FETCH_OP_SUB(_release) +ATOMIC64_FETCH_OP_SUB( ) + +#undef ATOMIC64_FETCH_OP_SUB + +#define ATOMIC64_OP_ADD_SUB_RETURN(name, mb, cl...) \ static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\ { \ unsigned long tmp; \ @@ -221,14 +207,19 @@ static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\ : cl); \ \ return i; \ +} \ + \ +static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v)\ +{ \ + return __lse_atomic64_add_return##name(-i, v); \ } -ATOMIC64_OP_ADD_RETURN(_relaxed, ) -ATOMIC64_OP_ADD_RETURN(_acquire, a, "memory") -ATOMIC64_OP_ADD_RETURN(_release, l, "memory") -ATOMIC64_OP_ADD_RETURN( , al, "memory") +ATOMIC64_OP_ADD_SUB_RETURN(_relaxed, ) +ATOMIC64_OP_ADD_SUB_RETURN(_acquire, a, "memory") +ATOMIC64_OP_ADD_SUB_RETURN(_release, l, "memory") +ATOMIC64_OP_ADD_SUB_RETURN( , al, "memory") -#undef ATOMIC64_OP_ADD_RETURN +#undef ATOMIC64_OP_ADD_SUB_RETURN static inline void __lse_atomic64_and(s64 i, atomic64_t *v) { @@ -261,61 +252,6 @@ ATOMIC64_FETCH_OP_AND( , al, "memory") #undef ATOMIC64_FETCH_OP_AND -static inline void __lse_atomic64_sub(s64 i, atomic64_t *v) -{ - asm volatile( - __LSE_PREAMBLE - " neg %[i], %[i]\n" - " stadd %[i], %[v]" - : [i] "+&r" (i), [v] "+Q" (v->counter) - : "r" (v)); -} - -#define ATOMIC64_OP_SUB_RETURN(name, mb, cl...) \ -static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v)\ -{ \ - unsigned long tmp; \ - \ - asm volatile( \ - __LSE_PREAMBLE \ - " neg %[i], %[i]\n" \ - " ldadd" #mb " %[i], %x[tmp], %[v]\n" \ - " add %[i], %[i], %x[tmp]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ - : "r" (v) \ - : cl); \ - \ - return i; \ -} - -ATOMIC64_OP_SUB_RETURN(_relaxed, ) -ATOMIC64_OP_SUB_RETURN(_acquire, a, "memory") -ATOMIC64_OP_SUB_RETURN(_release, l, "memory") -ATOMIC64_OP_SUB_RETURN( , al, "memory") - -#undef ATOMIC64_OP_SUB_RETURN - -#define ATOMIC64_FETCH_OP_SUB(name, mb, cl...) \ -static inline long __lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \ -{ \ - asm volatile( \ - __LSE_PREAMBLE \ - " neg %[i], %[i]\n" \ - " ldadd" #mb " %[i], %[i], %[v]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ - : cl); \ - \ - return i; \ -} - -ATOMIC64_FETCH_OP_SUB(_relaxed, ) -ATOMIC64_FETCH_OP_SUB(_acquire, a, "memory") -ATOMIC64_FETCH_OP_SUB(_release, l, "memory") -ATOMIC64_FETCH_OP_SUB( , al, "memory") - -#undef ATOMIC64_FETCH_OP_SUB - static inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v) { unsigned long tmp; -- GitLab From 5e9e43c987b2614078b795d68eae6598eea3067a Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 10 Dec 2021 15:14:08 +0000 Subject: [PATCH 534/965] arm64: atomics: lse: define ANDs in terms of ANDNOTs The FEAT_LSE atomic instructions include atomic bit-clear instructions (`ldclr*` and `stclr*`) which can be used to directly implement ANDNOT operations. Each AND op is implemented as a copy of the corresponding ANDNOT op with a leading `mvn` instruction to apply a bitwise NOT to the `i` argument. As the compiler has no visibility of the `mvn`, this leads to less than optimal code generation when generating `i` into a register. For example, __lse_atomic_fetch_and(0xf, v) can be compiled to: mov w1, #0xf mvn w1, w1 ldclral w1, w1, [x2] This patch improves this by replacing the `mvn` with NOT in C before the inline assembly block, e.g. i = ~i; This allows the compiler to generate `i` into a register more optimally, e.g. mov w1, #0xfffffff0 ldclral w1, w1, [x2] With this change the assembly for each AND op is identical to the corresponding ANDNOT op (including barriers and clobbers), so I've removed the inline assembly and rewritten each AND op in terms of the corresponding ANDNOT op, e.g. | static inline void __lse_atomic_and(int i, atomic_t *v) | { | return __lse_atomic_andnot(~i, v); | } This is intended as an optimization and cleanup. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Acked-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20211210151410.2782645-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/atomic_lse.h | 34 ++++------------------------- 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index 7454febb6d778..d707eafb76779 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -102,26 +102,13 @@ ATOMIC_OP_ADD_SUB_RETURN( , al, "memory") static inline void __lse_atomic_and(int i, atomic_t *v) { - asm volatile( - __LSE_PREAMBLE - " mvn %w[i], %w[i]\n" - " stclr %w[i], %[v]" - : [i] "+&r" (i), [v] "+Q" (v->counter) - : "r" (v)); + return __lse_atomic_andnot(~i, v); } #define ATOMIC_FETCH_OP_AND(name, mb, cl...) \ static inline int __lse_atomic_fetch_and##name(int i, atomic_t *v) \ { \ - asm volatile( \ - __LSE_PREAMBLE \ - " mvn %w[i], %w[i]\n" \ - " ldclr" #mb " %w[i], %w[i], %[v]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ - : cl); \ - \ - return i; \ + return __lse_atomic_fetch_andnot##name(~i, v); \ } ATOMIC_FETCH_OP_AND(_relaxed, ) @@ -223,26 +210,13 @@ ATOMIC64_OP_ADD_SUB_RETURN( , al, "memory") static inline void __lse_atomic64_and(s64 i, atomic64_t *v) { - asm volatile( - __LSE_PREAMBLE - " mvn %[i], %[i]\n" - " stclr %[i], %[v]" - : [i] "+&r" (i), [v] "+Q" (v->counter) - : "r" (v)); + return __lse_atomic64_andnot(~i, v); } #define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \ static inline long __lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \ { \ - asm volatile( \ - __LSE_PREAMBLE \ - " mvn %[i], %[i]\n" \ - " ldclr" #mb " %[i], %[i], %[v]" \ - : [i] "+&r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ - : cl); \ - \ - return i; \ + return __lse_atomic64_fetch_andnot##name(~i, v); \ } ATOMIC64_FETCH_OP_AND(_relaxed, ) -- GitLab From 8a578a759ad61b13240190a12cdfa8845c5fa949 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 10 Dec 2021 15:14:09 +0000 Subject: [PATCH 535/965] arm64: atomics: lse: improve constraints for simple ops We have overly conservative assembly constraints for the basic FEAT_LSE atomic instructions, and using more accurate and permissive constraints will allow for better code generation. The FEAT_LSE basic atomic instructions have come in two forms: LD{op}{order}{size} , , [] ST{op}{order}{size} , [] The ST* forms are aliases of the LD* forms where: ST{op}{order}{size} , [] Is: LD{op}{order}{size} , XZR, [] For either form, both and are read but not written back to, and is written with the original value of the memory location. Where ( == ) or ( == ), is written *after* the other register value(s) are consumed. There are no UNPREDICTABLE or CONSTRAINED UNPREDICTABLE behaviours when any pair of , , or are the same register. Our current inline assembly always uses == , treating this register as both an input and an output (using a '+r' constraint). This forces the compiler to do some unnecessary register shuffling and/or redundant value generation. For example, the compiler cannot reuse the value, and currently GCC 11.1.0 will compile: __lse_atomic_add(1, a); __lse_atomic_add(1, b); __lse_atomic_add(1, c); As: mov w3, #0x1 mov w4, w3 stadd w4, [x0] mov w0, w3 stadd w0, [x1] stadd w3, [x2] We can improve this with more accurate constraints, separating and , where is an input-only register ('r'), and is an output-only value ('=r'). As is written back after is consumed, it does not need to be earlyclobber ('=&r'), leaving the compiler free to use the same register for both and where this is desirable. At the same time, the redundant 'r' constraint for `v` is removed, as the `+Q` constraint is sufficient. With this change, the above example becomes: mov w3, #0x1 stadd w3, [x0] stadd w3, [x1] stadd w3, [x2] I've made this change for the non-value-returning and FETCH ops. The RETURN ops have a multi-instruction sequence for which we cannot use the same constraints, and a subsequent patch will rewrite hte RETURN ops in terms of the FETCH ops, relying on the ability for the compiler to reuse the value. This is intended as an optimization. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Acked-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20211210151410.2782645-5-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/atomic_lse.h | 30 +++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index d707eafb76779..e4c5c4c34ce60 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -16,8 +16,8 @@ static inline void __lse_atomic_##op(int i, atomic_t *v) \ asm volatile( \ __LSE_PREAMBLE \ " " #asm_op " %w[i], %[v]\n" \ - : [i] "+r" (i), [v] "+Q" (v->counter) \ - : "r" (v)); \ + : [v] "+Q" (v->counter) \ + : [i] "r" (i)); \ } ATOMIC_OP(andnot, stclr) @@ -35,14 +35,17 @@ static inline void __lse_atomic_sub(int i, atomic_t *v) #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \ static inline int __lse_atomic_fetch_##op##name(int i, atomic_t *v) \ { \ + int old; \ + \ asm volatile( \ __LSE_PREAMBLE \ - " " #asm_op #mb " %w[i], %w[i], %[v]" \ - : [i] "+r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ + " " #asm_op #mb " %w[i], %w[old], %[v]" \ + : [v] "+Q" (v->counter), \ + [old] "=r" (old) \ + : [i] "r" (i) \ : cl); \ \ - return i; \ + return old; \ } #define ATOMIC_FETCH_OPS(op, asm_op) \ @@ -124,8 +127,8 @@ static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \ asm volatile( \ __LSE_PREAMBLE \ " " #asm_op " %[i], %[v]\n" \ - : [i] "+r" (i), [v] "+Q" (v->counter) \ - : "r" (v)); \ + : [v] "+Q" (v->counter) \ + : [i] "r" (i)); \ } ATOMIC64_OP(andnot, stclr) @@ -143,14 +146,17 @@ static inline void __lse_atomic64_sub(s64 i, atomic64_t *v) #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \ static inline long __lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v)\ { \ + s64 old; \ + \ asm volatile( \ __LSE_PREAMBLE \ - " " #asm_op #mb " %[i], %[i], %[v]" \ - : [i] "+r" (i), [v] "+Q" (v->counter) \ - : "r" (v) \ + " " #asm_op #mb " %[i], %[old], %[v]" \ + : [v] "+Q" (v->counter), \ + [old] "=r" (old) \ + : [i] "r" (i) \ : cl); \ \ - return i; \ + return old; \ } #define ATOMIC64_FETCH_OPS(op, asm_op) \ -- GitLab From 053f58bab331e6c31c486661fdb5f6bad5f413de Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 10 Dec 2021 15:14:10 +0000 Subject: [PATCH 536/965] arm64: atomics: lse: define RETURN ops in terms of FETCH ops The FEAT_LSE atomic instructions include LD* instructions which return the original value of a memory location can be used to directly implement FETCH opertations. Each RETURN op is implemented as a copy of the corresponding FETCH op with a trailing instruction to generate the new value of the memory location. We only directly implement *_fetch_add*(), for which we have a trailing `add` instruction. As the compiler has no visibility of the `add`, this leads to less than optimal code generation when consuming the result. For example, the compiler cannot constant-fold the addition into later operations, and currently GCC 11.1.0 will compile: return __lse_atomic_sub_return(1, v) == 0; As: mov w1, #0xffffffff ldaddal w1, w2, [x0] add w1, w1, w2 cmp w1, #0x0 cset w0, eq // eq = none ret This patch improves this by replacing the `add` with C addition after the inline assembly block, e.g. ret += i; This allows the compiler to manipulate `i`. This permits the compiler to merge the `add` and `cmp` for the above, e.g. mov w1, #0xffffffff ldaddal w1, w1, [x0] cmp w1, #0x1 cset w0, eq // eq = none ret With this change the assembly for each RETURN op is identical to the corresponding FETCH op (including barriers and clobbers) so I've removed the inline assembly and rewritten each RETURN op in terms of the corresponding FETCH op, e.g. | static inline void __lse_atomic_add_return(int i, atomic_t *v) | { | return __lse_atomic_fetch_add(i, v) + i | } The new construction does not adversely affect the common case, and before and after this patch GCC 11.1.0 can compile: __lse_atomic_add_return(i, v) As: ldaddal w0, w2, [x1] add w0, w0, w2 ... while having the freedom to do better elsewhere. This is intended as an optimization and cleanup. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Acked-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20211210151410.2782645-6-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/atomic_lse.h | 48 +++++++++-------------------- 1 file changed, 14 insertions(+), 34 deletions(-) diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index e4c5c4c34ce60..d955ade5df7c0 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -75,31 +75,21 @@ ATOMIC_FETCH_OP_SUB( ) #undef ATOMIC_FETCH_OP_SUB -#define ATOMIC_OP_ADD_SUB_RETURN(name, mb, cl...) \ +#define ATOMIC_OP_ADD_SUB_RETURN(name) \ static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \ { \ - u32 tmp; \ - \ - asm volatile( \ - __LSE_PREAMBLE \ - " ldadd" #mb " %w[i], %w[tmp], %[v]\n" \ - " add %w[i], %w[i], %w[tmp]" \ - : [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ - : "r" (v) \ - : cl); \ - \ - return i; \ + return __lse_atomic_fetch_add##name(i, v) + i; \ } \ \ static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \ { \ - return __lse_atomic_add_return##name(-i, v); \ + return __lse_atomic_fetch_sub(i, v) - i; \ } -ATOMIC_OP_ADD_SUB_RETURN(_relaxed, ) -ATOMIC_OP_ADD_SUB_RETURN(_acquire, a, "memory") -ATOMIC_OP_ADD_SUB_RETURN(_release, l, "memory") -ATOMIC_OP_ADD_SUB_RETURN( , al, "memory") +ATOMIC_OP_ADD_SUB_RETURN(_relaxed) +ATOMIC_OP_ADD_SUB_RETURN(_acquire) +ATOMIC_OP_ADD_SUB_RETURN(_release) +ATOMIC_OP_ADD_SUB_RETURN( ) #undef ATOMIC_OP_ADD_SUB_RETURN @@ -186,31 +176,21 @@ ATOMIC64_FETCH_OP_SUB( ) #undef ATOMIC64_FETCH_OP_SUB -#define ATOMIC64_OP_ADD_SUB_RETURN(name, mb, cl...) \ +#define ATOMIC64_OP_ADD_SUB_RETURN(name) \ static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\ { \ - unsigned long tmp; \ - \ - asm volatile( \ - __LSE_PREAMBLE \ - " ldadd" #mb " %[i], %x[tmp], %[v]\n" \ - " add %[i], %[i], %x[tmp]" \ - : [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \ - : "r" (v) \ - : cl); \ - \ - return i; \ + return __lse_atomic64_fetch_add##name(i, v) + i; \ } \ \ static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v)\ { \ - return __lse_atomic64_add_return##name(-i, v); \ + return __lse_atomic64_fetch_sub##name(i, v) - i; \ } -ATOMIC64_OP_ADD_SUB_RETURN(_relaxed, ) -ATOMIC64_OP_ADD_SUB_RETURN(_acquire, a, "memory") -ATOMIC64_OP_ADD_SUB_RETURN(_release, l, "memory") -ATOMIC64_OP_ADD_SUB_RETURN( , al, "memory") +ATOMIC64_OP_ADD_SUB_RETURN(_relaxed) +ATOMIC64_OP_ADD_SUB_RETURN(_acquire) +ATOMIC64_OP_ADD_SUB_RETURN(_release) +ATOMIC64_OP_ADD_SUB_RETURN( ) #undef ATOMIC64_OP_ADD_SUB_RETURN -- GitLab From 0714ccb54c38826f942848813cb06bc50d148e37 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 18 Dec 2019 13:49:14 +0100 Subject: [PATCH 537/965] ARM: tegra: Clean up external memory controller nodes The external memory controller should be sorted after the memory controller to keep the ordering by unit-address intact. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 432 +- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2602 ++-- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 11310 ++++++++-------- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 750 +- 4 files changed, 7576 insertions(+), 7518 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index a7ac805eeed58..25c1006a2c5a3 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -15,66 +15,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -84,6 +95,216 @@ }; }; + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 0x8000000a + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x77e30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 0x80000012 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x76230303 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 0x80000017 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74a30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 0x8000001e + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74230403 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 0x80000026 + 0x00000001 0x00000001 + 0x00000003 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0503 + 0x73c30504 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 0x80000040 + 0x00000001 0x00000001 + 0x00000004 0x00000002 + 0x00000003 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000004 0x00000006 + 0x06040203 0x000a0504 + 0x73840a05 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 0x80000040 + 0x00000001 0x00000002 + 0x00000007 0x00000004 + 0x00000004 0x00000001 + 0x00000002 0x00000007 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000b0607 + 0x77450e08 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 0x80000040 + 0x00000001 0x00000002 + 0x00000009 0x00000005 + 0x00000006 0x00000001 + 0x00000002 0x00000008 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000d0709 + 0x7586120a 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 0x80000040 + 0x00000002 0x00000003 + 0x0000000c 0x00000007 + 0x00000008 0x00000001 + 0x00000002 0x00000009 + 0x00000002 0x00000002 + 0x00000005 0x00000006 + 0x06050202 0x0010090c + 0x7428180d 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 0x80000040 + 0x00000003 0x00000004 + 0x0000000e 0x00000009 + 0x0000000a 0x00000001 + 0x00000003 0x0000000b + 0x00000002 0x00000002 + 0x00000005 0x00000007 + 0x07050202 0x00130b0e + 0x73a91b0f 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b 0x80000040 + 0x00000004 0x00000005 + 0x00000013 0x0000000c + 0x0000000d 0x00000002 + 0x00000003 0x0000000c + 0x00000002 0x00000002 + 0x00000006 0x00000008 + 0x08060202 0x00170e13 + 0x736c2414 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d 0x80000040 + 0x00000005 0x00000006 + 0x00000016 0x0000000e + 0x0000000f 0x00000002 + 0x00000004 0x0000000e + 0x00000002 0x00000002 + 0x00000006 0x00000009 + 0x09060202 0x001a1016 + 0x734e2a17 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1251,217 +1472,6 @@ 0x00000011 >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; }; }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index df4e463afbd1b..3ad2e02c7d3a2 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -10,66 +10,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -79,516 +90,330 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-3 { nvidia,ram-code = <3>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 + 0x00000008 0x00000003 + 0x00000002 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 0x00000002 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 0x00000002 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 >; }; - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + timing-40800000 { + clock-frequency = <40800000>; - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 0x00000003 + 0x00000008 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 0x00000002 + 0x00000000 0x00000002 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 >; }; - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + timing-102000000 { + clock-frequency = <102000000>; - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 0x00000001 - 0x0000000a - 0x00000000 0x00000001 + 0x00000003 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 + 0x00000002 + 0x00000001 0x00000003 + 0x00000008 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 0x00000002 + 0x00000003 0x00000001 - 0x00000000 + 0x00000003 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c + 0x00000003 + 0x00000002 0x00000004 - 0x00000005 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 0x00000003 - 0x0000f2f3 - 0x80000370 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 >; }; - timing-68000000 { - clock-frequency = <68000000>; + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -609,10 +434,10 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < + 0x00000000 0x00000003 - 0x00000011 0x00000000 - 0x00000002 + 0x00000000 0x00000000 0x00000004 0x0000000a @@ -640,25 +465,25 @@ 0x0000000c 0x0000000d 0x0000000f - 0x00000202 + 0x00000060 0x00000000 - 0x00000080 + 0x00000018 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 + 0x00000005 + 0x00000005 0x00000004 0x00000005 0x00000004 - 0x00000001 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x00000213 + 0x00000064 0x00000000 0x00000000 0x00000000 @@ -743,21 +568,21 @@ 0x00514514 0x51451400 0x0000003f - 0x00000022 + 0x00000007 0x00000000 0x00000042 0x000e000e 0x00000000 0x00000003 0x0000f2f3 - 0x8000050e + 0x800001c5 0x0000000a >; }; - timing-102000000 { - clock-frequency = <102000000>; - + timing-20400000 { + clock-frequency = <20400000>; + nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; @@ -777,17 +602,17 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000004 - 0x0000001a 0x00000000 - 0x00000003 - 0x00000001 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 0x00000004 0x0000000a 0x00000005 0x0000000b - 0x00000001 - 0x00000001 + 0x00000000 + 0x00000000 0x00000003 0x00000003 0x00000000 @@ -808,25 +633,25 @@ 0x0000000c 0x0000000d 0x0000000f - 0x00000304 + 0x0000009a 0x00000000 - 0x000000c1 + 0x00000026 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000018 + 0x00000007 0x0000000f - 0x0000001c - 0x0000001c + 0x00000006 + 0x00000006 0x00000004 0x00000005 0x00000004 - 0x00000002 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x0000031c + 0x000000a0 0x00000000 0x00000000 0x00000000 @@ -911,20 +736,20 @@ 0x00514514 0x51451400 0x0000003f - 0x00000033 + 0x0000000b 0x00000000 0x00000042 0x000e000e 0x00000000 0x00000003 0x0000f2f3 - 0x80000713 + 0x8000023a 0x0000000a >; }; - timing-204000000 { - clock-frequency = <204000000>; + timing-40800000 { + clock-frequency = <40800000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -932,7 +757,7 @@ nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000008>; nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; @@ -942,59 +767,59 @@ nvidia,emc-sel-dpd-ctrl = <0x00040128>; nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000009 - 0x00000035 + 0x00000001 + 0x0000000a 0x00000000 - 0x00000006 - 0x00000002 - 0x00000005 + 0x00000001 + 0x00000000 + 0x00000004 0x0000000a 0x00000005 0x0000000b - 0x00000002 - 0x00000002 + 0x00000000 + 0x00000000 0x00000003 0x00000003 0x00000000 - 0x00000005 - 0x00000005 + 0x00000006 + 0x00000006 0x00000006 0x00000002 0x00000000 - 0x00000004 - 0x00000006 + 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000003 + 0x00000004 + 0x0000000c 0x0000000d 0x0000000f - 0x00000011 - 0x00000607 + 0x00000134 0x00000000 - 0x00000181 + 0x0000004d 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000032 + 0x00000008 0x0000000f - 0x00000038 - 0x00000038 + 0x0000000c + 0x0000000c 0x00000004 0x00000005 0x00000004 - 0x00000006 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x00000638 + 0x0000013f 0x00000000 0x00000000 0x00000000 @@ -1027,10 +852,8 @@ 0x00000000 0x00000000 0x00000000 - 0x00008000 0x00000000 0x00000000 - 0x00008000 0x00000000 0x00000000 0x00000000 @@ -1055,21 +878,23 @@ 0x00000000 0x00000000 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000707 + 0x00000e0e 0x81f1f108 0x07070004 0x0000003f @@ -1079,112 +904,112 @@ 0x00514514 0x51451400 0x0000003f - 0x00000066 + 0x00000015 0x00000000 - 0x00000100 + 0x00000042 0x000e000e 0x00000000 0x00000003 - 0x0000d2b3 - 0x80000d22 + 0x0000f2f3 + 0x80000370 0x0000000a >; }; - timing-300000000 { - clock-frequency = <300000000>; + timing-68000000 { + clock-frequency = <68000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x0000000d - 0x0000004d - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 0x00000003 - 0x00000003 - 0x00000002 + 0x00000011 + 0x00000000 0x00000002 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 0x00000003 0x00000003 - 0x00000005 - 0x00000002 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 0x00000002 - 0x00000007 - 0x00020000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 + 0x00000080 + 0x00000002 + 0x00000002 0x00000001 0x00000000 - 0x0000004b - 0x0000000e - 0x00000052 - 0x00000200 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 0x00000004 0x00000005 0x00000004 - 0x00000008 + 0x00000001 0x00000000 0x00000005 0x00000005 - 0x00000924 + 0x00000213 0x00000000 0x00000000 0x00000000 - 0x104ab098 + 0x106aa298 0x002c00a0 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1193,11 +1018,7 @@ 0x00000000 0x00000000 0x00000000 - 0x00098000 - 0x00098000 0x00000000 - 0x00098000 - 0x00098000 0x00000000 0x00000000 0x00000000 @@ -1223,136 +1044,140 @@ 0x00000000 0x00000000 0x00000000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x00005000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000505 + 0x00000e0e 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 0x0000003f - 0x00000096 + 0x00000022 0x00000000 - 0x00000100 - 0x0173000e + 0x00000042 + 0x000e000e 0x00000000 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 + 0x0000f2f3 + 0x8000050e + 0x0000000a >; }; - timing-396000000 { - clock-frequency = <396000000>; + timing-102000000 { + clock-frequency = <102000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000011 - 0x00000066 - 0x00000000 - 0x0000000c 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 0x00000004 - 0x00000008 - 0x00000002 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 + 0x00000005 + 0x0000000b + 0x00000001 + 0x00000001 0x00000003 0x00000003 - 0x00000005 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 0x00000002 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 + 0x00000005 + 0x00000005 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 + 0x00000304 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 + 0x000000c1 + 0x00000002 + 0x00000002 0x00000001 0x00000000 - 0x00000063 + 0x00000018 0x0000000f - 0x0000006c - 0x00000200 + 0x0000001c + 0x0000001c 0x00000004 0x00000005 0x00000004 - 0x0000000b + 0x00000002 0x00000000 0x00000005 0x00000005 - 0x00000c11 + 0x0000031c 0x00000000 0x00000000 0x00000000 - 0x104ab098 + 0x106aa298 0x002c00a0 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1361,11 +1186,7 @@ 0x00000000 0x00000000 0x00000000 - 0x00070000 - 0x00070000 0x00000000 - 0x00070000 - 0x00070000 0x00000000 0x00000000 0x00000000 @@ -1391,136 +1212,140 @@ 0x00000000 0x00000000 0x00000000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00003800 - 0x00003800 - 0x00003800 - 0x00003800 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000505 + 0x00000e0e 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 0x0000003f - 0x000000c6 + 0x00000033 0x00000000 - 0x00000100 - 0x015b000e + 0x00000042 + 0x000e000e 0x00000000 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 + 0x0000f2f3 + 0x80000713 + 0x0000000a >; }; - timing-528000000 { - clock-frequency = <528000000>; + timing-204000000 { + clock-frequency = <204000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000018 - 0x00000088 + 0x00000009 + 0x00000035 0x00000000 - 0x00000010 0x00000006 - 0x00000006 - 0x00000009 0x00000002 - 0x0000000d - 0x00000006 - 0x00000006 + 0x00000005 + 0x0000000a + 0x00000005 + 0x0000000b 0x00000002 0x00000002 - 0x00000000 0x00000003 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 0x00000006 0x00000002 0x00000000 - 0x00000001 - 0x00000009 - 0x00030000 + 0x00000004 + 0x00000006 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 0x00000000 - 0x00000010 - 0x00000012 - 0x00000014 - 0x00000fd6 - 0x00000000 - 0x000003f5 + 0x00000181 + 0x00000002 0x00000002 - 0x0000000b 0x00000001 0x00000000 - 0x00000085 - 0x00000012 - 0x00000090 - 0x00000200 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 0x00000004 0x00000005 0x00000004 - 0x00000010 - 0x00000000 - 0x00000006 0x00000006 - 0x00001017 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 0x00000000 0x00000000 - 0x104ab098 - 0xe01200b1 + 0x00000000 + 0x106aa298 + 0x002c00a0 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1529,14 +1354,12 @@ 0x00000000 0x00000000 0x00000000 - 0x00054000 - 0x00054000 0x00000000 - 0x00054000 - 0x00054000 0x00000000 + 0x00008000 0x00000000 0x00000000 + 0x00008000 0x00000000 0x00000000 0x00000000 @@ -1559,136 +1382,138 @@ 0x00000000 0x00000000 0x00000000 - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x100002a0 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 - 0x77ffc085 - 0x00000505 + 0x77ffc081 + 0x00000707 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 - 0x0606003f - 0x00000000 + 0x0000003f + 0x00000066 0x00000000 0x00000100 - 0x0139000e + 0x000e000e 0x00000000 0x00000003 - 0x000042a0 - 0x80002062 + 0x0000d2b3 + 0x80000d22 0x0000000a >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-300000000 { + clock-frequency = <300000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-2 = <0x80200000>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000001b - 0x0000009b + 0x0000000d + 0x0000004d 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 0x00000002 0x00000002 0x00000000 + 0x00000003 + 0x00000003 0x00000005 - 0x00000005 - 0x0000000a 0x00000002 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 + 0x00000002 + 0x00000007 + 0x00020000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000002 + 0x00000001 + 0x0000000e + 0x00000010 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 + 0x000008e4 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d + 0x00000239 + 0x00000001 + 0x00000008 0x00000001 0x00000000 - 0x00000097 - 0x00000015 - 0x000000a3 + 0x0000004b + 0x0000000e + 0x00000052 0x00000200 0x00000004 0x00000005 0x00000004 - 0x00000013 + 0x00000008 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 + 0x00000005 + 0x00000005 + 0x00000924 0x00000000 0x00000000 0x00000000 0x104ab098 - 0xe00e00b1 + 0x002c00a0 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 0x00000000 0x00000000 0x00000000 @@ -1697,11 +1522,11 @@ 0x00000000 0x00000000 0x00000000 - 0x00048000 - 0x00048000 + 0x00098000 + 0x00098000 0x00000000 - 0x00048000 - 0x00048000 + 0x00098000 + 0x00098000 0x00000000 0x00000000 0x00000000 @@ -1727,20 +1552,20 @@ 0x00000000 0x00000000 0x00000000 - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x100002a0 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 - 0x77ffc085 + 0x77ffc081 0x00000505 0x81f1f108 0x07070004 @@ -1750,113 +1575,113 @@ 0x00514514 0x00514514 0x51451400 - 0x0606003f - 0x00000000 + 0x0000003f + 0x00000096 0x00000000 0x00000100 - 0x0127000e + 0x0173000e 0x00000000 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e + 0x000052a3 + 0x800012d7 + 0x00000009 >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-396000000 { + clock-frequency = <396000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-2 = <0x80200000>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000024 - 0x000000cd + 0x00000011 + 0x00000066 0x00000000 - 0x00000019 - 0x0000000a - 0x00000008 - 0x0000000d + 0x0000000c 0x00000004 - 0x00000013 - 0x0000000a + 0x00000004 + 0x00000008 + 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b 0x00000002 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 0x00000000 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 + 0x00000008 + 0x00020000 0x00000003 - 0x00000011 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 0x00000001 0x00000000 - 0x000000c7 - 0x00000018 - 0x000000d7 + 0x00000063 + 0x0000000f + 0x0000006c 0x00000200 + 0x00000004 0x00000005 - 0x00000006 - 0x00000005 - 0x00000019 + 0x00000004 + 0x0000000b 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 + 0x00000005 + 0x00000005 + 0x00000c11 0x00000000 0x00000000 0x00000000 0x104ab098 - 0xe00700b1 + 0x002c00a0 0x00008000 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 0x00000000 0x00000000 0x00000000 @@ -1865,11 +1690,11 @@ 0x00000000 0x00000000 0x00000000 - 0x00034000 - 0x00034000 + 0x00070000 + 0x00070000 0x00000000 - 0x00034000 - 0x00034000 + 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 @@ -1879,62 +1704,62 @@ 0x00000000 0x00000000 0x00000000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 0x00000000 - 0x00111111 0x00000000 0x00000000 - 0x77ffc085 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 0x81f1f108 0x07070004 0x00000000 0x016eeeee - 0x61861820 + 0x51451420 0x00514514 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 + 0x51451400 + 0x0000003f + 0x000000c6 0x00000000 0x00000100 - 0x00f7000e + 0x015b000e 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 >; }; - timing-924000000 { - clock-frequency = <924000000>; + timing-528000000 { + clock-frequency = <528000000>; - nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; @@ -1943,101 +1768,104 @@ nvidia,emc-cfg-2 = <0x0000089d>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000002b - 0x000000f0 + 0x00000018 + 0x00000088 0x00000000 - 0x0000001e - 0x0000000b + 0x00000010 + 0x00000006 + 0x00000006 0x00000009 - 0x0000000f - 0x00000005 - 0x00000016 - 0x0000000b - 0x0000000b - 0x00000004 0x00000002 - 0x00000000 - 0x00000007 - 0x00000007 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 0x00000002 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 0x00000002 - 0x0000000f - 0x000a0000 - 0x00000004 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 0x00000000 0x00000000 0x00000000 - 0x00000001 - 0x00000016 - 0x0000001a - 0x0000001c - 0x00001be7 0x00000000 - 0x000006f9 - 0x00000004 - 0x00000015 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b 0x00000001 0x00000000 - 0x000000e7 - 0x0000001b - 0x000000fb + 0x00000085 + 0x00000012 + 0x00000090 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000010 + 0x00000000 0x00000006 - 0x00000007 0x00000006 - 0x0000001e + 0x00001017 + 0x00000000 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a 0x0000000a 0x0000000a - 0x00001c28 0x00000000 0x00000000 0x00000000 - 0x104ab898 - 0xe00400b1 - 0x00008000 - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00054000 + 0x00054000 0x00000000 + 0x00054000 + 0x00054000 0x00000000 0x00000000 - 0x0002c000 - 0x0002c000 0x00000000 - 0x0002c000 - 0x0002c000 0x00000000 0x00000000 0x00000000 @@ -2047,374 +1875,556 @@ 0x00000000 0x00000000 0x00000000 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c 0x100002a0 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc085 - 0x00000000 + 0x00000505 0x81f1f108 0x07070004 0x00000000 0x016eeeee - 0x5d75d720 + 0x51451420 0x00514514 0x00514514 - 0x5d75d700 + 0x51451400 0x0606003f 0x00000000 0x00000000 - 0x00000128 - 0x00cd000e + 0x00000100 + 0x0139000e 0x00000000 - 0x00000004 - 0x00004080 - 0x800037ea - 0x00000011 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a >; }; - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; + timing-600000000 { + clock-frequency = <600000000>; - timing-12750000 { - clock-frequency = <12750000>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 0x00000002 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 + 0x00000005 + 0x00000005 + 0x0000000a 0x00000002 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 0x00000003 - 0x00000002 + 0x0000000b + 0x00070000 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 + 0x00000000 + 0x00000000 + 0x00000000 0x00000000 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 0x00000000 + 0x00000482 0x00000002 + 0x0000000d 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e >; }; - timing-300000000 { - clock-frequency = <300000000>; + timing-792000000 { + clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 0x00000002 - 0x00000002 - 0x00000004 + 0x00000000 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 + 0x0000000b 0x00000002 + 0x00000000 0x00000002 + 0x0000000d + 0x00080000 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 + 0x00000011 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 0x00000005 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 + 0x00000019 + 0x00000000 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f >; }; timing-924000000 { clock-frequency = <924000000>; - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f 0x00000005 - 0x00000006 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 + 0x0000000b + 0x0000000b 0x00000004 - 0x0000000e 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 + 0x00000007 + 0x00000006 + 0x0000001e + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000128 + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 >; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index a0f56cc9da5c4..49a6d6afc6334 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -14,60 +14,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -85,60 +95,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -156,60 +176,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -219,3707 +249,583 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000005 /* EMC_DLL_XFORM_DQS0 */ - 0x00000005 /* EMC_DLL_XFORM_DQS1 */ - 0x00000005 /* EMC_DLL_XFORM_DQS2 */ - 0x00000005 /* EMC_DLL_XFORM_DQS3 */ - 0x00000005 /* EMC_DLL_XFORM_DQS4 */ - 0x00000005 /* EMC_DLL_XFORM_DQS5 */ - 0x00000005 /* EMC_DLL_XFORM_DQS6 */ - 0x00000005 /* EMC_DLL_XFORM_DQS7 */ - 0x00000005 /* EMC_DLL_XFORM_DQS8 */ - 0x00000005 /* EMC_DLL_XFORM_DQS9 */ - 0x00000005 /* EMC_DLL_XFORM_DQS10 */ - 0x00000005 /* EMC_DLL_XFORM_DQS11 */ - 0x00000005 /* EMC_DLL_XFORM_DQS12 */ - 0x00000005 /* EMC_DLL_XFORM_DQS13 */ - 0x00000005 /* EMC_DLL_XFORM_DQS14 */ - 0x00000005 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x0000000a /* EMC_DLL_XFORM_DQ4 */ - 0x0000000a /* EMC_DLL_XFORM_DQ5 */ - 0x0000000a /* EMC_DLL_XFORM_DQ6 */ - 0x0000000a /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000e /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000f /* EMC_TXSR */ - 0x0000000f /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000017 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000015 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000019 /* EMC_TXSR */ - 0x00000019 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x00000023 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000021 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000025 /* EMC_TXSR */ - 0x00000025 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000047 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000006 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000044 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000004a /* EMC_TXSR */ - 0x0000004a /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000321>; - nvidia,emc-mrs-wait-cnt = <0x0117000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + timing-68000000 { + clock-frequency = <68000000>; - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x00000067 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000065 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0117000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000521>; - nvidia,emc-mrs-wait-cnt = <0x00f5000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 /* EMC_RC */ - 0x00000089 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000087 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000941>; - nvidia,emc-mrs-wait-cnt = <0x00c8000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x000000b7 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000010 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000b4 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x000000bf /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-20400000 { + clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000b61>; - nvidia,emc-mrs-wait-cnt = <0x00b0000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77430303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x0000001b /* EMC_RC */ - 0x000000d0 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000cc /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75430403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-102000000 { + clock-frequency = <102000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000d71>; - nvidia,emc-mrs-wait-cnt = <0x006f000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000024 /* EMC_RC */ - 0x00000114 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000019 /* EMC_RAS */ - 0x0000000a /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x0000000a /* EMC_RD_RCD */ - 0x0000000a /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000010d /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x0000011e /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ - 0x007f400c /* EMC_DLL_XFORM_DQS2 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ - 0x007f400c /* EMC_DLL_XFORM_DQS10 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00492492 /* EMC_XM2DQSPADCTRL4 */ - 0x00492492 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x006f000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ + 0x7488180d /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x74691b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ + 0x746c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; }; @@ -3930,677 +836,297 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-40800000 { - clock-frequency = <40800000>; + timing-204000000 { + clock-frequency = <204000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-68000000 { - clock-frequency = <68000000>; + timing-600000000 { + clock-frequency = <600000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; + }; + }; - timing-102000000 { - clock-frequency = <102000000>; + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -4621,17 +1147,17 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ 0x00000004 /* EMC_R2W */ 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ @@ -4652,25 +1178,25 @@ 0x0000000c /* EMC_QSAFE */ 0x0000000d /* EMC_RDV */ 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ + 0x00000060 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ + 0x00000064 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ @@ -4755,20 +1281,20 @@ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000007 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ 0x00000042 /* EMC_ZCAL_WAIT_CNT */ 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ 0x0000000a /* EMC_QPOP */ >; }; - timing-204000000 { - clock-frequency = <204000000>; + timing-20400000 { + clock-frequency = <20400000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -4776,69 +1302,69 @@ nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000008>; nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; nvidia,emc-mode-reset = <0x80001221>; nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ + 0x000000a0 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ @@ -4899,14 +1425,14 @@ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ @@ -4923,280 +1449,112 @@ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x0000000b /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-396000000 { - clock-frequency = <396000000>; + timing-40800000 { + clock-frequency = <40800000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ + 0x0000013f /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x106aa298 /* EMC_FBIO_CFG5 */ 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5205,12 +1563,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5235,136 +1593,136 @@ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000015 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-528000000 { - clock-frequency = <528000000>; + timing-68000000 { + clock-frequency = <68000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ + 0x00000001 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5373,12 +1731,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5387,152 +1745,152 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-102000000 { + clock-frequency = <102000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ + 0x00000003 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5541,12 +1899,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5555,152 +1913,152 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-204000000 { + clock-frequency = <204000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000009 /* EMC_DLL_XFORM_DQS0 */ - 0x00000009 /* EMC_DLL_XFORM_DQS1 */ - 0x00000009 /* EMC_DLL_XFORM_DQS2 */ - 0x00000007 /* EMC_DLL_XFORM_DQS3 */ - 0x00000006 /* EMC_DLL_XFORM_DQS4 */ - 0x00000006 /* EMC_DLL_XFORM_DQS5 */ - 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ - 0x00000006 /* EMC_DLL_XFORM_DQS7 */ - 0x00000009 /* EMC_DLL_XFORM_DQS8 */ - 0x00000009 /* EMC_DLL_XFORM_DQS9 */ - 0x00000009 /* EMC_DLL_XFORM_DQS10 */ - 0x00000007 /* EMC_DLL_XFORM_DQS11 */ - 0x00000006 /* EMC_DLL_XFORM_DQS12 */ - 0x00000007 /* EMC_DLL_XFORM_DQS13 */ - 0x00000009 /* EMC_DLL_XFORM_DQS14 */ - 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5709,12 +2067,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5723,347 +2081,895 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000005 /* EMC_DLL_XFORM_DQS0 */ + 0x00000005 /* EMC_DLL_XFORM_DQS1 */ + 0x00000005 /* EMC_DLL_XFORM_DQS2 */ + 0x00000005 /* EMC_DLL_XFORM_DQS3 */ + 0x00000005 /* EMC_DLL_XFORM_DQS4 */ + 0x00000005 /* EMC_DLL_XFORM_DQS5 */ + 0x00000005 /* EMC_DLL_XFORM_DQS6 */ + 0x00000005 /* EMC_DLL_XFORM_DQS7 */ + 0x00000005 /* EMC_DLL_XFORM_DQS8 */ + 0x00000005 /* EMC_DLL_XFORM_DQS9 */ + 0x00000005 /* EMC_DLL_XFORM_DQS10 */ + 0x00000005 /* EMC_DLL_XFORM_DQS11 */ + 0x00000005 /* EMC_DLL_XFORM_DQS12 */ + 0x00000005 /* EMC_DLL_XFORM_DQS13 */ + 0x00000005 /* EMC_DLL_XFORM_DQS14 */ + 0x00000005 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a /* EMC_DLL_XFORM_DQ4 */ + 0x0000000a /* EMC_DLL_XFORM_DQ5 */ + 0x0000000a /* EMC_DLL_XFORM_DQ6 */ + 0x0000000a /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; @@ -6074,286 +2980,1848 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77430303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-40800000 { clock-frequency = <40800000>; - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000e /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000f /* EMC_TXSR */ + 0x0000000f /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-68000000 { clock-frequency = <68000000>; - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75430403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000017 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000015 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000019 /* EMC_TXSR */ + 0x00000019 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-102000000 { clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x00000023 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000021 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000025 /* EMC_TXSR */ + 0x00000025 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-204000000 { clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000047 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000006 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000044 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000004a /* EMC_TXSR */ + 0x0000004a /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000321>; + nvidia,emc-mrs-wait-cnt = <0x0117000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x00000067 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000065 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0117000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000521>; + nvidia,emc-mrs-wait-cnt = <0x00f5000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 /* EMC_RC */ + 0x00000089 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000087 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ - 0x7488180d /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000941>; + nvidia,emc-mrs-wait-cnt = <0x00c8000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x000000b7 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000010 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000b4 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x000000bf /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x74691b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000b61>; + nvidia,emc-mrs-wait-cnt = <0x00b0000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b /* EMC_RC */ + 0x000000d0 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000cc /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ - 0x746c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000d71>; + nvidia,emc-mrs-wait-cnt = <0x006f000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 /* EMC_RC */ + 0x00000114 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000019 /* EMC_RAS */ + 0x0000000a /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x0000000a /* EMC_RD_RCD */ + 0x0000000a /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000010d /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x0000011e /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ + 0x007f400c /* EMC_DLL_XFORM_DQS2 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ + 0x007f400c /* EMC_DLL_XFORM_DQS10 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00492492 /* EMC_XM2DQSPADCTRL4 */ + 0x00492492 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x006f000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; @@ -6364,286 +4832,1848 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-40800000 { clock-frequency = <40800000>; - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-68000000 { clock-frequency = <68000000>; - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-102000000 { clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-204000000 { clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000009 /* EMC_DLL_XFORM_DQS0 */ + 0x00000009 /* EMC_DLL_XFORM_DQS1 */ + 0x00000009 /* EMC_DLL_XFORM_DQS2 */ + 0x00000007 /* EMC_DLL_XFORM_DQS3 */ + 0x00000006 /* EMC_DLL_XFORM_DQS4 */ + 0x00000006 /* EMC_DLL_XFORM_DQS5 */ + 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ + 0x00000006 /* EMC_DLL_XFORM_DQS7 */ + 0x00000009 /* EMC_DLL_XFORM_DQS8 */ + 0x00000009 /* EMC_DLL_XFORM_DQS9 */ + 0x00000009 /* EMC_DLL_XFORM_DQS10 */ + 0x00000007 /* EMC_DLL_XFORM_DQS11 */ + 0x00000006 /* EMC_DLL_XFORM_DQS12 */ + 0x00000007 /* EMC_DLL_XFORM_DQS13 */ + 0x00000009 /* EMC_DLL_XFORM_DQS14 */ + 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 35c98734d35fb..7360a1f35389c 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -10,55 +10,65 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -68,110 +78,402 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a + 0x00000002 0x00000003 - 0x0000000b - 0x00000000 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 + 0x00000002 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 0x00000002 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 0x00000000 - 0x00000000 - 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 + 0x00000001 0x00000002 + 0x00000008 + 0x00000003 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 0x00000001 - 0x00000000 + 0x00000002 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 0x00000004 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 @@ -1751,300 +2053,6 @@ 0x0000000f >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; }; }; }; -- GitLab From 0a6a64f904c6fda33f4b7d50abcae3b8302e89f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:08:42 +0100 Subject: [PATCH 538/965] ARM: tegra: Specify correct PMIC compatible on Tegra114 boards The PMIC found on Dalmore, TN7 and Roth is a TPS65913, so add the specific compatible string in addition to the generic Palmas series compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 7fd901f8d39ab..82caefe5928cd 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -894,7 +894,7 @@ }; palmas: tps65913@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 07960171fabee..71a2806c0f595 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -801,7 +801,7 @@ }; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 745d234b105ba..753130b1e37b7 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -62,7 +62,7 @@ clock-frequency = <400000>; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; -- GitLab From 0b9f3940d6305dd0fc059f7ffaa8334d2e2dd8b6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:19:28 +0100 Subject: [PATCH 539/965] ARM: tegra: Rename SPI flash chip nodes SPI flash chip nodes should be named "flash" instead of "spi-flash". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++- arch/arm/boot/dts/tegra124-venice2.dts | 3 ++- arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++- arch/arm/boot/dts/tegra30-beaver.dts | 3 ++- arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 82caefe5928cd..e64199ba82cbe 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1084,7 +1084,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 35ab296408e10..b2b3eea81232a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1655,7 +1655,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index e6b54ac1ebd1a..02cf986c75678 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -881,7 +881,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4bc87bc0c2a45..beae368f827a4 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -287,7 +287,8 @@ spi@7000c380 { status = "okay"; spi-max-frequency = <48000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q80bl", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <48000000>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e159feeedef72..f724abcdb1a55 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1898,7 +1898,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 448f1397e64a9..e7bfe0e5ee067 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -374,7 +374,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; -- GitLab From 4f74ed817ef8d8aa2ef5049537f329fde2f9fca7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:14:03 +0300 Subject: [PATCH 540/965] ARM: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 16 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index e64199ba82cbe..ad8116780dc9f 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1152,7 +1152,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 71a2806c0f595..ed6ebbf008e10 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1016,7 +1016,7 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 753130b1e37b7..36717331101ee 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -273,7 +273,7 @@ power-supply = <&lcd_bl_en>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index b2b3eea81232a..f59135b93cb0a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1869,7 +1869,7 @@ vbus-supply = <&vdd_usb3_vbus>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 63a81270300a6..f15623f83893d 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -582,7 +582,7 @@ 256>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 02cf986c75678..14eeb1242b156 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1062,7 +1062,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 23d3f8daab232..1aaee6f09fd83 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -827,7 +827,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k-in { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -839,7 +839,7 @@ * oscillator is used as a reference clock-source by the * Azurewave WiFi/BT module. */ - rtc_32k_wifi: clock@1 { + rtc_32k_wifi: clock-32k-wifi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index ae4312eedcbd5..4d137461f3c46 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -640,7 +640,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5b38b0606f993..d3d24523553e1 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -575,7 +575,7 @@ default-brightness-level = <10>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 92d494b8c3d25..ffeae5da22e7e 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -792,7 +792,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index dd4d506683de7..d5f1a46da0bc3 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -502,7 +502,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index beae368f827a4..49c3b3bfac51b 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -380,7 +380,7 @@ bus-width = <4>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 5a2578b3707f4..ef97457f13344 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -606,7 +606,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 07d4ea130964f..72159eb55a3df 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1069,7 +1069,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index f724abcdb1a55..91ecca0be5a22 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1967,7 +1967,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index e7bfe0e5ee067..6074885280fc3 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -434,7 +434,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; -- GitLab From c629196d04c8cdb0624a0763cec78fa18ba8ab1f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:04 +0300 Subject: [PATCH 541/965] ARM: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 14 +++++----- arch/arm/boot/dts/tegra114-roth.dts | 12 ++++----- arch/arm/boot/dts/tegra114-tn7.dts | 6 ++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 24 ++++++++--------- arch/arm/boot/dts/tegra124-nyan.dtsi | 26 +++++++++---------- arch/arm/boot/dts/tegra124-venice2.dts | 26 +++++++++---------- .../boot/dts/tegra20-acer-a500-picasso.dts | 8 +++--- arch/arm/boot/dts/tegra20-harmony.dts | 14 +++++----- arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +++--- arch/arm/boot/dts/tegra20-paz00.dts | 4 +-- arch/arm/boot/dts/tegra20-plutux.dts | 8 +++--- arch/arm/boot/dts/tegra20-seaboard.dts | 14 +++++----- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 8 +++--- arch/arm/boot/dts/tegra20-trimslice.dts | 10 +++---- arch/arm/boot/dts/tegra20-ventana.dts | 10 +++---- .../tegra30-asus-nexus7-grouper-common.dtsi | 8 +++--- ...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +-- .../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 18 ++++++------- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 ++++----- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +++++----- arch/arm/boot/dts/tegra30-cardhu.dtsi | 26 +++++++++---------- 23 files changed, 139 insertions(+), 139 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index ad8116780dc9f..658edfb8d7fa8 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1187,7 +1187,7 @@ }; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -1195,7 +1195,7 @@ regulator-always-on; }; - dvdd_ts_reg: regulator@1 { + dvdd_ts_reg: regulator-ts { compatible = "regulator-fixed"; regulator-name = "dvdd_ts"; regulator-min-microvolt = <1800000>; @@ -1204,7 +1204,7 @@ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@3 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -1215,7 +1215,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - usb3_vbus_reg: regulator@4 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb2_vbus"; regulator-min-microvolt = <5000000>; @@ -1226,7 +1226,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_hdmi_reg: regulator@5 { + vdd_hdmi_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd_hdmi_5v0"; regulator-min-microvolt = <5000000>; @@ -1234,7 +1234,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_cam_1v8_reg: regulator@6 { + vdd_cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "vdd_cam_1v8_reg"; regulator-min-microvolt = <1800000>; @@ -1243,7 +1243,7 @@ gpio = <&palmas_gpio 6 0>; }; - vdd_5v0_hdmi: regulator@7 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index ed6ebbf008e10..2498cf18fd391 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1045,7 +1045,7 @@ }; }; - lcd_bl_en: regulator@0 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "lcd_bl_en"; regulator-min-microvolt = <5000000>; @@ -1053,7 +1053,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@1 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "vdd_lcd_1v8"; regulator-min-microvolt = <1800000>; @@ -1064,7 +1064,7 @@ regulator-boot-on; }; - regulator@2 { + regulator-1v8ts { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_ts"; regulator-min-microvolt = <1800000>; @@ -1073,7 +1073,7 @@ regulator-boot-on; }; - regulator@3 { + regulator-3v3ts { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_ts"; regulator-min-microvolt = <3300000>; @@ -1083,7 +1083,7 @@ regulator-boot-on; }; - regulator@4 { + regulator-1v8com { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_com"; regulator-min-microvolt = <1800000>; @@ -1094,7 +1094,7 @@ regulator-boot-on; }; - regulator@5 { + regulator-3v3com { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_com"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 36717331101ee..ef8f722dd9cba 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -303,7 +303,7 @@ }; /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { + vs_sys: regulator-vs { compatible = "regulator-fixed"; regulator-name = "VS_SYS"; regulator-min-microvolt = <4200000>; @@ -312,7 +312,7 @@ regulator-boot-on; }; - lcd_bl_en: regulator@1 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_BL"; regulator-min-microvolt = <16500000>; @@ -323,7 +323,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@2 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "VD_LCD_1V8"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f59135b93cb0a..c3edb332187a2 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1893,7 +1893,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1902,7 +1902,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1912,7 +1912,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1922,7 +1922,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1934,7 +1934,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1942,7 +1942,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_usb1_vbus: regulator@5 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+USB0_VBUS_SW"; regulator-min-microvolt = <5000000>; @@ -1953,7 +1953,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@6 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1964,7 +1964,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_lp0: regulator@7 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1976,7 +1976,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@8 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1985,7 +1985,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@9 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1996,7 +1996,7 @@ }; /* Molex power connector */ - vdd_5v0_sata: regulator@10 { + vdd_5v0_sata: regulator-5v0sata { compatible = "regulator-fixed"; regulator-name = "+5V_SATA"; regulator-min-microvolt = <5000000>; @@ -2006,7 +2006,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_12v0_sata: regulator@11 { + vdd_12v0_sata: regulator-12v0sata { compatible = "regulator-fixed"; regulator-name = "+12V_SATA"; regulator-min-microvolt = <12000000>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f15623f83893d..2d045d1a9bcff 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -615,7 +615,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -624,7 +624,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -634,7 +634,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -644,7 +644,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -656,7 +656,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -664,7 +664,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; @@ -672,7 +672,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -683,7 +683,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -694,7 +694,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -705,7 +705,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -715,7 +715,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -730,7 +730,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -739,7 +739,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 14eeb1242b156..5f17a2f7d2709 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1096,7 +1096,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1128,7 +1128,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1136,7 +1136,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1146,7 +1146,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1168,7 +1168,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1179,7 +1179,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1189,7 +1189,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1204,7 +1204,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1213,7 +1213,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 1aaee6f09fd83..2e6340e92fe1c 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -964,7 +964,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -972,7 +972,7 @@ regulator-always-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_vs"; regulator-min-microvolt = <3300000>; @@ -981,7 +981,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_1v8_sys: regulator@2 { + vdd_1v8_sys: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_vs"; regulator-min-microvolt = <1800000>; @@ -990,7 +990,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@3 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 4d137461f3c46..a8494378c3826 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -666,7 +666,7 @@ backlight = <&backlight>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -674,7 +674,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -682,7 +682,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -691,7 +691,7 @@ enable-active-high; }; - pci_vdd_reg: regulator@3 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; @@ -700,7 +700,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pn1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -709,7 +709,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -718,7 +718,7 @@ enable-active-high; }; - vdd_5v0_hdmi: regulator@6 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index b31c9bca16e6a..cb6199d7d2249 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -92,7 +92,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -100,7 +100,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -109,7 +109,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d3d24523553e1..46d81d7035488 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -612,7 +612,7 @@ backlight = <&backlight>; }; - p5valw_reg: regulator@0 { + p5valw_reg: regulator-5v0alw { compatible = "regulator-fixed"; regulator-name = "+5valw"; regulator-min-microvolt = <5000000>; @@ -620,7 +620,7 @@ regulator-always-on; }; - vdd_pnl_reg: regulator@1 { + vdd_pnl_reg: regulator-3v0 { compatible = "regulator-fixed"; regulator-name = "+3VS,vdd_pnl"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 5811b7006a9bf..71a8236491dff 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -60,7 +60,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ffeae5da22e7e..ca7adeb1fdd97 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -828,7 +828,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -836,7 +836,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -844,7 +844,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -853,7 +853,7 @@ enable-active-high; }; - vbus_reg: regulator@3 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "vdd_vbus_wup1"; regulator-min-microvolt = <5000000>; @@ -864,7 +864,7 @@ regulator-boot-on; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -873,7 +873,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -882,7 +882,7 @@ enable-active-high; }; - vdd_hdmi: regulator@6 { + vdd_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index d5f1a46da0bc3..2ad56f84bb627 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -508,7 +508,7 @@ #clock-cells = <0>; }; - pci_vdd_reg: regulator@1 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 10ff09d86efa7..4f41c74384b2c 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -69,7 +69,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -95,7 +95,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 49c3b3bfac51b..dd05e2c87c29c 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -402,7 +402,7 @@ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - hdmi_vdd_reg: regulator@0 { + hdmi_vdd_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi"; regulator-min-microvolt = <3300000>; @@ -410,7 +410,7 @@ regulator-always-on; }; - hdmi_pll_reg: regulator@1 { + hdmi_pll_reg: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; @@ -418,7 +418,7 @@ regulator-always-on; }; - vbus_reg: regulator@2 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -429,7 +429,7 @@ regulator-boot-on; }; - pci_clk_reg: regulator@3 { + pci_clk_reg: regulator-pciclk { compatible = "regulator-fixed"; regulator-name = "pci_clk"; regulator-min-microvolt = <3300000>; @@ -437,7 +437,7 @@ regulator-always-on; }; - pci_vdd_reg: regulator@4 { + pci_vdd_reg: regulator-pcivdd { compatible = "regulator-fixed"; regulator-name = "pci_vdd"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ef97457f13344..4284054ebd2c8 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -647,7 +647,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -655,7 +655,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -663,7 +663,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -672,7 +672,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@3 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -681,7 +681,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@4 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 72159eb55a3df..e6aed19a5f3bb 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1207,7 +1207,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -1216,7 +1216,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; regulator-min-microvolt = <3300000>; @@ -1226,7 +1226,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@2 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; @@ -1237,7 +1237,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vcc_3v3_ts: regulator@3 { + vcc_3v3_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "ldo_s-1167_3v3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 53966fa4eef25..cd28e8782f7db 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -166,12 +166,12 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; - regulator@4 { + regulator-usb { compatible = "regulator-fixed"; regulator-name = "avdd_usb"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index 9365ae607239f..ee4a3f4827690 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -143,7 +143,7 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 91ecca0be5a22..7c2b70b13cc4d 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1986,7 +1986,7 @@ }; }; - vdd_5v_in_reg: regulator@0 { + vdd_5v_in_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v_in"; regulator-min-microvolt = <5000000>; @@ -1994,7 +1994,7 @@ regulator-always-on; }; - chargepump_5v_reg: regulator@1 { + chargepump_5v_reg: regulator-chargepump { compatible = "regulator-fixed"; regulator-name = "chargepump_5v"; regulator-min-microvolt = <5000000>; @@ -2005,7 +2005,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - ddr_reg: regulator@2 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -2017,7 +2017,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - vdd_5v_sata_reg: regulator@3 { + vdd_5v_sata_reg: regulator-sata { compatible = "regulator-fixed"; regulator-name = "vdd_5v_sata"; regulator-min-microvolt = <5000000>; @@ -2029,7 +2029,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb1_vbus_reg: regulator@4 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -2040,7 +2040,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb3_vbus_reg: regulator@5 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -2051,7 +2051,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_reg: regulator@6 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3,vdd_3v3_alw"; regulator-min-microvolt = <3300000>; @@ -2063,7 +2063,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_pexs_reg: regulator@7 { + sys_3v3_pexs_reg: regulator-pexs { compatible = "regulator-fixed"; regulator-name = "sys_3v3_pexs"; regulator-min-microvolt = <3300000>; @@ -2075,7 +2075,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_5v0_hdmi: regulator@8 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+VDD_5V_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index 4899e05a0d9c4..247185314f469 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index a11028b8b67bc..2911f08863a06 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; @@ -80,7 +80,7 @@ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; }; - vdd_bl2_reg: regulator@106 { + vdd_bl2_reg: regulator-bl2 { compatible = "regulator-fixed"; regulator-name = "vdd_bl2"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 6074885280fc3..886d4bb2d82c7 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -476,7 +476,7 @@ backlight = <&backlight>; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -484,7 +484,7 @@ regulator-always-on; }; - cam_1v8_reg: regulator@1 { + cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "cam_1v8"; regulator-min-microvolt = <1800000>; @@ -494,7 +494,7 @@ vin-supply = <&vio_reg>; }; - cp_5v_reg: regulator@2 { + cp_5v_reg: regulator-5v0cp { compatible = "regulator-fixed"; regulator-name = "cp_5v"; regulator-min-microvolt = <5000000>; @@ -505,7 +505,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - emmc_3v3_reg: regulator@3 { + emmc_3v3_reg: regulator-emmc { compatible = "regulator-fixed"; regulator-name = "emmc_3v3"; regulator-min-microvolt = <3300000>; @@ -517,7 +517,7 @@ vin-supply = <&sys_3v3_reg>; }; - modem_3v3_reg: regulator@4 { + modem_3v3_reg: regulator-modem { compatible = "regulator-fixed"; regulator-name = "modem_3v3"; regulator-min-microvolt = <3300000>; @@ -526,7 +526,7 @@ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; }; - pex_hvdd_3v3_reg: regulator@5 { + pex_hvdd_3v3_reg: regulator-pex { compatible = "regulator-fixed"; regulator-name = "pex_hvdd_3v3"; regulator-min-microvolt = <3300000>; @@ -536,7 +536,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam1_ldo_reg: regulator@6 { + vdd_cam1_ldo_reg: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "vdd_cam1_ldo"; regulator-min-microvolt = <2800000>; @@ -546,7 +546,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam2_ldo_reg: regulator@7 { + vdd_cam2_ldo_reg: regulator-cam2 { compatible = "regulator-fixed"; regulator-name = "vdd_cam2_ldo"; regulator-min-microvolt = <2800000>; @@ -556,7 +556,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam3_ldo_reg: regulator@8 { + vdd_cam3_ldo_reg: regulator-cam3 { compatible = "regulator-fixed"; regulator-name = "vdd_cam3_ldo"; regulator-min-microvolt = <3300000>; @@ -566,7 +566,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_com_reg: regulator@9 { + vdd_com_reg: regulator-com { compatible = "regulator-fixed"; regulator-name = "vdd_com"; regulator-min-microvolt = <3300000>; @@ -578,7 +578,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: regulator@10 { + vdd_fuse_3v3_reg: regulator-fuse { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -588,7 +588,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_pnl1_reg: regulator@11 { + vdd_pnl1_reg: regulator-pnl1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl1"; regulator-min-microvolt = <3300000>; @@ -600,7 +600,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_vid_reg: regulator@12 { + vdd_vid_reg: regulator-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; -- GitLab From f8d5db7e27b389825b7c61255f14f81d6104061b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:55:06 +0100 Subject: [PATCH 542/965] ARM: tegra: Fix compatible string for Tegra114+ timer The TKE (time-keeping engine) found on Tegra114 and later is no longer backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Note that while the hardware block is strictly backwards-compatible, an architectural timer exists on those newer SoCs that is more reliable, so that should always be preferred. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 546272e396b4c..328425dba0235 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -164,7 +164,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; reg = <0x60005000 0x400>; interrupts = , , diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 63a64171b422a..f4ac0c327c2eb 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -259,7 +259,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , -- GitLab From 82d03bec4e97f01d982b1663d438c55b100de7e3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:56:21 +0100 Subject: [PATCH 543/965] ARM: tegra: Add #reset-cells for Tegra114 MC The Tegra memory controller provides reset controls for hotflush reset, so the #reset-cells property must be specified. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 328425dba0235..ce7410ee08b82 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -542,6 +542,7 @@ interrupts = ; + #reset-cells = <1>; #iommu-cells = <1>; }; -- GitLab From 63658cbc66a27b5fcb683623d299e59cc2771964 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:59:24 +0100 Subject: [PATCH 544/965] ARM: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ++-- arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +++--- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 28c29b6813a71..3209554ec7e6c 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -246,7 +246,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index f3afde4106156..814257c79bf17 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -248,7 +248,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index cde9ae8fa04b7..4ba4d5229fcf1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2055,7 +2055,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2063,7 +2063,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index a46d9ba9bb7a4..3760744cc1b00 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2047,7 +2047,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2055,7 +2055,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 585a5b441cf64..80e439003a6d5 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -747,7 +747,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -755,7 +755,7 @@ }; /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe { + npwe-hog { gpio-hog; gpios = ; output-high; @@ -763,7 +763,7 @@ }; /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr { + rdnwr-hog { gpio-hog; gpios = ; output-low; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9f653ef41da44..93b83b3c56554 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -239,7 +239,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index 86e138e8c7f02..fbfa75e53f321 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -257,7 +257,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 413e35215804b..fcd3d26bef2d2 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1044,7 +1044,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; -- GitLab From 1b5bad01abdcefd1bbf58590d5a78e15741f6a34 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:03:12 +0100 Subject: [PATCH 545/965] ARM: tegra: Rename GPU node on Tegra124 In order to be able to pass DT schema validation, change the GPU nodes' unit-address to the standard notation. Previously this was using a "0," prefix that originated from a time when the top-level device tree node contained #address-cells = <2>. Note that this technically breaks backwards-compatibility with certain older versions of the U-Boot bootloader because early versions used a hard-coded DT path lookup to find the GPU node and perform some fixups on it. However, this was changed to a compatible string based lookup in April 2016, so it's reasonable to expect people to update U-Boot on the systems that they want to use this updated kernel DTB with. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 7 +------ 6 files changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 4ba4d5229fcf1..f00ef4d08fd40 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -57,7 +57,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 3760744cc1b00..e6d25813b4163 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -56,7 +56,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index c3edb332187a2..f42191f22c199 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -72,7 +72,7 @@ status = "okay"; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 2d045d1a9bcff..998b129321f89 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -61,7 +61,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { status = "okay"; vdd-supply = <&vdd_gpu>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 5f17a2f7d2709..7985d1cbc1c08 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -51,7 +51,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f4ac0c327c2eb..d0ec1a30ff54b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -223,12 +223,7 @@ interrupt-parent = <&gic>; }; - /* - * Please keep the following 0, notation in place as a former mainline - * U-Boot version was looking for that particular notation in order to - * perform required fix-ups on that GPU node. - */ - gpu@0,57000000 { + gpu@57000000 { compatible = "nvidia,gk20a"; reg = <0x0 0x57000000 0x0 0x01000000>, <0x0 0x58000000 0x0 0x01000000>; -- GitLab From 9ab9ecd83a3ecf269e8cda08233652203347f5f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:11:33 +0100 Subject: [PATCH 546/965] ARM: tegra: Drop reg-shift for Tegra HS UART When the Tegra High-Speed UART is used instead of the regular UART, the reg-shift property is implied from the compatible string and should not be explicitly listed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 +++ arch/arm/boot/dts/tegra124-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 ++ arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 +++ arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 ++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-ouya.dts | 3 ++- 11 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f00ef4d08fd40..b952b272afc00 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1539,14 +1539,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index e6d25813b4163..2b1bb4382b424 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1532,14 +1532,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c400 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f42191f22c199..e805cb2e20f49 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1389,6 +1389,7 @@ */ serial@70006000 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; @@ -1401,6 +1402,7 @@ */ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2e6340e92fe1c..f973df0158c9f 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -382,11 +382,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Azurewave AW-NH665 BCM4329B1 */ diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 80e439003a6d5..6fed5706da794 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -428,10 +428,12 @@ serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; nand-controller@70008000 { diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6a3a72f81c445..6fe775b2b38d9 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -829,14 +829,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index b2ac51fb15b14..7df2841690d7e 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -820,14 +820,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index e6aed19a5f3bb..ab33ceb63fffb 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -804,11 +804,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 886d4bb2d82c7..12e185846dcb9 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -175,6 +175,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index fcd3d26bef2d2..b585831e32128 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -701,10 +701,12 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 4259871b76c9f..2a6dc423b9fc5 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -82,8 +82,9 @@ }; uartc: serial@70006200 { - status = "okay"; compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, <9600 115200 200>, -- GitLab From 272c5c3a3792366dfd441182f1bd94aa4b6e346f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:14:33 +0100 Subject: [PATCH 547/965] ARM: tegra: Rename thermal zone nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-apalis.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- arch/arm/boot/dts/tegra124.dtsi | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index b952b272afc00..f5440ae14cb4e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2024,7 +2024,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2034,7 +2034,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2044,7 +2044,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 2b1bb4382b424..1d83f2e254c58 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2016,7 +2016,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2026,7 +2026,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2036,7 +2036,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e805cb2e20f49..28b889e4e33bb 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -2047,7 +2047,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2057,7 +2057,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2067,7 +2067,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d0ec1a30ff54b..752a28268024e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1242,7 +1242,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1270,7 +1270,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1298,7 +1298,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1326,7 +1326,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; -- GitLab From c6d4a8977598c022355521fcf29d706dd95c7a83 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:41 +0300 Subject: [PATCH 548/965] ARM: tegra: Rename CPU and EMC OPP table device-tree nodes OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. Reorganize CPU and EMC OPP table device-tree nodes. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 4 +- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 4 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 8 +- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 8 +- .../boot/dts/tegra124-peripherals-opp.dtsi | 140 ++++++++--------- .../boot/dts/tegra20-acer-a500-picasso.dts | 4 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 82 +++++----- arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 82 +++++----- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 36 ++--- ...30-asus-nexus7-grouper-memory-timings.dtsi | 12 +- .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 144 +++++++++--------- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 144 +++++++++--------- arch/arm/boot/dts/tegra30-ouya.dts | 4 +- .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 128 ++++++++-------- 16 files changed, 402 insertions(+), 402 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 25c1006a2c5a3..7143c6b2ec3ed 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1477,9 +1477,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 3ad2e02c7d3a2..79e776db5f375 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2432,9 +2432,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 49a6d6afc6334..31b2e26c69d46 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6681,11 +6681,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 7360a1f35389c..2ce1b12be44d2 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2058,11 +2058,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi index 781ac86010302..b262c1289da5a 100644 --- a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -1,421 +1,421 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,800 { + opp-12750000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0003>; }; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@12750000,1050 { + opp-12750000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0010>; }; - opp@12750000,1110 { + opp-12750000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0004>; }; - opp@20400000,800 { + opp-20400000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0003>; }; - opp@20400000,950 { + opp-20400000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0008>; }; - opp@20400000,1050 { + opp-20400000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0010>; }; - opp@20400000,1110 { + opp-20400000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0004>; }; - opp@40800000,800 { + opp-40800000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0003>; }; - opp@40800000,950 { + opp-40800000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0008>; }; - opp@40800000,1050 { + opp-40800000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0010>; }; - opp@40800000,1110 { + opp-40800000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0004>; }; - opp@68000000,800 { + opp-68000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0003>; }; - opp@68000000,950 { + opp-68000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0008>; }; - opp@68000000,1050 { + opp-68000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0010>; }; - opp@68000000,1110 { + opp-68000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0004>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0003>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,1050 { + opp-102000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0010>; }; - opp@102000000,1110 { + opp-102000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0004>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0003>; opp-suspend; }; - opp@204000000,950 { + opp-204000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@204000000,1050 { + opp-204000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0010>; opp-suspend; }; - opp@204000000,1110 { + opp-204000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0004>; opp-suspend; }; - opp@264000000,800 { + opp-264000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0003>; }; - opp@264000000,950 { + opp-264000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0008>; }; - opp@264000000,1050 { + opp-264000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0010>; }; - opp@264000000,1110 { + opp-264000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0004>; }; - opp@300000000,850 { + opp-300000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0003>; }; - opp@300000000,950 { + opp-300000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0008>; }; - opp@300000000,1050 { + opp-300000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0010>; }; - opp@300000000,1110 { + opp-300000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0004>; }; - opp@348000000,850 { + opp-348000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0003>; }; - opp@348000000,950 { + opp-348000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0008>; }; - opp@348000000,1050 { + opp-348000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0010>; }; - opp@348000000,1110 { + opp-348000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0004>; }; - opp@396000000,950 { + opp-396000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0008>; }; - opp@396000000,1000 { + opp-396000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0003>; }; - opp@396000000,1050 { + opp-396000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0010>; }; - opp@396000000,1110 { + opp-396000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0004>; }; - opp@528000000,950 { + opp-528000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0008>; }; - opp@528000000,1000 { + opp-528000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0003>; }; - opp@528000000,1050 { + opp-528000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0010>; }; - opp@528000000,1110 { + opp-528000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0004>; }; - opp@600000000,950 { + opp-600000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0008>; }; - opp@600000000,1000 { + opp-600000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0003>; }; - opp@600000000,1050 { + opp-600000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0010>; }; - opp@600000000,1110 { + opp-600000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0004>; }; - opp@792000000,1000 { + opp-792000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x000B>; }; - opp@792000000,1050 { + opp-792000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0010>; }; - opp@792000000,1110 { + opp-792000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0004>; }; - opp@924000000,1100 { + opp-924000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <204000>; }; - opp@20400000 { + opp-20400000 { opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <326400>; }; - opp@40800000 { + opp-40800000 { opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <652800>; }; - opp@68000000 { + opp-68000000 { opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1088000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1632000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <3264000>; opp-suspend; }; - opp@264000000 { + opp-264000000 { opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4224000>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4800000>; }; - opp@348000000 { + opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <5568000>; }; - opp@396000000 { + opp-396000000 { opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <6336000>; }; - opp@528000000 { + opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <8448000>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <9600000>; }; - opp@792000000 { + opp-792000000 { opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <12672000>; }; - opp@924000000 { + opp-924000000 { opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; opp-peak-kBps = <14784000>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; opp-peak-kBps = <19200000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index f973df0158c9f..2d5fead9de6bd 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1508,6 +1508,6 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@666000000; - /delete-node/ opp@760000000; + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6fed5706da794..e36b258c82df3 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -745,7 +745,7 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; &gpio { diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi index 6f3e8c5fc5f0d..7330c1b13d933 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -1,164 +1,164 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@216000000,750 { + cpu0_opp_table: opp-table-cpu0 { + opp-216000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@216000000,800 { + opp-216000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@312000000,750 { + opp-312000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@312000000,800 { + opp-312000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,750 { + opp-456000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@456000000,800 { + opp-456000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,825 { + opp-456000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,750 { + opp-608000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@608000000,800 { + opp-608000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000,825 { + opp-608000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@608000000,900 { + opp-608000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,775 { + opp-760000000-775 { opp-microvolt = <775000 775000 1125000>; }; - opp@760000000,800 { + opp-760000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@760000000,875 { + opp-760000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@816000000,800 { + opp-816000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@816000000,875 { + opp-816000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@816000000,950 { + opp-816000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@816000000,1000 { + opp-816000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,850 { + opp-912000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@912000000,900 { + opp-912000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@912000000,925 { + opp-912000000-925 { opp-microvolt = <925000 925000 1125000>; }; - opp@912000000,950 { + opp-912000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000,1000 { + opp-912000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,1050 { + opp-912000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1000000000,875 { + opp-1000000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@1000000000,950 { + opp-1000000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1125000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { opp-microvolt = <1125000 1125000 1125000>; }; }; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi index 135de316383b5..47c8e78ca9581 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -1,250 +1,250 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@216000000,750 { + opp-216000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@216000000,800 { + opp-216000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@312000000,750 { + opp-312000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,800 { + opp-312000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <312000000>; }; - opp@456000000,750 { + opp-456000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0C 0x0003>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,800 { + opp-456000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, <0x08 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,825 { + opp-456000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <456000000>; }; - opp@608000000,750 { + opp-608000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,800 { + opp-608000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,825 { + opp-608000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,900 { + opp-608000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@760000000,775 { + opp-760000000-775 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,800 { + opp-760000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,875 { + opp-760000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, <0x01 0x0004>, <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,800 { + opp-816000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,875 { + opp-816000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0005>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,950 { + opp-816000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,1000 { + opp-816000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <816000000>; }; - opp@912000000,850 { + opp-912000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,900 { + opp-912000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,925 { + opp-912000000-925 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,950 { + opp-912000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, <0x04 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1000 { + opp-912000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1050 { + opp-912000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@1000000000,875 { + opp-1000000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,950 { + opp-1000000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1200000000>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 46d81d7035488..1fd5a7458c7af 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -705,5 +705,5 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index ef3ad2e5f2701..d4d0a5fa70155 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,107 +1,107 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@36000000 { + opp-36000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; }; - opp@47500000 { + opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; }; - opp@50000000 { + opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; }; - opp@54000000 { + opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; }; - opp@57000000 { + opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; }; - opp@100000000 { + opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; }; - opp@108000000 { + opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; }; - opp@126666000 { + opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; }; - opp@150000000 { + opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; }; - opp@190000000 { + opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; }; - opp@216000000 { + opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; opp-suspend; }; - opp@300000000 { + opp-300000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; }; - opp@333000000 { + opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; }; - opp@380000000 { + opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; }; - opp@600000000 { + opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; }; - opp@666000000 { + opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; }; - opp@760000000 { + opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index bcff0997ee517..6c229e1d67e71 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1565,13 +1565,13 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@750000000,1300; - /delete-node/ opp@800000000,1300; - /delete-node/ opp@900000000,1350; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@750000000; - /delete-node/ opp@800000000; - /delete-node/ opp@900000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi index 1be715d2a442b..b8e0e91170212 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -1,288 +1,288 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@51000000,800 { + cpu0_opp_table: opp-table-cpu0 { + opp-51000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@51000000,850 { + opp-51000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@51000000,912 { + opp-51000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@102000000,850 { + opp-102000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@102000000,912 { + opp-102000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@204000000,850 { + opp-204000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@204000000,912 { + opp-204000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@312000000,850 { + opp-312000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@312000000,912 { + opp-312000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@340000000,800 { + opp-340000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@340000000,850 { + opp-340000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@370000000,800 { + opp-370000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@456000000,850 { + opp-456000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@456000000,912 { + opp-456000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@475000000,800 { + opp-475000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@475000000,850 { + opp-475000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,912 { + opp-608000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@620000000,850 { + opp-620000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,850 { + opp-640000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,900 { + opp-640000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,912 { + opp-760000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@816000000,912 { + opp-816000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@860000000,850 { + opp-860000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@860000000,900 { + opp-860000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000,975 { + opp-860000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000,1000 { + opp-860000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@910000000,900 { + opp-910000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,900 { + opp-1100000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1100000000,975 { + opp-1100000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1150000000,975 { + opp-1150000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,975 { + opp-1200000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { opp-microvolt = <1200000 1200000 1250000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi index 72f2fe26cc0e9..5b9ebb75a09f8 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -1,116 +1,116 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@51000000,800 { + opp-51000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,850 { + opp-51000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,912 { + opp-51000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <51000000>; }; - opp@102000000,800 { + opp-102000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,850 { + opp-102000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,912 { + opp-102000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <102000000>; }; - opp@204000000,800 { + opp-204000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,850 { + opp-204000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,912 { + opp-204000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@312000000,850 { + opp-312000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,912 { + opp-312000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <312000000>; }; - opp@340000000,800 { + opp-340000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0192>; opp-hz = /bits/ 64 <340000000>; }; - opp@340000000,850 { + opp-340000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <340000000>; }; - opp@370000000,800 { + opp-370000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <370000000>; }; - opp@456000000,850 { + opp-456000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,912 { + opp-456000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <456000000>; }; - opp@475000000,800 { + opp-475000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x31FE>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000,850 { + opp-475000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, <0x01 0x0010>, <0x01 0x0080>, @@ -118,25 +118,25 @@ opp-hz = /bits/ 64 <475000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,912 { + opp-608000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <608000000>; }; - opp@620000000,850 { + opp-620000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <620000000>; }; - opp@640000000,850 { + opp-640000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x08 0x0002>, @@ -149,13 +149,13 @@ opp-hz = /bits/ 64 <640000000>; }; - opp@640000000,900 { + opp-640000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <640000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -165,7 +165,7 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x02 0x0004>, @@ -177,37 +177,37 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,912 { + opp-760000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,912 { + opp-816000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <816000000>; }; - opp@860000000,850 { + opp-860000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,900 { + opp-860000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -220,7 +220,7 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,975 { + opp-860000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x02 0x0004>, <0x02 0x0008>, @@ -229,25 +229,25 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,1000 { + opp-860000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <860000000>; }; - opp@910000000,900 { + opp-910000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <910000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -260,25 +260,25 @@ opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1100000000,900 { + opp-1100000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,975 { + opp-1100000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -288,7 +288,7 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -297,31 +297,31 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1150000000,975 { + opp-1150000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <1150000000>; }; - opp@1200000000,975 { + opp-1200000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -331,7 +331,7 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -340,39 +340,39 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, <0x10 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0080>, <0x08 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -383,68 +383,68 @@ opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, <0x04 0x0008>, <0x04 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x001C>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x307C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, <0x10 0x0040>, <0x10 0x1000>, @@ -452,7 +452,7 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, <0x08 0x0040>, <0x08 0x1000>, @@ -460,37 +460,37 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1700000000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1700000000>; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 2a6dc423b9fc5..9e59d9bd6b35a 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4524,9 +4524,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@900000000,1350; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@900000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index 2c97803197257..ff25350869b35 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,383 +1,383 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; }; - opp@12750000,1000 { + opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; }; - opp@12750000,1250 { + opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@25500000,950 { + opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; }; - opp@25500000,1000 { + opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; }; - opp@25500000,1250 { + opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; }; - opp@27000000,950 { + opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; }; - opp@27000000,1000 { + opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; }; - opp@27000000,1250 { + opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; }; - opp@51000000,950 { + opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; }; - opp@51000000,1000 { + opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; }; - opp@51000000,1250 { + opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; }; - opp@54000000,950 { + opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; }; - opp@54000000,1000 { + opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; }; - opp@54000000,1250 { + opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; }; - opp@102000000,1000 { + opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; }; - opp@102000000,1250 { + opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@108000000,1000 { + opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; }; - opp@108000000,1250 { + opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; }; - opp@204000000,1000 { + opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; opp-suspend; }; - opp@204000000,1250 { + opp-204000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@333500000,1000 { + opp-333500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; }; - opp@333500000,1200 { + opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; }; - opp@333500000,1250 { + opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; }; - opp@375000000,1000 { + opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; }; - opp@375000000,1200 { + opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; }; - opp@375000000,1250 { + opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; }; - opp@400000000,1000 { + opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; }; - opp@400000000,1200 { + opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; }; - opp@400000000,1250 { + opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; }; - opp@416000000,1200 { + opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; }; - opp@416000000,1250 { + opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; }; - opp@450000000,1200 { + opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; }; - opp@450000000,1250 { + opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; }; - opp@533000000,1200 { + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; }; - opp@533000000,1250 { + opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; }; - opp@625000000,1200 { + opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; }; - opp@625000000,1250 { + opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; }; - opp@667000000,1200 { + opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; }; - opp@750000000,1300 { + opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; }; - opp@800000000,1300 { + opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; }; - opp@900000000,1350 { + opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <102000>; }; - opp@25500000 { + opp-25500000 { opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <204000>; }; - opp@27000000 { + opp-27000000 { opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <216000>; }; - opp@51000000 { + opp-51000000 { opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <408000>; }; - opp@54000000 { + opp-54000000 { opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <432000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <816000>; }; - opp@108000000 { + opp-108000000 { opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <864000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <1632000>; opp-suspend; }; - opp@333500000 { + opp-333500000 { opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <2668000>; }; - opp@375000000 { + opp-375000000 { opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3000000>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3200000>; }; - opp@416000000 { + opp-416000000 { opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3328000>; }; - opp@450000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3600000>; }; - opp@533000000 { + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <4264000>; }; - opp@625000000 { + opp-625000000 { opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x000E>; opp-peak-kBps = <5000000>; }; - opp@667000000 { + opp-667000000 { opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; opp-peak-kBps = <5336000>; }; - opp@750000000 { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6000000>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6400000>; }; - opp@900000000 { + opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <7200000>; -- GitLab From 9b07cfe27647639e52a411d07413608cb5cda7dc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:22:26 +0100 Subject: [PATCH 549/965] ARM: tegra: Fix Tegra124 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 752a28268024e..0e0a769fb30fc 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -438,7 +438,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -453,7 +453,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -468,7 +468,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -483,7 +483,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -498,7 +498,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -513,7 +513,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; -- GitLab From e51c87b7cb1a41d99e059ca3a9c8edf41656ce1f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:23:43 +0100 Subject: [PATCH 550/965] ARM: tegra: Drop unused AHCI clocks on Tegra124 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra124, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0e0a769fb30fc..36566a777e49c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -672,10 +672,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; -- GitLab From 4b7f222d832364e17363e4232d5110c7e7660932 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:25:49 +0100 Subject: [PATCH 551/965] ARM: tegra: Sort Tegra124 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 36566a777e49c..e87da6c24f7cd 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -710,8 +710,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -719,7 +719,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, -- GitLab From 959fddf537c8d3f305df135881976318d7e13b93 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:27:46 +0100 Subject: [PATCH 552/965] ARM: tegra: Avoid pwm- prefix in pinmux nodes The "pwm-" prefix currently matches the DT schema for PWM controllers and throws an error in that case. This is something that should be fixed in the PWM DT schema, but in this case we can also preempt any such conflict by naming the nodes after the pins like we do for many others of these nodes. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri-iris.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index a05fb3853da8e..d2a3bf9d28bd7 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 425494b9ed541..00ecbbd5e9e16 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index e36b258c82df3..28e22097578d6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -113,7 +113,7 @@ }; /* Colibri Backlight PWM, PWM */ - pwm-a-b { + sdc { nvidia,pins = "sdc"; nvidia,function = "pwm"; nvidia,tristate = ; @@ -242,7 +242,7 @@ }; /* Colibri PWM, PWM */ - pwm-c-d { + sdb_sdd { nvidia,pins = "sdb", "sdd"; nvidia,function = "pwm"; nvidia,tristate = ; -- GitLab From d4c4844a9b47dc1c7e8ccce0cdd899602f5479fd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Dec 2021 14:16:13 +0000 Subject: [PATCH 553/965] arm64: perf: Support Denver and Carmel PMUs Add support for the NVIDIA Denver and Carmel PMUs using the generic PMUv3 event map for now. Acked-by: Mark Rutland Signed-off-by: Thierry Reding [ rm: reorder entries alphabetically ] Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/5f0f69d47acca78a9e479501aa4d8b429e23cf11.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index b4044469527e0..035da52e04bfe 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) armv8_vulcan_map_event); } +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel", + armv8_pmuv3_map_event); +} + +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver", + armv8_pmuv3_map_event); +} + static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init}, @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, + {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init}, + {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init}, {}, }; -- GitLab From 6ac9f30bd43baf9e05696e9a614fcd7e83c74afa Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 14 Dec 2021 14:16:14 +0000 Subject: [PATCH 554/965] arm64: perf: Simplify registration boilerplate With the trend for per-core events moving to userspace JSON, registering names for PMUv3 implementations is increasingly a pure boilerplate exercise. Let's wrap things a step further so we can generate the basic PMUv3 init function with a macro invocation, and reduce further new addition to just 2 lines each. Suggested-by: Mark Rutland Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/b79477ea3b97f685d00511d4ecd2f686184dca34.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 113 +++++++++------------------------ 1 file changed, 31 insertions(+), 82 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 035da52e04bfe..ed6d8cd2f88f4 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1145,17 +1145,26 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name, return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL); } -static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", - armv8_pmuv3_map_event); +#define PMUV3_INIT_SIMPLE(name) \ +static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ +{ \ + return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\ } -static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", - armv8_pmuv3_map_event); -} +PMUV3_INIT_SIMPLE(armv8_pmuv3) + +PMUV3_INIT_SIMPLE(armv8_cortex_a34) +PMUV3_INIT_SIMPLE(armv8_cortex_a55) +PMUV3_INIT_SIMPLE(armv8_cortex_a65) +PMUV3_INIT_SIMPLE(armv8_cortex_a75) +PMUV3_INIT_SIMPLE(armv8_cortex_a76) +PMUV3_INIT_SIMPLE(armv8_cortex_a77) +PMUV3_INIT_SIMPLE(armv8_cortex_a78) +PMUV3_INIT_SIMPLE(armv8_neoverse_e1) +PMUV3_INIT_SIMPLE(armv8_neoverse_n1) + +PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) +PMUV3_INIT_SIMPLE(armv8_nvidia_denver) static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu) { @@ -1169,24 +1178,12 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) armv8_a53_map_event); } -static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", - armv8_pmuv3_map_event); -} - static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57", armv8_a57_map_event); } -static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", - armv8_pmuv3_map_event); -} - static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72", @@ -1199,42 +1196,6 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) armv8_a73_map_event); } -static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", - armv8_pmuv3_map_event); -} - -static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", - armv8_pmuv3_map_event); -} - -static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", - armv8_pmuv3_map_event); -} - -static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", - armv8_pmuv3_map_event); -} - -static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", - armv8_pmuv3_map_event); -} - -static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", - armv8_pmuv3_map_event); -} - static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder", @@ -1247,38 +1208,26 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) armv8_vulcan_map_event); } -static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel", - armv8_pmuv3_map_event); -} - -static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver", - armv8_pmuv3_map_event); -} - static const struct of_device_id armv8_pmu_of_device_ids[] = { - {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, - {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init}, + {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, + {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init}, {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, - {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init}, + {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, - {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init}, + {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init}, - {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init}, - {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init}, - {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init}, - {.compatible = "arm,cortex-a78-pmu", .data = armv8_a78_pmu_init}, - {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init}, - {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init}, + {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, + {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, + {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, + {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, + {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, + {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, - {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init}, - {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init}, + {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, + {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, {}, }; @@ -1301,7 +1250,7 @@ static int __init armv8_pmu_driver_init(void) if (acpi_disabled) return platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_init); + return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); } device_initcall(armv8_pmu_driver_init) -- GitLab From 893c34b60a59cd0bdb496084f5c096be720bd244 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 14 Dec 2021 14:16:15 +0000 Subject: [PATCH 555/965] arm64: perf: Support new DT compatibles Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/62d14ba12d847ec7f1fba7cb0b3b881b437e1cc5.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index ed6d8cd2f88f4..4c1698f63f345 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1160,8 +1160,14 @@ PMUV3_INIT_SIMPLE(armv8_cortex_a75) PMUV3_INIT_SIMPLE(armv8_cortex_a76) PMUV3_INIT_SIMPLE(armv8_cortex_a77) PMUV3_INIT_SIMPLE(armv8_cortex_a78) +PMUV3_INIT_SIMPLE(armv9_cortex_a510) +PMUV3_INIT_SIMPLE(armv9_cortex_a710) +PMUV3_INIT_SIMPLE(armv8_cortex_x1) +PMUV3_INIT_SIMPLE(armv9_cortex_x2) PMUV3_INIT_SIMPLE(armv8_neoverse_e1) PMUV3_INIT_SIMPLE(armv8_neoverse_n1) +PMUV3_INIT_SIMPLE(armv9_neoverse_n2) +PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1222,8 +1228,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, + {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, + {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, + {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, + {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, + {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, + {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, -- GitLab From 9be34be87cc8d1afe3c3bc2e645b4dee512d9eda Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 14 Dec 2021 15:27:12 +0000 Subject: [PATCH 556/965] arm64: Add macro version of the BTI instruction BTI is only available from v8.5 so we need to encode it using HINT in generic code and for older toolchains. Add an assembler macro based on one written by Mark Rutland which lets us use the mnemonic and update the existing users. Suggested-by: Mark Rutland Acked-by: Ard Biesheuvel Acked-by: Will Deacon Signed-off-by: Mark Brown Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20211214152714.2380849-2-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/crypto/aes-modes.S | 10 +++++----- arch/arm64/include/asm/assembler.h | 10 ++++++++++ arch/arm64/include/asm/linkage.h | 7 +------ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/arm64/crypto/aes-modes.S b/arch/arm64/crypto/aes-modes.S index b495de22bb380..ff01f0167ba2c 100644 --- a/arch/arm64/crypto/aes-modes.S +++ b/arch/arm64/crypto/aes-modes.S @@ -363,15 +363,15 @@ ST5( mov v4.16b, vctr.16b ) adr x16, 1f sub x16, x16, x12, lsl #3 br x16 - hint 34 // bti c + bti c mov v0.d[0], vctr.d[0] - hint 34 // bti c + bti c mov v1.d[0], vctr.d[0] - hint 34 // bti c + bti c mov v2.d[0], vctr.d[0] - hint 34 // bti c + bti c mov v3.d[0], vctr.d[0] -ST5( hint 34 ) +ST5( bti c ) ST5( mov v4.d[0], vctr.d[0] ) 1: b 2f .previous diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 136d13f3d6e92..e8bd0af0141c3 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -790,6 +790,16 @@ alternative_endif .Lnoyield_\@: .endm +/* + * Branch Target Identifier (BTI) + */ + .macro bti, targets + .equ .L__bti_targets_c, 34 + .equ .L__bti_targets_j, 36 + .equ .L__bti_targets_jc,38 + hint #.L__bti_targets_\targets + .endm + /* * This macro emits a program property note section identifying * architecture features which require special handling, mainly for diff --git a/arch/arm64/include/asm/linkage.h b/arch/arm64/include/asm/linkage.h index 9906541a68619..c5d0c11d7709b 100644 --- a/arch/arm64/include/asm/linkage.h +++ b/arch/arm64/include/asm/linkage.h @@ -6,12 +6,7 @@ #if defined(CONFIG_ARM64_BTI_KERNEL) && defined(__aarch64__) -/* - * Since current versions of gas reject the BTI instruction unless we - * set the architecture version to v8.5 we use the hint instruction - * instead. - */ -#define BTI_C hint 34 ; +#define BTI_C bti c ; /* * When using in-kernel BTI we need to ensure that PCS-conformant assembly -- GitLab From 481ee45ce9e078715b4ca50fcaea518e3aee1aa7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 14 Dec 2021 15:27:13 +0000 Subject: [PATCH 557/965] arm64: Unconditionally override SYM_FUNC macros Currently we only override the SYM_FUNC macros when we need to insert BTI C into them, do this unconditionally to make it more likely that we'll notice bugs in our override. Suggested-by: Mark Rutland Acked-by: Ard Biesheuvel Signed-off-by: Mark Brown Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20211214152714.2380849-3-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/linkage.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/linkage.h b/arch/arm64/include/asm/linkage.h index c5d0c11d7709b..1cfa8bb33eddf 100644 --- a/arch/arm64/include/asm/linkage.h +++ b/arch/arm64/include/asm/linkage.h @@ -8,10 +8,18 @@ #define BTI_C bti c ; +#else + +#define BTI_C + +#endif + /* - * When using in-kernel BTI we need to ensure that PCS-conformant assembly - * functions have suitable annotations. Override SYM_FUNC_START to insert - * a BTI landing pad at the start of everything. + * When using in-kernel BTI we need to ensure that PCS-conformant + * assembly functions have suitable annotations. Override + * SYM_FUNC_START to insert a BTI landing pad at the start of + * everything, the override is done unconditionally so we're more + * likely to notice any drift from the overridden definitions. */ #define SYM_FUNC_START(name) \ SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) \ @@ -37,8 +45,6 @@ SYM_START(name, SYM_L_WEAK, SYM_A_NONE) \ BTI_C -#endif - /* * Annotate a function as position independent, i.e., safe to be called before * the kernel virtual mapping is activated. -- GitLab From 742a15b1a23aa43bde2d9d681281ec1925be13fd Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 14 Dec 2021 15:27:14 +0000 Subject: [PATCH 558/965] arm64: Use BTI C directly and unconditionally Now we have a macro for BTI C that looks like a regular instruction change all the users of the current BTI_C macro to just emit a BTI C directly and remove the macro. This does mean that we now unconditionally BTI annotate all assembly functions, meaning that they are worse in this respect than code generated by the compiler. The overhead should be minimal for implementations with a reasonable HINT implementation. Signed-off-by: Mark Brown Reviewed-by: Ard Biesheuvel Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20211214152714.2380849-4-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/linkage.h | 22 ++++++---------------- arch/arm64/kernel/entry-ftrace.S | 8 ++------ arch/arm64/lib/kasan_sw_tags.S | 4 +--- 3 files changed, 9 insertions(+), 25 deletions(-) diff --git a/arch/arm64/include/asm/linkage.h b/arch/arm64/include/asm/linkage.h index 1cfa8bb33eddf..9065e4749b42a 100644 --- a/arch/arm64/include/asm/linkage.h +++ b/arch/arm64/include/asm/linkage.h @@ -4,16 +4,6 @@ #define __ALIGN .align 2 #define __ALIGN_STR ".align 2" -#if defined(CONFIG_ARM64_BTI_KERNEL) && defined(__aarch64__) - -#define BTI_C bti c ; - -#else - -#define BTI_C - -#endif - /* * When using in-kernel BTI we need to ensure that PCS-conformant * assembly functions have suitable annotations. Override @@ -23,27 +13,27 @@ */ #define SYM_FUNC_START(name) \ SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) \ - BTI_C + bti c ; #define SYM_FUNC_START_NOALIGN(name) \ SYM_START(name, SYM_L_GLOBAL, SYM_A_NONE) \ - BTI_C + bti c ; #define SYM_FUNC_START_LOCAL(name) \ SYM_START(name, SYM_L_LOCAL, SYM_A_ALIGN) \ - BTI_C + bti c ; #define SYM_FUNC_START_LOCAL_NOALIGN(name) \ SYM_START(name, SYM_L_LOCAL, SYM_A_NONE) \ - BTI_C + bti c ; #define SYM_FUNC_START_WEAK(name) \ SYM_START(name, SYM_L_WEAK, SYM_A_ALIGN) \ - BTI_C + bti c ; #define SYM_FUNC_START_WEAK_NOALIGN(name) \ SYM_START(name, SYM_L_WEAK, SYM_A_NONE) \ - BTI_C + bti c ; /* * Annotate a function as position independent, i.e., safe to be called before diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S index 8cf970d219f5d..e535480a4069b 100644 --- a/arch/arm64/kernel/entry-ftrace.S +++ b/arch/arm64/kernel/entry-ftrace.S @@ -77,17 +77,13 @@ .endm SYM_CODE_START(ftrace_regs_caller) -#ifdef BTI_C - BTI_C -#endif + bti c ftrace_regs_entry 1 b ftrace_common SYM_CODE_END(ftrace_regs_caller) SYM_CODE_START(ftrace_caller) -#ifdef BTI_C - BTI_C -#endif + bti c ftrace_regs_entry 0 b ftrace_common SYM_CODE_END(ftrace_caller) diff --git a/arch/arm64/lib/kasan_sw_tags.S b/arch/arm64/lib/kasan_sw_tags.S index 5b04464c045eb..20784ce75defb 100644 --- a/arch/arm64/lib/kasan_sw_tags.S +++ b/arch/arm64/lib/kasan_sw_tags.S @@ -38,9 +38,7 @@ * incremented by 256 prior to return). */ SYM_CODE_START(__hwasan_tag_mismatch) -#ifdef BTI_C - BTI_C -#endif + bti c add x29, sp, #232 stp x2, x3, [sp, #8 * 2] stp x4, x5, [sp, #8 * 4] -- GitLab From 97bcbee404e386195614b58e98ab2e7eddd89a5c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:40:57 +0000 Subject: [PATCH 559/965] arm64/sve: Make sysctl interface for SVE reusable by SME The vector length configuration for SME is very similar to that for SVE so in order to allow reuse refactor the SVE configuration so that it takes the vector type from the struct ctl_table. Since there's no dedicated space for this we repurpose the extra1 field to store the vector type, this is otherwise unused for integer sysctls. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-2-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/kernel/fpsimd.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index fa244c426f610..23e575c4e5804 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -406,12 +407,13 @@ static unsigned int find_supported_vector_length(enum vec_type type, #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) -static int sve_proc_do_default_vl(struct ctl_table *table, int write, +static int vec_proc_do_default_vl(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { - struct vl_info *info = &vl_info[ARM64_VEC_SVE]; + struct vl_info *info = table->extra1; + enum vec_type type = info->type; int ret; - int vl = get_sve_default_vl(); + int vl = get_default_vl(type); struct ctl_table tmp_table = { .data = &vl, .maxlen = sizeof(vl), @@ -428,7 +430,7 @@ static int sve_proc_do_default_vl(struct ctl_table *table, int write, if (!sve_vl_valid(vl)) return -EINVAL; - set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, vl)); + set_default_vl(type, find_supported_vector_length(type, vl)); return 0; } @@ -436,7 +438,8 @@ static struct ctl_table sve_default_vl_table[] = { { .procname = "sve_default_vector_length", .mode = 0644, - .proc_handler = sve_proc_do_default_vl, + .proc_handler = vec_proc_do_default_vl, + .extra1 = &vl_info[ARM64_VEC_SVE], }, { } }; @@ -1107,7 +1110,7 @@ static void fpsimd_flush_thread_vl(enum vec_type type) vl = get_default_vl(type); if (WARN_ON(!sve_vl_valid(vl))) - vl = SVE_VL_MIN; + vl = vl_info[type].min_vl; supported_vl = find_supported_vector_length(type, vl); if (WARN_ON(supported_vl != vl)) -- GitLab From 30c43e73b3fa2d75f5d4e72fea345380ba5eb21b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:40:58 +0000 Subject: [PATCH 560/965] arm64/sve: Generalise vector length configuration prctl() for SME In preparation for adding SME support update the bulk of the implementation for the vector length configuration prctl() calls to be independent of vector type. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-3-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/fpsimd.h | 6 ++--- arch/arm64/kernel/fpsimd.c | 47 ++++++++++++++++++--------------- arch/arm64/kernel/ptrace.c | 4 +-- arch/arm64/kvm/reset.c | 8 +++--- 4 files changed, 34 insertions(+), 31 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index dbb4b30a5648d..cb24385e3632a 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -51,8 +51,8 @@ extern void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *state, extern void fpsimd_flush_task_state(struct task_struct *target); extern void fpsimd_save_and_flush_cpu_state(void); -/* Maximum VL that SVE VL-agnostic software can transparently support */ -#define SVE_VL_ARCH_MAX 0x100 +/* Maximum VL that SVE/SME VL-agnostic software can transparently support */ +#define VL_ARCH_MAX 0x100 /* Offset of FFR in the SVE register dump */ static inline size_t sve_ffr_offset(int vl) @@ -122,7 +122,7 @@ extern void fpsimd_sync_to_sve(struct task_struct *task); extern void sve_sync_to_fpsimd(struct task_struct *task); extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task); -extern int sve_set_vector_length(struct task_struct *task, +extern int vec_set_vector_length(struct task_struct *task, enum vec_type type, unsigned long vl, unsigned long flags); extern int sve_set_current_vl(unsigned long arg); diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 23e575c4e5804..4a98cc3b1df12 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -632,7 +632,7 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task) __fpsimd_to_sve(sst, fst, vq); } -int sve_set_vector_length(struct task_struct *task, +int vec_set_vector_length(struct task_struct *task, enum vec_type type, unsigned long vl, unsigned long flags) { if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | @@ -643,33 +643,35 @@ int sve_set_vector_length(struct task_struct *task, return -EINVAL; /* - * Clamp to the maximum vector length that VL-agnostic SVE code can - * work with. A flag may be assigned in the future to allow setting - * of larger vector lengths without confusing older software. + * Clamp to the maximum vector length that VL-agnostic code + * can work with. A flag may be assigned in the future to + * allow setting of larger vector lengths without confusing + * older software. */ - if (vl > SVE_VL_ARCH_MAX) - vl = SVE_VL_ARCH_MAX; + if (vl > VL_ARCH_MAX) + vl = VL_ARCH_MAX; - vl = find_supported_vector_length(ARM64_VEC_SVE, vl); + vl = find_supported_vector_length(type, vl); if (flags & (PR_SVE_VL_INHERIT | PR_SVE_SET_VL_ONEXEC)) - task_set_sve_vl_onexec(task, vl); + task_set_vl_onexec(task, type, vl); else /* Reset VL to system default on next exec: */ - task_set_sve_vl_onexec(task, 0); + task_set_vl_onexec(task, type, 0); /* Only actually set the VL if not deferred: */ if (flags & PR_SVE_SET_VL_ONEXEC) goto out; - if (vl == task_get_sve_vl(task)) + if (vl == task_get_vl(task, type)) goto out; /* * To ensure the FPSIMD bits of the SVE vector registers are preserved, * write any live register state back to task_struct, and convert to a - * non-SVE thread. + * regular FPSIMD thread. Since the vector length can only be changed + * with a syscall we can't be in streaming mode while reconfiguring. */ if (task == current) { get_cpu_fpsimd_context(); @@ -690,10 +692,10 @@ int sve_set_vector_length(struct task_struct *task, */ sve_free(task); - task_set_sve_vl(task, vl); + task_set_vl(task, type, vl); out: - update_tsk_thread_flag(task, TIF_SVE_VL_INHERIT, + update_tsk_thread_flag(task, vec_vl_inherit_flag(type), flags & PR_SVE_VL_INHERIT); return 0; @@ -701,20 +703,21 @@ out: /* * Encode the current vector length and flags for return. - * This is only required for prctl(): ptrace has separate fields + * This is only required for prctl(): ptrace has separate fields. + * SVE and SME use the same bits for _ONEXEC and _INHERIT. * - * flags are as for sve_set_vector_length(). + * flags are as for vec_set_vector_length(). */ -static int sve_prctl_status(unsigned long flags) +static int vec_prctl_status(enum vec_type type, unsigned long flags) { int ret; if (flags & PR_SVE_SET_VL_ONEXEC) - ret = task_get_sve_vl_onexec(current); + ret = task_get_vl_onexec(current, type); else - ret = task_get_sve_vl(current); + ret = task_get_vl(current, type); - if (test_thread_flag(TIF_SVE_VL_INHERIT)) + if (test_thread_flag(vec_vl_inherit_flag(type))) ret |= PR_SVE_VL_INHERIT; return ret; @@ -732,11 +735,11 @@ int sve_set_current_vl(unsigned long arg) if (!system_supports_sve() || is_compat_task()) return -EINVAL; - ret = sve_set_vector_length(current, vl, flags); + ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags); if (ret) return ret; - return sve_prctl_status(flags); + return vec_prctl_status(ARM64_VEC_SVE, flags); } /* PR_SVE_GET_VL */ @@ -745,7 +748,7 @@ int sve_get_current_vl(void) if (!system_supports_sve() || is_compat_task()) return -EINVAL; - return sve_prctl_status(0); + return vec_prctl_status(ARM64_VEC_SVE, 0); } static void vec_probe_vqs(struct vl_info *info, diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 88a9034fb9b50..716dde2894464 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -812,9 +812,9 @@ static int sve_set(struct task_struct *target, /* * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by - * sve_set_vector_length(), which will also validate them for us: + * vec_set_vector_length(), which will also validate them for us: */ - ret = sve_set_vector_length(target, header.vl, + ret = vec_set_vector_length(target, ARM64_VEC_SVE, header.vl, ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); if (ret) goto out; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 426bd7fbc3fd5..27386f0d81e45 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -52,10 +52,10 @@ int kvm_arm_init_sve(void) * The get_sve_reg()/set_sve_reg() ioctl interface will need * to be extended with multiple register slice support in * order to support vector lengths greater than - * SVE_VL_ARCH_MAX: + * VL_ARCH_MAX: */ - if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX)) - kvm_sve_max_vl = SVE_VL_ARCH_MAX; + if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX)) + kvm_sve_max_vl = VL_ARCH_MAX; /* * Don't even try to make use of vector lengths that @@ -103,7 +103,7 @@ static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) * set_sve_vls(). Double-check here just to be sure: */ if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() || - vl > SVE_VL_ARCH_MAX)) + vl > VL_ARCH_MAX)) return -EIO; buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL_ACCOUNT); -- GitLab From aed34d9e52b80b4e7485119272c77c5553a21499 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:40:59 +0000 Subject: [PATCH 561/965] arm64/sve: Minor clarification of ABI documentation As suggested by Luis for the SME version of this explicitly say that the vector length should be extracted from the return value of a set vector length prctl() with a bitwise and rather than just any old and. Suggested-by: Luis Machado Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-4-broonie@kernel.org Signed-off-by: Catalin Marinas --- Documentation/arm64/sve.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index 03137154299e5..9d9a4de5bc34a 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -255,7 +255,7 @@ prctl(PR_SVE_GET_VL) vector length change (which would only normally be the case between a fork() or vfork() and the corresponding execve() in typical use). - To extract the vector length from the result, and it with + To extract the vector length from the result, bitwise and it with PR_SVE_VL_LEN_MASK. Return value: a nonnegative value on success, or a negative value on error: -- GitLab From 18edbb6b3259332b577c2b92b6b4d8dfd86ff00e Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:41:00 +0000 Subject: [PATCH 562/965] kselftest/arm64: Parameterise ptrace vector length information SME introduces a new mode called streaming mode in which the SVE registers have a different vector length. Since the ptrace interface for this is based on the existing SVE interface prepare for supporting this by moving the regset specific configuration into struct and passing that around, allowing these tests to be reused for streaming mode. As we will also have to verify the interoperation of the SVE and streaming SVE regsets don't just iterate over an array. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-5-broonie@kernel.org Signed-off-by: Catalin Marinas --- tools/testing/selftests/arm64/fp/sve-ptrace.c | 219 ++++++++++++------ 1 file changed, 142 insertions(+), 77 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/sve-ptrace.c b/tools/testing/selftests/arm64/fp/sve-ptrace.c index c4417bc48d4f8..af798b9d232cc 100644 --- a/tools/testing/selftests/arm64/fp/sve-ptrace.c +++ b/tools/testing/selftests/arm64/fp/sve-ptrace.c @@ -21,16 +21,37 @@ #include "../../kselftest.h" -#define VL_TESTS (((SVE_VQ_MAX - SVE_VQ_MIN) + 1) * 3) -#define FPSIMD_TESTS 5 - -#define EXPECTED_TESTS (VL_TESTS + FPSIMD_TESTS) +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) /* and don't like each other, so: */ #ifndef NT_ARM_SVE #define NT_ARM_SVE 0x405 #endif +struct vec_type { + const char *name; + unsigned long hwcap_type; + unsigned long hwcap; + int regset; + int prctl_set; +}; + +static const struct vec_type vec_types[] = { + { + .name = "SVE", + .hwcap_type = AT_HWCAP, + .hwcap = HWCAP_SVE, + .regset = NT_ARM_SVE, + .prctl_set = PR_SVE_SET_VL, + }, +}; + +#define VL_TESTS (((SVE_VQ_MAX - SVE_VQ_MIN) + 1) * 3) +#define FLAG_TESTS 2 +#define FPSIMD_TESTS 3 + +#define EXPECTED_TESTS ((VL_TESTS + FLAG_TESTS + FPSIMD_TESTS) * ARRAY_SIZE(vec_types)) + static void fill_buf(char *buf, size_t size) { int i; @@ -59,7 +80,8 @@ static int get_fpsimd(pid_t pid, struct user_fpsimd_state *fpsimd) return ptrace(PTRACE_GETREGSET, pid, NT_PRFPREG, &iov); } -static struct user_sve_header *get_sve(pid_t pid, void **buf, size_t *size) +static struct user_sve_header *get_sve(pid_t pid, const struct vec_type *type, + void **buf, size_t *size) { struct user_sve_header *sve; void *p; @@ -80,7 +102,7 @@ static struct user_sve_header *get_sve(pid_t pid, void **buf, size_t *size) iov.iov_base = *buf; iov.iov_len = sz; - if (ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov)) + if (ptrace(PTRACE_GETREGSET, pid, type->regset, &iov)) goto error; sve = *buf; @@ -96,17 +118,18 @@ error: return NULL; } -static int set_sve(pid_t pid, const struct user_sve_header *sve) +static int set_sve(pid_t pid, const struct vec_type *type, + const struct user_sve_header *sve) { struct iovec iov; iov.iov_base = (void *)sve; iov.iov_len = sve->size; - return ptrace(PTRACE_SETREGSET, pid, NT_ARM_SVE, &iov); + return ptrace(PTRACE_SETREGSET, pid, type->regset, &iov); } /* Validate setting and getting the inherit flag */ -static void ptrace_set_get_inherit(pid_t child) +static void ptrace_set_get_inherit(pid_t child, const struct vec_type *type) { struct user_sve_header sve; struct user_sve_header *new_sve = NULL; @@ -118,9 +141,10 @@ static void ptrace_set_get_inherit(pid_t child) sve.size = sizeof(sve); sve.vl = sve_vl_from_vq(SVE_VQ_MIN); sve.flags = SVE_PT_VL_INHERIT; - ret = set_sve(child, &sve); + ret = set_sve(child, type, &sve); if (ret != 0) { - ksft_test_result_fail("Failed to set SVE_PT_VL_INHERIT\n"); + ksft_test_result_fail("Failed to set %s SVE_PT_VL_INHERIT\n", + type->name); return; } @@ -128,35 +152,39 @@ static void ptrace_set_get_inherit(pid_t child) * Read back the new register state and verify that we have * set the flags we expected. */ - if (!get_sve(child, (void **)&new_sve, &new_sve_size)) { - ksft_test_result_fail("Failed to read SVE flags\n"); + if (!get_sve(child, type, (void **)&new_sve, &new_sve_size)) { + ksft_test_result_fail("Failed to read %s SVE flags\n", + type->name); return; } ksft_test_result(new_sve->flags & SVE_PT_VL_INHERIT, - "SVE_PT_VL_INHERIT set\n"); + "%s SVE_PT_VL_INHERIT set\n", type->name); /* Now clear */ sve.flags &= ~SVE_PT_VL_INHERIT; - ret = set_sve(child, &sve); + ret = set_sve(child, type, &sve); if (ret != 0) { - ksft_test_result_fail("Failed to clear SVE_PT_VL_INHERIT\n"); + ksft_test_result_fail("Failed to clear %s SVE_PT_VL_INHERIT\n", + type->name); return; } - if (!get_sve(child, (void **)&new_sve, &new_sve_size)) { - ksft_test_result_fail("Failed to read SVE flags\n"); + if (!get_sve(child, type, (void **)&new_sve, &new_sve_size)) { + ksft_test_result_fail("Failed to read %s SVE flags\n", + type->name); return; } ksft_test_result(!(new_sve->flags & SVE_PT_VL_INHERIT), - "SVE_PT_VL_INHERIT cleared\n"); + "%s SVE_PT_VL_INHERIT cleared\n", type->name); free(new_sve); } /* Validate attempting to set the specfied VL via ptrace */ -static void ptrace_set_get_vl(pid_t child, unsigned int vl, bool *supported) +static void ptrace_set_get_vl(pid_t child, const struct vec_type *type, + unsigned int vl, bool *supported) { struct user_sve_header sve; struct user_sve_header *new_sve = NULL; @@ -166,10 +194,10 @@ static void ptrace_set_get_vl(pid_t child, unsigned int vl, bool *supported) *supported = false; /* Check if the VL is supported in this process */ - prctl_vl = prctl(PR_SVE_SET_VL, vl); + prctl_vl = prctl(type->prctl_set, vl); if (prctl_vl == -1) - ksft_exit_fail_msg("prctl(PR_SVE_SET_VL) failed: %s (%d)\n", - strerror(errno), errno); + ksft_exit_fail_msg("prctl(PR_%s_SET_VL) failed: %s (%d)\n", + type->name, strerror(errno), errno); /* If the VL is not supported then a supported VL will be returned */ *supported = (prctl_vl == vl); @@ -178,9 +206,10 @@ static void ptrace_set_get_vl(pid_t child, unsigned int vl, bool *supported) memset(&sve, 0, sizeof(sve)); sve.size = sizeof(sve); sve.vl = vl; - ret = set_sve(child, &sve); + ret = set_sve(child, type, &sve); if (ret != 0) { - ksft_test_result_fail("Failed to set VL %u\n", vl); + ksft_test_result_fail("Failed to set %s VL %u\n", + type->name, vl); return; } @@ -188,12 +217,14 @@ static void ptrace_set_get_vl(pid_t child, unsigned int vl, bool *supported) * Read back the new register state and verify that we have the * same VL that we got from prctl() on ourselves. */ - if (!get_sve(child, (void **)&new_sve, &new_sve_size)) { - ksft_test_result_fail("Failed to read VL %u\n", vl); + if (!get_sve(child, type, (void **)&new_sve, &new_sve_size)) { + ksft_test_result_fail("Failed to read %s VL %u\n", + type->name, vl); return; } - ksft_test_result(new_sve->vl = prctl_vl, "Set VL %u\n", vl); + ksft_test_result(new_sve->vl = prctl_vl, "Set %s VL %u\n", + type->name, vl); free(new_sve); } @@ -209,7 +240,7 @@ static void check_u32(unsigned int vl, const char *reg, } /* Access the FPSIMD registers via the SVE regset */ -static void ptrace_sve_fpsimd(pid_t child) +static void ptrace_sve_fpsimd(pid_t child, const struct vec_type *type) { void *svebuf = NULL; size_t svebufsz = 0; @@ -219,17 +250,18 @@ static void ptrace_sve_fpsimd(pid_t child) unsigned char *p; /* New process should start with FPSIMD registers only */ - sve = get_sve(child, &svebuf, &svebufsz); + sve = get_sve(child, type, &svebuf, &svebufsz); if (!sve) { - ksft_test_result_fail("get_sve: %s\n", strerror(errno)); + ksft_test_result_fail("get_sve(%s): %s\n", + type->name, strerror(errno)); return; } else { - ksft_test_result_pass("get_sve(FPSIMD)\n"); + ksft_test_result_pass("get_sve(%s FPSIMD)\n", type->name); } ksft_test_result((sve->flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD, - "Set FPSIMD registers\n"); + "Set FPSIMD registers via %s\n", type->name); if ((sve->flags & SVE_PT_REGS_MASK) != SVE_PT_REGS_FPSIMD) goto out; @@ -243,9 +275,9 @@ static void ptrace_sve_fpsimd(pid_t child) p[j] = j; } - if (set_sve(child, sve)) { - ksft_test_result_fail("set_sve(FPSIMD): %s\n", - strerror(errno)); + if (set_sve(child, type, sve)) { + ksft_test_result_fail("set_sve(%s FPSIMD): %s\n", + type->name, strerror(errno)); goto out; } @@ -257,16 +289,20 @@ static void ptrace_sve_fpsimd(pid_t child) goto out; } if (memcmp(fpsimd, &new_fpsimd, sizeof(*fpsimd)) == 0) - ksft_test_result_pass("get_fpsimd() gave same state\n"); + ksft_test_result_pass("%s get_fpsimd() gave same state\n", + type->name); else - ksft_test_result_fail("get_fpsimd() gave different state\n"); + ksft_test_result_fail("%s get_fpsimd() gave different state\n", + type->name); out: free(svebuf); } /* Validate attempting to set SVE data and read SVE data */ -static void ptrace_set_sve_get_sve_data(pid_t child, unsigned int vl) +static void ptrace_set_sve_get_sve_data(pid_t child, + const struct vec_type *type, + unsigned int vl) { void *write_buf; void *read_buf = NULL; @@ -281,8 +317,8 @@ static void ptrace_set_sve_get_sve_data(pid_t child, unsigned int vl) data_size = SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, SVE_PT_REGS_SVE); write_buf = malloc(data_size); if (!write_buf) { - ksft_test_result_fail("Error allocating %d byte buffer for VL %u\n", - data_size, vl); + ksft_test_result_fail("Error allocating %d byte buffer for %s VL %u\n", + data_size, type->name, vl); return; } write_sve = write_buf; @@ -306,23 +342,26 @@ static void ptrace_set_sve_get_sve_data(pid_t child, unsigned int vl) /* TODO: Generate a valid FFR pattern */ - ret = set_sve(child, write_sve); + ret = set_sve(child, type, write_sve); if (ret != 0) { - ksft_test_result_fail("Failed to set VL %u data\n", vl); + ksft_test_result_fail("Failed to set %s VL %u data\n", + type->name, vl); goto out; } /* Read the data back */ - if (!get_sve(child, (void **)&read_buf, &read_sve_size)) { - ksft_test_result_fail("Failed to read VL %u data\n", vl); + if (!get_sve(child, type, (void **)&read_buf, &read_sve_size)) { + ksft_test_result_fail("Failed to read %s VL %u data\n", + type->name, vl); goto out; } read_sve = read_buf; /* We might read more data if there's extensions we don't know */ if (read_sve->size < write_sve->size) { - ksft_test_result_fail("Wrote %d bytes, only read %d\n", - write_sve->size, read_sve->size); + ksft_test_result_fail("%s wrote %d bytes, only read %d\n", + type->name, write_sve->size, + read_sve->size); goto out_read; } @@ -349,7 +388,8 @@ static void ptrace_set_sve_get_sve_data(pid_t child, unsigned int vl) check_u32(vl, "FPCR", write_buf + SVE_PT_SVE_FPCR_OFFSET(vq), read_buf + SVE_PT_SVE_FPCR_OFFSET(vq), &errors); - ksft_test_result(errors == 0, "Set and get SVE data for VL %u\n", vl); + ksft_test_result(errors == 0, "Set and get %s data for VL %u\n", + type->name, vl); out_read: free(read_buf); @@ -358,7 +398,9 @@ out: } /* Validate attempting to set SVE data and read SVE data */ -static void ptrace_set_sve_get_fpsimd_data(pid_t child, unsigned int vl) +static void ptrace_set_sve_get_fpsimd_data(pid_t child, + const struct vec_type *type, + unsigned int vl) { void *write_buf; struct user_sve_header *write_sve; @@ -376,8 +418,8 @@ static void ptrace_set_sve_get_fpsimd_data(pid_t child, unsigned int vl) data_size = SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, SVE_PT_REGS_SVE); write_buf = malloc(data_size); if (!write_buf) { - ksft_test_result_fail("Error allocating %d byte buffer for VL %u\n", - data_size, vl); + ksft_test_result_fail("Error allocating %d byte buffer for %s VL %u\n", + data_size, type->name, vl); return; } write_sve = write_buf; @@ -395,16 +437,17 @@ static void ptrace_set_sve_get_fpsimd_data(pid_t child, unsigned int vl) fill_buf(write_buf + SVE_PT_SVE_FPSR_OFFSET(vq), SVE_PT_SVE_FPSR_SIZE); fill_buf(write_buf + SVE_PT_SVE_FPCR_OFFSET(vq), SVE_PT_SVE_FPCR_SIZE); - ret = set_sve(child, write_sve); + ret = set_sve(child, type, write_sve); if (ret != 0) { - ksft_test_result_fail("Failed to set VL %u data\n", vl); + ksft_test_result_fail("Failed to set %s VL %u data\n", + type->name, vl); goto out; } /* Read the data back */ if (get_fpsimd(child, &fpsimd_state)) { - ksft_test_result_fail("Failed to read VL %u FPSIMD data\n", - vl); + ksft_test_result_fail("Failed to read %s VL %u FPSIMD data\n", + type->name, vl); goto out; } @@ -419,7 +462,8 @@ static void ptrace_set_sve_get_fpsimd_data(pid_t child, unsigned int vl) sizeof(tmp)); if (tmp != fpsimd_state.vregs[i]) { - printf("# Mismatch in FPSIMD for VL %u Z%d\n", vl, i); + printf("# Mismatch in FPSIMD for %s VL %u Z%d\n", + type->name, vl, i); errors++; } } @@ -429,8 +473,8 @@ static void ptrace_set_sve_get_fpsimd_data(pid_t child, unsigned int vl) check_u32(vl, "FPCR", write_buf + SVE_PT_SVE_FPCR_OFFSET(vq), &fpsimd_state.fpcr, &errors); - ksft_test_result(errors == 0, "Set and get FPSIMD data for VL %u\n", - vl); + ksft_test_result(errors == 0, "Set and get FPSIMD data for %s VL %u\n", + type->name, vl); out: free(write_buf); @@ -440,7 +484,7 @@ static int do_parent(pid_t child) { int ret = EXIT_FAILURE; pid_t pid; - int status; + int status, i; siginfo_t si; unsigned int vq, vl; bool vl_supported; @@ -499,26 +543,47 @@ static int do_parent(pid_t child) } } - /* FPSIMD via SVE regset */ - ptrace_sve_fpsimd(child); - - /* prctl() flags */ - ptrace_set_get_inherit(child); - - /* Step through every possible VQ */ - for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) { - vl = sve_vl_from_vq(vq); + for (i = 0; i < ARRAY_SIZE(vec_types); i++) { + /* FPSIMD via SVE regset */ + if (getauxval(vec_types[i].hwcap_type) & vec_types[i].hwcap) { + ptrace_sve_fpsimd(child, &vec_types[i]); + } else { + ksft_test_result_skip("%s FPSIMD get via SVE\n", + vec_types[i].name); + ksft_test_result_skip("%s FPSIMD set via SVE\n", + vec_types[i].name); + ksft_test_result_skip("%s set read via FPSIMD\n", + vec_types[i].name); + } - /* First, try to set this vector length */ - ptrace_set_get_vl(child, vl, &vl_supported); + /* prctl() flags */ + ptrace_set_get_inherit(child, &vec_types[i]); + + /* Step through every possible VQ */ + for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) { + vl = sve_vl_from_vq(vq); + + /* First, try to set this vector length */ + if (getauxval(vec_types[i].hwcap_type) & + vec_types[i].hwcap) { + ptrace_set_get_vl(child, &vec_types[i], vl, + &vl_supported); + } else { + ksft_test_result_skip("%s get/set VL %d\n", + vec_types[i].name, vl); + vl_supported = false; + } - /* If the VL is supported validate data set/get */ - if (vl_supported) { - ptrace_set_sve_get_sve_data(child, vl); - ptrace_set_sve_get_fpsimd_data(child, vl); - } else { - ksft_test_result_skip("set SVE get SVE for VL %d\n", vl); - ksft_test_result_skip("set SVE get FPSIMD for VL %d\n", vl); + /* If the VL is supported validate data set/get */ + if (vl_supported) { + ptrace_set_sve_get_sve_data(child, &vec_types[i], vl); + ptrace_set_sve_get_fpsimd_data(child, &vec_types[i], vl); + } else { + ksft_test_result_skip("%s set SVE get SVE for VL %d\n", + vec_types[i].name, vl); + ksft_test_result_skip("%s set SVE get FPSIMD for VL %d\n", + vec_types[i].name, vl); + } } } -- GitLab From 9331a604858a0f399ef8f886a88dd94927f136aa Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:41:01 +0000 Subject: [PATCH 563/965] kselftest/arm64: Allow signal tests to trigger from a function Currently we have the facility to specify custom code to trigger a signal but none of the tests use it and for some reason the framework requires us to also specify a signal to send as a trigger in order to make use of a custom trigger. This doesn't seem to make much sense, instead allow the use of a custom trigger function without specifying a signal to inject. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-6-broonie@kernel.org Signed-off-by: Catalin Marinas --- .../selftests/arm64/signal/test_signals_utils.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.c b/tools/testing/selftests/arm64/signal/test_signals_utils.c index 22722abc9dfa9..2f8c23af3b5e0 100644 --- a/tools/testing/selftests/arm64/signal/test_signals_utils.c +++ b/tools/testing/selftests/arm64/signal/test_signals_utils.c @@ -310,14 +310,12 @@ int test_setup(struct tdescr *td) int test_run(struct tdescr *td) { - if (td->sig_trig) { - if (td->trigger) - return td->trigger(td); - else - return default_trigger(td); - } else { + if (td->trigger) + return td->trigger(td); + else if (td->sig_trig) + return default_trigger(td); + else return td->run(td, NULL, NULL); - } } void test_result(struct tdescr *td) -- GitLab From b77e995e3b9638e759d482e93deba1fa0760cb26 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2021 18:41:02 +0000 Subject: [PATCH 564/965] kselftest/arm64: Add a test program to exercise the syscall ABI Currently we don't have any coverage of the syscall ABI so let's add a very dumb test program which sets up register patterns, does a sysscall and then checks that the register state after the syscall matches what we expect. The program is written in an extremely simplistic fashion with the goal of making it easy to verify that it's doing what it thinks it's doing, it is not a model of how one should write actual code. Currently we validate the general purpose, FPSIMD and SVE registers. There are other thing things that could be covered like FPCR and flags registers, these can be covered incrementally - my main focus at the minute is covering the ABI for the SVE registers. The program repeats the tests for all possible SVE vector lengths in case some vector length specific optimisation causes issues, as well as testing FPSIMD only. It tries two syscalls, getpid() and sched_yield(), in an effort to cover both immediate return to userspace and scheduling another task though there are no guarantees which cases will be hit. A new test directory "abi" is added to hold the test, it doesn't seem to fit well into any of the existing directories. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211210184133.320748-7-broonie@kernel.org Signed-off-by: Catalin Marinas --- tools/testing/selftests/arm64/Makefile | 2 +- tools/testing/selftests/arm64/abi/.gitignore | 1 + tools/testing/selftests/arm64/abi/Makefile | 8 + .../selftests/arm64/abi/syscall-abi-asm.S | 240 +++++++++++++ .../testing/selftests/arm64/abi/syscall-abi.c | 318 ++++++++++++++++++ 5 files changed, 568 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/arm64/abi/.gitignore create mode 100644 tools/testing/selftests/arm64/abi/Makefile create mode 100644 tools/testing/selftests/arm64/abi/syscall-abi-asm.S create mode 100644 tools/testing/selftests/arm64/abi/syscall-abi.c diff --git a/tools/testing/selftests/arm64/Makefile b/tools/testing/selftests/arm64/Makefile index ced910fb40198..1e8d9a8f59df8 100644 --- a/tools/testing/selftests/arm64/Makefile +++ b/tools/testing/selftests/arm64/Makefile @@ -4,7 +4,7 @@ ARCH ?= $(shell uname -m 2>/dev/null || echo not) ifneq (,$(filter $(ARCH),aarch64 arm64)) -ARM64_SUBTARGETS ?= tags signal pauth fp mte bti +ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi else ARM64_SUBTARGETS := endif diff --git a/tools/testing/selftests/arm64/abi/.gitignore b/tools/testing/selftests/arm64/abi/.gitignore new file mode 100644 index 0000000000000..b79cf5814c230 --- /dev/null +++ b/tools/testing/selftests/arm64/abi/.gitignore @@ -0,0 +1 @@ +syscall-abi diff --git a/tools/testing/selftests/arm64/abi/Makefile b/tools/testing/selftests/arm64/abi/Makefile new file mode 100644 index 0000000000000..96eba974ac8d5 --- /dev/null +++ b/tools/testing/selftests/arm64/abi/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited + +TEST_GEN_PROGS := syscall-abi + +include ../../lib.mk + +$(OUTPUT)/syscall-abi: syscall-abi.c syscall-abi-asm.S diff --git a/tools/testing/selftests/arm64/abi/syscall-abi-asm.S b/tools/testing/selftests/arm64/abi/syscall-abi-asm.S new file mode 100644 index 0000000000000..983467cfcee0e --- /dev/null +++ b/tools/testing/selftests/arm64/abi/syscall-abi-asm.S @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2021 ARM Limited. +// +// Assembly portion of the syscall ABI test + +// +// Load values from memory into registers, invoke a syscall and save the +// register values back to memory for later checking. The syscall to be +// invoked is configured in x8 of the input GPR data. +// +// x0: SVE VL, 0 for FP only +// +// GPRs: gpr_in, gpr_out +// FPRs: fpr_in, fpr_out +// Zn: z_in, z_out +// Pn: p_in, p_out +// FFR: ffr_in, ffr_out + +.arch_extension sve + +.globl do_syscall +do_syscall: + // Store callee saved registers x19-x29 (80 bytes) plus x0 and x1 + stp x29, x30, [sp, #-112]! + mov x29, sp + stp x0, x1, [sp, #16] + stp x19, x20, [sp, #32] + stp x21, x22, [sp, #48] + stp x23, x24, [sp, #64] + stp x25, x26, [sp, #80] + stp x27, x28, [sp, #96] + + // Load GPRs x8-x28, and save our SP/FP for later comparison + ldr x2, =gpr_in + add x2, x2, #64 + ldp x8, x9, [x2], #16 + ldp x10, x11, [x2], #16 + ldp x12, x13, [x2], #16 + ldp x14, x15, [x2], #16 + ldp x16, x17, [x2], #16 + ldp x18, x19, [x2], #16 + ldp x20, x21, [x2], #16 + ldp x22, x23, [x2], #16 + ldp x24, x25, [x2], #16 + ldp x26, x27, [x2], #16 + ldr x28, [x2], #8 + str x29, [x2], #8 // FP + str x30, [x2], #8 // LR + + // Load FPRs if we're not doing SVE + cbnz x0, 1f + ldr x2, =fpr_in + ldp q0, q1, [x2] + ldp q2, q3, [x2, #16 * 2] + ldp q4, q5, [x2, #16 * 4] + ldp q6, q7, [x2, #16 * 6] + ldp q8, q9, [x2, #16 * 8] + ldp q10, q11, [x2, #16 * 10] + ldp q12, q13, [x2, #16 * 12] + ldp q14, q15, [x2, #16 * 14] + ldp q16, q17, [x2, #16 * 16] + ldp q18, q19, [x2, #16 * 18] + ldp q20, q21, [x2, #16 * 20] + ldp q22, q23, [x2, #16 * 22] + ldp q24, q25, [x2, #16 * 24] + ldp q26, q27, [x2, #16 * 26] + ldp q28, q29, [x2, #16 * 28] + ldp q30, q31, [x2, #16 * 30] +1: + + // Load the SVE registers if we're doing SVE + cbz x0, 1f + + ldr x2, =z_in + ldr z0, [x2, #0, MUL VL] + ldr z1, [x2, #1, MUL VL] + ldr z2, [x2, #2, MUL VL] + ldr z3, [x2, #3, MUL VL] + ldr z4, [x2, #4, MUL VL] + ldr z5, [x2, #5, MUL VL] + ldr z6, [x2, #6, MUL VL] + ldr z7, [x2, #7, MUL VL] + ldr z8, [x2, #8, MUL VL] + ldr z9, [x2, #9, MUL VL] + ldr z10, [x2, #10, MUL VL] + ldr z11, [x2, #11, MUL VL] + ldr z12, [x2, #12, MUL VL] + ldr z13, [x2, #13, MUL VL] + ldr z14, [x2, #14, MUL VL] + ldr z15, [x2, #15, MUL VL] + ldr z16, [x2, #16, MUL VL] + ldr z17, [x2, #17, MUL VL] + ldr z18, [x2, #18, MUL VL] + ldr z19, [x2, #19, MUL VL] + ldr z20, [x2, #20, MUL VL] + ldr z21, [x2, #21, MUL VL] + ldr z22, [x2, #22, MUL VL] + ldr z23, [x2, #23, MUL VL] + ldr z24, [x2, #24, MUL VL] + ldr z25, [x2, #25, MUL VL] + ldr z26, [x2, #26, MUL VL] + ldr z27, [x2, #27, MUL VL] + ldr z28, [x2, #28, MUL VL] + ldr z29, [x2, #29, MUL VL] + ldr z30, [x2, #30, MUL VL] + ldr z31, [x2, #31, MUL VL] + + ldr x2, =ffr_in + ldr p0, [x2, #0] + wrffr p0.b + + ldr x2, =p_in + ldr p0, [x2, #0, MUL VL] + ldr p1, [x2, #1, MUL VL] + ldr p2, [x2, #2, MUL VL] + ldr p3, [x2, #3, MUL VL] + ldr p4, [x2, #4, MUL VL] + ldr p5, [x2, #5, MUL VL] + ldr p6, [x2, #6, MUL VL] + ldr p7, [x2, #7, MUL VL] + ldr p8, [x2, #8, MUL VL] + ldr p9, [x2, #9, MUL VL] + ldr p10, [x2, #10, MUL VL] + ldr p11, [x2, #11, MUL VL] + ldr p12, [x2, #12, MUL VL] + ldr p13, [x2, #13, MUL VL] + ldr p14, [x2, #14, MUL VL] + ldr p15, [x2, #15, MUL VL] +1: + + // Do the syscall + svc #0 + + // Save GPRs x8-x30 + ldr x2, =gpr_out + add x2, x2, #64 + stp x8, x9, [x2], #16 + stp x10, x11, [x2], #16 + stp x12, x13, [x2], #16 + stp x14, x15, [x2], #16 + stp x16, x17, [x2], #16 + stp x18, x19, [x2], #16 + stp x20, x21, [x2], #16 + stp x22, x23, [x2], #16 + stp x24, x25, [x2], #16 + stp x26, x27, [x2], #16 + stp x28, x29, [x2], #16 + str x30, [x2] + + // Restore x0 and x1 for feature checks + ldp x0, x1, [sp, #16] + + // Save FPSIMD state + ldr x2, =fpr_out + stp q0, q1, [x2] + stp q2, q3, [x2, #16 * 2] + stp q4, q5, [x2, #16 * 4] + stp q6, q7, [x2, #16 * 6] + stp q8, q9, [x2, #16 * 8] + stp q10, q11, [x2, #16 * 10] + stp q12, q13, [x2, #16 * 12] + stp q14, q15, [x2, #16 * 14] + stp q16, q17, [x2, #16 * 16] + stp q18, q19, [x2, #16 * 18] + stp q20, q21, [x2, #16 * 20] + stp q22, q23, [x2, #16 * 22] + stp q24, q25, [x2, #16 * 24] + stp q26, q27, [x2, #16 * 26] + stp q28, q29, [x2, #16 * 28] + stp q30, q31, [x2, #16 * 30] + + // Save the SVE state if we have some + cbz x0, 1f + + ldr x2, =z_out + str z0, [x2, #0, MUL VL] + str z1, [x2, #1, MUL VL] + str z2, [x2, #2, MUL VL] + str z3, [x2, #3, MUL VL] + str z4, [x2, #4, MUL VL] + str z5, [x2, #5, MUL VL] + str z6, [x2, #6, MUL VL] + str z7, [x2, #7, MUL VL] + str z8, [x2, #8, MUL VL] + str z9, [x2, #9, MUL VL] + str z10, [x2, #10, MUL VL] + str z11, [x2, #11, MUL VL] + str z12, [x2, #12, MUL VL] + str z13, [x2, #13, MUL VL] + str z14, [x2, #14, MUL VL] + str z15, [x2, #15, MUL VL] + str z16, [x2, #16, MUL VL] + str z17, [x2, #17, MUL VL] + str z18, [x2, #18, MUL VL] + str z19, [x2, #19, MUL VL] + str z20, [x2, #20, MUL VL] + str z21, [x2, #21, MUL VL] + str z22, [x2, #22, MUL VL] + str z23, [x2, #23, MUL VL] + str z24, [x2, #24, MUL VL] + str z25, [x2, #25, MUL VL] + str z26, [x2, #26, MUL VL] + str z27, [x2, #27, MUL VL] + str z28, [x2, #28, MUL VL] + str z29, [x2, #29, MUL VL] + str z30, [x2, #30, MUL VL] + str z31, [x2, #31, MUL VL] + + ldr x2, =p_out + str p0, [x2, #0, MUL VL] + str p1, [x2, #1, MUL VL] + str p2, [x2, #2, MUL VL] + str p3, [x2, #3, MUL VL] + str p4, [x2, #4, MUL VL] + str p5, [x2, #5, MUL VL] + str p6, [x2, #6, MUL VL] + str p7, [x2, #7, MUL VL] + str p8, [x2, #8, MUL VL] + str p9, [x2, #9, MUL VL] + str p10, [x2, #10, MUL VL] + str p11, [x2, #11, MUL VL] + str p12, [x2, #12, MUL VL] + str p13, [x2, #13, MUL VL] + str p14, [x2, #14, MUL VL] + str p15, [x2, #15, MUL VL] + + ldr x2, =ffr_out + rdffr p0.b + str p0, [x2, #0] +1: + + // Restore callee saved registers x19-x30 + ldp x19, x20, [sp, #32] + ldp x21, x22, [sp, #48] + ldp x23, x24, [sp, #64] + ldp x25, x26, [sp, #80] + ldp x27, x28, [sp, #96] + ldp x29, x30, [sp], #112 + + ret diff --git a/tools/testing/selftests/arm64/abi/syscall-abi.c b/tools/testing/selftests/arm64/abi/syscall-abi.c new file mode 100644 index 0000000000000..d8eeeafb50dcb --- /dev/null +++ b/tools/testing/selftests/arm64/abi/syscall-abi.c @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 ARM Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../kselftest.h" + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) +#define NUM_VL ((SVE_VQ_MAX - SVE_VQ_MIN) + 1) + +extern void do_syscall(int sve_vl); + +static void fill_random(void *buf, size_t size) +{ + int i; + uint32_t *lbuf = buf; + + /* random() returns a 32 bit number regardless of the size of long */ + for (i = 0; i < size / sizeof(uint32_t); i++) + lbuf[i] = random(); +} + +/* + * We also repeat the test for several syscalls to try to expose different + * behaviour. + */ +static struct syscall_cfg { + int syscall_nr; + const char *name; +} syscalls[] = { + { __NR_getpid, "getpid()" }, + { __NR_sched_yield, "sched_yield()" }, +}; + +#define NUM_GPR 31 +uint64_t gpr_in[NUM_GPR]; +uint64_t gpr_out[NUM_GPR]; + +static void setup_gpr(struct syscall_cfg *cfg, int sve_vl) +{ + fill_random(gpr_in, sizeof(gpr_in)); + gpr_in[8] = cfg->syscall_nr; + memset(gpr_out, 0, sizeof(gpr_out)); +} + +static int check_gpr(struct syscall_cfg *cfg, int sve_vl) +{ + int errors = 0; + int i; + + /* + * GPR x0-x7 may be clobbered, and all others should be preserved. + */ + for (i = 9; i < ARRAY_SIZE(gpr_in); i++) { + if (gpr_in[i] != gpr_out[i]) { + ksft_print_msg("%s SVE VL %d mismatch in GPR %d: %llx != %llx\n", + cfg->name, sve_vl, i, + gpr_in[i], gpr_out[i]); + errors++; + } + } + + return errors; +} + +#define NUM_FPR 32 +uint64_t fpr_in[NUM_FPR * 2]; +uint64_t fpr_out[NUM_FPR * 2]; + +static void setup_fpr(struct syscall_cfg *cfg, int sve_vl) +{ + fill_random(fpr_in, sizeof(fpr_in)); + memset(fpr_out, 0, sizeof(fpr_out)); +} + +static int check_fpr(struct syscall_cfg *cfg, int sve_vl) +{ + int errors = 0; + int i; + + if (!sve_vl) { + for (i = 0; i < ARRAY_SIZE(fpr_in); i++) { + if (fpr_in[i] != fpr_out[i]) { + ksft_print_msg("%s Q%d/%d mismatch %llx != %llx\n", + cfg->name, + i / 2, i % 2, + fpr_in[i], fpr_out[i]); + errors++; + } + } + } + + return errors; +} + +static uint8_t z_zero[__SVE_ZREG_SIZE(SVE_VQ_MAX)]; +uint8_t z_in[SVE_NUM_PREGS * __SVE_ZREG_SIZE(SVE_VQ_MAX)]; +uint8_t z_out[SVE_NUM_PREGS * __SVE_ZREG_SIZE(SVE_VQ_MAX)]; + +static void setup_z(struct syscall_cfg *cfg, int sve_vl) +{ + fill_random(z_in, sizeof(z_in)); + fill_random(z_out, sizeof(z_out)); +} + +static int check_z(struct syscall_cfg *cfg, int sve_vl) +{ + size_t reg_size = sve_vl; + int errors = 0; + int i; + + if (!sve_vl) + return 0; + + /* + * After a syscall the low 128 bits of the Z registers should + * be preserved and the rest be zeroed or preserved. + */ + for (i = 0; i < SVE_NUM_ZREGS; i++) { + void *in = &z_in[reg_size * i]; + void *out = &z_out[reg_size * i]; + + if (memcmp(in, out, SVE_VQ_BYTES) != 0) { + ksft_print_msg("%s SVE VL %d Z%d low 128 bits changed\n", + cfg->name, sve_vl, i); + errors++; + } + } + + return errors; +} + +uint8_t p_in[SVE_NUM_PREGS * __SVE_PREG_SIZE(SVE_VQ_MAX)]; +uint8_t p_out[SVE_NUM_PREGS * __SVE_PREG_SIZE(SVE_VQ_MAX)]; + +static void setup_p(struct syscall_cfg *cfg, int sve_vl) +{ + fill_random(p_in, sizeof(p_in)); + fill_random(p_out, sizeof(p_out)); +} + +static int check_p(struct syscall_cfg *cfg, int sve_vl) +{ + size_t reg_size = sve_vq_from_vl(sve_vl) * 2; /* 1 bit per VL byte */ + + int errors = 0; + int i; + + if (!sve_vl) + return 0; + + /* After a syscall the P registers should be preserved or zeroed */ + for (i = 0; i < SVE_NUM_PREGS * reg_size; i++) + if (p_out[i] && (p_in[i] != p_out[i])) + errors++; + if (errors) + ksft_print_msg("%s SVE VL %d predicate registers non-zero\n", + cfg->name, sve_vl); + + return errors; +} + +uint8_t ffr_in[__SVE_PREG_SIZE(SVE_VQ_MAX)]; +uint8_t ffr_out[__SVE_PREG_SIZE(SVE_VQ_MAX)]; + +static void setup_ffr(struct syscall_cfg *cfg, int sve_vl) +{ + /* + * It is only valid to set a contiguous set of bits starting + * at 0. For now since we're expecting this to be cleared by + * a syscall just set all bits. + */ + memset(ffr_in, 0xff, sizeof(ffr_in)); + fill_random(ffr_out, sizeof(ffr_out)); +} + +static int check_ffr(struct syscall_cfg *cfg, int sve_vl) +{ + size_t reg_size = sve_vq_from_vl(sve_vl) * 2; /* 1 bit per VL byte */ + int errors = 0; + int i; + + if (!sve_vl) + return 0; + + /* After a syscall the P registers should be preserved or zeroed */ + for (i = 0; i < reg_size; i++) + if (ffr_out[i] && (ffr_in[i] != ffr_out[i])) + errors++; + if (errors) + ksft_print_msg("%s SVE VL %d FFR non-zero\n", + cfg->name, sve_vl); + + return errors; +} + +typedef void (*setup_fn)(struct syscall_cfg *cfg, int sve_vl); +typedef int (*check_fn)(struct syscall_cfg *cfg, int sve_vl); + +/* + * Each set of registers has a setup function which is called before + * the syscall to fill values in a global variable for loading by the + * test code and a check function which validates that the results are + * as expected. Vector lengths are passed everywhere, a vector length + * of 0 should be treated as do not test. + */ +static struct { + setup_fn setup; + check_fn check; +} regset[] = { + { setup_gpr, check_gpr }, + { setup_fpr, check_fpr }, + { setup_z, check_z }, + { setup_p, check_p }, + { setup_ffr, check_ffr }, +}; + +static bool do_test(struct syscall_cfg *cfg, int sve_vl) +{ + int errors = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(regset); i++) + regset[i].setup(cfg, sve_vl); + + do_syscall(sve_vl); + + for (i = 0; i < ARRAY_SIZE(regset); i++) + errors += regset[i].check(cfg, sve_vl); + + return errors == 0; +} + +static void test_one_syscall(struct syscall_cfg *cfg) +{ + int sve_vq, sve_vl; + + /* FPSIMD only case */ + ksft_test_result(do_test(cfg, 0), + "%s FPSIMD\n", cfg->name); + + if (!(getauxval(AT_HWCAP) & HWCAP_SVE)) + return; + + for (sve_vq = SVE_VQ_MAX; sve_vq > 0; --sve_vq) { + sve_vl = prctl(PR_SVE_SET_VL, sve_vq * 16); + if (sve_vl == -1) + ksft_exit_fail_msg("PR_SVE_SET_VL failed: %s (%d)\n", + strerror(errno), errno); + + sve_vl &= PR_SVE_VL_LEN_MASK; + + if (sve_vq != sve_vq_from_vl(sve_vl)) + sve_vq = sve_vq_from_vl(sve_vl); + + ksft_test_result(do_test(cfg, sve_vl), + "%s SVE VL %d\n", cfg->name, sve_vl); + } +} + +int sve_count_vls(void) +{ + unsigned int vq; + int vl_count = 0; + int vl; + + if (!(getauxval(AT_HWCAP) & HWCAP_SVE)) + return 0; + + /* + * Enumerate up to SVE_VQ_MAX vector lengths + */ + for (vq = SVE_VQ_MAX; vq > 0; --vq) { + vl = prctl(PR_SVE_SET_VL, vq * 16); + if (vl == -1) + ksft_exit_fail_msg("PR_SVE_SET_VL failed: %s (%d)\n", + strerror(errno), errno); + + vl &= PR_SVE_VL_LEN_MASK; + + if (vq != sve_vq_from_vl(vl)) + vq = sve_vq_from_vl(vl); + + vl_count++; + } + + return vl_count; +} + +int main(void) +{ + int i; + + srandom(getpid()); + + ksft_print_header(); + ksft_set_plan(ARRAY_SIZE(syscalls) * (sve_count_vls() + 1)); + + for (i = 0; i < ARRAY_SIZE(syscalls); i++) + test_one_syscall(&syscalls[i]); + + ksft_print_cnts(); + + return 0; +} -- GitLab From 12b792e5e2344772434ea817572bedde8ad9c172 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 7 Dec 2021 16:32:50 +0000 Subject: [PATCH 565/965] arm64/fp: Add comments documenting the usage of state restore functions Add comments to help people figure out when fpsimd_bind_state_to_cpu() and fpsimd_update_current_state() are used. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211207163250.1373542-1-broonie@kernel.org Signed-off-by: Catalin Marinas --- arch/arm64/kernel/fpsimd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index fa244c426f610..aad59051b3b76 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1213,7 +1213,8 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, /* * Load the userland FPSIMD state of 'current' from memory, but only if the * FPSIMD state already held in the registers is /not/ the most recent FPSIMD - * state of 'current' + * state of 'current'. This is called when we are preparing to return to + * userspace to ensure that userspace sees a good register state. */ void fpsimd_restore_current_state(void) { @@ -1244,7 +1245,9 @@ void fpsimd_restore_current_state(void) /* * Load an updated userland FPSIMD state for 'current' from memory and set the * flag that indicates that the FPSIMD register contents are the most recent - * FPSIMD state of 'current' + * FPSIMD state of 'current'. This is used by the signal code to restore the + * register state when returning from a signal handler in FPSIMD only cases, + * any SVE context will be discarded. */ void fpsimd_update_current_state(struct user_fpsimd_state const *state) { -- GitLab From 2c94ebedc844d64459bfe73b25ae725c3f040526 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Dec 2021 16:51:07 +0000 Subject: [PATCH 566/965] kselftest/arm64: Add pidbench for floating point syscall cases Since it's likely to be useful for performance work with SVE let's have a pidbench that gives us some numbers for consideration. In order to ensure that we test exactly the scenario we want this is written in assembly - if system libraries use SVE this would stop us exercising the case where the process has never used SVE. We exercise three cases: - Never having used SVE. - Having used SVE once. - Using SVE after each syscall. by spinning running getpid() for a fixed number of iterations with the time measured using CNTVCT_EL0 reported on the console. This is obviously a totally unrealistic benchmark which will show the extremes of any performance variation but equally given the potential gotchas with use of FP instructions by system libraries it's good to have some concrete code shared to make it easier to compare notes on results. Testing over multiple SVE vector lengths will need to be done with vlset currently, the test could be extended to iterate over all of them if desired. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20211202165107.1075259-1-broonie@kernel.org Signed-off-by: Catalin Marinas --- tools/testing/selftests/arm64/fp/.gitignore | 1 + tools/testing/selftests/arm64/fp/Makefile | 4 +- .../testing/selftests/arm64/fp/fp-pidbench.S | 71 +++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/arm64/fp/fp-pidbench.S diff --git a/tools/testing/selftests/arm64/fp/.gitignore b/tools/testing/selftests/arm64/fp/.gitignore index b67395903b9bb..c50d86331ed2f 100644 --- a/tools/testing/selftests/arm64/fp/.gitignore +++ b/tools/testing/selftests/arm64/fp/.gitignore @@ -1,3 +1,4 @@ +fp-pidbench fpsimd-test rdvl-sve sve-probe-vls diff --git a/tools/testing/selftests/arm64/fp/Makefile b/tools/testing/selftests/arm64/fp/Makefile index ba1488c7c3153..95f0b877a060b 100644 --- a/tools/testing/selftests/arm64/fp/Makefile +++ b/tools/testing/selftests/arm64/fp/Makefile @@ -2,13 +2,15 @@ CFLAGS += -I../../../../../usr/include/ TEST_GEN_PROGS := sve-ptrace sve-probe-vls vec-syscfg -TEST_PROGS_EXTENDED := fpsimd-test fpsimd-stress \ +TEST_PROGS_EXTENDED := fp-pidbench fpsimd-test fpsimd-stress \ rdvl-sve \ sve-test sve-stress \ vlset all: $(TEST_GEN_PROGS) $(TEST_PROGS_EXTENDED) +fp-pidbench: fp-pidbench.S asm-utils.o + $(CC) -nostdlib $^ -o $@ fpsimd-test: fpsimd-test.o asm-utils.o $(CC) -nostdlib $^ -o $@ rdvl-sve: rdvl-sve.o rdvl.o diff --git a/tools/testing/selftests/arm64/fp/fp-pidbench.S b/tools/testing/selftests/arm64/fp/fp-pidbench.S new file mode 100644 index 0000000000000..16a436389bfcd --- /dev/null +++ b/tools/testing/selftests/arm64/fp/fp-pidbench.S @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2021 ARM Limited. +// Original author: Mark Brown +// +// Trivial syscall overhead benchmark. +// +// This is implemented in asm to ensure that we don't have any issues with +// system libraries using instructions that disrupt the test. + +#include +#include "assembler.h" + +.arch_extension sve + +.macro test_loop per_loop + mov x10, x20 + mov x8, #__NR_getpid + mrs x11, CNTVCT_EL0 +1: + \per_loop + svc #0 + sub x10, x10, #1 + cbnz x10, 1b + + mrs x12, CNTVCT_EL0 + sub x0, x12, x11 + bl putdec + puts "\n" +.endm + +// Main program entry point +.globl _start +function _start +_start: + puts "Iterations per test: " + mov x20, #10000 + lsl x20, x20, #8 + mov x0, x20 + bl putdec + puts "\n" + + // Test having never used SVE + puts "No SVE: " + test_loop + + // Check for SVE support - should use hwcap but that's hard in asm + mrs x0, ID_AA64PFR0_EL1 + ubfx x0, x0, #32, #4 + cbnz x0, 1f + puts "System does not support SVE\n" + b out +1: + + // Execute a SVE instruction + puts "SVE VL: " + rdvl x0, #8 + bl putdec + puts "\n" + + puts "SVE used once: " + test_loop + + // Use SVE per syscall + puts "SVE used per syscall: " + test_loop "rdvl x0, #8" + + // And we're done +out: + mov x0, #0 + mov x8, #__NR_exit + svc #0 -- GitLab From dd03762ab608e058c8f390ad9cf667e490089796 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Sat, 11 Dec 2021 21:17:34 +0800 Subject: [PATCH 567/965] arm64: Enable KCSAN This patch enables KCSAN for arm64, with updates to build rules to not use KCSAN for several incompatible compilation units. Recent GCC version(at least GCC10) made outline-atomics as the default option(unlike Clang), which will cause linker errors for kernel/kcsan/core.o. Disables the out-of-line atomics by no-outline-atomics to fix the linker errors. Meanwhile, as Mark said[1], some latent issues are needed to be fixed which isn't just a KCSAN problem, we make the KCSAN depends on EXPERT for now. Tested selftest and kcsan_test(built with GCC11 and Clang 13), and all passed. [1] https://lkml.kernel.org/r/YadiUPpJ0gADbiHQ@FVFF77S0Q05N Acked-by: Marco Elver # kernel/kcsan Tested-by: Joey Gouly Signed-off-by: Kefeng Wang Link: https://lore.kernel.org/r/20211211131734.126874-1-wangkefeng.wang@huawei.com [catalin.marinas@arm.com: added comment to justify EXPERT] Signed-off-by: Catalin Marinas --- arch/arm64/Kconfig | 2 ++ arch/arm64/kernel/vdso/Makefile | 1 + arch/arm64/kvm/hyp/nvhe/Makefile | 1 + kernel/kcsan/Makefile | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c4207cf9bb17f..1d98e935c4d6c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -150,6 +150,8 @@ config ARM64 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) + # Some instrumentation may be unsound, hence EXPERT + select HAVE_ARCH_KCSAN if EXPERT select HAVE_ARCH_KFENCE select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile index 700767dfd221e..60813497a3815 100644 --- a/arch/arm64/kernel/vdso/Makefile +++ b/arch/arm64/kernel/vdso/Makefile @@ -32,6 +32,7 @@ ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os $(CC_FLAGS_SCS) $(GCC_PLUGINS_CFLAGS) \ $(CC_FLAGS_LTO) KASAN_SANITIZE := n +KCSAN_SANITIZE := n UBSAN_SANITIZE := n OBJECT_FILES_NON_STANDARD := y KCOV_INSTRUMENT := n diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile index c3c11974fa3b3..24b2c2425b384 100644 --- a/arch/arm64/kvm/hyp/nvhe/Makefile +++ b/arch/arm64/kvm/hyp/nvhe/Makefile @@ -89,6 +89,7 @@ KBUILD_CFLAGS := $(filter-out $(CC_FLAGS_FTRACE) $(CC_FLAGS_SCS) $(CC_FLAGS_CFI) # cause crashes. Just disable it. GCOV_PROFILE := n KASAN_SANITIZE := n +KCSAN_SANITIZE := n UBSAN_SANITIZE := n KCOV_INSTRUMENT := n diff --git a/kernel/kcsan/Makefile b/kernel/kcsan/Makefile index c2bb07f5bcc72..e893b0e1d62a8 100644 --- a/kernel/kcsan/Makefile +++ b/kernel/kcsan/Makefile @@ -8,6 +8,7 @@ CFLAGS_REMOVE_debugfs.o = $(CC_FLAGS_FTRACE) CFLAGS_REMOVE_report.o = $(CC_FLAGS_FTRACE) CFLAGS_core.o := $(call cc-option,-fno-conserve-stack) \ + $(call cc-option,-mno-outline-atomics) \ -fno-stack-protector -DDISABLE_BRANCH_PROFILING obj-y := core.o debugfs.o report.o -- GitLab From f2cefc0c2d2a0baf5be40388371c289c41db01b9 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Thu, 9 Dec 2021 17:19:22 +0800 Subject: [PATCH 568/965] docs/arm64: delete a space from tagged-address-abi Since e71e2ace5721("userfaultfd: do not untag user pointers") which introduced a warning: linux/Documentation/arm64/tagged-address-abi.rst:52: WARNING: Unexpected indentation. Let's fix it. Signed-off-by: Yanteng Si Link: https://lore.kernel.org/r/20211209091922.560979-1-siyanteng@loongson.cn Signed-off-by: Catalin Marinas --- Documentation/arm64/tagged-address-abi.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arm64/tagged-address-abi.rst b/Documentation/arm64/tagged-address-abi.rst index 0c9120ec58ae6..540a1d4fc6c9e 100644 --- a/Documentation/arm64/tagged-address-abi.rst +++ b/Documentation/arm64/tagged-address-abi.rst @@ -49,7 +49,7 @@ how the user addresses are used by the kernel: - ``brk()``, ``mmap()`` and the ``new_address`` argument to ``mremap()`` as these have the potential to alias with existing - user addresses. + user addresses. NOTE: This behaviour changed in v5.6 and so some earlier kernels may incorrectly accept valid tagged pointers for the ``brk()``, -- GitLab From 8c4e1b1617bba39658c46449ad480b2bf4b9ff6f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 6 Dec 2021 02:11:58 +0100 Subject: [PATCH 569/965] ARM: configs: gemini: Activate crypto driver This enables the SL3516 crypto driver on the Gemini platforms where it is available, by default in the defconfig. Clean up some noise around the crypto options while we're at it. Signed-off-by: Linus Walleij Cc: Corentin Labbe Link: https://lore.kernel.org/r/20211206011158.4180141-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann --- arch/arm/configs/gemini_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig index e6ff844821cfb..a7acfee11ffcb 100644 --- a/arch/arm/configs/gemini_defconfig +++ b/arch/arm/configs/gemini_defconfig @@ -63,7 +63,6 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_RUNTIME_UARTS=1 CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_GPIO=y @@ -99,5 +98,5 @@ CONFIG_TMPFS_POSIX_ACL=y CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_CRYPTO_DEV_SL3516=y CONFIG_DEBUG_FS=y -- GitLab From 8f8ef3860d4403d1bf0887380f9e3376be092c40 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Mon, 6 Dec 2021 23:32:49 -0800 Subject: [PATCH 570/965] dt-bindings: clock: Add SDX65 GCC clock bindings Add device tree bindings for global clock controller on SDX65 SOCs. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com --- .../bindings/clock/qcom,gcc-sdx65.yaml | 80 ++++++++++++ include/dt-bindings/clock/qcom,gcc-sdx65.h | 122 ++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx65.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 0000000000000..16c4cdc7b4d63 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 + +maintainers: + - Vamsi krishna Lanka + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX65 + + See also: + - dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + - description: PLL test clock source (Optional clock) + minItems: 5 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + - const: core_bi_pll_test_se # Optional clock + minItems: 5 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-sdx65.h b/include/dt-bindings/clock/qcom,gcc-sdx65.h new file mode 100644 index 0000000000000..75ecc9237d8f1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx65.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GCC_AHB_PCIE_LINK_CLK 2 +#define GCC_BLSP1_AHB_CLK 3 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_BLSP1_UART4_APPS_CLK 27 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 28 +#define GCC_BOOT_ROM_AHB_CLK 29 +#define GCC_CPUSS_AHB_CLK 30 +#define GCC_CPUSS_AHB_CLK_SRC 31 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 +#define GCC_CPUSS_GNOC_CLK 33 +#define GCC_GP1_CLK 34 +#define GCC_GP1_CLK_SRC 35 +#define GCC_GP2_CLK 36 +#define GCC_GP2_CLK_SRC 37 +#define GCC_GP3_CLK 38 +#define GCC_GP3_CLK_SRC 39 +#define GCC_PCIE_0_CLKREF_EN 40 +#define GCC_PCIE_AUX_CLK 41 +#define GCC_PCIE_AUX_CLK_SRC 42 +#define GCC_PCIE_AUX_PHY_CLK_SRC 43 +#define GCC_PCIE_CFG_AHB_CLK 44 +#define GCC_PCIE_MSTR_AXI_CLK 45 +#define GCC_PCIE_PIPE_CLK 46 +#define GCC_PCIE_PIPE_CLK_SRC 47 +#define GCC_PCIE_RCHNG_PHY_CLK 48 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 +#define GCC_PCIE_SLEEP_CLK 50 +#define GCC_PCIE_SLV_AXI_CLK 51 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 52 +#define GCC_PDM2_CLK 53 +#define GCC_PDM2_CLK_SRC 54 +#define GCC_PDM_AHB_CLK 55 +#define GCC_PDM_XO4_CLK 56 +#define GCC_RX1_USB2_CLKREF_EN 57 +#define GCC_SDCC1_AHB_CLK 58 +#define GCC_SDCC1_APPS_CLK 59 +#define GCC_SDCC1_APPS_CLK_SRC 60 +#define GCC_SPMI_FETCHER_AHB_CLK 61 +#define GCC_SPMI_FETCHER_CLK 62 +#define GCC_SPMI_FETCHER_CLK_SRC 63 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 64 +#define GCC_USB30_MASTER_CLK 65 +#define GCC_USB30_MASTER_CLK_SRC 66 +#define GCC_USB30_MOCK_UTMI_CLK 67 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 68 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define GCC_USB30_MSTR_AXI_CLK 70 +#define GCC_USB30_SLEEP_CLK 71 +#define GCC_USB30_SLV_AHB_CLK 72 +#define GCC_USB3_PHY_AUX_CLK 73 +#define GCC_USB3_PHY_AUX_CLK_SRC 74 +#define GCC_USB3_PHY_PIPE_CLK 75 +#define GCC_USB3_PHY_PIPE_CLK_SRC 76 +#define GCC_USB3_PRIM_CLKREF_EN 77 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 +#define GCC_XO_DIV4_CLK 79 +#define GCC_XO_PCIE_LINK_CLK 80 + +/* GCC resets */ +#define GCC_BLSP1_QUP1_BCR 0 +#define GCC_BLSP1_QUP2_BCR 1 +#define GCC_BLSP1_QUP3_BCR 2 +#define GCC_BLSP1_QUP4_BCR 3 +#define GCC_BLSP1_UART1_BCR 4 +#define GCC_BLSP1_UART2_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_UART4_BCR 7 +#define GCC_PCIE_BCR 8 +#define GCC_PCIE_LINK_DOWN_BCR 9 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_PHY_BCR 11 +#define GCC_PCIE_PHY_CFG_AHB_BCR 12 +#define GCC_PCIE_PHY_COM_BCR 13 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 +#define GCC_PDM_BCR 15 +#define GCC_QUSB2PHY_BCR 16 +#define GCC_SDCC1_BCR 17 +#define GCC_SPMI_FETCHER_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 + +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 + +#endif -- GitLab From 3b338c9a6a2afd6db46d5d8e39ae4f5eef420bf8 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:03 -0700 Subject: [PATCH 571/965] dt-bindings: arm: qcom: Document SDX65 platform and boards Document the SDX65 platform binding and also the boards using it. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-2-git-send-email-quic_vamslank@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64b..2d613282816a8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -48,6 +48,7 @@ description: | sdx65 sm7225 sm8150 + sdx65 sm8250 sm8350 @@ -224,6 +225,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + - items: - enum: - qcom,ipq6018-cp01 -- GitLab From bae2f5979c6e537334c9099013b5407019e88c44 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:04 -0700 Subject: [PATCH 572/965] ARM: dts: qcom: Add SDX65 platform and MTP board support Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 210 +++++++++++++++++++++++++++ 3 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bba17ee51e297..3497c08c1afc3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -987,7 +987,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts new file mode 100644 index 0000000000000..59457da8e5f1d --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "qcom-sdx65.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX65 MTP"; + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; + qcom,board-id = <0x2010008 0x302>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi new file mode 100644 index 0000000000000..5aecb004e953b --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX65 SoC device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + reg = <0x8fee0000 0x20000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x00100000 0x001f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx65-pdc", "qcom,pdc"; + reg = <0xb210000 0x10000>; + qcom,pdc-ranges = <0 147 52>, <52 266 32>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, + <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , + , + , + ; + + rpmhcc: clock-controller@1 { + compatible = "qcom,sdx65-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; +}; -- GitLab From ff8b573a6ccf4deba10285abef072c577099e038 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:05 -0700 Subject: [PATCH 573/965] ARM: dts: qcom: sdx65: Add pincontrol node This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5aecb004e953b..796641d30e06c 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,18 @@ status = "disabled"; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; -- GitLab From 72a0ca203ca7fae34fe61668906fe483b97d9039 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 7 Dec 2021 17:10:02 +0530 Subject: [PATCH 574/965] dt-bindings: clock: Add SM8450 GCC clock bindings Add device tree bindings for global clock controller on SM8450 SoCs. Signed-off-by: Vinod Koul Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207114003.100693-2-vkoul@kernel.org --- .../bindings/clock/qcom,gcc-sm8450.yaml | 85 ++++++ include/dt-bindings/clock/qcom,gcc-sm8450.h | 244 ++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8450.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 0000000000000..58d98a766de6c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vinod Koul + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8450 + + See also: + - dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxillary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h new file mode 100644 index 0000000000000..cf1469312c4c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PHY_AUX_CLK 2 +#define PCIE_1_PIPE_CLK 3 +#define UFS_PHY_RX_SYMBOL_0_CLK 4 +#define UFS_PHY_RX_SYMBOL_1_CLK 5 +#define UFS_PHY_TX_SYMBOL_0_CLK 6 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7 + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 10 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_ANOC_PCIE_PWRCTL_CLK 13 +#define GCC_BOOT_ROM_AHB_CLK 14 +#define GCC_CAMERA_AHB_CLK 15 +#define GCC_CAMERA_HF_AXI_CLK 16 +#define GCC_CAMERA_SF_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 +#define GCC_CPUSS_AHB_CLK 21 +#define GCC_CPUSS_AHB_CLK_SRC 22 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23 +#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +#define GCC_DISP_AHB_CLK 27 +#define GCC_DISP_HF_AXI_CLK 28 +#define GCC_DISP_SF_AXI_CLK 29 +#define GCC_DISP_XO_CLK 30 +#define GCC_EUSB3_0_CLKREF_EN 31 +#define GCC_GP1_CLK 32 +#define GCC_GP1_CLK_SRC 33 +#define GCC_GP2_CLK 34 +#define GCC_GP2_CLK_SRC 35 +#define GCC_GP3_CLK 36 +#define GCC_GP3_CLK_SRC 37 +#define GCC_GPLL0 38 +#define GCC_GPLL0_OUT_EVEN 39 +#define GCC_GPLL4 40 +#define GCC_GPLL9 41 +#define GCC_GPU_CFG_AHB_CLK 42 +#define GCC_GPU_GPLL0_CLK_SRC 43 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_PCIE_0_AUX_CLK 47 +#define GCC_PCIE_0_AUX_CLK_SRC 48 +#define GCC_PCIE_0_CFG_AHB_CLK 49 +#define GCC_PCIE_0_CLKREF_EN 50 +#define GCC_PCIE_0_MSTR_AXI_CLK 51 +#define GCC_PCIE_0_PHY_RCHNG_CLK 52 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 +#define GCC_PCIE_0_PIPE_CLK 54 +#define GCC_PCIE_0_PIPE_CLK_SRC 55 +#define GCC_PCIE_0_SLV_AXI_CLK 56 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_1_AUX_CLK 58 +#define GCC_PCIE_1_AUX_CLK_SRC 59 +#define GCC_PCIE_1_CFG_AHB_CLK 60 +#define GCC_PCIE_1_CLKREF_EN 61 +#define GCC_PCIE_1_MSTR_AXI_CLK 62 +#define GCC_PCIE_1_PHY_AUX_CLK 63 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64 +#define GCC_PCIE_1_PHY_RCHNG_CLK 65 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 +#define GCC_PCIE_1_PIPE_CLK 67 +#define GCC_PCIE_1_PIPE_CLK_SRC 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PDM2_CLK 71 +#define GCC_PDM2_CLK_SRC 72 +#define GCC_PDM_AHB_CLK 73 +#define GCC_PDM_XO4_CLK 74 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 76 +#define GCC_QMIP_DISP_AHB_CLK 77 +#define GCC_QMIP_GPU_AHB_CLK 78 +#define GCC_QMIP_PCIE_AHB_CLK 79 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_CLK 85 +#define GCC_QUPV3_WRAP0_S0_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S1_CLK 88 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S2_CLK 90 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S3_CLK 92 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S4_CLK 94 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S5_CLK 96 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S6_CLK 98 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S7_CLK 100 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102 +#define GCC_QUPV3_WRAP1_CORE_CLK 103 +#define GCC_QUPV3_WRAP1_S0_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S1_CLK 106 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S2_CLK 108 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S3_CLK 110 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S4_CLK 112 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S5_CLK 114 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115 +#define GCC_QUPV3_WRAP1_S6_CLK 116 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118 +#define GCC_QUPV3_WRAP2_CORE_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK 120 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S1_CLK 122 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S2_CLK 124 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125 +#define GCC_QUPV3_WRAP2_S3_CLK 126 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127 +#define GCC_QUPV3_WRAP2_S4_CLK 128 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129 +#define GCC_QUPV3_WRAP2_S5_CLK 130 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131 +#define GCC_QUPV3_WRAP2_S6_CLK 132 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 +#define GCC_SDCC2_AHB_CLK 140 +#define GCC_SDCC2_APPS_CLK 141 +#define GCC_SDCC2_APPS_CLK_SRC 142 +#define GCC_SDCC2_AT_CLK 143 +#define GCC_SDCC4_AHB_CLK 144 +#define GCC_SDCC4_APPS_CLK 145 +#define GCC_SDCC4_APPS_CLK_SRC 146 +#define GCC_SDCC4_AT_CLK 147 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +#define GCC_UFS_0_CLKREF_EN 149 +#define GCC_UFS_PHY_AHB_CLK 150 +#define GCC_UFS_PHY_AXI_CLK 151 +#define GCC_UFS_PHY_AXI_CLK_SRC 152 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 +#define GCC_UFS_PHY_ICE_CORE_CLK 154 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 +#define GCC_UFS_PHY_PHY_AUX_CLK 157 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK 169 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173 +#define GCC_USB30_PRIM_SLEEP_CLK 174 +#define GCC_USB3_0_CLKREF_EN 175 +#define GCC_USB3_PRIM_PHY_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 179 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_AXI1_CLK 183 +#define GCC_VIDEO_XO_CLK 184 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33 +#define GCC_VIDEO_AXI0_CLK_ARES 34 +#define GCC_VIDEO_AXI1_CLK_ARES 35 +#define GCC_VIDEO_BCR 36 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_PHY_GDSC 2 +#define USB30_PRIM_GDSC 3 + +#endif -- GitLab From 8e6de09c716f37dbdc8181e803455603c89c4bd2 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 9 Dec 2021 22:59:38 +0000 Subject: [PATCH 575/965] arm64: dts: qcom: sdm845-oneplus-*: add msm-id and board-id The msm-id and board-id can be used to select the correct dtb when multiple are provided to the bootloader. Multiple DTBs can be provided on sdm845 devices using boot image header v1 by appending them all to the kernel image before creating the boot image. The bootloader then selects them like this: Best match DTB tags 321/00000008/0x00000000/20001/20014/20115/20018/0/(offset)0x79998E27/(size)0x000173CD Using pmic info 0x20014/0x20115/0x20018/0x0 for device 0x20014/0x20115/0x20018/0x0 Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209225938.2427342-1-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 2 ++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 73493079d13ea..5936b47dee5f8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -11,6 +11,8 @@ model = "OnePlus 6"; compatible = "oneplus,enchilada", "qcom,sdm845"; chassis-type = "handset"; + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <8 0 17819 22>; }; &display_panel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index b63ebc48f62f9..78a0b99144e6c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -11,6 +11,8 @@ model = "OnePlus 6T"; compatible = "oneplus,fajita", "qcom,sdm845"; chassis-type = "handset"; + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <8 0 18801 41>; }; &display_panel { -- GitLab From c16160cfa5651039f886d5cc6a6d9129e1fe789d Mon Sep 17 00:00:00 2001 From: Katherine Perez Date: Thu, 9 Dec 2021 10:32:46 -0800 Subject: [PATCH 576/965] arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2 This is a minimal devicetree for Microsoft Surface Duo 2 with SM8350 Chipset Signed-off-by: Katherine Perez Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209183246.842880-2-kaperez@linux.microsoft.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm8350-microsoft-surface-duo2.dts | 369 ++++++++++++++++++ 2 files changed, 370 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 693b30c51e33d..a3eedb8b33ee4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts new file mode 100644 index 0000000000000..9cb1d8455fd0d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2021, Microsoft Corporation + */ + +/dts-v1/; + +#include +#include "sm8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" + +/ { + model = "Microsoft Surface Duo 2"; + compatible = "microsoft,surface-duo2", "qcom,sm8350"; + chassis-type = "handset"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&adsp { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/adsp.mbn"; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; + vdd-l8-supply = <&vreg_s2c_0p8>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1360000>; + }; + + vreg_l1b_0p88: ldo1 { + regulator-name = "vreg_l1b_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1c_1p86>; + vdd-l2-l8-supply = <&vreg_s1c_1p86>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l4c_uim1: ldo4 { + regulator-name = "vreg_l4c_uim1"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_uim2: ldo5 { + regulator-name = "vreg_l5c_uim2"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_1p2: ldo10 { + regulator-name = "vreg_l10c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p96: ldo11 { + regulator-name = "vreg_l11c_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; +}; + +&cdsp { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/cdsp.mbn"; +}; + +&ipa { + status = "okay"; + + memory-region = <&pil_ipa_fw_mem>; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/modem.mbn"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&slpi { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/slpi.mbn"; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, <12 4>, <56 4>, <76 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-max-microamp = <91600>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p88>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l5b_0p88>; +}; -- GitLab From d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 14 Dec 2021 19:09:24 +0200 Subject: [PATCH 577/965] dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example Now that HSI2C binding [1] is converted to dt-schema format, it reveals incorrect HSI2C clocks order in USI binding example: .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:0: 'hsi2c' was expected From schema: .../i2c-exynos5.yaml .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected From schema: .../i2c-exynos5.yaml Change HSI2C clock order in USI binding example to satisfy HSI2C binding requirements and fix above warnings. [1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 0af4821fae5e4..273f2d95a0437 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -152,8 +152,8 @@ examples: interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&cmu_peri 32>, <&cmu_peri 31>; - clock-names = "hsi2c_pclk", "hsi2c"; + clocks = <&cmu_peri 31>, <&cmu_peri 32>; + clock-names = "hsi2c", "hsi2c_pclk"; status = "disabled"; }; }; -- GitLab From 92c959bae2e54ba1e2540ba5f813f7752bd76be1 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 15 Dec 2021 11:14:23 +0100 Subject: [PATCH 578/965] reset: renesas: Fix Runtime PM usage If pm_runtime_resume_and_get() fails then it returns w/o the RPM usage counter being incremented. In this case call pm_runtime_put() in remove() will result in a usage counter imbalance. Therefore check the return code of pm_runtime_resume_and_get() and bail out in case of error. Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver") Signed-off-by: Heiner Kallweit Reviewed-by: Biju Das Link: https://lore.kernel.org/r/ec24e13f-0530-b091-7a08-864577b9b3be@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c index e0704fd2b5336..1e83150388506 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -137,7 +137,12 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) dev_set_drvdata(dev, priv); pm_runtime_enable(&pdev->dev); - pm_runtime_resume_and_get(&pdev->dev); + error = pm_runtime_resume_and_get(&pdev->dev); + if (error < 0) { + pm_runtime_disable(&pdev->dev); + reset_control_assert(priv->rstc); + return dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed"); + } /* put pll and phy into reset state */ spin_lock_irqsave(&priv->lock, flags); -- GitLab From c2c529b27ceb394ff4d3273ed1f552195fc4d555 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 6 Dec 2021 12:47:12 +0000 Subject: [PATCH 579/965] arm64: remove __dma_*_area() aliases The __dma_inv_area() and __dma_clean_area() aliases make cache.S harder to navigate, but don't gain us anything in practice. For clarity, let's remove them along with their redundant comments. The only users are __dma_map_area() and __dma_unmap_area(), which need to be position independent, and can call __pi_dcache_inval_poc() and __pi_dcache_clean_poc() directly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Ard Biesheuvel Cc: Fuad Tabba Cc: Marc Zyngier Cc: Will Deacon Acked-by: Catalin Marinas Acked-by: Mark Brown Acked-by: Ard Biesheuvel Link: https://lore.kernel.org/r/20211206124715.4101571-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/mm/cache.S | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 5051b3c1a4f12..7d0563db42014 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -140,15 +140,7 @@ SYM_FUNC_END(dcache_clean_pou) * - start - kernel start address of region * - end - kernel end address of region */ -SYM_FUNC_START_LOCAL(__dma_inv_area) SYM_FUNC_START_PI(dcache_inval_poc) - /* FALLTHROUGH */ - -/* - * __dma_inv_area(start, end) - * - start - virtual start address of region - * - end - virtual end address of region - */ dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? @@ -167,7 +159,6 @@ SYM_FUNC_START_PI(dcache_inval_poc) dsb sy ret SYM_FUNC_END_PI(dcache_inval_poc) -SYM_FUNC_END(__dma_inv_area) /* * dcache_clean_poc(start, end) @@ -178,19 +169,10 @@ SYM_FUNC_END(__dma_inv_area) * - start - virtual start address of region * - end - virtual end address of region */ -SYM_FUNC_START_LOCAL(__dma_clean_area) SYM_FUNC_START_PI(dcache_clean_poc) - /* FALLTHROUGH */ - -/* - * __dma_clean_area(start, end) - * - start - virtual start address of region - * - end - virtual end address of region - */ dcache_by_line_op cvac, sy, x0, x1, x2, x3 ret SYM_FUNC_END_PI(dcache_clean_poc) -SYM_FUNC_END(__dma_clean_area) /* * dcache_clean_pop(start, end) @@ -232,8 +214,8 @@ SYM_FUNC_END_PI(__dma_flush_area) SYM_FUNC_START_PI(__dma_map_area) add x1, x0, x1 cmp w2, #DMA_FROM_DEVICE - b.eq __dma_inv_area - b __dma_clean_area + b.eq __pi_dcache_inval_poc + b __pi_dcache_clean_poc SYM_FUNC_END_PI(__dma_map_area) /* @@ -245,6 +227,6 @@ SYM_FUNC_END_PI(__dma_map_area) SYM_FUNC_START_PI(__dma_unmap_area) add x1, x0, x1 cmp w2, #DMA_TO_DEVICE - b.ne __dma_inv_area + b.ne __pi_dcache_inval_poc ret SYM_FUNC_END_PI(__dma_unmap_area) -- GitLab From 57337b252442128605f89a3e96df128c2e5404bf Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 5 Oct 2021 23:24:21 +0900 Subject: [PATCH 580/965] arm64: dts: apple: t8103: Rename clk24 to clkref We now know that this frequency comes from the external reference oscillator and is used for various SoC blocks, and isn't just a random 24MHz clock, so let's call it something more appropriate. Reviewed-by: Mark Kettenis Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8203c60d4819c..33c9ea6c7c639 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -96,11 +96,11 @@ ; }; - clk24: clock-24m { + clkref: clock-ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; - clock-output-names = "clk24"; + clock-output-names = "clkref"; }; soc { @@ -114,7 +114,7 @@ i2c0: i2c@235010000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35010000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c0_pins>; @@ -127,7 +127,7 @@ i2c1: i2c@235014000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35014000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c1_pins>; @@ -140,7 +140,7 @@ i2c2: i2c@235018000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35018000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c2_pins>; @@ -154,7 +154,7 @@ i2c3: i2c@23501c000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x3501c000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c3_pins>; @@ -167,7 +167,7 @@ i2c4: i2c@235020000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35020000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c4_pins>; @@ -188,7 +188,7 @@ * TODO: figure out the clocking properly, there may * be a third selectable clock. */ - clocks = <&clk24>, <&clk24>; + clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; power-domains = <&ps_uart0>; status = "disabled"; @@ -200,7 +200,7 @@ reg-io-width = <4>; interrupt-parent = <&aic>; interrupts = ; - clocks = <&clk24>, <&clk24>; + clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; power-domains = <&ps_uart2>; status = "disabled"; @@ -327,7 +327,7 @@ wdt: watchdog@23d2b0000 { compatible = "apple,t8103-wdt", "apple,wdt"; reg = <0x2 0x3d2b0000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; }; -- GitLab From 8adf987ce08275433a7b2eb281a19785b5d30c30 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sun, 12 Dec 2021 10:40:16 +0900 Subject: [PATCH 581/965] arm64: dts: apple: t8103: Sort nodes by address We decided to keep SoC nodes sorted by address for sanity; fix a couple that slipped into the wrong place. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 56 ++++++++++++++-------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 33c9ea6c7c639..4950e6340995f 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -274,34 +274,6 @@ }; }; - pmgr_mini: power-management@23d280000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3d280000 0 0x4000>; - }; - - pinctrl_aop: pinctrl@24a820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x4a820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - }; - pinctrl_nub: pinctrl@23d1f0000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3d1f0000 0x0 0x4000>; @@ -324,6 +296,13 @@ ; }; + pmgr_mini: power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0 0x4000>; + }; + wdt: watchdog@23d2b0000 { compatible = "apple,t8103-wdt", "apple,wdt"; reg = <0x2 0x3d2b0000 0x0 0x4000>; @@ -353,6 +332,27 @@ ; }; + pinctrl_aop: pinctrl@24a820000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x4a820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 42>; + apple,npins = <42>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + pcie0_dart_0: dart@681008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x81008000 0x0 0x4000>; -- GitLab From 301f651614c3396d711a8cc3f92f6fb95b12f5c5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:50:42 +0900 Subject: [PATCH 582/965] dt-bindings: mailbox: apple,mailbox: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 2c1704b34e7aa..c4255f42e8019 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -56,6 +56,9 @@ properties: "#mbox-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg -- GitLab From 8e136c5ea43ae08c5d672deb1c3f494782a4392a Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 15 Dec 2021 20:27:54 +0900 Subject: [PATCH 583/965] soc: apple: apple-pmgr-pwrstate: Do not build as a module This doesn't make any sense as a module since it is a critical device, and it turns out of_phandle_iterator_args was not exported so the module version doesn't build anyway. Fixes: 6df9d38f9146 ("soc: apple: Add driver for Apple PMGR power state controls") Reported-by: kernel test robot Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- drivers/soc/apple/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig index 3eb14abf8d337..9b8de31d6a8f8 100644 --- a/drivers/soc/apple/Kconfig +++ b/drivers/soc/apple/Kconfig @@ -5,7 +5,7 @@ if ARCH_APPLE || COMPILE_TEST menu "Apple SoC drivers" config APPLE_PMGR_PWRSTATE - tristate "Apple SoC PMGR power state control" + bool "Apple SoC PMGR power state control" depends on PM select REGMAP select MFD_SYSCON -- GitLab From cbb469f7518f12b06b9f66eb39e84e097278b682 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:11 +0300 Subject: [PATCH 584/965] ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets Enable charger, touchpad and EC drivers found on Acer Tegra124 (Nyan) Chromebooks, display bridge found on ASUS TF700T and audio codecs found on ASUS tablets. Suggested-by: Thomas Graichen # Nyan options Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/tegra_defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 8a8f12b3e6dd8..a8093b2225516 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -104,6 +104,8 @@ CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m CONFIG_RT2X00=y CONFIG_RT2800USB=m CONFIG_INPUT_JOYDEV=y @@ -112,6 +114,8 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_TEGRA=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_KEYBOARD_CAP11XX=y +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y @@ -131,6 +135,7 @@ CONFIG_SERIAL_DEV_BUS=y # CONFIG_HW_RANDOM is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y @@ -151,7 +156,9 @@ CONFIG_GPIO_TPS65910=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_BATTERY_SBS=y +CONFIG_CHARGER_BQ24735=y CONFIG_BATTERY_BQ27XXX=y CONFIG_CHARGER_GPIO=y CONFIG_CHARGER_SMB347=y @@ -200,7 +207,9 @@ CONFIG_DRM_TEGRA_STAGING=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y CONFIG_DRM_LVDS_CODEC=y +CONFIG_DRM_TOSHIBA_TC358768=y CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y @@ -279,6 +288,9 @@ CONFIG_STAGING_MEDIA=y CONFIG_TEGRA_VDE=y CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_SPI=m +CONFIG_I2C_CROS_EC_TUNNEL=m CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARCH_TEGRA_2x_SOC=y -- GitLab From ca1f7d245f530fd8ad57e7f596826da4d56bec80 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:12 +0300 Subject: [PATCH 585/965] ARM: config: multi v7: Enable display drivers used by Tegra devices Enable display-related drivers used by various Tegra-based tablets. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index c951aeed2138c..3d509bc134440 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -382,6 +382,7 @@ CONFIG_TCG_TPM=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_DEMUX_PINCTRL=y @@ -680,19 +681,23 @@ CONFIG_DRM_FSL_DCU=m CONFIG_DRM_TEGRA=y CONFIG_DRM_STM=m CONFIG_DRM_STM_DSI=m +CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_LVDS_CODEC=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_SII902X=m CONFIG_DRM_SII9234=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358768=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_STI=m -- GitLab From c96ebc5fde274edcc02543dcfb6a1ee097f98070 Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 6 Dec 2021 16:31:17 +0100 Subject: [PATCH 586/965] dt-bindings: arm: samsung: document jackpotlte board binding Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)). Signed-off-by: David Virag Reviewed-by: Rob Herring Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211206153124.427102-4-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index ef6dc14be4b5d..d885712027134 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -199,6 +199,12 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7885 based boards + items: + - enum: + - samsung,jackpotlte # Samsung Galaxy A8 (2018) + - const: samsung,exynos7885 + - description: Exynos Auto v9 based boards items: - enum: -- GitLab From 86a3a7f8a42bcdda6281b949d7e78e6e20ddc8ff Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:51:33 +0100 Subject: [PATCH 587/965] ARM: tegra: Add compatible string for built-in ASIX on Colibri boards The device tree node for the built-in ASIX Ethernet device on Colibri boards needs a compatible string in order to pass DT schema validation. Add the USB VID,PID compatible string as required by the DT schema for USB devices. Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 28e22097578d6..b1f2f7f82928b 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -691,6 +691,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index b585831e32128..febcb403412cb 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -953,6 +953,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; -- GitLab From e1808b09df868135240b6b489b692e105d0b17a7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:57:40 +0100 Subject: [PATCH 588/965] ARM: tegra: Remove PHY reset GPIO references from USB controller node The PHY reset GPIO references belong in the USB PHY nodes, where they already exist. There is no need to keep them in the USB controller's device tree node as well. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-harmony.dts | 2 -- arch/arm/boot/dts/tegra20-paz00.dts | 2 -- arch/arm/boot/dts/tegra20-seaboard.dts | 2 -- arch/arm/boot/dts/tegra20-trimslice.dts | 2 -- arch/arm/boot/dts/tegra20-ventana.dts | 2 -- 5 files changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index a8494378c3826..f560bf743a192 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -595,8 +595,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 1fd5a7458c7af..12c245869a740 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -533,8 +533,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ca7adeb1fdd97..98e61068b981a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -742,8 +742,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dd05e2c87c29c..8bb0eaa610f28 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -349,8 +349,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 4284054ebd2c8..b1c92ba789be4 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -556,8 +556,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { -- GitLab From c98167bbe865591351df10fd88f759f41006d060 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:59:59 +0100 Subject: [PATCH 589/965] ARM: tegra: Add dummy backlight power supplies The Medcom Wide and PAZ00 boards don't specify the power supply for the backlight, which means that the Linux driver will provide a dummy one. Wire up an explicit dummy to also make the DT schema validation succeed. Unfortunately I don't have access to the schematics for the Medcom Wide, so I don't know if a more accurate description is possible. The AC100 (PAZ00) schematics from here: https://www.s-manuals.com/pdf/motherboard/compal/compal_la-6352p_r1.0a_schematics.pdf aren't entirely clear which one of the supplies powers backlight, but the panel supply is probably close enough. Based on work by David Heidelberg . Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 3 +++ arch/arm/boot/dts/tegra20-paz00.dts | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index cb6199d7d2249..f144487c5da3c 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -54,6 +54,9 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + + /* close enough */ + power-supply = <&vdd_3v3_reg>; }; panel: panel { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 12c245869a740..5ce6a1ff93de1 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -571,6 +571,9 @@ brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; default-brightness-level = <10>; + + /* close enough */ + power-supply = <&vdd_pnl_reg>; }; clk32k_in: clock-32k { -- GitLab From 9b34a2a1bc6e29562d0a2a2f77934d8829daedb4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:01:53 +0100 Subject: [PATCH 590/965] ARM: tegra: Use correct vendor prefix for Invensense The correct vendor prefix for Invensense is "invensense," rather than "invn,". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 98e61068b981a..f9309c07a9f22 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -358,7 +358,7 @@ }; gyrometer@68 { - compatible = "invn,mpu3050"; + compatible = "invensense,mpu3050"; reg = <0x68>; interrupt-parent = <&gpio>; interrupts = ; -- GitLab From fe3c94e8e7e458dca28024e39fdaad537b2ea28c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:03:00 +0100 Subject: [PATCH 591/965] ARM: tegra: Remove unsupported properties on Apalis The +V1.2_VDD_CORE regulator on Apalis and Colibri boards uses the unsupported ti,vsel{0,1}-state-low properties. It turns out that these are in fact the default and can be overridden by ti,vsel{0,1}-state-high properties if needed. Drop them since they are not needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 --- arch/arm/boot/dts/tegra30-apalis.dtsi | 3 --- arch/arm/boot/dts/tegra30-colibri.dtsi | 3 --- 3 files changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6fe775b2b38d9..380f22a35821a 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1050,9 +1050,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7df2841690d7e..9bdc4cb71449c 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1033,9 +1033,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index febcb403412cb..9bf8170fee798 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -901,9 +901,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; -- GitLab From e6cc64655480de215993cabec45d1f32bb1f5857 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 20:36:05 +0300 Subject: [PATCH 592/965] ARM: tegra: nexus7: Drop clock-frequency from NFC node The clock-frequency property was never used and is deprecated now. Remove it from Nexus 7 device-tree. Signed-off-by: David Heidelberg Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 - arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index a044dbd200a9f..564cfcde21a9c 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -137,7 +137,6 @@ nfc@28 { compatible = "nxp,pn544-i2c"; reg = <0x28>; - clock-frequency = <100000>; interrupt-parent = <&gpio>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index a681ad51fdddf..cd63e0ef74455 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -223,8 +223,6 @@ compatible = "nxp,pn544-i2c"; reg = <0x2a>; - clock-frequency = <100000>; - interrupt-parent = <&gpio>; interrupts = ; -- GitLab From e3cc9c1c51f872629e860ef3b780ddf07f515123 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:06:16 +0100 Subject: [PATCH 593/965] ARM: tegra: Remove stray #reset-cells property The Ouya board specifies the #reset-cells property for the GPIO controller. Since the GPIO controller doesn't provide reset controls this is not needed, so they can be dropped. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9e59d9bd6b35a..9a774500cb88e 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -70,7 +70,6 @@ gpio: gpio@6000d000 { gpio-ranges = <&pinmux 0 0 248>; - #reset-cells = <1>; }; pinmux@70000868 { -- GitLab From 695494bb969a6070663c20425608c7b72f22887f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:07:30 +0100 Subject: [PATCH 594/965] ARM: tegra: Fix SLINK compatible string on Tegra30 The SLINK controller found on Tegra30 is not compatible with its predecessor found on Tegra20. Drop the fallback compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ae3df73c20a73..46befba0bc72b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -666,7 +666,7 @@ }; spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d400 0x200>; interrupts = ; #address-cells = <1>; @@ -680,7 +680,7 @@ }; spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d600 0x200>; interrupts = ; #address-cells = <1>; @@ -694,7 +694,7 @@ }; spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d800 0x200>; interrupts = ; #address-cells = <1>; @@ -708,7 +708,7 @@ }; spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000da00 0x200>; interrupts = ; #address-cells = <1>; @@ -722,7 +722,7 @@ }; spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000dc00 0x200>; interrupts = ; #address-cells = <1>; @@ -736,7 +736,7 @@ }; spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000de00 0x200>; interrupts = ; #address-cells = <1>; -- GitLab From b716d046041e19af9ba188bd2865e141f749a76a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:08:32 +0100 Subject: [PATCH 595/965] ARM: tegra: Fix I2C mux reset GPIO reference on Cardhu Use the correct "reset-gpios" property for the I2C mux reset GPIO reference instead of the deprecated "reset-gpio" property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 12e185846dcb9..c2a56eb0b9fa8 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -210,7 +210,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; }; }; -- GitLab From c6e331a2bb0696075d28810e1afd5c35658c240e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 13:49:02 +0100 Subject: [PATCH 596/965] ARM: tegra: Avoid phandle indirection on Ouya Move the default state pinmux definition into the pinmux node. There's no need for the indirection via the phandle. Note that the phandle indirection is kept for the EMC operating performance point tables because they reference nodes that are defined in an external file. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 8912 ++++++++++++++-------------- 1 file changed, 4590 insertions(+), 4322 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9a774500cb88e..b28c5504e1b19 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -75,4450 +75,4718 @@ pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; + state_default: pinmux { - /* located at $state_default below */ - }; - }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - uartc: serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* Azurewave AW-NH660 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - max-speed = <4000000>; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vbat-supply = <&sys_3v3_reg>; - vddio-supply = <&vdd_1v8>; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - }; - }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - uartd: serial@70006300 { - status = "okay"; - }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupt-parent = <&gpio>; - interrupts = ; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #thermal-sensor-cells = <1>; - }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #gpio-cells = <2>; - gpio-controller; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vcc1-supply = <&vdd_5v0_reg>; - vcc2-supply = <&vdd_5v0_reg>; - vcc3-supply = <&vdd_1v8>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_5v0_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v0_reg>; - vccio-supply = <&vdd_5v0_reg>; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1270000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,tegra-cpu-regulator; - }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_1v8: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* LDO3 is not connected to anything */ + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - }; - vdd_core: tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - regulator-name = "vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - ti,enable-vout-discharge; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,tegra-core-regulator; - }; - }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - mc_timings: memory-controller@7000f000 { - /* timings located at &mc_timings below */ - }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - emc_timings: memory-controller@7000f400 { - /* timings located at &emc_timings below */ - }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - hda@70030000 { - status = "okay"; - }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc3: mmc@78000400 { - status = "okay"; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #address-cells = <1>; - #size-cells = <0>; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - max-frequency = <50000000>; - keep-power-in-suspend; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - bus-width = <4>; - non-removable; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - mmc-pwrseq = <&wifi_pwrseq>; - vmmc-supply = <&sdmmc_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* Azurewave AW-NH660 BCM4330 */ - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc4: mmc@78000600 { - status = "okay"; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - keep-power-in-suspend; - bus-width = <8>; - non-removable; - vmmc-supply = <&sys_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; - nvidia,default-tap = <0x0F>; - max-frequency = <25500000>; - }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d000000 { - status = "okay"; - dr_mode = "peripheral"; - }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - smsc@2 { /* SMSC 10/100T Ethernet Controller */ - compatible = "usb424,9e00"; - reg = <2>; - local-mac-address = [00 11 22 33 44 55]; - }; - }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d004000 { - vbus-supply = <&vdd_smsc>; - status = "okay"; - }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d008000 { - status = "okay"; - }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu1: cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu2: cpu@2 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu3: cpu@3 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - fan: gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; - #cooling-cells = <2>; - }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - thermal-sensors = <&cpu_temp 1>; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - }; - }; - vdd_12v_in: vdd_12v_in { - compatible = "regulator-fixed"; - regulator-name = "vdd_12v_in"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc_3v3_reg: sdmmc_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "sdmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - regulator-always-on; - }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_vid_reg: vdd_vid_reg { - compatible = "regulator-fixed"; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - regulator-boot-on; - }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ddr_reg: ddr_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sys_3v3_reg: sys_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_5v0_reg: vdd_5v0_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_smsc: vdd_smsc { - compatible = "regulator-fixed"; - regulator-name = "vdd_smsc"; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; - }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb3_vbus_reg: usb3_vbus_reg { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - gpio-keys { - compatible = "gpio-keys"; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - leds { - compatible = "gpio-leds"; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; - }; - }; -}; -&mc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74430504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x74040a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; -}; -&emc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; }; }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000f /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000010 /* EMC_TXSR */ - 0x00000010 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001e /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000020 /* EMC_TXSR */ - 0x00000020 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x0000003d /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000040 /* EMC_TXSR */ - 0x00000040 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000076 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000007c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00044000 /* EMC_DLL_XFORM_DQS0 */ - 0x00044000 /* EMC_DLL_XFORM_DQS1 */ - 0x00044000 /* EMC_DLL_XFORM_DQS2 */ - 0x00044000 /* EMC_DLL_XFORM_DQS3 */ - 0x00044000 /* EMC_DLL_XFORM_DQS4 */ - 0x00044000 /* EMC_DLL_XFORM_DQS5 */ - 0x00044000 /* EMC_DLL_XFORM_DQS6 */ - 0x00044000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00058000 /* EMC_DLL_XFORM_DQ0 */ - 0x00058000 /* EMC_DLL_XFORM_DQ1 */ - 0x00058000 /* EMC_DLL_XFORM_DQ2 */ - 0x00058000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0148000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ee /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000f8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000c /* EMC_DLL_XFORM_DQS0 */ - 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00d0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH660 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&sys_3v3_reg>; + vddio-supply = <&vdd_1v8>; + + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; }; }; -}; -&state_default { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + uartd: serial@70006300 { + status = "okay"; }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_reg>; + vcc2-supply = <&vdd_5v0_reg>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_5v0_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_reg>; + vccio-supply = <&vdd_5v0_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1270000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + + nvidia,tegra-core-regulator; + }; }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + hda@70030000 { + status = "okay"; }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&sdmmc_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH660 BCM4330 */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc4: mmc@78000600 { + status = "okay"; + + keep-power-in-suspend; + bus-width = <8>; + non-removable; + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + nvidia,default-tap = <0x0F>; + max-frequency = <25500000>; }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + smsc@2 { /* SMSC 10/100T Ethernet Controller */ + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + usb-phy@7d004000 { + vbus-supply = <&vdd_smsc>; + status = "okay"; }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + usb@7d008000 { + status = "okay"; }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + + thermal-sensors = <&cpu_temp 1>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_12v_in: vdd_12v_in { + compatible = "regulator-fixed"; + regulator-name = "vdd_12v_in"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc_3v3_reg: sdmmc_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sdmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + regulator-always-on; }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_vid_reg: vdd_vid_reg { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + regulator-boot-on; }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + ddr_reg: ddr_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sys_3v3_reg: sys_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_5v0_reg: vdd_5v0_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_smsc: vdd_smsc { + compatible = "regulator-fixed"; + regulator-name = "vdd_smsc"; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + usb3_vbus_reg: usb3_vbus_reg { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + gpio-keys { + compatible = "gpio-keys"; + + power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; }; - drive_groups { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; + + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; }; }; -- GitLab From b405066bd3e04e9d0c34a25db85adf19c08274ef Mon Sep 17 00:00:00 2001 From: Nikola Milosavljevic Date: Sun, 12 Dec 2021 00:13:49 +0300 Subject: [PATCH 597/965] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Add device-tree for Tegra20-based ASUS Transformer EeePad TF101. Link: https://wiki.postmarketos.org/wiki/ASUS_Eee_Pad_Transformer_(asus-tf101) Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Co-developed-by: Antoni Aloy Torrens Signed-off-by: Antoni Aloy Torrens Signed-off-by: Nikola Milosavljevic Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra20-asus-tf101.dts | 1280 ++++++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 2 +- 3 files changed, 1282 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd87..f51edce19a604 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1304,6 +1304,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ tegra20-harmony.dtb \ tegra20-colibri-eval-v3.dtb \ tegra20-colibri-iris.dtb \ diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts new file mode 100644 index 0000000000000..020172ee7340e --- /dev/null +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -0,0 +1,1280 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "ASUS EeePad Transformer TF101"; + compatible = "asus,tf101", "nvidia,tegra20"; + chassis-type = "convertible"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi_en>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + gpio@6000d000 { + charging-enable-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap4", + "dte", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", "sdc", + "sdd", "slxc", "slxd", "slxk", "spdi", + "spdo", "uac", "uad", + "uda", "csus"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", + "owc", "spia", "spib", "spic", + "spid", "spie", "spig", "slxa"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + + conf_crtp { + nvidia,pins = "crtp", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_csus { + nvidia,pins = "drive_csus"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /* GPS BCM4751 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + status = "okay"; + + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0xe>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_sys>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0x83>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0x00000400 /* Mic bias current detect */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + /* Atmel MXT1386 Touchscreen */ + touchscreen@5b { + compatible = "atmel,maxtouch"; + reg = <0x5b>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0xf>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@3 { + reg = <0x3>; + + #address-cells = <1>; + #size-cells = <0>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dc010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e0 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + /* Peripheral USB via ASUS connector */ + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <40000000>; + + max-frequency = <40000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH615 BCM4329B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 4000000>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + /* AUO B101EW05 using custom timings */ + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c2>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie_vdd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi_en: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_hdmi_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf101", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus EeePad Transformer WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents TF101 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <200>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9508248fd1666..6f493a8a8a9f7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -523,7 +523,7 @@ status = "disabled"; }; - i2c@7000c400 { + i2c2: i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; interrupts = ; -- GitLab From 91ead34f47c907d931a1f6d396d7dfbbc068263a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:50 +0300 Subject: [PATCH 598/965] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common DTSI for Tegra30 ASUS Transformers. It will be used by multiple device-trees of ASUS devices. The common part initially was born out of the ASUS TF300T tablet's device-tree that was created by Michał Mirosław. It was heavily reworked and improved by Svyatoslav Ryhel, Maxim Schwalm, Ion Agorria et al. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Michał Mirosław Signed-off-by: Michał Mirosław Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- .../dts/tegra30-asus-transformer-common.dtsi | 1787 +++++++++++++++++ 1 file changed, 1787 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi new file mode 100644 index 0000000000000..85b43a86a26d9 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -0,0 +1,1787 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000000"; /* uSD slot */ + mmc2 = "/mmc@78000400"; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + gpio@6000d000 { + init-lpm-in-hog { + gpio-hog; + gpios = , + ; + input; + }; + + init-lpm-out-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + + usb-charge-limit-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_com>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_vio>; + }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_vio>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_bat>; + vcc2-supply = <&vdd_5v0_bat>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_bat>; + vcc6-supply = <&vdd_3v3_sys>; + vcc7-supply = <&vdd_5v0_bat>; + vccio-supply = <&vdd_5v0_bat>; + + pmic-sleep-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Transformers */ + + vddio_ddr: vdd2 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + /* FIXME: Without this, voltage switching fails */ + regulator-always-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* LDO5 is not used by Transformers */ + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + /* FIXME: LP1 doesn't work at the moment */ + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + + /* FIXME: Full 208Mhz clock rate doesn't work reliably */ + max-frequency = <104000000>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_com>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + mmc-ddr-3_3v; + non-removable; + }; + + /* USB via ASUS connector */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_bat>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + vdd_5v0_bat: regulator-bat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_cp: regulator-sby { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sby"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_1v5_ddr: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_com: regulator-com { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + nvidia,i2s-controller = <&tegra_i2s1>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformers from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; +}; -- GitLab From a0d7dba8c3c125692405ac3e2db0e9414952c14f Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:13:51 +0300 Subject: [PATCH 599/965] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets All Tegra30 ASUS tablets have a similar design pattern in terms of hardware integration of LVDS display panels, like exactly the same GPIOs are used for power and reset, etc. Add a common device-tree for LVDS display panels of Tegra30 ASUS tablets to avoid replicating the boilerplate panel description. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-lvds-display.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi new file mode 100644 index 0000000000000..a047abfa63692 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ + +/ { + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + display-panel { + power-supply = <&vdd_pnl>; + ddc-i2c-bus = <&lcd_ddc>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; +}; -- GitLab From 9b66bd835dfd85efaf5f590f34230d1d75b446f9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:52 +0300 Subject: [PATCH 600/965] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Add device-tree for ASUS Transformer Prime TF201, which is a NVIDIA Tegra30-based 2-in-1 detachable, orignally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Prime_(asus-tf201) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf201.dts | 627 +++++++++++++++++++++++ 2 files changed, 628 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f51edce19a604..fcc48f8aa3b47 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1321,6 +1321,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-PM269.dtb \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts new file mode 100644 index 0000000000000..315c6dc068c5f --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Atmel MXT768E touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0x80000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emem-configuration = < 0x00000007 0x8000005a + 0x00000003 0x00000004 0x0000000e 0x00000009 + 0x0000000c 0x00000002 0x00000002 0x00000008 + 0x00000001 0x00000000 0x00000004 0x00000005 + 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000a0000 0x000a0000 0x000a0000 + 0x000a0000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00120220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00074000 0x00074000 0x00074000 + 0x00074000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00078000 0x00078000 0x00078000 + 0x00078000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x0002c000 0x0002c000 0x0002c000 + 0x0002c000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000024 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000d0000 0x000d0000 0x000d0000 + 0x000d0000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020005>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000002d>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001d + 0x00000040 0x00000014 0x00000008 0x00000007 + 0x00000009 0x00000003 0x0000000d 0x00000008 + 0x00000008 0x00000004 0x00000002 0x00000000 + 0x00000004 0x00000008 0x00000005 0x0000000d + 0x0000000f 0x00000763 0x00000000 0x000001d8 + 0x00000003 0x00000003 0x00000008 0x00000000 + 0x00000001 0x0000000e 0x00000046 0x00000046 + 0x00000008 0x00000019 0x0000000b 0x00000004 + 0x00000002 0x00000820 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0140091 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000b4 0x000d000d 0xa0f10404 0x00000000 + 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >; + }; + }; + }; + + usb-phy@7d000000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + usb-phy@7d008000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + display-panel { + compatible = "hannstar,hsd101pww2"; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- GitLab From 65fce832a97cb7ed3e4896475baabeb7f506de3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Date: Sun, 12 Dec 2021 00:13:53 +0300 Subject: [PATCH 601/965] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device-tree for ASUS Transformer Pad TF300T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Tested-by: Ihor Didenko Tested-by: Andreas Westman Dorcsak Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Michał Mirosław Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1034 +++++++++++++++++++++ 2 files changed, 1035 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fcc48f8aa3b47..71ec43e72380c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts new file mode 100644 index 0000000000000..f47434871a5c8 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -0,0 +1,1034 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + tf300t-init-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0605 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000005 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000011 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0f000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000003 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000b 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x0000006a 0x00000018 0x00000008 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0155000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000008 + 0x00000008 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf300t", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus Transformer Pad TF300T WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1L", "Mic Jack", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,audio-codec = <&wm8903>; + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,headset; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- GitLab From 2602de4800e6058f811b467b40e1cd16a21d0a30 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:54 +0300 Subject: [PATCH 602/965] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Add device-tree for ASUS Transformer Pad TF300TG, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. It's a variant of the TF300T that has a 3G modem. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1087 ++++++++++++++++++++ 2 files changed, 1088 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 71ec43e72380c..c957986f023ce 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1323,6 +1323,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts new file mode 100644 index 0000000000000..96345f821c3d2 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; + + gpio@6000d000 { + tf300tg-init-hog { + gpio-hog; + gpios = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0x8000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0x80000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0a000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00040000 0x00040000 0x00040000 + 0x00040000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- GitLab From e6d391a0b29bd083dabc620534892f0d05707501 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:55 +0300 Subject: [PATCH 603/965] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Add device-tree for ASUS Transformer Infinity TF700T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/Asus_Transformer_Pad_Infinity_TF700T_(asus-tf700t) Tested-by: Andreas Westman Dorcsak Tested-by: Jasper Korten Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf700t.dts | 823 ++++++++++++++++++++++ 2 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c957986f023ce..47cd157496f90 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1324,6 +1324,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts new file mode 100644 index 0000000000000..18a9bfa5e97bc --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" + +/ { + model = "Asus Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + host1x@50000000 { + lcd: dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2944>; + touchscreen-size-y = <1856>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + }; + + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&lcd_ddc>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi-bridge@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-900000000; +}; -- GitLab From 2b69c7b5fd350754b524c3410563a8d0fc452f99 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:13:56 +0300 Subject: [PATCH 604/965] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Add device-tree for Tegra114-based ASUS Transformer Pad TF701T (K00C) tablet. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(TF701T)_(asus-tf701t) Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra114-asus-tf701t.dts | 807 +++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsi | 4 +- 3 files changed, 810 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 47cd157496f90..faaeae1f2a58d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1331,6 +1331,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-colibri-eval-v3.dtb \ tegra30-ouya.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts new file mode 100644 index 0000000000000..b791ce97424bd --- /dev/null +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include + +#include "tegra114.dtsi" + +/ { + model = "Asus Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000400"; /* uSD slot */ + mmc2 = "/mmc@78000000"; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; + linux,cma-default; + reusable; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + nvidia,ganged-mode = <&dsib>; + + panel_primary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + + dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + asus_pad_ec_default: asus-pad-ec-default { + ec-interrupt { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec-request { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + backlight_default: backlight-default { + backlight-enable { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + codec_default: codec-default { + ldo1-en { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_keys_default: gpio-keys-default { + power { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + volume { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + hp_det_default: hp-det-default { + gmi_iordy_pi5 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + imu_default: imu-default { + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pwm_default: pwm-default { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + /* XXX make this something more sensible */ + pwm_sleep: pwm-sleep { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + sdmmc3_default: sdmmc3-default { + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + sdmmc3_vdd_default: sdmmc3-vdd-default { + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + vdd_lcd_default: vdd-lcd-default { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + /* GPS */ + }; + + serial@70006200 { + /* Bluetooth */ + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0xc>; + + vdd-supply = <&vdd_3v3_sys>; + }; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_default>; + }; + + motion-tracker@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@1c { + compatible = "dynaimage,al3320a"; + reg = <0x1c>; + + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c700 { + /* HDMI DDC */ + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&tps65913_smps7>; + ldo2-in-supply = <&tps65913_smps7>; + ldo4-in-supply = <&tps65913_smps8>; + ldo5-in-supply = <&tps65913_smps9>; + ldo6-in-supply = <&tps65913_smps9>; + ldo7-in-supply = <&tps65913_smps9>; + ldo9-in-supply = <&tps65913_smps9>; + + regulators { + tps65913_smps123: smps123 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + tps65913_smps45: smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps7: smps7 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps8: smps8 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps9: smps9 { + regulator-name = "vdd-sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + tps65913_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_ldo1: ldo1 { + regulator-name = "vdd-hdmi-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + ti,roof-floor = <3>; + }; + + tps65913_ldo2: ldo2 { + regulator-name = "vdd-2v8-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4 { + regulator-name = "vdd-1v2-cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo5 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6 { + regulator-name = "vdd-dev"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "vdd-2v8-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + tps65913_ldo8: ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + tps65913_ldo9: ldo9 { + regulator-name = "vdd-sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + }; + + tps65913_ldoln: ldoln { + regulator-name = "vdd-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "vdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + }; + }; + }; + }; + + ahub@70080000 { + i2s@70080300 { + status = "okay"; + }; + }; + + mmc@78000000 { + /* WiFi */ + }; + + /* MicroSD card */ + mmc@78000400 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&tps65913_ldo9>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_default>; + }; + + mmc@78000600 { + /* eMMC */ + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-udc"; + status = "okay"; + dr_mode = "peripheral"; + + /* Peripheral USB via ASUS connector */ + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + + /* Host USB via dock */ + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <224>; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_default>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + label = "GPIO Buttons"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + sound { + compatible = "asus,tegra-audio-rt5639-tf701t", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "Asus Transformer Pad TF701T RT5639"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_default>; + }; + + vdd_5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_lcd: regulator-vdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&tps65913_smps8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + + pinctrl-names = "default"; + pinctrl-0 = <&vdd_lcd_default>; + }; + + vdd_usd: regulator-vdd-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd_slot"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + vin-supply = <&tps65913_smps9>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_vdd_default>; + }; +}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ce7410ee08b82..8b45f4617b2f3 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -105,7 +105,7 @@ status = "disabled"; }; - dsi@54300000 { + dsia: dsi@54300000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIA>, @@ -121,7 +121,7 @@ #size-cells = <0>; }; - dsi@54400000 { + dsib: dsi@54400000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, -- GitLab From 87d9cf2e846968c7ca8e2a3299e4fb93899bd7fc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:57 +0300 Subject: [PATCH 605/965] ARM: tegra: Add device-tree for Pegatron Chagall Add device-tree for Pegatron Chagall, which is a NVIDIA Tegra30-based Android tablet. Link: https://wiki.postmarketos.org/wiki/Pegatron_Chagall_(pegatron-chagall) Co-developed-by: Raffaele Tranquillini Signed-off-by: Raffaele Tranquillini Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- .../arm/boot/dts/tegra30-pegatron-chagall.dts | 2859 +++++++++++++++++ 2 files changed, 2861 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faaeae1f2a58d..8f93e9e65a7ce 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1329,7 +1329,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts new file mode 100644 index 0000000000000..f4b2d4218849c --- /dev/null +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -0,0 +1,2859 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + mmc2 = &sdmmc3; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-AH663 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c3: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + + /* AsahiKASEI AK8975 magnetometer sensor */ + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vdd_3v3_sen>; + vid-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sen>; + vlogic-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c5: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_1v8_vio>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vddio_1v2_ddr>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + pmic-sleep-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>, + <2 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Chagall */ + + vddio_1v2_ddr: vdd2 { + regulator-name = "vddio_1v2_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <3200000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_1v3_cam_isp"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_sen: regulator-sensors { + compatible = "regulator-fixed"; + regulator-name = "sen_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb1: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_micro_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb3: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_typea_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00038000 0x00038000 0x00038000 + 0x00038000 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10404 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x00060220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0200003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000a0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-AH663 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&vdd_vbus_usb1>; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_vbus_usb3>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "jeida-24"; + + panel-timing { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + vsync-len = <5>; + vfront-porch = <3>; + vback-porch = <12>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-insert { + label = "Chagall Dock"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + sound { + compatible = "pegatron,tegra-audio-wm8903-chagall", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Pegatron Chagall WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1R", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Chagall from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- GitLab From ef6fb9875ce0f495115ebb22a635a1aaafc0f467 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:13:58 +0300 Subject: [PATCH 606/965] ARM: tegra: Add device-tree for 1080p version of Nyan Big Add dedicated device-tree for 1080p version of Nyan Big in order to describe display panel properly. FHD panel doesn't support modes other than 1080p, hence it's wrong to use incompatible lower resolution panel in device-tree. Tested-by: Thomas Graichen Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8f93e9e65a7ce..a8763a75b3b24 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1341,6 +1341,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-apalis-v1.2-eval.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ tegra124-nyan-blaze.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts new file mode 100644 index 0000000000000..d35fb79d2f51b --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan-big.dts" + +/ { + /* Version of Nyan Big with 1080p panel */ + panel { + compatible = "auo,b133htn01"; + }; +}; -- GitLab From e6fd5c1e9fc5b35ad855cf748cc18b86776b6389 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Sun, 12 Dec 2021 00:13:59 +0300 Subject: [PATCH 607/965] ARM: tegra: Add usb-role-switch property to USB OTG ports If an USB port is an OTG port, then we should add the usb-role-switch property. Otherwise XUSB setup fails and therefore padctl is unable to set up the ports. This leads to broken USB and PCIe ports. Add the usb-role-switch properties to Tegra124 device-trees to fix the problem. The error message shown without this patch is e.g: usb2-0: usb-role-switch not found for otg mode [digetx@gmail.com: improved commit message] Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Stefan Eichenberger Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 + arch/arm/boot/dts/tegra124-apalis.dtsi | 1 + arch/arm/boot/dts/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/tegra124-venice2.dts | 2 +- 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f5440ae14cb4e..dbb0da08cb95d 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1888,6 +1888,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 1d83f2e254c58..d3f16c117b0ca 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1880,6 +1880,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 998b129321f89..cab0a6e95b7e5 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -466,6 +466,7 @@ vbus-supply = <&vdd_usb1_vbus>; status = "okay"; mode = "otg"; + usb-role-switch; }; usb2-1 { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7985d1cbc1c08..232c90604df9f 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -973,7 +973,7 @@ usb2-0 { status = "okay"; mode = "otg"; - + usb-role-switch; vbus-supply = <&vdd_usb1_vbus>; }; -- GitLab From 770586291f9a99c0abb6edee7d709a189355ac7e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:00 +0300 Subject: [PATCH 608/965] ARM: tegra: Enable HDMI CEC on Nyan Enable HDMI CEC on Nyan Chromebooks. It allows to control TV over HDMI. Suggested-by: Thomas Graichen Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index cab0a6e95b7e5..e702f91e07073 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -390,6 +390,10 @@ nvidia,sys-clock-req-active-high; }; + cec@70015000 { + status = "okay"; + }; + hda@70030000 { status = "okay"; }; -- GitLab From 894ea1121b29713c5da17e1032d1049f31e11d19 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:01 +0300 Subject: [PATCH 609/965] ARM: tegra: Enable CPU DFLL on Nyan Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due to Linux kernel CPUFreq driver which didn't support suspend-resume. That problem was fixed years ago, but DFLL was never re-enabled. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index e702f91e07073..f693daad68d85 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -532,7 +532,7 @@ /* CPU DFLL clock */ clock@70110000 { - status = "disabled"; + status = "okay"; vdd-cpu-supply = <&vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; -- GitLab From 7525c2a354e083a33f8775f810edd544f11ec108 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:02 +0300 Subject: [PATCH 610/965] ARM: tegra: Add CPU thermal zones to Nyan device-tree CPU of Nyan Chromebooks is overheating badly because apparently hardware soctherm controller doesn't work well. Add CPU thermal zones to enable software thermal control over CPU and fix the overheat trouble. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 49 +++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f693daad68d85..a93cfb492ba10 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include "tegra124.dtsi" / { @@ -87,7 +88,7 @@ interrupts = ; }; - temperature-sensor@4c { + tmp451: temperature-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; interrupt-parent = <&gpio>; @@ -789,6 +790,52 @@ gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; priority = <200>; }; + + cpus { + cpu0: cpu@0 { + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tmp451 0>; + + trips { + cpu_passive_trip: cpu-alert0 { + /* throttle at 70C until temperature drops to 69.8C */ + temperature = <70000>; + hysteresis = <200>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; #include "cros-ec-keyboard.dtsi" -- GitLab From a28c1b4f11fc201103faf51902bb207edba76c73 Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:14:06 +0300 Subject: [PATCH 611/965] ARM: tegra: nexus7: Use common LVDS display device-tree Make Nexus 7 device-tree to use common LVDS bridge description. This makes device-trees more consistent. [digetx@gmail.com: factored Nexus7 change into separate patch and wrote commit message] Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../tegra30-asus-nexus7-grouper-common.dtsi | 54 ++----------------- 1 file changed, 3 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ab33ceb63fffb..d79a99470ac20 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -8,6 +8,7 @@ #include "tegra30.dtsi" #include "tegra30-cpu-opp.dtsi" #include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" / { aliases { @@ -59,21 +60,6 @@ }; }; - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port@0 { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <24>; - }; - }; - }; - }; - }; - gpio@6000d000 { init-mode-hog { gpio-hog; @@ -1116,20 +1102,14 @@ */ compatible = "panel-lvds"; - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - width-mm = <94>; height-mm = <150>; rotation = <180>; data-mapping = "jeida-24"; - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; + /* DDC unconnected on Nexus 7 */ + /delete-property/ ddc-i2c-bus; }; firmware { @@ -1181,34 +1161,6 @@ }; }; - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; -- GitLab From e6e395578a6e92307c54232bc695bb08b32b0f86 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:14:08 +0300 Subject: [PATCH 612/965] ARM: tegra: Enable video decoder on Tegra114 Add Video Decoder Engine node to Tegra114 device-tree. Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8b45f4617b2f3..ae1be90a9385c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -17,6 +17,19 @@ reg = <0x80000000 0x0>; }; + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; @@ -253,6 +266,30 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra114-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA114_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64>, /* Chip revision */ -- GitLab From 19ebf10e8d837c0a296274b571a681b0c2885e4e Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:32:21 +0800 Subject: [PATCH 613/965] dt-bindings: arm64: dts: mediatek: Add mt7986 series MT7986 series is Mediatek's new 4-core SoC, which is mainly for wifi-router application. The difference between mt7986a and mt7986b is that some pins do not exist on mt7986b. Signed-off-by: Sam Shih Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211122123222.8016-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 723810cffce2e..0ffe1acf1344b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -77,6 +77,14 @@ properties: - enum: - mediatek,mt7629-rfb - const: mediatek,mt7629 + - items: + - enum: + - mediatek,mt7986a-rfb + - const: mediatek,mt7986a + - items: + - enum: + - mediatek,mt7986b-rfb + - const: mediatek,mt7986b - items: - enum: - mediatek,mt8127-moose -- GitLab From 50137c150f5f478e083b0b24b650de49f55ebfa2 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:32:22 +0800 Subject: [PATCH 614/965] arm64: dts: mediatek: add basic mt7986 support Add basic chip support for Mediatek mt7986, include basic uart nodes, rng node and watchdog node. Add cpu node, timer node, gic node, psci and reserved-memory node for ARM Trusted Firmware. Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123222.8016-3-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 37 +++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 148 +++++++++++++++++++ 3 files changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 1613259b68657..0127284dbc2d0 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts new file mode 100644 index 0000000000000..6911862390d72 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi new file mode 100644 index 0000000000000..77906839cc853 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + system_clk: dummy40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + enable-method = "psci"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&system_clk>; + clock-names = "rng"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + }; + +}; -- GitLab From fd31f778da81fec188f3ac8e03da4338642a8f08 Mon Sep 17 00:00:00 2001 From: Prashant Malani Date: Thu, 9 Dec 2021 11:51:12 -0800 Subject: [PATCH 615/965] arm64: dts: mt8183: kukui: Add Type C node Add a node describing the USB Type C connector, in order to utilize the Chromium OS USB Type-C driver that enumerates Type-C ports and connected cables/peripherals and makes them visible to userspace. Cc: Alexandru M Stan Cc: Benson Leung Signed-off-by: Prashant Malani Reviewed-by: Alexandru M Stan Reviewed-by: Benson Leung Link: https://lore.kernel.org/r/20211209195112.366176-1-pmalani@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 94c13c4591944..0f9480f912610 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -886,6 +886,20 @@ cbas { compatible = "google,cros-cbas"; }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "sink"; + }; + }; }; }; -- GitLab From c3a064a32ed98437dd62ff30e07a4ea3c659852f Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:35:51 +0800 Subject: [PATCH 616/965] arm64: dts: mediatek: add pinctrl support for mt7986a Add mt7986a pinctrl node, and update pinmux setting for mt7986a Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123552.8218-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 20 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 6911862390d72..5cd760abff51b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -29,9 +29,29 @@ }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; status = "okay"; }; + +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 77906839cc853..b8da76b6ba471 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -107,6 +107,27 @@ status = "disabled"; }; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; -- GitLab From f40c0f800f15e9e3566cb39a9eee2855c634eb5f Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:35:52 +0800 Subject: [PATCH 617/965] arm64: dts: mediatek: add pinctrl support for mt7986b Add mt7986b pinctrl node Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123552.8218-3-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 29 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 12 ++++++++ 3 files changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 0127284dbc2d0..8c1e18032f9f3 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts new file mode 100644 index 0000000000000..5fb752edd7543 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986b.dtsi" + +/ { + model = "MediaTek MT7986b RFB"; + compatible = "mediatek,mt7986b-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi new file mode 100644 index 0000000000000..23923b9f8944b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7986a.dtsi" + +&pio { + compatible = "mediatek,mt7986b-pinctrl"; + gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; +}; -- GitLab From c02b360ca67ebeb9de07b47b2fe53f964c2561d1 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 9 Dec 2021 17:53:41 +0000 Subject: [PATCH 618/965] arm64: dts: qcom: c630: Fix soundcard setup Currently Soundcard has 1 rx device for headset and SoundWire Speaker Playback. This setup has issues, ex if we try to play on headset the audio stream is also sent to SoundWire Speakers and we will hear sound in both headsets and speakers. Make a separate device for Speakers and Headset so that the streams are different and handled properly. Fixes: 45021d35fcb2 ("arm64: dts: qcom: c630: Enable audio support") Signed-off-by: Srinivas Kandagatla Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209175342.20386-2-srinivas.kandagatla@linaro.org --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index d6b2ba4396f68..2e882a977e2c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -523,6 +523,10 @@ dai@1 { reg = <1>; }; + + dai@2 { + reg = <2>; + }; }; &sound { @@ -535,6 +539,7 @@ "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT", "MM_DL1", "MultiMedia1 Playback", + "MM_DL3", "MultiMedia3 Playback", "MultiMedia2 Capture", "MM_UL2"; mm1-dai-link { @@ -551,6 +556,13 @@ }; }; + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + slim-dai-link { link-name = "SLIM Playback"; cpu { @@ -580,6 +592,21 @@ sound-dai = <&wcd9340 1>; }; }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; + }; + }; }; &tlmm { -- GitLab From ef10e1b89508d3315e47e23098fec60b33b1f6b3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 9 Dec 2021 17:53:42 +0000 Subject: [PATCH 619/965] arm64: dts: qcom: c630: add headset jack and button detection support Add MBHC support available in WCD934X codec. Signed-off-by: Srinivas Kandagatla Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209175342.20386-3-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 2e882a977e2c4..58845a14805f6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -771,6 +771,9 @@ vdd-tx-supply = <&vreg_s4a_1p8>; vdd-rx-supply = <&vreg_s4a_1p8>; vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { left_spkr: wsa8810-left{ -- GitLab From 202f69cd4e1dad6c86a35d8b29fc693877c6c91d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 2 Dec 2021 01:43:28 +0100 Subject: [PATCH 620/965] Revert "arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer" This reverts commit ed9500c1df59437856d43e657f185fb1eb5d817d. The clock-frequency property was meant to aid platforms with broken firmwares that don't set up the timer properly on their own. Don't include it where it is not the case. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211202004328.459899-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7323ed74f41a7..53b39e718fb66 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3193,6 +3193,5 @@ , , ; - clock-frequency = <19200000>; }; }; -- GitLab From 409fd3f10c0b71dabff735d5f290096d6bb6b4df Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 19:47:06 +0100 Subject: [PATCH 621/965] arm64: qcom: dts: drop legacy property #stream-id-cells Property #stream-id-cells is legacy leftover and isn't currently documented nor used. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211208184707.100716-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 - 8 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1ac78d9909abf..91bc974aeb0a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -962,7 +962,6 @@ gpu: gpu@b00000 { compatible = "qcom,adreno-530.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0x00b00000 0x3f000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 408f265e277b6..f273bc1ff629b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1446,7 +1446,6 @@ iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; - #stream-id-cells = <16>; status = "disabled"; gpu_opp_table: opp-table { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index faf8b807d0ff8..2151cd8c8c7ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1952,7 +1952,6 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-618.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, <0 0x05061000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 40b409f279f5f..937c2e0e93eb9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1753,7 +1753,6 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>, <0 0x03d9e000 0 0x1000>, <0 0x03d61000 0 0x800>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b75bb87ed2900..9217c3a51f791 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1019,7 +1019,6 @@ adreno_gpu: gpu@5000000 { compatible = "qcom,adreno-508.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0x05000000 0x40000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 526087586ba42..ff344a9a81a63 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4415,7 +4415,6 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 81b4ff2cc4cdd..6012322a59846 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1785,7 +1785,6 @@ compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; - #stream-id-cells = <16>; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 40f18d539d80e..5617a46e5ccdd 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2399,7 +2399,6 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; -- GitLab From 4cc7c85cccc87e436a86b4281ddcd886eb0bf58f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 20:25:30 -0700 Subject: [PATCH 622/965] arm64: dts: qcom: pm8998: Add ADC Thermal Monitor node Add a node for the ADC Thermal Monitor found in the PM8998 PMIC. This is used to connect thermal zones with ADC channels. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20211005032531.2251928-4-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 6f5bb6b37ec2a..d09f2954b6f99 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -84,6 +84,16 @@ }; }; + pm8998_adc_tm: adc-tm@3400 { + compatible = "qcom,spmi-adc-tm-hc"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; -- GitLab From d5e12f3823aed1e35ee2411bdf0ab61dc1011387 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 20:25:31 -0700 Subject: [PATCH 623/965] arm64: dts: qcom: sdm845: mtp: Add vadc channels and thermal zones Downstream defines four ADC channels related to thermal sensors external to the PM8998 and two channels for internal voltage measurements. Add these to the upstream SDM845 MTP, describe the thermal monitor channels and add thermal_zones for these. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20211005032531.2251928-5-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 140 ++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 5e6e8f4fb5be0..7713e8060c5b6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -9,6 +9,8 @@ #include #include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; @@ -45,6 +47,68 @@ vin-supply = <&vph_pwr>; }; + + thermal-zones { + xo_thermal: xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 1>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + msm_thermal: msm-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 2>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pa_thermal: pa-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 3>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + quiet_thermal: quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 4>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + }; }; &adsp_pas { @@ -467,6 +531,82 @@ firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; }; +&pm8998_adc { + adc-chan@4c { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@4d { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@4f { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@51 { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@83 { + reg = ; + label = "vph_pwr"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@85 { + reg = ; + label = "vcoin"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8998_adc_tm { + status = "okay"; + + xo-thermistor@1 { + reg = <1>; + io-channels = <&pm8998_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-thermistor@2 { + reg = <2>; + io-channels = <&pm8998_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-thermistor@3 { + reg = <3>; + io-channels = <&pm8998_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-thermistor@4 { + reg = <4>; + io-channels = <&pm8998_adc ADC5_AMUX_THM5_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &qupv3_id_1 { status = "okay"; }; -- GitLab From c8b9d64bb262033775ff64dde6ca7cf18899651b Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 13 Dec 2021 20:02:28 +0100 Subject: [PATCH 624/965] arm64: dts: qcom: sdm845: add QFPROM chipset specific compatible Use correct compatible according to dt-binding. Fixes + few other lines of `make qcom/sdm845-oneplus-fajita.dtb`: arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: qfprom@784000: compatible: ['qcom,qfprom'] is too short From schema: Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213190228.106924-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ff344a9a81a63..cfdeaa81f1bbc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1078,7 +1078,7 @@ }; qfprom@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; -- GitLab From 72cb4c48a46a7cfa58eb5842c0d3672ddd5bd9ad Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 7 Dec 2021 09:27:10 +0200 Subject: [PATCH 625/965] arm64: dts: qcom: ipq6018: Fix gpio-ranges property There must be three parameters in gpio-ranges property. Fixes this not very helpful error message: OF: /soc/pinctrl@1000000: (null) = 3 found 3 Fixes: 1e8277854b49 ("arm64: dts: Add ipq6018 SoC and CP01 board support") Cc: Sricharan R Signed-off-by: Baruch Siach Tested-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/8a744cfd96aff5754bfdcf7298d208ddca5b319a.1638862030.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 933b56103a464..66ec5615651d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -220,7 +220,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 80>; + gpio-ranges = <&tlmm 0 0 80>; interrupt-controller; #interrupt-cells = <2>; -- GitLab From 5188049c9b36d718124e2cce91803a26a34a0ad6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:30 +0530 Subject: [PATCH 626/965] arm64: dts: qcom: Add base SM8450 DTSI This add based DTSI for SM8450 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to shell with console on boards with this SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 476 +++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi new file mode 100644 index 0000000000000..96fbf4be3f897 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <327>; + exit-latency-us = <1502>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-off"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + local-timer-stop; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8450", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17423000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17425000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17427000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17429000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x1742b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x1742d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>, + <0x0 0x17a30000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8450-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; -- GitLab From ec950d55728459248e78f5c70ab3e3c2f7c22e38 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:31 +0530 Subject: [PATCH 627/965] arm64: dts: qcom: sm8450: Add tlmm nodes Add tlmm node found in SM8450 SoC and uart pin configuration Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 96fbf4be3f897..fb93d53d34335 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,8 @@ reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +368,32 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx { + pins = "gpio26"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx { + pins = "gpio27"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- GitLab From 285f97bc4b017b013d273a69ba3ee12252990812 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:32 +0530 Subject: [PATCH 628/965] arm64: dts: qcom: sm8450: Add reserved memory nodes Add the reserved memory nodes for SM8450. This is based on the downstream documentation. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-4-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 221 +++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fb93d53d34335..d9439c6ebfa2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -310,6 +310,227 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_dt_log_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: memory@80640000 { + reg = <0x0 0x80640000 0x0 0x180000>; + no-map; + }; + + xbl_sc_mem: memory@807c0000 { + reg = <0x0 0x807c0000 0x0 0x40000>; + no-map; + }; + + aop_image_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: memory@808a0000 { + reg = <0x0 0x808a0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: memory@808e0000 { + reg = <0x0 0x808e0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: memory@808e4000 { + reg = <0x0 0x808e4000 0x0 0x10000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: memory@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + camera_mem: memory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x700000>; + no-map; + }; + + adsp_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x2100000>; + no-map; + }; + + slpi_mem: memory@88000000 { + reg = <0x0 0x88000000 0x0 0x1900000>; + no-map; + }; + + cdsp_mem: memory@89900000 { + reg = <0x0 0x89900000 0x0 0x2000000>; + no-map; + }; + + ipa_fw_mem: memory@8b900000 { + reg = <0x0 0x8b900000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8b910000 { + reg = <0x0 0x8b910000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: memory@8b91a000 { + reg = <0x0 0x8b91a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: memory@8ba00000 { + reg = <0x0 0x8ba00000 0x0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: memory@8bb80000 { + reg = <0x0 0x8bb80000 0x0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: memory@8bbe0000 { + reg = <0x0 0x8bbe0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: memory@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x13200000>; + no-map; + }; + + cvp_mem: memory@9ee00000 { + reg = <0x0 0x9ee00000 0x0 0x700000>; + no-map; + }; + + global_sync_mem: memory@a6f00000 { + reg = <0x0 0xa6f00000 0x0 0x100000>; + no-map; + }; + + /* uefi region can be reused by APPS */ + + /* Linux kernel image is loaded at 0xa0000000 */ + + oem_vm_mem: memory@bb000000 { + reg = <0x0 0xbb000000 0x0 0x5000000>; + no-map; + }; + + mte_mem: memory@c0000000 { + reg = <0x0 0xc0000000 0x0 0x20000000>; + no-map; + }; + + qheebsp_reserved_mem: memory@e0000000 { + reg = <0x0 0xe0000000 0x0 0x600000>; + no-map; + }; + + cpusys_vm_mem: memory@e0600000 { + reg = <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + hyp_reserved_mem: memory@e0a00000 { + reg = <0x0 0xe0a00000 0x0 0x100000>; + no-map; + }; + + trust_ui_vm_mem: memory@e0b00000 { + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + no-map; + }; + + trust_ui_vm_qrtr: memory@e55f3000 { + reg = <0x0 0xe55f3000 0x0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: memory@e55fc000 { + reg = <0x0 0xe55fc000 0x0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: memory@e5600000 { + reg = <0x0 0xe5600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: memory@e8800000 { + reg = <0x0 0xe8800000 0x0 0x100000>; + no-map; + }; + + tags_mem: memory@e8900000 { + reg = <0x0 0xe8900000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: memory@e9b00000 { + reg = <0x0 0xe9b00000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: memory@ea000000 { + reg = <0x0 0xea000000 0x0 0x3900000>; + no-map; + }; + + trusted_apps_ext_mem: memory@ed900000 { + reg = <0x0 0xed900000 0x0 0x3b00000>; + no-map; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; -- GitLab From 892d5395396d5515c42e502810884225776b3b10 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:33 +0530 Subject: [PATCH 629/965] arm64: dts: qcom: sm8450: add smmu nodes Add the apps smmu node as found in the SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-5-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d9439c6ebfa2d..d29680c405bf6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -615,6 +615,109 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- GitLab From 24de05c38e6bfe80fccc3b632c142accfaa7232d Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:34 +0530 Subject: [PATCH 630/965] arm64: dts: qcom: Add base SM8450 QRD DTS Add DTS for Qualcomm QRD platform which uses SM8450 SoC and mark the reserved nodes. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-6-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a3eedb8b33ee4..f7232052d2862 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -121,3 +121,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts new file mode 100644 index 0000000000000..8dcd41c4e5ab5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 QRD"; + compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + +&uart7 { + status = "okay"; +}; -- GitLab From 128914ad230354ab4af9c3b86fdce2147f467553 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:35 +0530 Subject: [PATCH 631/965] arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes Add the RPMH regulators found in QRD-SM8450 platform Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-7-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 322 ++++++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8dcd41c4e5ab5..2ab19608a455f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm8450.dtsi" / { @@ -18,6 +19,327 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; }; &qupv3_id_0 { -- GitLab From 07fa917a335e139a108e94085c6beac3098e3874 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:36 +0530 Subject: [PATCH 632/965] arm64: dts: qcom: sm8450: add ufs nodes Add the UFS and QMP PHY node for SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-8-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d29680c405bf6..9556d2fc46e06 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -815,6 +815,78 @@ clocks = <&xo_board>; }; }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8450-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", "ref_aux", "qref"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + #clock-cells = <0>; + }; + }; }; timer { -- GitLab From 8f8f98c881686d21fc937f469d3a198f2f9bb9ba Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:37 +0530 Subject: [PATCH 633/965] arm64: dts: qcom: sm8450-qrd: enable ufs nodes Enable the UFS and phy node and add the regulators used by them. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-9-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 2ab19608a455f..4b7ad190d538f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -353,3 +353,23 @@ &uart7 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; -- GitLab From 61eba74e473ed4cd64ec17440092f4a98913cda3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 10:04:38 +0530 Subject: [PATCH 634/965] arm64: dts: qcom: sm8450: Add rpmhpd node This adds RPMH power domain found in SM8450 SoC Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-10-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9556d2fc46e06..8fff4d54933fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -814,6 +815,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8450-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; ufs_mem_hc: ufshc@1d84000 { -- GitLab From 015a89f0d317dce4d2174059155c2fc39db7cbc8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 15 Dec 2021 10:04:39 +0530 Subject: [PATCH 635/965] arm64: dts: qcom: sm8450: add cpufreq support The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-11-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8fff4d54933fc..56e3e8f771bde 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -44,6 +44,7 @@ next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -61,6 +62,7 @@ next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -75,6 +77,7 @@ next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -89,6 +92,7 @@ next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +107,7 @@ next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -117,6 +122,7 @@ next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -132,6 +138,7 @@ next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -146,6 +153,7 @@ next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -867,6 +875,21 @@ }; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; -- GitLab From bf0a257a9418ebcbe6ab2a73728f76969942e52a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 10:04:40 +0530 Subject: [PATCH 636/965] arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes Add device tree nodes for two i2c blocks: i2c13 and i2c14. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-12-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 56e3e8f771bde..62082ed5335dd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -582,6 +582,44 @@ }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -609,6 +647,20 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins = "gpio48", "gpio49"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins = "gpio52", "gpio53"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; -- GitLab From ef5ad2608511596b8bd28f1e2b4fa8fadfd2f536 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 23 Nov 2021 23:19:22 +0700 Subject: [PATCH 637/965] ARM: dts: qcom: Drop input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211123161919.1506755-1-danct12@riseup.net --- arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 1 - arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 1 - arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 1 - arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts | 1 - 7 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index f8c97efc61fc2..0cee62c7b8b04 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -19,7 +19,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index ea15b645b2299..6d77e0f8ca4d4 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 30ee913faae6a..0691361701985 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -450,7 +450,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 003f0fa9c8572..96e1c978b878c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -349,7 +349,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts index 398a3eaf306b4..79e2cfbbb1ba2 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts index b4dd85bd4faf0..e66937e3f7dd4 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 9743beebd84d0..a62e5c25b23c0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; -- GitLab From eb197dfe389a35566c8e27c537355aaed04fed67 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 10 Dec 2021 10:23:19 -0300 Subject: [PATCH 638/965] ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMaster Add DTS of BSH SMM-M2 SystemMaster. This version comes with: - 128 MiB DDR3 RAM - 256 MiB Nand - wifi - bluetooth Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts | 146 +++++++++++++++++++++++ 2 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 51a6dd6871918..ab965ad2d6a9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -701,7 +701,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ulz-14x14-evk.dtb + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts new file mode 100644 index 0000000000000..59bcfc9a6b10f --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include +#include "imx6ulz.dtsi" + +/ { + model = "BSH SMM M2"; + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; + + chosen { + stdout-path = &uart4; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + cap-sdio-irq; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ + >; + }; +}; -- GitLab From 538e5f7106f61e6b8404b0509f71f518123968cd Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 8 Dec 2021 22:40:45 +1000 Subject: [PATCH 639/965] ARM: dts: imx7d-remarkable2: add wacom digitizer device Add Wacom I2C support for the reMarkable 2 eInk tablet using the generic I2C HID framework. Signed-off-by: Alistair Francis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-remarkable2.dts | 59 +++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index 89cbf13097a43..a2a91bfdd98e2 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -34,6 +34,19 @@ startup-delay-us = <150>; }; + reg_digitizer: regulator-digitizer { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_DIGITIZER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_digitizer_reg>; + pinctrl-1 = <&pinctrl_digitizer_reg>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; /* 100 ms */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -51,6 +64,26 @@ assigned-clock-rates = <0>, <32768>; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + wacom_digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + hid-descr-addr = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wacom>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vdd-supply = <®_digitizer>; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -117,6 +150,25 @@ fsl,ext-reset-output; }; +&iomuxc_lpsr { + pinctrl_digitizer_reg: digitizerreggrp { + fsl,pins = < + /* DIGITIZER_PWR_EN */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 + >; + }; + + pinctrl_wacom: wacomgrp { + fsl,pins = < + /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ + /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ + /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ + >; + }; +}; + &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < @@ -125,6 +177,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- GitLab From ee47d510b4d2a771ff42b2dca637195ec5e24d0b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 11 Dec 2021 23:17:43 +0100 Subject: [PATCH 640/965] arm64: dts: nitrogen8-som: correct network PHY reset Add the missing reset-gpios property to allow Linux to fully reset the network PHY and fix the pinmux to add the neccessary pull-ups for the PHY strap configuration. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi index 36fc428ebe300..5f27d3a17ddbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi @@ -69,6 +69,9 @@ reg = <4>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; @@ -191,13 +194,13 @@ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 >; }; -- GitLab From 92d2c17edb2a796ed548b3b50da46c8a29e28e0f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 12 Dec 2021 14:49:12 +0100 Subject: [PATCH 641/965] arm64: dts: nitrogen8-som: correct i2c1 pad-ctrl The slew rate and drive-strength of the i2c1 pads were much too high. Bring them down to avoid signal quality issues. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi index 5f27d3a17ddbd..395f77b5aca7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi @@ -206,8 +206,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 >; }; -- GitLab From c720e38f4c2dd1e0b5cf4f7dcf8bb6951cd3856d Mon Sep 17 00:00:00 2001 From: Johann Neuhauser Date: Mon, 13 Dec 2021 12:18:08 +0100 Subject: [PATCH 642/965] ARM: imx_v6_v7_defconfig: Enable for DHCOM devices required RTC_DRV_RV3029C2 All imx6 DHCOM devices uses a on module gold cap/battery powered i2c rtc "microcrystal,rv3029", which isn't enabled in the imx_v6_v7_defconfig. The rtc for all imx6 DHCOM devices is defined in: imx6qdl-dhcom-som.dtsi To have a working clock on all imx6qdl DHCOM based devices, enable the driver. Signed-off-by: Johann Neuhauser Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 1fbb8e45e6048..f7498df08dfe7 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -378,6 +378,7 @@ CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_RC5T619=y +CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_DA9063=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y -- GitLab From 0baddea60e8d536fd240008882128fc32eda74d6 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 29 Nov 2021 19:26:33 +0100 Subject: [PATCH 643/965] arm64: dts: allwinner: h6: Add Hantro G2 node H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 46ed529a4dc24..fbe94abbb1f9c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -153,6 +153,15 @@ }; }; + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + video-codec@1c0e000 { compatible = "allwinner,sun50i-h6-video-engine"; reg = <0x01c0e000 0x2000>; -- GitLab From 842912c42e88748648901e22c238834f7a6ccb26 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 13 Dec 2021 21:40:47 +0100 Subject: [PATCH 644/965] arm64: dts: imx8mm: don't assign PLL2 in SoC dtsi The base i.MX8MM dtsi changes the audio PLL2 rate, which gets in the way if it should be used for anything else than audio. As this PLL doesn't seem to be used by any upstream supported board, just remove the rate configuration to allow boards to set it up as they wish. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c84d768604417..f77f90ed416f9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -619,8 +619,7 @@ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; + <&clk IMX8MM_AUDIO_PLL1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, <&clk IMX8MM_SYS_PLL3_OUT>, @@ -630,8 +629,7 @@ <400000000>, <750000000>, <594000000>, - <393216000>, - <361267200>; + <393216000>; }; src: reset-controller@30390000 { -- GitLab From 674d63dfadb5da1e28678574e5bce4793b9f65f3 Mon Sep 17 00:00:00 2001 From: Ioana Radulescu Date: Tue, 14 Dec 2021 01:23:34 -0600 Subject: [PATCH 645/965] arm64: dts: lx2160a-rdb: Add Inphi PHY node DPMAC5 and DPMAC6 are connected to 25G Inphi PHY Signed-off-by: Vicentiu Galanopulo Signed-off-by: Florin Chiculita Signed-off-by: Ioana Radulescu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 028ff8074b9d0..0ec41838e54ec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -49,6 +49,14 @@ managed = "in-band-status"; }; +&dpmac5 { + phy-handle = <&inphi_phy>; +}; + +&dpmac6 { + phy-handle = <&inphi_phy>; +}; + &dpmac17 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii-id"; @@ -109,6 +117,15 @@ }; }; +&emdio2 { + status = "okay"; + + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; -- GitLab From 519bace37b2d160a7a1cb4199f9828d12c28ba12 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 14 Dec 2021 01:23:35 -0600 Subject: [PATCH 646/965] arm64: dts: lx2160a: add optee-tz node Disabled by default in SoC dtsi and enables in board dts files. Signed-off-by: Pankaj Gupta Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 4 ++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index d858d9c8b583d..8354af0b31e36 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -156,6 +156,10 @@ }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 0ec41838e54ec..0c44b3cbef773 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -219,6 +219,10 @@ }; }; +&optee { + status = "okay"; +}; + &pcs_mdio3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index dc8661ebd1f66..3123dea573f68 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1751,4 +1751,12 @@ }; }; }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 67e07a8a42bd2..5b7c51c1e3c2b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -315,6 +315,10 @@ }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; -- GitLab From eb70c4a3b1aa2a9d6195ce8bb6ff09b40bc6451e Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Tue, 14 Dec 2021 01:23:36 -0600 Subject: [PATCH 647/965] arm64: dts: lx2160a-qds: Add mdio mux nodes The two external MDIO buses used to communicate with phy devices that are external to SOC are muxed in LX2160AQDS board. These buses can be routed to any one of the eight IO slots on LX2160AQDS board depending on value in fpga register 0x54. Additionally the external MDIO1 is used to communicate to the onboard RGMII phy devices. The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga register. Signed-off-by: Pankaj Bansal Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 8354af0b31e36..2ecfa90f5e28e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -31,6 +31,130 @@ regulator-boot-on; regulator-always-on; }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board PHY #1 RGMI1*/ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { /* On-board PHY #2 RGMI2*/ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &can0 { @@ -81,6 +205,14 @@ }; }; +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -107,6 +239,19 @@ &i2c0 { status = "okay"; + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; -- GitLab From a5b13770faf324e4cf25a9c0de323fca8dd789fa Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Tue, 14 Dec 2021 01:23:40 -0600 Subject: [PATCH 648/965] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes Enable USB3 HW LPM feature for lx2160a. Signed-off-by: Ran Wang Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 3123dea573f68..6274bec3ec326 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1023,6 +1023,7 @@ interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; @@ -1034,6 +1035,7 @@ interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; -- GitLab From 23817c8396730371662f47f33c30c29e45649a01 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 14 Dec 2021 01:23:41 -0600 Subject: [PATCH 649/965] arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0 adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2. Add speed modes properties supported by the two adapters in device tree node. Signed-off-by: Yangbo Lu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 5b7c51c1e3c2b..dcca026446d86 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -234,10 +234,17 @@ }; &esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; status = "okay"; }; &esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; status = "okay"; }; -- GitLab From cc03211c745a729d072a33133379c32411b5ce52 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 01:23:42 -0600 Subject: [PATCH 650/965] arm64: dts: lx2162a-qds: add interrupt line for RTC node Add interrupt line for RTC node on lx2162a-qds Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index dcca026446d86..a1644ceed154b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -317,6 +317,8 @@ rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */ + interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; -- GitLab From 20c7b41d03d3c1d75cd652a45554b3594e513e3d Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Tue, 14 Dec 2021 10:03:53 +0100 Subject: [PATCH 651/965] ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layer Add USB overcurrent pin muxing on SoM layer. On DRC02 and PDK2 the USB overcurrent pin isn't connected, but a USB hub on the board takes care of the USB overcurrent instead. Therefore disable it there with the property disable-over-current. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi index 3d0a50a9ab210..702cd4a1b2e61 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi @@ -95,6 +95,10 @@ rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi index dc21853706a56..dc89b554e694e 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -260,6 +260,10 @@ status = "okay"; }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index b2b7daf43ede7..5befbe13d1a3d 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -729,6 +729,7 @@ pinctrl_usbh1: usbh1-grp { fsl,pins = < MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 >; }; -- GitLab From e84e22c0c3b34898269eb054c6366a75b331d395 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Tue, 14 Dec 2021 03:32:33 -0600 Subject: [PATCH 652/965] arm64: dts: ls1028a: Add PCIe EP nodes Add PCIe EP nodes for ls1028a to support EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index fd3f3e8bb6ce7..9010c535252ad 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -637,6 +637,18 @@ status = "disabled"; }; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ @@ -664,6 +676,18 @@ status = "disabled"; }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; -- GitLab From dd3d936a1b17d2d63deb3347d8e8d1dad2a410a9 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:34 -0600 Subject: [PATCH 653/965] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc wakeup source for rdb and qds boards instead of the original flextimer1 which is used by PWM. The ftm_alarm0 node hence is disabled by default. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 6e2a1da662fb4..00d5b81bdef36 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -25,7 +25,7 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; }; chosen { @@ -234,6 +234,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 639f40740d563..6d26b010187c3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -21,7 +21,7 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; spi0 = &fspi; ethernet0 = &enetc_port0; ethernet1 = &enetc_port2; @@ -181,6 +181,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9010c535252ad..f2564faf70677 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1198,6 +1198,15 @@ reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; interrupts = ; + status = "disabled"; + }; + + ftm_alarm1: timer@2810000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2810000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = ; + status = "disabled"; }; }; -- GitLab From 71799672ea24d2935322d655d2407c1ccd7db9ff Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:35 -0600 Subject: [PATCH 654/965] arm64: dts: ls1028a: add flextimer based pwm nodes Add pwm nodes using flextimer controller. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f2564faf70677..5a7b26a1bad22 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -66,6 +66,13 @@ }; }; + rtc_clk: rtc-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1186,6 +1193,94 @@ reg = <0x01 0xf0800000 0x0 0x10000>; }; + pwm0: pwm@2800000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2800000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm1: pwm@2810000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2810000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm2: pwm@2820000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2820000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm3: pwm@2830000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2830000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm4: pwm@2840000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2840000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm5: pwm@2850000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2850000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm6: pwm@2860000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2860000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm7: pwm@2870000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2870000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + rcpm: power-controller@1e34040 { compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1e34040 0x0 0x1c>; -- GitLab From b2e2d3e02fb60f4d45843ceebef0465c59c8d392 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:37 -0600 Subject: [PATCH 655/965] arm64: dts: ls1028a-rdb: enable pwm0 Enable pwm0 on ls1028a-rdb board which uses flextimer1. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 6d26b010187c3..68c31cb8eead1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -286,6 +286,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sai4 { status = "okay"; }; -- GitLab From cbe9d948eadfe352ad45495a7cc5bf20a1b29d90 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:38 -0600 Subject: [PATCH 656/965] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 00d5b81bdef36..baa1cc9b98354 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -276,11 +276,6 @@ vcc-supply = <&sb_3v3>; }; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; @@ -322,6 +317,15 @@ }; +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + &enetc_port1 { phy-handle = <&qds_phy1>; phy-mode = "rgmii-id"; -- GitLab From 52b98481171eee3fa5abbedd57f9e64cbfb727e1 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Tue, 14 Dec 2021 03:32:39 -0600 Subject: [PATCH 657/965] arm64: dts: ls1028a-qds: enable lpuart1 LPUART nodes by default are disabled in LS1028A device tree, Enabling LPUART1 node. Signed-off-by: Vabhav Sharma Acked-by: Fugang Duan Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index baa1cc9b98354..782853a449cc6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -336,6 +336,10 @@ status = "okay"; }; +&lpuart1 { + status = "okay"; +}; + &sai1 { status = "okay"; }; -- GitLab From e426d63e752bdbe7d5ba2d872319dde9ab844a07 Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Tue, 14 Dec 2021 03:32:40 -0600 Subject: [PATCH 658/965] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Add overlays for various serdes protocols on LS1028A QDS board using different PHY cards. These should be applied at boot, based on serdes configuration. If no overlay is applied, only the RGMII interface on the QDS is available in Linux. Building device tree fragments requires passing the "-@" argument to dtc, which increases the base dtb size and might cause some platforms to fail to store the new binary. To avoid that, it would be nice to only pass "-@" for the platforms where fragments will be used, aka LS1028A-QDS. One approach suggested by Rob Herring is used here: https://lore.kernel.org/patchwork/patch/821645/ Also moved the enet* override nodes in dts file to be in alphabetic order. Signed-off-by: Alex Marginean Signed-off-by: Ioana Ciornei Signed-off-by: Dong Aisheng Signed-off-by: Jason Liu Signed-off-by: Vladimir Oltean Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 16 +++ .../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++ .../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++ .../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++ .../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 9 files changed, 595 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5018b8b1e5f23..6d8f0a5325875 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,4 +1,14 @@ # SPDX-License-Identifier: GPL-2.0 + +# required for overlay support +DTC_FLAGS_fsl-ls1028a-qds := -@ +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-899b := -@ +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts new file mode 100644 index 0000000000000..f748a2c12a70e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts new file mode 100644 index 0000000000000..8ffb707a15765 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts new file mode 100644 index 0000000000000..eb6a1e674f106 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts new file mode 100644 index 0000000000000..8e90c3088ba16 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts new file mode 100644 index 0000000000000..5d0a094e6c441 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mscc_felix_ports>; + __overlay__ { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts new file mode 100644 index 0000000000000..1ef743c48e84e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 782853a449cc6..177bc1405f0fe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -211,6 +211,16 @@ status = "okay"; }; +&enetc_port1 { + phy-handle = <&qds_phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { status = "okay"; }; @@ -326,17 +336,16 @@ }; }; -&enetc_port1 { - phy-handle = <&qds_phy1>; - phy-mode = "rgmii-id"; +&lpuart0 { status = "okay"; }; -&lpuart0 { +&lpuart1 { status = "okay"; }; -&lpuart1 { +&mscc_felix_port4 { + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5a7b26a1bad22..5bb8c26e08255 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1115,7 +1115,7 @@ interrupts = ; status = "disabled"; - ports { + mscc_felix_ports: ports { #address-cells = <1>; #size-cells = <0>; -- GitLab From 841b71c57bcf63137983bad340ffc7b6bfbc6b0a Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:05 +0100 Subject: [PATCH 659/965] ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board The PHYTEC PEV-EVAL-01 expansion board adds support for additional gpio-triggered user-leds and gpio-key support. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 +++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 75 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 9f7f9f98139dd..b057fa664a6b8 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index 2e70ea5623c66..db6e2cc36759d 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 65d2e483c1366..51ff601b1aec5 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi new file mode 100644 index 0000000000000..037b60197598b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + sleep { + label = "Sleep Button"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index f27d7ab42626a..06fe0c5315fc0 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6qp.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; -- GitLab From d3af422c0587f55f9d9d3375bf6bb61bea53f014 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:06 +0100 Subject: [PATCH 660/965] ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to connect parallel LCD displays, either with capacitive or resistive touch. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 ++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 123 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index b057fa664a6b8..8165fae2b1d11 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index db6e2cc36759d..bbf5097ca974f 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 51ff601b1aec5..95051e18324f2 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi new file mode 100644 index 0000000000000..393475cb0f4d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +/ { + display: display0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&peb_panel_lcd_in>; + }; + }; + }; + + panel-lcd { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_pwr>; + power-supply = <®_display>; + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + peb_panel_lcd_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; + + reg_display: regulator-peb-display { + compatible = "regulator-fixed"; + regulator-name = "peb-display"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c1 { + edt_ft5x06: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_NONE>; + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_disp0: disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_pwr: disp0pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_edt_ft5x06: edtft5x06grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 06fe0c5315fc0..343639cb035ce 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; -- GitLab From 0bc3e333a0c82ee8691bcfdf441644ce02bd8be0 Mon Sep 17 00:00:00 2001 From: Xiaoliang Yang Date: Thu, 16 Dec 2021 17:24:48 +0800 Subject: [PATCH 661/965] arm64: dts: imx8mp-evk: configure multiple queues on eqos Eqos ethernet support five queues on hardware, enable these queues and configure the priority of each queue. Uses Strict Priority as scheduling algorithms to ensure that the TSN function works. The priority of each queue is a bitmask value that maps VLAN tag priority to the queue. Since the hardware only supports five queues, this patch maps priority 0-4 to queues one by one, and priority 5-7 to queue 4. The total fifo size of 5 queues is 8192 bytes, if enable 5 queues with store-and-forward mode, it's not enough for large packets, which would trigger fifo overflow frequently. This patch set DMA to thresh mode to enable all 5 queues. Signed-off-by: Xiaoliang Yang Reviewed-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 68 ++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index cf03a82f9dcda..2eb9432106780 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -86,6 +86,9 @@ pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -103,6 +106,71 @@ realtek,clkout-disable; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { -- GitLab From 1bb0b8b195d821d009bae61248da14f2b17bd44a Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Tue, 14 Dec 2021 01:55:44 +0000 Subject: [PATCH 662/965] soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_init Since devm_ioremap_resource() function return error pointers. The pktdma_get_regs() function does not return NULL, It return error pointers too. Using IS_ERR() to check the return value to fix this. Signed-off-by: Miaoqian Lin Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20211214015544.7270-1-linmq006@gmail.com --- drivers/soc/ti/knav_dma.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index 591d14ebcb112..700d8eecd8c45 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -646,31 +646,31 @@ static int dma_init(struct device_node *cloud, struct device_node *dma_node) } dma->reg_global = pktdma_get_regs(dma, node, 0, &size); - if (!dma->reg_global) - return -ENODEV; + if (IS_ERR(dma->reg_global)) + return PTR_ERR(dma->reg_global); if (size < sizeof(struct reg_global)) { dev_err(kdev->dev, "bad size %pa for global regs\n", &size); return -ENODEV; } dma->reg_tx_chan = pktdma_get_regs(dma, node, 1, &size); - if (!dma->reg_tx_chan) - return -ENODEV; + if (IS_ERR(dma->reg_tx_chan)) + return PTR_ERR(dma->reg_tx_chan); max_tx_chan = size / sizeof(struct reg_chan); dma->reg_rx_chan = pktdma_get_regs(dma, node, 2, &size); - if (!dma->reg_rx_chan) - return -ENODEV; + if (IS_ERR(dma->reg_rx_chan)) + return PTR_ERR(dma->reg_rx_chan); max_rx_chan = size / sizeof(struct reg_chan); dma->reg_tx_sched = pktdma_get_regs(dma, node, 3, &size); - if (!dma->reg_tx_sched) - return -ENODEV; + if (IS_ERR(dma->reg_tx_sched)) + return PTR_ERR(dma->reg_tx_sched); max_tx_sched = size / sizeof(struct reg_tx_sched); dma->reg_rx_flow = pktdma_get_regs(dma, node, 4, &size); - if (!dma->reg_rx_flow) - return -ENODEV; + if (IS_ERR(dma->reg_rx_flow)) + return PTR_ERR(dma->reg_rx_flow); max_rx_flow = size / sizeof(struct reg_rx_flow); dma->rx_priority = DMA_PRIO_DEFAULT; -- GitLab From 66209e6fbd564f1bb3c69248423e4b761904a943 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:10 +0300 Subject: [PATCH 663/965] soc/tegra: Don't print error message when OPPs not available Previously we assumed that devm_tegra_core_dev_init_opp_table() will be used only by drivers that will always have device with OPP table, but this is not true anymore. For example now Tegra30 will have OPP table for PWM, but Tegra20 not and both use the same driver. Hence let's not print the error message about missing OPP table in the common helper, we can print it elsewhere. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/common.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 35c882da55fcd..32c346b72635a 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -136,9 +136,7 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev, */ err = devm_pm_opp_of_add_table(dev); if (err) { - if (err == -ENODEV) - dev_err_once(dev, "OPP table not found, please update device-tree\n"); - else + if (err != -ENODEV) dev_err(dev, "failed to add OPP table: %d\n", err); return err; -- GitLab From 765d95f8ac54af611c804bb956b79391cfc1d27b Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 30 Nov 2021 11:44:06 +0000 Subject: [PATCH 664/965] soc/tegra: pmc: Add reboot notifier The Tegra PMC driver implements a restart handler that supports Tegra specific reboot commands such as placing the device into 'recovery' mode in order to reprogram the platform. This is accomplished by setting the appropriate bit in the PMC scratch0 register prior to rebooting the platform. For Tegra platforms that support PSCI or EFI, the default Tegra restart handler is not called and the PSCI or EFI restart handler is called instead. Hence, for Tegra platforms that support PSCI or EFI, the Tegra specific reboot commands do not currently work. Fix this by moving the code that programs the PMC scratch0 register into a separate reboot notifier that will always be called on reboot. Signed-off-by: Jon Hunter Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 575d6d5b42941..6db0e31ac6fad 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1064,10 +1064,8 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) return tegra_powergate_remove_clamping(id); } -static int tegra_pmc_restart_notify(struct notifier_block *this, - unsigned long action, void *data) +static void tegra_pmc_program_reboot_reason(const char *cmd) { - const char *cmd = data; u32 value; value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); @@ -1085,6 +1083,25 @@ static int tegra_pmc_restart_notify(struct notifier_block *this, } tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); +} + +static int tegra_pmc_reboot_notify(struct notifier_block *this, + unsigned long action, void *data) +{ + if (action == SYS_RESTART) + tegra_pmc_program_reboot_reason(data); + + return NOTIFY_DONE; +} + +static struct notifier_block tegra_pmc_reboot_notifier = { + .notifier_call = tegra_pmc_reboot_notify, +}; + +static int tegra_pmc_restart_notify(struct notifier_block *this, + unsigned long action, void *data) +{ + u32 value; /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2890,6 +2907,14 @@ static int tegra_pmc_probe(struct platform_device *pdev) goto cleanup_sysfs; } + err = devm_register_reboot_notifier(&pdev->dev, + &tegra_pmc_reboot_notifier); + if (err) { + dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", + err); + goto cleanup_debugfs; + } + err = register_restart_handler(&tegra_pmc_restart_handler); if (err) { dev_err(&pdev->dev, "unable to register restart handler, %d\n", -- GitLab From aeecc50ace0480e6df565093e578b129902918db Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:35 +0300 Subject: [PATCH 665/965] soc/tegra: fuse: Reset hardware The FUSE controller is enabled at a boot time. Reset it in order to put hardware and clock into clean and disabled state. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 25 +++++++++++++++++++++++++ drivers/soc/tegra/fuse/fuse.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index f2151815db585..cc032729a143e 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -243,6 +244,30 @@ static int tegra_fuse_probe(struct platform_device *pdev) goto restore; } + fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); + if (IS_ERR(fuse->rst)) { + err = PTR_ERR(fuse->rst); + dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n", + fuse->rst); + goto restore; + } + + /* + * FUSE clock is enabled at a boot time, hence this resume/suspend + * disables the clock besides the h/w resetting. + */ + err = pm_runtime_resume_and_get(&pdev->dev); + if (err) + goto restore; + + err = reset_control_reset(fuse->rst); + pm_runtime_put(&pdev->dev); + + if (err < 0) { + dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); + goto restore; + } + /* release the early I/O memory mapping */ iounmap(base); diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index de58feba04350..1b719d85bd045 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -43,6 +43,7 @@ struct tegra_fuse { void __iomem *base; phys_addr_t phys; struct clk *clk; + struct reset_control *rst; u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset); u32 (*read)(struct tegra_fuse *fuse, unsigned int offset); -- GitLab From 88724b78a84c85350c21ac8d4432f2cf5a77a10a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:36 +0300 Subject: [PATCH 666/965] soc/tegra: fuse: Use resource-managed helpers Use resource-managed helpers to make code cleaner and more correct, properly releasing all resources in case of driver probe error. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++++++++++++++------------ drivers/soc/tegra/fuse/fuse-tegra20.c | 33 ++++++++++++++++++++++++--- 2 files changed, 48 insertions(+), 17 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index cc032729a143e..fe4f935ce73ad 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -182,6 +182,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { }, }; +static void tegra_fuse_restore(void *base) +{ + fuse->clk = NULL; + fuse->base = base; +} + static int tegra_fuse_probe(struct platform_device *pdev) { void __iomem *base = fuse->base; @@ -189,13 +195,16 @@ static int tegra_fuse_probe(struct platform_device *pdev) struct resource *res; int err; + err = devm_add_action(&pdev->dev, tegra_fuse_restore, base); + if (err) + return err; + /* take over the memory region from the early initialization */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); fuse->phys = res->start; fuse->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(fuse->base)) { err = PTR_ERR(fuse->base); - fuse->base = base; return err; } @@ -205,19 +214,20 @@ static int tegra_fuse_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to get FUSE clock: %ld", PTR_ERR(fuse->clk)); - fuse->base = base; return PTR_ERR(fuse->clk); } platform_set_drvdata(pdev, fuse); fuse->dev = &pdev->dev; - pm_runtime_enable(&pdev->dev); + err = devm_pm_runtime_enable(&pdev->dev); + if (err) + return err; if (fuse->soc->probe) { err = fuse->soc->probe(fuse); if (err < 0) - goto restore; + return err; } memset(&nvmem, 0, sizeof(nvmem)); @@ -241,7 +251,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) err = PTR_ERR(fuse->nvmem); dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", err); - goto restore; + return err; } fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); @@ -249,7 +259,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) err = PTR_ERR(fuse->rst); dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n", fuse->rst); - goto restore; + return err; } /* @@ -258,26 +268,20 @@ static int tegra_fuse_probe(struct platform_device *pdev) */ err = pm_runtime_resume_and_get(&pdev->dev); if (err) - goto restore; + return err; err = reset_control_reset(fuse->rst); pm_runtime_put(&pdev->dev); if (err < 0) { dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); - goto restore; + return err; } /* release the early I/O memory mapping */ iounmap(base); return 0; - -restore: - fuse->clk = NULL; - fuse->base = base; - pm_runtime_disable(&pdev->dev); - return err; } static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index 8ec9fc5e5e4b5..12503f563e360 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -94,9 +94,28 @@ static bool dma_filter(struct dma_chan *chan, void *filter_param) return of_device_is_compatible(np, "nvidia,tegra20-apbdma"); } +static void tegra20_fuse_release_channel(void *data) +{ + struct tegra_fuse *fuse = data; + + dma_release_channel(fuse->apbdma.chan); + fuse->apbdma.chan = NULL; +} + +static void tegra20_fuse_free_coherent(void *data) +{ + struct tegra_fuse *fuse = data; + + dma_free_coherent(fuse->dev, sizeof(u32), fuse->apbdma.virt, + fuse->apbdma.phys); + fuse->apbdma.virt = NULL; + fuse->apbdma.phys = 0x0; +} + static int tegra20_fuse_probe(struct tegra_fuse *fuse) { dma_cap_mask_t mask; + int err; dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); @@ -105,13 +124,21 @@ static int tegra20_fuse_probe(struct tegra_fuse *fuse) if (!fuse->apbdma.chan) return -EPROBE_DEFER; + err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_release_channel, + fuse); + if (err) + return err; + fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32), &fuse->apbdma.phys, GFP_KERNEL); - if (!fuse->apbdma.virt) { - dma_release_channel(fuse->apbdma.chan); + if (!fuse->apbdma.virt) return -ENOMEM; - } + + err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_free_coherent, + fuse); + if (err) + return err; fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -- GitLab From 80ef351c98714bb95bafd30b3faa6f11d8d58eb7 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:37 +0300 Subject: [PATCH 667/965] soc/tegra: regulators: Prepare for suspend Depending on hardware version, Tegra SoC may require a higher voltages during resume from system suspend, otherwise hardware will crash. Set SoC voltages to a nominal levels during suspend. Link: https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf057@gmail.com/ Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/regulators-tegra20.c | 99 ++++++++++++++++++++ drivers/soc/tegra/regulators-tegra30.c | 122 +++++++++++++++++++++++++ 2 files changed, 221 insertions(+) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index b8ce9fd0650dd..6a2f90ab9d3eb 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -16,7 +16,9 @@ #include #include #include +#include +#include #include struct tegra_regulator_coupler { @@ -25,9 +27,12 @@ struct tegra_regulator_coupler { struct regulator_dev *cpu_rdev; struct regulator_dev *rtc_rdev; struct notifier_block reboot_notifier; + struct notifier_block suspend_notifier; int core_min_uV, cpu_min_uV; bool sys_reboot_mode_req; bool sys_reboot_mode; + bool sys_suspend_mode_req; + bool sys_suspend_mode; }; static inline struct tegra_regulator_coupler * @@ -105,6 +110,28 @@ static int tegra20_core_rtc_max_spread(struct regulator_dev *core_rdev, return 150000; } +static int tegra20_cpu_nominal_uV(void) +{ + switch (tegra_sku_info.soc_speedo_id) { + case 0: + return 1100000; + case 1: + return 1025000; + default: + return 1125000; + } +} + +static int tegra20_core_nominal_uV(void) +{ + switch (tegra_sku_info.soc_speedo_id) { + default: + return 1225000; + case 2: + return 1300000; + } +} + static int tegra20_core_rtc_update(struct tegra_regulator_coupler *tegra, struct regulator_dev *core_rdev, struct regulator_dev *rtc_rdev, @@ -144,6 +171,11 @@ static int tegra20_core_rtc_update(struct tegra_regulator_coupler *tegra, if (err) return err; + /* prepare voltage level for suspend */ + if (tegra->sys_suspend_mode) + core_min_uV = clamp(tegra20_core_nominal_uV(), + core_min_uV, core_max_uV); + core_uV = regulator_get_voltage_rdev(core_rdev); if (core_uV < 0) return core_uV; @@ -279,6 +311,11 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, if (tegra->sys_reboot_mode) cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + /* prepare voltage level for suspend */ + if (tegra->sys_suspend_mode) + cpu_min_uV = clamp(tegra20_cpu_nominal_uV(), + cpu_min_uV, cpu_max_uV); + if (cpu_min_uV > cpu_uV) { err = tegra20_core_rtc_update(tegra, core_rdev, rtc_rdev, cpu_uV, cpu_min_uV); @@ -320,6 +357,7 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, } tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + tegra->sys_suspend_mode = READ_ONCE(tegra->sys_suspend_mode_req); if (rdev == cpu_rdev) return tegra20_cpu_voltage_update(tegra, cpu_rdev, @@ -334,6 +372,63 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, return -EPERM; } +static int tegra20_regulator_prepare_suspend(struct tegra_regulator_coupler *tegra, + bool sys_suspend_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->rtc_rdev || !tegra->cpu_rdev) + return 0; + + /* + * All power domains are enabled early during resume from suspend + * by GENPD core. Domains like VENC may require a higher voltage + * when enabled during resume from suspend. This also prepares + * hardware for resuming from LP0. + */ + + WRITE_ONCE(tegra->sys_suspend_mode_req, sys_suspend_mode); + + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + return 0; +} + +static int tegra20_regulator_suspend(struct notifier_block *notifier, + unsigned long mode, void *arg) +{ + struct tegra_regulator_coupler *tegra; + int ret = 0; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + suspend_notifier); + + switch (mode) { + case PM_HIBERNATION_PREPARE: + case PM_RESTORE_PREPARE: + case PM_SUSPEND_PREPARE: + ret = tegra20_regulator_prepare_suspend(tegra, true); + break; + + case PM_POST_HIBERNATION: + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + ret = tegra20_regulator_prepare_suspend(tegra, false); + break; + } + + if (ret) + pr_err("failed to prepare regulators: %d\n", ret); + + return notifier_from_errno(ret); +} + static int tegra20_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, bool sys_reboot_mode) { @@ -444,6 +539,7 @@ static struct tegra_regulator_coupler tegra20_coupler = { .balance_voltage = tegra20_regulator_balance_voltage, }, .reboot_notifier.notifier_call = tegra20_regulator_reboot, + .suspend_notifier.notifier_call = tegra20_regulator_suspend, }; static int __init tegra_regulator_coupler_init(void) @@ -456,6 +552,9 @@ static int __init tegra_regulator_coupler_init(void) err = register_reboot_notifier(&tegra20_coupler.reboot_notifier); WARN_ON(err); + err = register_pm_notifier(&tegra20_coupler.suspend_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra20_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index e74bbc9c78597..8fd43c6891349 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -25,9 +26,12 @@ struct tegra_regulator_coupler { struct regulator_dev *core_rdev; struct regulator_dev *cpu_rdev; struct notifier_block reboot_notifier; + struct notifier_block suspend_notifier; int core_min_uV, cpu_min_uV; bool sys_reboot_mode_req; bool sys_reboot_mode; + bool sys_suspend_mode_req; + bool sys_suspend_mode; }; static inline struct tegra_regulator_coupler * @@ -113,6 +117,52 @@ static int tegra30_core_cpu_limit(int cpu_uV) return -EINVAL; } +static int tegra30_cpu_nominal_uV(void) +{ + switch (tegra_sku_info.cpu_speedo_id) { + case 10 ... 11: + return 850000; + + case 9: + return 912000; + + case 1 ... 3: + case 7 ... 8: + return 1050000; + + default: + return 1125000; + + case 4 ... 6: + case 12 ... 13: + return 1237000; + } +} + +static int tegra30_core_nominal_uV(void) +{ + switch (tegra_sku_info.soc_speedo_id) { + case 0: + return 1200000; + + case 1: + if (tegra_sku_info.cpu_speedo_id != 7 && + tegra_sku_info.cpu_speedo_id != 8) + return 1200000; + + fallthrough; + + case 2: + if (tegra_sku_info.cpu_speedo_id != 13) + return 1300000; + + return 1350000; + + default: + return 1250000; + } +} + static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, struct regulator_dev *cpu_rdev, struct regulator_dev *core_rdev) @@ -168,6 +218,11 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (err) return err; + /* prepare voltage level for suspend */ + if (tegra->sys_suspend_mode) + core_min_uV = clamp(tegra30_core_nominal_uV(), + core_min_uV, core_max_uV); + core_uV = regulator_get_voltage_rdev(core_rdev); if (core_uV < 0) return core_uV; @@ -223,6 +278,11 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (tegra->sys_reboot_mode) cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + /* prepare voltage level for suspend */ + if (tegra->sys_suspend_mode) + cpu_min_uV = clamp(tegra30_cpu_nominal_uV(), + cpu_min_uV, cpu_max_uV); + if (core_min_limited_uV > core_uV) { pr_err("core voltage constraint violated: %d %d %d\n", core_uV, core_min_limited_uV, cpu_uV); @@ -292,10 +352,68 @@ static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler, } tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + tegra->sys_suspend_mode = READ_ONCE(tegra->sys_suspend_mode_req); return tegra30_voltage_update(tegra, cpu_rdev, core_rdev); } +static int tegra30_regulator_prepare_suspend(struct tegra_regulator_coupler *tegra, + bool sys_suspend_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->cpu_rdev) + return 0; + + /* + * All power domains are enabled early during resume from suspend + * by GENPD core. Domains like VENC may require a higher voltage + * when enabled during resume from suspend. This also prepares + * hardware for resuming from LP0. + */ + + WRITE_ONCE(tegra->sys_suspend_mode_req, sys_suspend_mode); + + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + return 0; +} + +static int tegra30_regulator_suspend(struct notifier_block *notifier, + unsigned long mode, void *arg) +{ + struct tegra_regulator_coupler *tegra; + int ret = 0; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + suspend_notifier); + + switch (mode) { + case PM_HIBERNATION_PREPARE: + case PM_RESTORE_PREPARE: + case PM_SUSPEND_PREPARE: + ret = tegra30_regulator_prepare_suspend(tegra, true); + break; + + case PM_POST_HIBERNATION: + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + ret = tegra30_regulator_prepare_suspend(tegra, false); + break; + } + + if (ret) + pr_err("failed to prepare regulators: %d\n", ret); + + return notifier_from_errno(ret); +} + static int tegra30_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, bool sys_reboot_mode) { @@ -395,6 +513,7 @@ static struct tegra_regulator_coupler tegra30_coupler = { .balance_voltage = tegra30_regulator_balance_voltage, }, .reboot_notifier.notifier_call = tegra30_regulator_reboot, + .suspend_notifier.notifier_call = tegra30_regulator_suspend, }; static int __init tegra_regulator_coupler_init(void) @@ -407,6 +526,9 @@ static int __init tegra_regulator_coupler_init(void) err = register_reboot_notifier(&tegra30_coupler.reboot_notifier); WARN_ON(err); + err = register_pm_notifier(&tegra30_coupler.suspend_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra30_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); -- GitLab From 006da96c840ff60a1764fc38ee7adc3dc4191d79 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:08 +0300 Subject: [PATCH 668/965] soc/tegra: Enable runtime PM during OPP state-syncing GENPD core now can set up domain's performance state properly while device is RPM-suspended. Runtime PM of a device must be enabled during setup because GENPD checks whether device is suspended and check doesn't work while RPM is disabled. Instead of replicating the boilerplate RPM-enable code around OPP helper for each driver, let's make OPP helper to take care of enabling it. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/common.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index cd33e99249c3a..35c882da55fcd 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -43,6 +44,7 @@ static int tegra_core_dev_init_opp_state(struct device *dev) { unsigned long rate; struct clk *clk; + bool rpm_enabled; int err; clk = devm_clk_get(dev, NULL); @@ -57,8 +59,31 @@ static int tegra_core_dev_init_opp_state(struct device *dev) return -EINVAL; } + /* + * Runtime PM of the device must be enabled in order to set up + * GENPD's performance properly because GENPD core checks whether + * device is suspended and this check doesn't work while RPM is + * disabled. This makes sure the OPP vote below gets cached in + * GENPD for the device. Instead, the vote is done the next time + * the device gets runtime resumed. + */ + rpm_enabled = pm_runtime_enabled(dev); + if (!rpm_enabled) + pm_runtime_enable(dev); + + /* should never happen in practice */ + if (!pm_runtime_enabled(dev)) { + dev_WARN(dev, "failed to enable runtime PM\n"); + pm_runtime_disable(dev); + return -EINVAL; + } + /* first dummy rate-setting initializes voltage vote */ err = dev_pm_opp_set_rate(dev, rate); + + if (!rpm_enabled) + pm_runtime_disable(dev); + if (err) { dev_err(dev, "failed to initialize OPP clock: %d\n", err); return err; -- GitLab From 8d1a3411da0c90f506c5e2f69529f4ba2954d3a3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:38 +0300 Subject: [PATCH 669/965] soc/tegra: pmc: Rename 3d power domains Device-tree schema doesn't allow domain name to start with a number. We don't use 3d domain yet in device-trees, so rename it to the name used by Tegra TRMs: TD, TD2. Reported-by: David Heidelberg Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 6db0e31ac6fad..cc8c223273112 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -2988,7 +2988,7 @@ static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); static const char * const tegra20_powergates[] = { [TEGRA_POWERGATE_CPU] = "cpu", - [TEGRA_POWERGATE_3D] = "3d", + [TEGRA_POWERGATE_3D] = "td", [TEGRA_POWERGATE_VENC] = "venc", [TEGRA_POWERGATE_VDEC] = "vdec", [TEGRA_POWERGATE_PCIE] = "pcie", @@ -3096,7 +3096,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { static const char * const tegra30_powergates[] = { [TEGRA_POWERGATE_CPU] = "cpu0", - [TEGRA_POWERGATE_3D] = "3d0", + [TEGRA_POWERGATE_3D] = "td", [TEGRA_POWERGATE_VENC] = "venc", [TEGRA_POWERGATE_VDEC] = "vdec", [TEGRA_POWERGATE_PCIE] = "pcie", @@ -3108,7 +3108,7 @@ static const char * const tegra30_powergates[] = { [TEGRA_POWERGATE_CPU2] = "cpu2", [TEGRA_POWERGATE_CPU3] = "cpu3", [TEGRA_POWERGATE_CELP] = "celp", - [TEGRA_POWERGATE_3D1] = "3d1", + [TEGRA_POWERGATE_3D1] = "td2", }; static const u8 tegra30_cpu_powergates[] = { @@ -3157,7 +3157,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { static const char * const tegra114_powergates[] = { [TEGRA_POWERGATE_CPU] = "crail", - [TEGRA_POWERGATE_3D] = "3d", + [TEGRA_POWERGATE_3D] = "td", [TEGRA_POWERGATE_VENC] = "venc", [TEGRA_POWERGATE_VDEC] = "vdec", [TEGRA_POWERGATE_MPE] = "mpe", -- GitLab From 9131c6331726514f0d0364c41f8733cc5eec11ab Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:09 +0300 Subject: [PATCH 670/965] soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() Only couple drivers need to get the -ENODEV error code and majority of drivers need to explicitly initialize the performance state. Add new common helper which sets up OPP table for these drivers. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- include/soc/tegra/common.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index af41ad80ec216..8ec1ac07fc85c 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -39,4 +39,19 @@ devm_tegra_core_dev_init_opp_table(struct device *dev, } #endif +static inline int +devm_tegra_core_dev_init_opp_table_common(struct device *dev) +{ + struct tegra_core_opp_params opp_params = {}; + int err; + + opp_params.init_state = true; + + err = devm_tegra_core_dev_init_opp_table(dev, &opp_params); + if (err != -ENODEV) + return err; + + return 0; +} + #endif /* __SOC_TEGRA_COMMON_H__ */ -- GitLab From 81c4c86c66650f61c6d7a712737d43a3e4d072bf Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:39 +0300 Subject: [PATCH 671/965] soc/tegra: pmc: Rename core power domain CORE power domain uses name of device-tree node, which is inconsistent with the names of PMC domains. Set the name to "core" to make it consistent. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cc8c223273112..5aceacbd8ce04 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1370,7 +1370,7 @@ static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) if (!genpd) return -ENOMEM; - genpd->name = np->name; + genpd->name = "core"; genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; -- GitLab From 8b85e11c1a7a75007e027efd1dbc5add689aa5a0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:26 +0300 Subject: [PATCH 672/965] usb: chipidea: tegra: Add runtime PM and OPP support The Tegra USB controller belongs to the core power domain and we're going to enable GENPD support for the core domain. Now USB controller must be resumed using runtime PM API in order to initialize the USB power state. We already support runtime PM for the CI device, but CI's PM is separated from the RPM managed by tegra-usb driver. Add runtime PM and OPP support to the driver. Acked-by: Peter Chen Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/usb/chipidea/ci_hdrc_tegra.c | 53 ++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index 60361141ac04f..a72a9474afea7 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -15,6 +16,8 @@ #include #include +#include + #include "../host/ehci.h" #include "ci.h" @@ -278,6 +281,8 @@ static int tegra_usb_probe(struct platform_device *pdev) if (!usb) return -ENOMEM; + platform_set_drvdata(pdev, usb); + soc = of_device_get_match_data(&pdev->dev); if (!soc) { dev_err(&pdev->dev, "failed to match OF data\n"); @@ -296,11 +301,14 @@ static int tegra_usb_probe(struct platform_device *pdev) return err; } - err = clk_prepare_enable(usb->clk); - if (err < 0) { - dev_err(&pdev->dev, "failed to enable clock: %d\n", err); + err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); + if (err) + return err; + + pm_runtime_enable(&pdev->dev); + err = pm_runtime_resume_and_get(&pdev->dev); + if (err) return err; - } if (device_property_present(&pdev->dev, "nvidia,needs-double-reset")) usb->needs_double_reset = true; @@ -320,8 +328,6 @@ static int tegra_usb_probe(struct platform_device *pdev) if (err) goto fail_power_off; - platform_set_drvdata(pdev, usb); - /* setup and register ChipIdea HDRC device */ usb->soc = soc; usb->data.name = "tegra-usb"; @@ -350,7 +356,9 @@ static int tegra_usb_probe(struct platform_device *pdev) phy_shutdown: usb_phy_shutdown(usb->phy); fail_power_off: - clk_disable_unprepare(usb->clk); + pm_runtime_put_sync_suspend(&pdev->dev); + pm_runtime_force_suspend(&pdev->dev); + return err; } @@ -360,15 +368,46 @@ static int tegra_usb_remove(struct platform_device *pdev) ci_hdrc_remove_device(usb->dev); usb_phy_shutdown(usb->phy); + + pm_runtime_put_sync_suspend(&pdev->dev); + pm_runtime_force_suspend(&pdev->dev); + + return 0; +} + +static int __maybe_unused tegra_usb_runtime_resume(struct device *dev) +{ + struct tegra_usb *usb = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(usb->clk); + if (err < 0) { + dev_err(dev, "failed to enable clock: %d\n", err); + return err; + } + + return 0; +} + +static int __maybe_unused tegra_usb_runtime_suspend(struct device *dev) +{ + struct tegra_usb *usb = dev_get_drvdata(dev); + clk_disable_unprepare(usb->clk); return 0; } +static const struct dev_pm_ops tegra_usb_pm = { + SET_RUNTIME_PM_OPS(tegra_usb_runtime_suspend, tegra_usb_runtime_resume, + NULL) +}; + static struct platform_driver tegra_usb_driver = { .driver = { .name = "tegra-usb", .of_match_table = tegra_usb_of_match, + .pm = &tegra_usb_pm, }, .probe = tegra_usb_probe, .remove = tegra_usb_remove, -- GitLab From 59caf73284d11188d5e6a4ad25ab4678c05ef639 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:27 +0300 Subject: [PATCH 673/965] bus: tegra-gmi: Add runtime PM and OPP support The GMI bus on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now GMI must be resumed using runtime PM API in order to initialize the GMI power state. Add runtime PM and OPP support to the GMI driver. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/bus/tegra-gmi.c | 50 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c index a6570789f7afe..35b59f92fa66c 100644 --- a/drivers/bus/tegra-gmi.c +++ b/drivers/bus/tegra-gmi.c @@ -13,8 +13,11 @@ #include #include #include +#include #include +#include + #define TEGRA_GMI_CONFIG 0x00 #define TEGRA_GMI_CONFIG_GO BIT(31) #define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30) @@ -54,9 +57,10 @@ static int tegra_gmi_enable(struct tegra_gmi *gmi) { int err; - err = clk_prepare_enable(gmi->clk); - if (err < 0) { - dev_err(gmi->dev, "failed to enable clock: %d\n", err); + pm_runtime_enable(gmi->dev); + err = pm_runtime_resume_and_get(gmi->dev); + if (err) { + pm_runtime_disable(gmi->dev); return err; } @@ -83,7 +87,9 @@ static void tegra_gmi_disable(struct tegra_gmi *gmi) writel(config, gmi->base + TEGRA_GMI_CONFIG); reset_control_assert(gmi->rst); - clk_disable_unprepare(gmi->clk); + + pm_runtime_put_sync_suspend(gmi->dev); + pm_runtime_force_suspend(gmi->dev); } static int tegra_gmi_parse_dt(struct tegra_gmi *gmi) @@ -213,6 +219,7 @@ static int tegra_gmi_probe(struct platform_device *pdev) if (!gmi) return -ENOMEM; + platform_set_drvdata(pdev, gmi); gmi->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -232,6 +239,10 @@ static int tegra_gmi_probe(struct platform_device *pdev) return PTR_ERR(gmi->rst); } + err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); + if (err) + return err; + err = tegra_gmi_parse_dt(gmi); if (err) return err; @@ -247,8 +258,6 @@ static int tegra_gmi_probe(struct platform_device *pdev) return err; } - platform_set_drvdata(pdev, gmi); - return 0; } @@ -262,6 +271,34 @@ static int tegra_gmi_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev) +{ + struct tegra_gmi *gmi = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(gmi->clk); + if (err < 0) { + dev_err(gmi->dev, "failed to enable clock: %d\n", err); + return err; + } + + return 0; +} + +static int __maybe_unused tegra_gmi_runtime_suspend(struct device *dev) +{ + struct tegra_gmi *gmi = dev_get_drvdata(dev); + + clk_disable_unprepare(gmi->clk); + + return 0; +} + +static const struct dev_pm_ops tegra_gmi_pm = { + SET_RUNTIME_PM_OPS(tegra_gmi_runtime_suspend, tegra_gmi_runtime_resume, + NULL) +}; + static const struct of_device_id tegra_gmi_id_table[] = { { .compatible = "nvidia,tegra20-gmi", }, { .compatible = "nvidia,tegra30-gmi", }, @@ -275,6 +312,7 @@ static struct platform_driver tegra_gmi_driver = { .driver = { .name = "tegra-gmi", .of_match_table = tegra_gmi_id_table, + .pm = &tegra_gmi_pm, }, }; module_platform_driver(tegra_gmi_driver); -- GitLab From 3da9b0feaa1617061eddfd0eedcc24164c71528a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:28 +0300 Subject: [PATCH 674/965] pwm: tegra: Add runtime PM and OPP support The PWM on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now PWM must be resumed using runtime PM API in order to initialize the PWM power state. The PWM clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the PWM driver. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tegra.c | 82 ++++++++++++++++++++++++++++++++--------- 1 file changed, 64 insertions(+), 18 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 11a10b575ace9..18cf974ac776b 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -42,12 +42,16 @@ #include #include #include +#include #include #include #include +#include #include #include +#include + #define PWM_ENABLE (1 << 31) #define PWM_DUTY_WIDTH 8 #define PWM_DUTY_SHIFT 16 @@ -145,7 +149,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; - err = clk_set_rate(pc->clk, required_clk_rate); + err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); if (err < 0) return -EINVAL; @@ -181,8 +185,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * before writing the register. Otherwise, keep it enabled. */ if (!pwm_is_enabled(pwm)) { - err = clk_prepare_enable(pc->clk); - if (err < 0) + err = pm_runtime_resume_and_get(pc->dev); + if (err) return err; } else val |= PWM_ENABLE; @@ -193,7 +197,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * If the PWM is not enabled, turn the clock off again to save power. */ if (!pwm_is_enabled(pwm)) - clk_disable_unprepare(pc->clk); + pm_runtime_put(pc->dev); return 0; } @@ -204,8 +208,8 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) int rc = 0; u32 val; - rc = clk_prepare_enable(pc->clk); - if (rc < 0) + rc = pm_runtime_resume_and_get(pc->dev); + if (rc) return rc; val = pwm_readl(pc, pwm->hwpwm); @@ -224,7 +228,7 @@ static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) val &= ~PWM_ENABLE; pwm_writel(pc, pwm->hwpwm, val); - clk_disable_unprepare(pc->clk); + pm_runtime_put_sync(pc->dev); } static const struct pwm_ops tegra_pwm_ops = { @@ -256,11 +260,20 @@ static int tegra_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + /* Set maximum frequency of the IP */ - ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); + ret = dev_pm_opp_set_rate(pwm->dev, pwm->soc->max_frequency); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); - return ret; + goto put_pm; } /* @@ -278,7 +291,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->rst)) { ret = PTR_ERR(pwm->rst); dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); - return ret; + goto put_pm; } reset_control_deassert(pwm->rst); @@ -291,10 +304,16 @@ static int tegra_pwm_probe(struct platform_device *pdev) if (ret < 0) { dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); reset_control_assert(pwm->rst); - return ret; + goto put_pm; } + pm_runtime_put(&pdev->dev); + return 0; +put_pm: + pm_runtime_put_sync_suspend(&pdev->dev); + pm_runtime_force_suspend(&pdev->dev); + return ret; } static int tegra_pwm_remove(struct platform_device *pdev) @@ -305,20 +324,44 @@ static int tegra_pwm_remove(struct platform_device *pdev) reset_control_assert(pc->rst); + pm_runtime_force_suspend(&pdev->dev); + return 0; } -#ifdef CONFIG_PM_SLEEP -static int tegra_pwm_suspend(struct device *dev) +static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) { - return pinctrl_pm_select_sleep_state(dev); + struct tegra_pwm_chip *pc = dev_get_drvdata(dev); + int err; + + clk_disable_unprepare(pc->clk); + + err = pinctrl_pm_select_sleep_state(dev); + if (err) { + clk_prepare_enable(pc->clk); + return err; + } + + return 0; } -static int tegra_pwm_resume(struct device *dev) +static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) { - return pinctrl_pm_select_default_state(dev); + struct tegra_pwm_chip *pc = dev_get_drvdata(dev); + int err; + + err = pinctrl_pm_select_default_state(dev); + if (err) + return err; + + err = clk_prepare_enable(pc->clk); + if (err) { + pinctrl_pm_select_sleep_state(dev); + return err; + } + + return 0; } -#endif static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, @@ -344,7 +387,10 @@ static const struct of_device_id tegra_pwm_of_match[] = { MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); static const struct dev_pm_ops tegra_pwm_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume) + SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static struct platform_driver tegra_pwm_driver = { -- GitLab From d618978dd4d33ec3920aeca8efbfb5f59fbe7df0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:29 +0300 Subject: [PATCH 675/965] mmc: sdhci-tegra: Add runtime PM and OPP support The SDHCI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SDHCI must be resumed using runtime PM API in order to initialize the SDHCI power state. The SDHCI clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the SDHCI driver. Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Acked-by: Adrian Hunter Signed-off-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 81 +++++++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a5001875876b9..6435a75142a6f 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include #include @@ -24,6 +26,8 @@ #include #include +#include + #include "sdhci-pltfm.h" #include "cqhci.h" @@ -760,7 +764,9 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct device *dev = mmc_dev(host->mmc); unsigned long host_clk; + int err; if (!clock) return sdhci_set_clock(host, clock); @@ -778,7 +784,12 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) * from clk_get_rate() is used. */ host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; - clk_set_rate(pltfm_host->clk, host_clk); + + err = dev_pm_opp_set_rate(dev, host_clk); + if (err) + dev_err(dev, "failed to set clk rate to %luHz: %d\n", + host_clk, err); + tegra_host->curr_clk_rate = host_clk; if (tegra_host->ddr_signaling) host->max_clk = host_clk; @@ -1705,7 +1716,6 @@ static int sdhci_tegra_probe(struct platform_device *pdev) "failed to get clock\n"); goto err_clk_get; } - clk_prepare_enable(clk); pltfm_host->clk = clk; tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, @@ -1716,15 +1726,24 @@ static int sdhci_tegra_probe(struct platform_device *pdev) goto err_rst_get; } - rc = reset_control_assert(tegra_host->rst); + rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); if (rc) goto err_rst_get; + pm_runtime_enable(&pdev->dev); + rc = pm_runtime_resume_and_get(&pdev->dev); + if (rc) + goto err_pm_get; + + rc = reset_control_assert(tegra_host->rst); + if (rc) + goto err_rst_assert; + usleep_range(2000, 4000); rc = reset_control_deassert(tegra_host->rst); if (rc) - goto err_rst_get; + goto err_rst_assert; usleep_range(2000, 4000); @@ -1736,8 +1755,11 @@ static int sdhci_tegra_probe(struct platform_device *pdev) err_add_host: reset_control_assert(tegra_host->rst); +err_rst_assert: + pm_runtime_put_sync_suspend(&pdev->dev); +err_pm_get: + pm_runtime_disable(&pdev->dev); err_rst_get: - clk_disable_unprepare(pltfm_host->clk); err_clk_get: clk_disable_unprepare(tegra_host->tmclk); err_power_req: @@ -1756,19 +1778,38 @@ static int sdhci_tegra_remove(struct platform_device *pdev) reset_control_assert(tegra_host->rst); usleep_range(2000, 4000); - clk_disable_unprepare(pltfm_host->clk); - clk_disable_unprepare(tegra_host->tmclk); + pm_runtime_put_sync_suspend(&pdev->dev); + pm_runtime_force_suspend(&pdev->dev); + + clk_disable_unprepare(tegra_host->tmclk); sdhci_pltfm_free(pdev); return 0; } -#ifdef CONFIG_PM_SLEEP -static int __maybe_unused sdhci_tegra_suspend(struct device *dev) +static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev) { struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + clk_disable_unprepare(pltfm_host->clk); + + return 0; +} + +static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return clk_prepare_enable(pltfm_host->clk); +} + +#ifdef CONFIG_PM_SLEEP +static int sdhci_tegra_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); int ret; if (host->mmc->caps2 & MMC_CAP2_CQE) { @@ -1783,17 +1824,22 @@ static int __maybe_unused sdhci_tegra_suspend(struct device *dev) return ret; } - clk_disable_unprepare(pltfm_host->clk); + ret = pm_runtime_force_suspend(dev); + if (ret) { + sdhci_resume_host(host); + cqhci_resume(host->mmc); + return ret; + } + return 0; } -static int __maybe_unused sdhci_tegra_resume(struct device *dev) +static int sdhci_tegra_resume(struct device *dev) { struct sdhci_host *host = dev_get_drvdata(dev); - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); int ret; - ret = clk_prepare_enable(pltfm_host->clk); + ret = pm_runtime_force_resume(dev); if (ret) return ret; @@ -1812,13 +1858,16 @@ static int __maybe_unused sdhci_tegra_resume(struct device *dev) suspend_host: sdhci_suspend_host(host); disable_clk: - clk_disable_unprepare(pltfm_host->clk); + pm_runtime_force_suspend(dev); return ret; } #endif -static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend, - sdhci_tegra_resume); +static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = { + SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume) +}; static struct platform_driver sdhci_tegra_driver = { .driver = { -- GitLab From 6902dc2fd57c9d72418f82e00a2af6d2ee7c7e0d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:30 +0300 Subject: [PATCH 676/965] mtd: rawnand: tegra: Add runtime PM and OPP support The NAND on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now NAND must be resumed using runtime PM API in order to initialize the NAND power state. Add runtime PM and OPP support to the NAND driver. Reviewed-by: Ulf Hansson Acked-by: Miquel Raynal Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/mtd/nand/raw/tegra_nand.c | 58 ++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index 32431bbe69b8e..b36e5260ae274 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -17,8 +17,11 @@ #include #include #include +#include #include +#include + #define COMMAND 0x00 #define COMMAND_GO BIT(31) #define COMMAND_CLE BIT(30) @@ -1151,6 +1154,7 @@ static int tegra_nand_probe(struct platform_device *pdev) return -ENOMEM; ctrl->dev = &pdev->dev; + platform_set_drvdata(pdev, ctrl); nand_controller_init(&ctrl->controller); ctrl->controller.ops = &tegra_nand_controller_ops; @@ -1166,14 +1170,23 @@ static int tegra_nand_probe(struct platform_device *pdev) if (IS_ERR(ctrl->clk)) return PTR_ERR(ctrl->clk); - err = clk_prepare_enable(ctrl->clk); + err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); + if (err) + return err; + + /* + * This driver doesn't support active power management yet, + * so we will simply keep device resumed. + */ + pm_runtime_enable(&pdev->dev); + err = pm_runtime_resume_and_get(&pdev->dev); if (err) return err; err = reset_control_reset(rst); if (err) { dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); - goto err_disable_clk; + goto err_put_pm; } writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD); @@ -1188,21 +1201,20 @@ static int tegra_nand_probe(struct platform_device *pdev) dev_name(&pdev->dev), ctrl); if (err) { dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); - goto err_disable_clk; + goto err_put_pm; } writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL); err = tegra_nand_chips_init(ctrl->dev, ctrl); if (err) - goto err_disable_clk; - - platform_set_drvdata(pdev, ctrl); + goto err_put_pm; return 0; -err_disable_clk: - clk_disable_unprepare(ctrl->clk); +err_put_pm: + pm_runtime_put_sync_suspend(ctrl->dev); + pm_runtime_force_suspend(ctrl->dev); return err; } @@ -1219,11 +1231,40 @@ static int tegra_nand_remove(struct platform_device *pdev) nand_cleanup(chip); + pm_runtime_put_sync_suspend(ctrl->dev); + pm_runtime_force_suspend(ctrl->dev); + + return 0; +} + +static int __maybe_unused tegra_nand_runtime_resume(struct device *dev) +{ + struct tegra_nand_controller *ctrl = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(ctrl->clk); + if (err) { + dev_err(dev, "Failed to enable clock: %d\n", err); + return err; + } + + return 0; +} + +static int __maybe_unused tegra_nand_runtime_suspend(struct device *dev) +{ + struct tegra_nand_controller *ctrl = dev_get_drvdata(dev); + clk_disable_unprepare(ctrl->clk); return 0; } +static const struct dev_pm_ops tegra_nand_pm = { + SET_RUNTIME_PM_OPS(tegra_nand_runtime_suspend, tegra_nand_runtime_resume, + NULL) +}; + static const struct of_device_id tegra_nand_of_match[] = { { .compatible = "nvidia,tegra20-nand" }, { /* sentinel */ } @@ -1234,6 +1275,7 @@ static struct platform_driver tegra_nand_driver = { .driver = { .name = "tegra-nand", .of_match_table = tegra_nand_of_match, + .pm = &tegra_nand_pm, }, .probe = tegra_nand_probe, .remove = tegra_nand_remove, -- GitLab From 07f837554bb59c17729951c12d3564d05d0ff4bb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:31 +0300 Subject: [PATCH 677/965] spi: tegra20-slink: Add OPP support The SPI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SPI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state in accordance to the rate. Add OPP support to the driver. Acked-by: Mark Brown Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/spi/spi-tegra20-slink.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index e8204e155484d..2a03739a0c609 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -18,12 +18,15 @@ #include #include #include +#include #include #include #include #include #include +#include + #define SLINK_COMMAND 0x000 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) @@ -680,7 +683,7 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi, bits_per_word = t->bits_per_word; speed = t->speed_hz; if (speed != tspi->cur_speed) { - clk_set_rate(tspi->clk, speed * 4); + dev_pm_opp_set_rate(tspi->dev, speed * 4); tspi->cur_speed = speed; } @@ -1066,6 +1069,10 @@ static int tegra_slink_probe(struct platform_device *pdev) goto exit_free_master; } + ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); + if (ret) + goto exit_free_master; + tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; -- GitLab From e0abae19535504cc012a32c98619c07ace8a91aa Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:34 +0300 Subject: [PATCH 678/965] media: staging: tegra-vde: Support generic power domain Currently driver supports legacy power domain API, this patch adds generic power domain support. This allows us to utilize a modern GENPD API for newer device-trees. Reviewed-by: Ulf Hansson Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/staging/media/tegra-vde/vde.c | 63 ++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/drivers/staging/media/tegra-vde/vde.c b/drivers/staging/media/tegra-vde/vde.c index ed4c1250b3038..859f60a709049 100644 --- a/drivers/staging/media/tegra-vde/vde.c +++ b/drivers/staging/media/tegra-vde/vde.c @@ -20,6 +20,7 @@ #include #include +#include #include #include "uapi.h" @@ -920,13 +921,17 @@ static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev) struct tegra_vde *vde = dev_get_drvdata(dev); int err; - err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC); - if (err) { - dev_err(dev, "Failed to power down HW: %d\n", err); - return err; + if (!dev->pm_domain) { + err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC); + if (err) { + dev_err(dev, "Failed to power down HW: %d\n", err); + return err; + } } clk_disable_unprepare(vde->clk); + reset_control_release(vde->rst); + reset_control_release(vde->rst_mc); return 0; } @@ -936,14 +941,45 @@ static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) struct tegra_vde *vde = dev_get_drvdata(dev); int err; - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC, - vde->clk, vde->rst); + err = reset_control_acquire(vde->rst_mc); if (err) { - dev_err(dev, "Failed to power up HW : %d\n", err); + dev_err(dev, "Failed to acquire mc reset: %d\n", err); return err; } + err = reset_control_acquire(vde->rst); + if (err) { + dev_err(dev, "Failed to acquire reset: %d\n", err); + goto release_mc_reset; + } + + if (!dev->pm_domain) { + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC, + vde->clk, vde->rst); + if (err) { + dev_err(dev, "Failed to power up HW : %d\n", err); + goto release_reset; + } + } else { + /* + * tegra_powergate_sequence_power_up() leaves clocks enabled, + * while GENPD not. + */ + err = clk_prepare_enable(vde->clk); + if (err) { + dev_err(dev, "Failed to enable clock: %d\n", err); + goto release_reset; + } + } + return 0; + +release_reset: + reset_control_release(vde->rst); +release_mc_reset: + reset_control_release(vde->rst_mc); + + return err; } static int tegra_vde_probe(struct platform_device *pdev) @@ -1001,14 +1037,14 @@ static int tegra_vde_probe(struct platform_device *pdev) return err; } - vde->rst = devm_reset_control_get(dev, NULL); + vde->rst = devm_reset_control_get_exclusive_released(dev, NULL); if (IS_ERR(vde->rst)) { err = PTR_ERR(vde->rst); dev_err(dev, "Could not get VDE reset %d\n", err); return err; } - vde->rst_mc = devm_reset_control_get_optional(dev, "mc"); + vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc"); if (IS_ERR(vde->rst_mc)) { err = PTR_ERR(vde->rst_mc); dev_err(dev, "Could not get MC reset %d\n", err); @@ -1026,6 +1062,12 @@ static int tegra_vde_probe(struct platform_device *pdev) return err; } + err = devm_tegra_core_dev_init_opp_table_common(dev); + if (err) { + dev_err(dev, "Could initialize OPP table %d\n", err); + return err; + } + vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0); if (!vde->iram_pool) { dev_err(dev, "Could not get IRAM pool\n"); @@ -1133,8 +1175,7 @@ static void tegra_vde_shutdown(struct platform_device *pdev) * On some devices bootloader isn't ready to a power-gated VDE on * a warm-reboot, machine will hang in that case. */ - if (pm_runtime_status_suspended(&pdev->dev)) - tegra_vde_runtime_resume(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); } static __maybe_unused int tegra_vde_pm_suspend(struct device *dev) -- GitLab From 3478494dcae155f0580e8f841458905f4fc739c2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:42 +0300 Subject: [PATCH 679/965] ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS Transformer tablets. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index ff25350869b35..af96404014024 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -216,6 +216,18 @@ opp-supported-hw = <0x0008>; }; + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0007>; + }; + + opp-500000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0008>; + }; + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; @@ -347,6 +359,12 @@ opp-peak-kBps = <3600000>; }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4000000>; + }; + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; -- GitLab From 83b7f0b8aeab4fc8271392fd32164efb7b3f55e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:43 +0300 Subject: [PATCH 680/965] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra20-acer-a500-picasso.dts | 1 + arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 1 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 912 ++++++++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 102 +- 10 files changed, 1033 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d5fead9de6bd..4aa0eb0c50fec 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -718,6 +718,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index b1f2f7f82928b..1eefb9ee4ac85 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -497,7 +497,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -603,6 +603,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index f560bf743a192..79b6b79fab65f 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -339,7 +339,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -565,6 +565,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5ce6a1ff93de1..fe1bffedc266a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -519,6 +519,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <0>; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index d4d0a5fa70155..1b808233a9339 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,6 +1,46 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1300000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-level = <1000000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-level = <1100000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-level = <1200000>; + }; + + core_opp_1225: opp-1225000 { + opp-microvolt = <1225000 1225000 1300000>; + opp-level = <1225000>; + }; + + core_opp_1275: opp-1275000 { + opp-microvolt = <1275000 1275000 1300000>; + opp-level = <1275000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-level = <1300000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,66 +48,77 @@ opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -75,36 +126,897 @@ opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1300>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-166000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-142500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <142500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-228000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-237500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-266000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <266000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-275500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1100>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-85000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <85000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-150000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-114000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-161500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-161500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-247000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-256500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-285000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-304000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-323000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-333500000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-333500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-351500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-380000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-400000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-400000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + dsi_dvfs_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-100000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-159500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <159500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-180500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <180500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-207000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <207000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-222500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <222500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-229500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <229500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-240000000-1225 { + opp-microvolt = <1225000 1225000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1225>; + }; + + opp-240000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-247000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-256500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-260000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <260000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-262000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <262000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1300>; + }; + + opp-264000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-277500000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <277500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1300>; + }; + + opp-285000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-292500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <292500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1275>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-237500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-275500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + }; + + ndflash_dvfs_opp_table: opp-table-ndflash { + compatible = "operating-points-v2"; + + opp-130000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-150000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-158000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-164000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-92000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <92000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc2_dvfs_opp_table: opp-table-sdmmc2 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f9309c07a9f22..c4a6a6a94559e 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -444,7 +444,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -689,6 +689,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f400 { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 2ad56f84bb627..de39c5465c0a9 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,7 +357,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -477,6 +477,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 8bb0eaa610f28..9d0c86711de21 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -322,6 +322,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { @@ -443,6 +444,14 @@ regulator-always-on; }; + vdd_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b1c92ba789be4..b0a00970b61c4 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -544,6 +544,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6f493a8a8a9f7..45fe111705aff 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,8 @@ clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + power-domains = <&pd_core>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -55,6 +57,8 @@ clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; }; vi@54080000 { @@ -64,6 +68,8 @@ clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; }; epp@540c0000 { @@ -73,6 +79,8 @@ clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_core>; + operating-points-v2 = <&epp_dvfs_opp_table>; }; isp@54100000 { @@ -82,6 +90,7 @@ clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; }; gr2d@54140000 { @@ -91,6 +100,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_core>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; }; gr3d@54180000 { @@ -99,6 +110,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + power-domains = <&pd_3d>; + operating-points-v2 = <&gr3d_dvfs_opp_table>; }; dc@54200000 { @@ -110,6 +123,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; nvidia,head = <0>; @@ -138,6 +153,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; nvidia,head = <1>; @@ -166,6 +183,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -174,6 +193,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -185,6 +206,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsi_dvfs_opp_table>; status = "disabled"; }; }; @@ -242,6 +265,13 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -319,6 +349,8 @@ clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -460,6 +492,8 @@ reset-names = "nand"; assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; assigned-clock-rates = <150000000>; + power-domains = <&pd_core>; + operating-points-v2 = <&ndflash_dvfs_opp_table>; status = "disabled"; }; @@ -473,6 +507,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -643,6 +679,52 @@ clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d: td { + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&mc TEGRA20_MC_RESET_3D>, + <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + resets = <&mc TEGRA20_MC_RESET_ISP>, + <&mc TEGRA20_MC_RESET_VI>, + <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -662,12 +744,13 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; + power-domains = <&pd_core>; #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; }; fuse@7000f800 { @@ -712,6 +795,9 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; + status = "disabled"; pci@1,0 { @@ -753,6 +839,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -792,6 +880,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -820,6 +910,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; @@ -856,6 +948,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -867,6 +961,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; status = "disabled"; }; @@ -878,6 +974,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -889,6 +987,8 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; status = "disabled"; }; -- GitLab From d71329b69bb6dd853ee2ab0b39c9c013e706b49a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:19 +0300 Subject: [PATCH 681/965] ARM: tegra_defconfig: Enable S/PDIF driver Enable Tegra20 S/PDIF driver. It's a part of HDMI audio subsystem on Tegra. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index a8093b2225516..289d022acc4ba 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -231,6 +231,7 @@ CONFIG_SND_HDA_CODEC_HDMI=y CONFIG_SND_SOC=y CONFIG_SND_SOC_TEGRA=y CONFIG_SND_SOC_TEGRA20_I2S=y +CONFIG_SND_SOC_TEGRA20_SPDIF=y CONFIG_SND_SOC_TEGRA30_I2S=y CONFIG_SND_SOC_TEGRA_RT5640=y CONFIG_SND_SOC_TEGRA_WM8753=y -- GitLab From 02e7cb574c21580eab3cffbcc863d3ac81787475 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:20 +0300 Subject: [PATCH 682/965] ARM: config: multi v7: Enable NVIDIA Tegra20 S/PDIF driver Enable Tegra20 S/PDIF driver that is a part of HDMI audio subsystem. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 3d509bc134440..172838566ecd6 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -762,6 +762,7 @@ CONFIG_SND_SOC_STM32_DFSDM=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m +CONFIG_SND_SOC_TEGRA20_SPDIF=m CONFIG_SND_SOC_TEGRA30_I2S=m CONFIG_SND_SOC_TEGRA_RT5640=m CONFIG_SND_SOC_TEGRA_WM8753=m -- GitLab From 8ed567fbea94ad05298d060974d5fa59946cf689 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:21 +0300 Subject: [PATCH 683/965] ARM: config: multi v7: Enable NVIDIA Tegra20 APB DMA driver All Tegra20/30/114 serial and audio drivers depend on the Tegra20 APB DMA driver, enable this DMA driver. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 172838566ecd6..8863fa969ede3 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -958,6 +958,7 @@ CONFIG_ST_FDMA=m CONFIG_STM32_DMA=y CONFIG_STM32_DMAMUX=y CONFIG_STM32_MDMA=y +CONFIG_TEGRA20_APB_DMA=y CONFIG_UNIPHIER_MDMAC=y CONFIG_XILINX_DMA=y CONFIG_QCOM_BAM_DMA=y -- GitLab From b6db8f72dddc79752585b115e478b47197ef5761 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 10:40:25 +0000 Subject: [PATCH 684/965] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Add Mali-G31 GPU node to SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2639fd383010a..cdf2adea4b10b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -112,6 +112,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -638,6 +682,27 @@ dma-channels = <16>; }; + gpu: gpu@11840000 { + compatible = "renesas,r9a07g044-mali", + "arm,mali-bifrost"; + reg = <0x0 0x11840000 0x0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPU_RESETN>, + <&cpg R9A07G044_GPU_AXI_RESETN>, + <&cpg R9A07G044_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- GitLab From d563f4bac9914fca6f34711ad22647125e773dd0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 10:40:26 +0000 Subject: [PATCH 685/965] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Add vdd core regulator (1.1 V). This patch add regulator support for gpu. The H/W manual mentions nothing about a gpu regulator. So using vdd core regulator for gpu. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 41fdae7ba66bd..9112e79079a13 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -52,6 +52,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -130,6 +139,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; }; -- GitLab From d875175d87268cbd6fa8a6ccfaeba6d9991527f0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:32 +0100 Subject: [PATCH 686/965] dt-bindings: tegra: Describe recent developer kits consistently Add descriptions to entries that were missing one and don't try to combine multiple entries into one to avoid confusion. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra.yaml | 20 ++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index d79d36ac0c44a..0235b510e0b0b 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -108,14 +108,17 @@ properties: - nvidia,p2571 - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - - items: - - enum: - - nvidia,p2771-0000 - - nvidia,p3509-0000+p3636-0001 + - description: Jetson TX2 Developer Kit + items: + - const: nvidia,p2771-0000 - const: nvidia,tegra186 - - items: - - enum: - - nvidia,p2972-0000 + - description: Jetson TX2 NX Developer Kit + items: + - const: nvidia,p3509-0000+p3636-0001 + - const: nvidia,tegra186 + - description: Jetson AGX Xavier Developer Kit + items: + - const: nvidia,p2972-0000 - const: nvidia,tegra194 - description: Jetson Xavier NX items: @@ -134,8 +137,7 @@ properties: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 - items: - - enum: - - nvidia,tegra234-vdk + - const: nvidia,tegra234-vdk - const: nvidia,tegra234 additionalProperties: true -- GitLab From b39cc79565771f7e9ffd262d3b735cbe1c718f66 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:33 +0100 Subject: [PATCH 687/965] dt-bindings: tegra: Document Jetson AGX Orin (and devkit) Add the compatible strings for the Jetson AGX Orin and the corresponding developer kit. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 0235b510e0b0b..3bd0920da2744 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -139,5 +139,14 @@ properties: - items: - const: nvidia,tegra234-vdk - const: nvidia,tegra234 + - description: Jetson AGX Orin + items: + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 + - description: Jetson AGX Orin Developer Kit + items: + - const: nvidia,p3737-0000+p3701-0000 + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 additionalProperties: true -- GitLab From fc5e0e37621973758e7e49dd85f28673e72e4b85 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:34 +0100 Subject: [PATCH 688/965] dt-bindings: Update headers for Tegra234 Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra234-clock.h | 17 ++++++++++++++--- include/dt-bindings/reset/tegra234-reset.h | 12 ++++++++++-- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 2c82072950ee7..21ed0c732fb9f 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -4,11 +4,22 @@ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +/** + * @file + * @defgroup bpmp_clock_ids Clock ID's + * @{ + */ /** @brief output of gate CLK_ENB_FUSE */ -#define TEGRA234_CLK_FUSE 40 +#define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ -#define TEGRA234_CLK_SDMMC4 123 +#define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ -#define TEGRA234_CLK_UARTA 155 +#define TEGRA234_CLK_UARTA 155U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ +#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA234_CLK_PLLC4 237U +/** @brief 32K input clock provided by PMIC */ +#define TEGRA234_CLK_CLK_32K 289U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index b3c63be06d2d5..50e13bced6424 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -4,7 +4,15 @@ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H #define DT_BINDINGS_RESET_TEGRA234_RESET_H -#define TEGRA234_RESET_SDMMC4 85 -#define TEGRA234_RESET_UARTA 100 +/** + * @file + * @defgroup bpmp_reset_ids Reset ID's + * @brief Identifiers for Resets controllable by firmware + * @{ + */ +#define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_UARTA 100U + +/** @} */ #endif -- GitLab From d9203d081a618fc8b3469b24f959495eaa138890 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:35 +0100 Subject: [PATCH 689/965] dt-bindings: sram: Document NVIDIA Tegra SYSRAM Tegra SoCs have extra on-chip RAM that can be used for inter-processor communication. Tegra186 and later make use of it to establish a two-way channel between the CCPLEX and BPMP. Add missing compatible strings for Tegra186 and Tegra194 as well as a new compatible string for Tegra234. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/sram/sram.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index d4e418b6a1c14..668a9a41a7754 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,9 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - nvidia,tegra186-sysram + - nvidia,tegra194-sysram + - nvidia,tegra234-sysram - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram -- GitLab From 8c970e7ee7ae9c41aa2432f234c7b382391200f2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:46 +0100 Subject: [PATCH 690/965] dt-bindings: memory: tegra: Update for Tegra194 The #interconnect-cells properties are required to hook up memory clients to the MC/EMC in interconnects properties. Add a description for these properties. For the nested EMC controller, the list of required properties was missing. Add it so that the validation can be more strict. Also, allow multiple reg entries required by Tegra194 and later. While at it, also remove the dummy BPMP node from the example because it is incomplete and fails validation. It's also not necessary for this file and the BPMP DT schema already has a full example. Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 78 ++++++++++++++++--- 1 file changed, 67 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 611bda38d1872..b496564b1bdff 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -33,10 +33,12 @@ properties: - nvidia,tegra194-mc reg: - maxItems: 1 + minItems: 1 + maxItems: 3 interrupts: - maxItems: 1 + items: + - description: MC general interrupt "#address-cells": const: 2 @@ -48,6 +50,9 @@ properties: dma-ranges: true + "#interconnect-cells": + const: 1 + patternProperties: "^external-memory-controller@[0-9a-f]+$": description: @@ -65,10 +70,12 @@ patternProperties: - nvidia,tegra194-emc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: - maxItems: 1 + items: + - description: EMC general interrupt clocks: items: @@ -78,11 +85,65 @@ patternProperties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,bpmp: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of the node representing the BPMP + allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-emc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-emc + then: + properties: + reg: + minItems: 2 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#interconnect-cells" + - nvidia,bpmp + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-mc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-mc + then: + properties: + reg: + minItems: 3 + +additionalProperties: false + required: - compatible - reg @@ -90,8 +151,6 @@ required: - "#address-cells" - "#size-cells" -additionalProperties: false - examples: - | #include @@ -124,12 +183,9 @@ examples: clocks = <&bpmp TEGRA186_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - #clock-cells = <1>; - }; -- GitLab From 57978838889d74ad3139cdf76ca2622e625f41e6 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:07 +0000 Subject: [PATCH 691/965] dt-bindings: Add YAML bindings for NVENC and NVJPG Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../gpu/host1x/nvidia,tegra210-nvenc.yaml | 135 ++++++++++++++++++ .../gpu/host1x/nvidia,tegra210-nvjpg.yaml | 94 ++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml new file mode 100644 index 0000000000000..e63ae1a008183 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVENC + +description: | + NVENC is the hardware video encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvenc@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + - nvidia,tegra194-nvenc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvenc + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + maxItems: 3 + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0x21 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - if: + properties: + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: write + - if: + properties: + compatible: + enum: + - nvidia,tegra194-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml new file mode 100644 index 0000000000000..8647404d67e4f --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVJPG + +description: | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically programmed + through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvjpg@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvjpg + - nvidia,tegra186-nvjpg + - nvidia,tegra194-nvjpg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvjpg + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvjpg + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; -- GitLab From c3859c1436e31461f27365ec6fc751c9bbeff3e2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:47 +0100 Subject: [PATCH 692/965] dt-bindings: memory: tegra: Add Tegra234 support Document the variant of the memory controller and external memory controllers found on Tegra234 and add some memory client and SMMU stream ID definitions for use in device tree files. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 20 ++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 9 ++++++ include/dt-bindings/memory/tegra234-mc.h | 32 +++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 include/dt-bindings/memory/tegra234-mc.h diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b496564b1bdff..13c4c82fd0d3b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -31,6 +31,7 @@ properties: - enum: - nvidia,tegra186-mc - nvidia,tegra194-mc + - nvidia,tegra234-mc reg: minItems: 1 @@ -68,6 +69,7 @@ patternProperties: - enum: - nvidia,tegra186-emc - nvidia,tegra194-emc + - nvidia,tegra234-emc reg: minItems: 1 @@ -112,6 +114,15 @@ patternProperties: reg: minItems: 2 + - if: + properties: + compatible: + const: nvidia,tegra234-emc + then: + properties: + reg: + minItems: 2 + additionalProperties: false required: @@ -142,6 +153,15 @@ allOf: reg: minItems: 3 + - if: + properties: + compatible: + const: nvidia,tegra234-mc + then: + properties: + reg: + minItems: 3 + additionalProperties: false required: diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 21ed0c732fb9f..8d7e66e1b6ef8 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -9,6 +9,15 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h new file mode 100644 index 0000000000000..2662f70c15c6e --- /dev/null +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H +#define DT_BINDINGS_MEMORY_TEGRA234_MC_H + +/* special clients */ +#define TEGRA234_SID_INVALID 0x00 +#define TEGRA234_SID_PASSTHROUGH 0x7f + + +/* NISO1 stream IDs */ +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_BPMP 0x10 + +/* + * memory client IDs + */ + +/* sdmmcd memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmcd memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +/* BPMP read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 + +#endif -- GitLab From 51a0f370886a76b4b7bd39ca9bf917a571068aac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:24 +0100 Subject: [PATCH 693/965] dt-bindings: misc: Convert Tegra MISC to json-schema Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/misc/nvidia,tegra186-misc.txt | 14 ----- .../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 ------- .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++ 4 files changed, 94 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt deleted file mode 100644 index 43d777ed83160..0000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra186 (and later) MISC register block - -The MISC register block found on Tegra186 and later SoCs contains registers -that can be used to identify a given chip and various strapping options. - -Required properties: -- compatible: Must be: - - Tegra186: "nvidia,tegra186-misc" - - Tegra194: "nvidia,tegra194-misc" - - Tegra234: "nvidia,tegra234-misc" -- reg: Should contain 2 entries: The first entry gives the physical address - and length of the register region which contains revision and debug - features. The second entry specifies the physical address and length - of the register region indicating the strapping options. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml new file mode 100644 index 0000000000000..cacb845868f44 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) MISC register block + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The MISC register block found on Tegra186 and later SoCs contains + registers that can be used to identify a given chip and various strapping + options. + +properties: + compatible: + enum: + - nvidia,tegra186-misc + - nvidia,tegra194-misc + - nvidia,tegra234-misc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + misc@100000 { + compatible = "nvidia,tegra186-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt deleted file mode 100644 index 83f6a251ba3eb..0000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra APBMISC block - -Required properties: -- compatible: Must be: - - Tegra20: "nvidia,tegra20-apbmisc" - - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" -- reg: Should contain 2 entries: the first entry gives the physical address - and length of the registers which contain revision and debug features. - The second entry gives the physical address and length of the - registers indicating the strapping options. - -Optional properties: -- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml new file mode 100644 index 0000000000000..6f504fa74007e --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APBMISC block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra210-apbmisc + - nvidia,tegra124-apbmisc + - nvidia,tegra114-apbmisc + - nvidia,tegra30-apbmisc + - const: nvidia,tegra20-apbmisc + + - items: + - const: nvidia,tegra20-apbmisc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + + nvidia,long-ram-code: + description: If present, the RAM code is long (4 bit). If not, short + (2 bit). + type: boolean + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; -- GitLab From 7fa307524a4d721d4a04523018509882c5414e72 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:37 +0100 Subject: [PATCH 694/965] arm64: tegra: Fixup SYSRAM references The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9ac4f0140700f..5f8132884be0c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1771,7 +1771,7 @@ iommus = <&smmu TEGRA186_SID_BPMP>; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 851e049b3519c..8d29b7fdb0449 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2467,7 +2467,7 @@ compatible = "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f0efb3a628040..28961ed31d87f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -122,20 +122,20 @@ }; }; - sysram@40000000 { + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; - cpu_bpmp_tx: shmem@4e000 { + cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: shmem@4f000 { + cpu_bpmp_rx: sram@4f000 { reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; @@ -146,7 +146,7 @@ compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- GitLab From e537adde131bd4cf426e6d77f99060ca302e2f08 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:38 +0100 Subject: [PATCH 695/965] arm64: tegra: Add clock for Tegra234 RTC The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 28961ed31d87f..400c01acc19fb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -93,6 +93,8 @@ reg = <0x0c2a0000 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_CLK_32K>; + clock-names = "rtc"; status = "disabled"; }; -- GitLab From 98094be152d34f8014ca67fbdc210e5261c4b09d Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:39 +0100 Subject: [PATCH 696/965] arm64: tegra: Update Tegra234 BPMP channel addresses On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 400c01acc19fb..844cab44aee65 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -126,19 +126,19 @@ sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; + reg = <0x0 0x40000000 0x0 0x80000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; + ranges = <0x0 0x0 0x40000000 0x80000>; - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; + cpu_bpmp_tx: sram@70000 { + reg = <0x70000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; + cpu_bpmp_rx: sram@71000 { + reg = <0x71000 0x1000>; label = "cpu-bpmp-rx"; pool; }; -- GitLab From e086d82d4f3e867a02a4ef4c245fc4f506173bbb Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:40 +0100 Subject: [PATCH 697/965] arm64: tegra: Fill in properties for Tegra234 eMMC Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 844cab44aee65..ffe300356e85b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -40,11 +40,24 @@ compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; interrupts = ; - clocks = <&bpmp TEGRA234_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_PLLC4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; - dma-coherent; + nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x14>; + nvidia,dqs-trim = <40>; + supports-cqe; status = "disabled"; }; -- GitLab From 06ad2ec4e5f84030ce6554d3859d6c21849bd5a3 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:41 +0100 Subject: [PATCH 698/965] arm64: tegra: Add Tegra234 TCU device Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index ffe300356e85b..bd3a01142704e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -192,6 +192,14 @@ method = "smc"; }; + tcu: serial { + compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- GitLab From f0e1266818f58ab5e687b3aec53d0689c7dc7db0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 17:02:05 +0100 Subject: [PATCH 699/965] arm64: tegra: Add main and AON GPIO controllers on Tegra234 These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index bd3a01142704e..f715671f0333f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -25,6 +25,65 @@ status = "okay"; }; + gpio: gpio@2200000 { + compatible = "nvidia,tegra234-gpio"; + reg-names = "security", "gpio"; + reg = <0x02200000 0x10000>, + <0x02210000 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; @@ -111,6 +170,21 @@ status = "disabled"; }; + gpio_aon: gpio@c2f0000 { + compatible = "nvidia,tegra234-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0x0c2f0000 0x1000>, + <0x0c2f1000 0x1000>; + interrupts = , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; reg = <0x0c360000 0x10000>, -- GitLab From a12cf5c339b082a93767b3fa5c85059b8269ab45 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 14:19:04 +0100 Subject: [PATCH 700/965] arm64: tegra: Describe Tegra234 CPU hierarchy The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++- 1 file changed, 363 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f715671f0333f..b60e4f6f06580 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -252,12 +252,373 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0_0: cpu@0 { + compatible = "arm,cortex-a78"; device_type = "cpu"; - reg = <0x000>; + reg = <0x00000>; enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_0>; + }; + + cpu0_1: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_1>; }; + + cpu0_2: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_2>; + }; + + cpu0_3: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_3>; + }; + + cpu1_0: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_0>; + }; + + cpu1_1: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_1>; + }; + + cpu1_2: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_2>; + }; + + cpu1_3: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_3>; + }; + + cpu2_0: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_0>; + }; + + cpu2_1: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_1>; + }; + + cpu2_2: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_2>; + }; + + cpu2_3: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_3>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0_0>; + }; + + core1 { + cpu = <&cpu0_1>; + }; + + core2 { + cpu = <&cpu0_2>; + }; + + core3 { + cpu = <&cpu0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1_0>; + }; + + core1 { + cpu = <&cpu1_1>; + }; + + core2 { + cpu = <&cpu1_2>; + }; + + core3 { + cpu = <&cpu1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2_0>; + }; + + core1 { + cpu = <&cpu2_1>; + }; + + core2 { + cpu = <&cpu2_2>; + }; + + core3 { + cpu = <&cpu2_3>; + }; + }; + }; + + l2c0_0: l2-cache00 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_1: l2-cache01 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_2: l2-cache02 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_3: l2-cache03 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c1_0: l2-cache10 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_1: l2-cache11 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_2: l2-cache12 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_3: l2-cache13 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c2_0: l2-cache20 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_1: l2-cache21 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_2: l2-cache22 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_3: l2-cache23 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l3c0: l3-cache0 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c1: l3-cache1 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c2: l3-cache2 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + }; + + pmu { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + status = "okay"; }; psci { -- GitLab From 533337d5c843650043771503221774f3dffbead0 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:42 +0100 Subject: [PATCH 701/965] arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 25 +++++++++++++++++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 24 ++++++++++++++++++ .../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 5 ++++ 4 files changed, 55 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index c80f7dc2935ea..ea3f338fd013e 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -12,3 +12,4 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi new file mode 100644 index 0000000000000..d3c9368221866 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin"; + compatible = "nvidia,p3701-0000", "nvidia,tegra234"; + + bus@0 { + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + only-1-8-v; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts new file mode 100644 index 0000000000000..efbbb878ba5ae --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra234-p3701-0000.dtsi" +#include "tegra234-p3737-0000.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin Developer Kit"; + compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234"; + + aliases { + mmc3 = "/bus@0/mmc@3460000"; + serial0 = &tcu; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi new file mode 100644 index 0000000000000..a85993c85e451 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3737-0000"; +}; -- GitLab From ff21087e6131e7d81c17d5b34bd786866ca90553 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Tue, 16 Nov 2021 17:32:36 +0530 Subject: [PATCH 702/965] arm64: tegra: Add support to enumerate SD in UHS mode Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8d29b7fdb0449..3b424496384e2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -893,6 +894,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -904,6 +908,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -920,6 +928,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC3>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc3_3v3>; + pinctrl-1 = <&sdmmc3_1v8>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -932,6 +943,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -1472,6 +1487,25 @@ #interrupt-cells = <2>; interrupt-controller; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; + }; smmu: iommu@12000000 { -- GitLab From f7eb2785728442cc349a68965bc3c9a869274336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:08 +0000 Subject: [PATCH 703/965] arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194 Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 +++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 54 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 5f8132884be0c..fe588666bcfcf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1538,6 +1538,21 @@ iommus = <&smmu TEGRA186_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; + dsib: dsi@15400000 { compatible = "nvidia,tegra186-dsi"; reg = <0x15400000 0x10000>; @@ -1569,6 +1584,21 @@ iommus = <&smmu TEGRA186_SID_NVDEC>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; + sor0: sor@15540000 { compatible = "nvidia,tegra186-sor"; reg = <0x15540000 0x10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3b424496384e2..c97febf90ead7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1739,6 +1739,22 @@ iommus = <&smmu TEGRA194_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra194-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA194_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_NVJPG>; + dma-coherent; + }; + nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; reg = <0x15480000 0x00040000>; @@ -1758,6 +1774,25 @@ nvidia,host1x-class = <0xf0>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC>; + dma-coherent; + + nvidia,host1x-class = <0x21>; + }; + dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; reg = <0x155c0000 0x10000>; @@ -1894,6 +1929,25 @@ }; }; + nvenc@15a80000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x15a80000 0x00040000>; + clocks = <&bpmp TEGRA194_CLK_NVENC1>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC1>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC1>; + dma-coherent; + + nvidia,host1x-class = <0x22>; + }; + sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; reg = <0x15b00000 0x40000>; -- GitLab From e762232f946679b6be60244d78079aa12cc5ed68 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 1 Dec 2021 15:57:16 +0000 Subject: [PATCH 704/965] arm64: tegra: Add ISO SMMU controller for Tegra194 The display controllers are attached to a separate ARM SMMU instance that is dedicated to servicing isochronous memory clients. Add this ISO instance of the ARM SMMU to device tree. Please note that the display controllers are not hooked up to this SMMU yet, because we are still missing a means to transition framebuffers used by the bootloader to the kernel. This based upon an initial patch by Thierry Reding . Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c97febf90ead7..f9b1900088ad8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1508,6 +1508,82 @@ }; + iommu@10000000 { + compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + smmu: iommu@12000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x12000000 0x800000>, -- GitLab From 4cc3e3e164c02c6f2fce38f2098a1fe1256ea58d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:58:55 +0100 Subject: [PATCH 705/965] arm64: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 8a51751526ee3..ecd58bd2770f1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1023,7 +1023,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6077d572d8280..d3e622c4a439e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -301,7 +301,7 @@ vqmmc-supply = <&vdd_1v8>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 58aa0518965e1..0a70daeffd85e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -40,7 +40,7 @@ non-removable; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 41beab626d953..ed73c3a0c1403 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1586,7 +1586,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 030f264eccd51..cbd8cda48f373 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1645,7 +1645,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 131c064d69919..43ff5e4bda198 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1726,7 +1726,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; -- GitLab From 097e01c61015e41975873a1e51e3106456aa581a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 18:02:18 +0100 Subject: [PATCH 706/965] arm64: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 26 +++++++------- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 6 ++-- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 30 ++++++++-------- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 36 +++++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 18 +++++----- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 16 ++++----- 12 files changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index ecd58bd2770f1..c84ed1cb9a8c4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1057,7 +1057,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-vdd-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <19000000>; @@ -1066,7 +1066,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1076,7 +1076,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1086,7 +1086,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-vdd-3v3-run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1098,7 +1098,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-vdd-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_usb1_vbus: regulator@6 { + vdd_usb1_vbus: regulator-vdd-usb1-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1127,7 +1127,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@7 { + vdd_usb3_vbus: regulator-vdd-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1138,7 +1138,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@8 { + vdd_3v3_panel: regulator-vdd-3v3-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1148,7 +1148,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@9 { + vdd_hdmi_pll: regulator-vdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; regulator-min-microvolt = <1050000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@10 { + vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1167,7 +1167,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_5v0_ts: regulator@11 { + vdd_5v0_ts: regulator-vdd-5v0-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS"; regulator-min-microvolt = <5000000>; @@ -1178,7 +1178,7 @@ enable-active-high; }; - vdd_3v3_lp0: regulator@12 { + vdd_3v3_lp0: regulator-vdd-3v3-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 52fa258533e62..2883049c4edf7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2250,7 +2250,7 @@ }; }; - vdd_sd: regulator@100 { + vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "SD_CARD_SW_PWR"; regulator-min-microvolt = <3300000>; @@ -2262,7 +2262,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@101 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -2274,7 +2274,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb0: regulator@102 { + vdd_usb0: regulator-vdd-usb0 { compatible = "regulator-fixed"; regulator-name = "VDD_USB0"; regulator-min-microvolt = <5000000>; @@ -2286,7 +2286,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1: regulator@103 { + vdd_usb1: regulator-vdd-usb1 { compatible = "regulator-fixed"; regulator-name = "VDD_USB1"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index fcd71bfc67079..4917b43995b0d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -393,7 +393,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -402,7 +402,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -411,7 +411,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index af33fe93e1d6b..28d59792eaa12 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -593,7 +593,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -602,7 +602,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -611,7 +611,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; @@ -623,7 +623,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c4058ee36fecb..ad217cac2b280 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -317,7 +317,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VIN_SYS_5V0"; regulator-min-microvolt = <5000000>; @@ -326,7 +326,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@1 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -335,7 +335,7 @@ enable-active-high; }; - vdd_3v3_pcie: regulator@2 { + vdd_3v3_pcie: regulator-vdd-3v3-pcie { compatible = "regulator-fixed"; regulator-name = "PEX_3V3"; regulator-min-microvolt = <3300000>; @@ -345,7 +345,7 @@ enable-active-high; }; - vdd_12v_pcie: regulator@3 { + vdd_12v_pcie: regulator-vdd-12v-pcie { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; regulator-min-microvolt = <1200000>; @@ -354,7 +354,7 @@ regulator-boot-on; }; - vdd_5v_sata: regulator@4 { + vdd_5v_sata: regulator-vdd-5v0-sata { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SATA"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index a055f17218bb3..8d3999cd1af29 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2000,7 +2000,7 @@ }; }; - vdd_5v0_sys: regulator@100 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; regulator-min-microvolt = <5000000>; @@ -2009,7 +2009,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@101 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -2018,7 +2018,7 @@ regulator-boot-on; }; - vdd_3v3_ao: regulator@102 { + vdd_3v3_ao: regulator-vdd-3v3-ao { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_AO"; regulator-min-microvolt = <3300000>; @@ -2027,7 +2027,7 @@ regulator-boot-on; }; - vdd_1v8: regulator@103 { + vdd_1v8: regulator-vdd-1v8 { compatible = "regulator-fixed"; regulator-name = "VDD_1V8"; regulator-min-microvolt = <1800000>; @@ -2036,7 +2036,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@104 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 14da4206ea66a..8c2c709dd54c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -20,7 +20,7 @@ }; }; - vdd_3v3_sd: regulator@0 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d3e622c4a439e..75eb743a72427 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -336,7 +336,7 @@ method = "smc"; }; - vdd_gpu: regulator@100 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d8409c1b43800..34276a84c68a9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1555,7 +1555,7 @@ }; }; - vdd_sys_mux: regulator@0 { + vdd_sys_mux: regulator-vdd-sys-mux { compatible = "regulator-fixed"; regulator-name = "VDD_SYS_MUX"; regulator-min-microvolt = <5000000>; @@ -1564,7 +1564,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -1576,7 +1576,7 @@ vin-supply = <&vdd_sys_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -1591,7 +1591,7 @@ regulator-disable-ramp-delay = <10000>; }; - vdd_5v0_io: regulator@3 { + vdd_5v0_io: regulator-vdd-5v0-io { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_IO_SYS"; regulator-min-microvolt = <5000000>; @@ -1600,7 +1600,7 @@ regulator-boot-on; }; - vdd_3v3_sd: regulator@4 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; @@ -1613,7 +1613,7 @@ regulator-disable-ramp-delay = <4880>; }; - vdd_dsi_csi: regulator@5 { + vdd_dsi_csi: regulator-vdd-dsi-csi { compatible = "regulator-fixed"; regulator-name = "AVDD_DSI_CSI_1V2"; regulator-min-microvolt = <1200000>; @@ -1621,7 +1621,7 @@ vin-supply = <&vdd_sys_1v2>; }; - vdd_3v3_dis: regulator@6 { + vdd_3v3_dis: regulator-vdd-3v3-dis { compatible = "regulator-fixed"; regulator-name = "VDD_DIS_3V3_LCD"; regulator-min-microvolt = <3300000>; @@ -1632,7 +1632,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_1v8_dis: regulator@7 { + vdd_1v8_dis: regulator-vdd-1v8-dis { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_1V8_DIS"; regulator-min-microvolt = <1800000>; @@ -1643,7 +1643,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_5v0_rtl: regulator@8 { + vdd_5v0_rtl: regulator-vdd-5v0-rtl { compatible = "regulator-fixed"; regulator-name = "RTL_5V"; regulator-min-microvolt = <5000000>; @@ -1653,7 +1653,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb_vbus: regulator@9 { + vdd_usb_vbus: regulator-vdd-usb-vbus { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN1"; regulator-min-microvolt = <5000000>; @@ -1663,7 +1663,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hdmi: regulator@10 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -1673,7 +1673,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator@11 { + vdd_cam_1v2: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; @@ -1683,7 +1683,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_2v8: regulator@12 { + vdd_cam_2v8: regulator-vdd-cam-2v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-2v8"; regulator-min-microvolt = <2800000>; @@ -1693,7 +1693,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_1v8: regulator@13 { + vdd_cam_1v8: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v8"; regulator-min-microvolt = <1800000>; @@ -1703,7 +1703,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_usb_vbus_otg: regulator@14 { + vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN0"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index ed73c3a0c1403..5cfbc0394173c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1635,7 +1635,7 @@ method = "smc"; }; - battery_reg: regulator@0 { + battery_reg: regulator-vdd-ac-bat { compatible = "regulator-fixed"; regulator-name = "vdd-ac-bat"; regulator-min-microvolt = <5000000>; @@ -1643,7 +1643,7 @@ regulator-always-on; }; - vdd_3v3: regulator@1 { + vdd_3v3: regulator-vdd-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd-3v3"; regulator-enable-ramp-delay = <160>; @@ -1655,7 +1655,7 @@ enable-active-high; }; - max77620_gpio7: regulator@2 { + max77620_gpio7: regulator-max77620-gpio7 { compatible = "regulator-fixed"; regulator-name = "max77620-gpio7"; regulator-enable-ramp-delay = <240>; @@ -1669,7 +1669,7 @@ enable-active-high; }; - lcd_bl_en: regulator@3 { + lcd_bl_en: regulator-lcd-bl-en { compatible = "regulator-fixed"; regulator-name = "lcd-bl-en"; regulator-min-microvolt = <1800000>; @@ -1680,7 +1680,7 @@ enable-active-high; }; - en_vdd_sd: regulator@4 { + en_vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "en-vdd-sd"; regulator-enable-ramp-delay = <472>; @@ -1692,7 +1692,7 @@ enable-active-high; }; - en_vdd_cam: regulator@5 { + en_vdd_cam: regulator-vdd-cam { compatible = "regulator-fixed"; regulator-name = "en-vdd-cam"; regulator-min-microvolt = <1800000>; @@ -1702,7 +1702,7 @@ enable-active-high; }; - vdd_sys_boost: regulator@6 { + vdd_sys_boost: regulator-vdd-sys-boost { compatible = "regulator-fixed"; regulator-name = "vdd-sys-boost"; regulator-enable-ramp-delay = <3090>; @@ -1714,7 +1714,7 @@ enable-active-high; }; - vdd_hdmi: regulator@7 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd-hdmi"; regulator-enable-ramp-delay = <468>; @@ -1727,21 +1727,21 @@ enable-active-high; }; - en_vdd_cpu_fixed: regulator@8 { + en_vdd_cpu_fixed: regulator-vdd-cpu-fixed { compatible = "regulator-fixed"; regulator-name = "vdd-cpu-fixed"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - vdd_aux_3v3: regulator@9 { + vdd_aux_3v3: regulator-vdd-aux-3v3 { compatible = "regulator-fixed"; regulator-name = "aux-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vdd_snsr_pm: regulator@10 { + vdd_snsr_pm: regulator-vdd-snsr-pm { compatible = "regulator-fixed"; regulator-name = "snsr_pm"; regulator-min-microvolt = <3300000>; @@ -1750,7 +1750,7 @@ enable-active-high; }; - vdd_usb_5v0: regulator@11 { + vdd_usb_5v0: regulator-vdd-usb-5v0 { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd-usb-5v0"; @@ -1761,7 +1761,7 @@ enable-active-high; }; - vdd_cdc_1v2_aud: regulator@101 { + vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd_cdc_1v2_aud"; @@ -1772,7 +1772,7 @@ enable-active-high; }; - vdd_disp_3v0: regulator@12 { + vdd_disp_3v0: regulator-vdd-disp-3v0 { compatible = "regulator-fixed"; regulator-name = "vdd-disp-3v0"; regulator-enable-ramp-delay = <232>; @@ -1784,7 +1784,7 @@ enable-active-high; }; - vdd_fan: regulator@13 { + vdd_fan: regulator-vdd-fan { compatible = "regulator-fixed"; regulator-name = "vdd-fan"; regulator-enable-ramp-delay = <284>; @@ -1795,7 +1795,7 @@ enable-active-high; }; - usb_vbus1: regulator@14 { + usb_vbus1: regulator-usb-vbus1 { compatible = "regulator-fixed"; regulator-name = "usb-vbus1"; regulator-min-microvolt = <5000000>; @@ -1806,7 +1806,7 @@ gpio-open-drain; }; - usb_vbus2: regulator@15 { + usb_vbus2: regulator-usb-vbus2 { compatible = "regulator-fixed"; regulator-name = "usb-vbus2"; regulator-min-microvolt = <5000000>; @@ -1817,7 +1817,7 @@ gpio-open-drain; }; - vdd_3v3_eth: regulator@16 { + vdd_3v3_eth: regulator-vdd-3v3-eth { compatible = "regulator-fixed"; regulator-name = "vdd-3v3-eth-a02"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index cbd8cda48f373..283b50febb6f5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1762,7 +1762,7 @@ method = "smc"; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; @@ -1772,7 +1772,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; @@ -1789,7 +1789,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_sd: regulator@2 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; @@ -1802,7 +1802,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi-5v0 { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; @@ -1812,7 +1812,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hub_3v3: regulator@4 { + vdd_hub_3v3: regulator-vdd-hub-3v3 { compatible = "regulator-fixed"; regulator-name = "VDD_HUB_3V3"; @@ -1825,7 +1825,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cpu: regulator@5 { + vdd_cpu: regulator-vdd-cpu { compatible = "regulator-fixed"; regulator-name = "VDD_CPU"; @@ -1840,7 +1840,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_gpu: regulator@6 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; @@ -1855,7 +1855,7 @@ vin-supply = <&vdd_5v0_sys>; }; - avdd_io_edp_1v05: regulator@7 { + avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { compatible = "regulator-fixed"; regulator-name = "AVDD_IO_EDP_1V05"; @@ -1868,7 +1868,7 @@ vin-supply = <&avdd_1v05_pll>; }; - vdd_5v0_usb: regulator@8 { + vdd_5v0_usb: regulator-vdd-5v-usb { compatible = "regulator-fixed"; regulator-name = "VDD_5V_USB"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43ff5e4bda198..6d59c28ff2a37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1807,7 +1807,7 @@ method = "smc"; }; - ppvar_sys: regulator@0 { + ppvar_sys: regulator-ppvar-sys { compatible = "regulator-fixed"; regulator-name = "PPVAR_SYS"; regulator-min-microvolt = <4400000>; @@ -1815,7 +1815,7 @@ regulator-always-on; }; - pplcd_vdd: regulator@1 { + pplcd_vdd: regulator-pplcd-vdd { compatible = "regulator-fixed"; regulator-name = "PPLCD_VDD"; regulator-min-microvolt = <4400000>; @@ -1825,7 +1825,7 @@ regulator-boot-on; }; - pp3000_always: regulator@2 { + pp3000_always: regulator-pp3000-always { compatible = "regulator-fixed"; regulator-name = "PP3000_ALWAYS"; regulator-min-microvolt = <3000000>; @@ -1833,7 +1833,7 @@ regulator-always-on; }; - pp3300: regulator@3 { + pp3300: regulator-pp3000 { compatible = "regulator-fixed"; regulator-name = "PP3300"; regulator-min-microvolt = <3300000>; @@ -1843,7 +1843,7 @@ enable-active-high; }; - pp5000: regulator@4 { + pp5000: regulator-pp5000 { compatible = "regulator-fixed"; regulator-name = "PP5000"; regulator-min-microvolt = <5000000>; @@ -1851,7 +1851,7 @@ regulator-always-on; }; - pp1800_lcdio: regulator@5 { + pp1800_lcdio: regulator-pp1800-lcdio { compatible = "regulator-fixed"; regulator-name = "PP1800_LCDIO"; regulator-min-microvolt = <1800000>; @@ -1861,7 +1861,7 @@ regulator-boot-on; }; - pp1800_cam: regulator@6 { + pp1800_cam: regulator-pp1800-cam { compatible = "regulator-fixed"; regulator-name = "PP1800_CAM"; regulator-min-microvolt = <1800000>; @@ -1870,7 +1870,7 @@ enable-active-high; }; - usbc_vbus: regulator@7 { + usbc_vbus: regulator-usbc-vbus { compatible = "regulator-fixed"; regulator-name = "USBC_VBUS"; regulator-min-microvolt = <5000000>; -- GitLab From bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Mar 2020 16:45:38 +0100 Subject: [PATCH 707/965] arm64: tegra: Add native timer support on Tegra186 The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index fe588666bcfcf..855ae6b705a83 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -508,6 +508,22 @@ }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; -- GitLab From 2c6fd24dcbf0a8cfb066ca886579a4a8b2275054 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:10:00 +0100 Subject: [PATCH 708/965] arm64: tegra: Fix unit-addresses on Norrin The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index c84ed1cb9a8c4..f9604968c01f0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -564,7 +564,7 @@ pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; - as3722_default: pinmux@0 { + as3722_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -770,7 +770,7 @@ google,remote-bus = <0>; - charger: bq24735 { + charger: bq24735@9 { compatible = "ti,bq24735"; reg = <0x9>; interrupt-parent = <&gpio>; @@ -781,7 +781,7 @@ GPIO_ACTIVE_HIGH>; }; - battery: smart-battery { + battery: smart-battery@b { compatible = "sbs,sbs-battery"; reg = <0xb>; sbs,i2c-retry-count = <2>; -- GitLab From 64b407827670f9bd5fe08a4ed10732349339c572 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:11:53 +0100 Subject: [PATCH 709/965] arm64: tegra: Remove unsupported properties on Norrin The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index f9604968c01f0..f16acb4cabaab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -885,14 +885,12 @@ pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; - #wake-cells = <3>; nvidia,cpu-pwr-good-time = <500>; nvidia,cpu-pwr-off-time = <300>; nvidia,core-pwr-good-time = <641 3845>; nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; }; usb@70090000 { -- GitLab From bb43b219c88c4d1fe7154af787024b885edd45f8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:13:37 +0100 Subject: [PATCH 710/965] arm64: tegra: Fix compatible string for Tegra132 timer The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 63aa3129d8fca..95bdcc8f31c91 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -210,7 +210,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , -- GitLab From ed9e9a6eb118daa25c0dc04fd5fae55bf8a5356a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:17:07 +0100 Subject: [PATCH 711/965] arm64: tegra: Add OPP tables on Tegra132 Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra132-peripherals-opp.dtsi | 426 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra132.dtsi | 13 +- 2 files changed, 438 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi new file mode 100644 index 0000000000000..66ffb7f8aaa73 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-12750000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp-12750000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp-12750000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp-20400000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp-20400000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp-20400000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp-20400000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-40800000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp-40800000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp-40800000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp-68000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp-68000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp-102000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp-102000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + opp-suspend; + }; + + opp-204000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + opp-suspend; + }; + + opp-204000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + opp-suspend; + }; + + opp-204000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + opp-suspend; + }; + + opp-264000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp-264000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp-264000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp-264000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp-300000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp-300000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp-300000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp-348000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp-348000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp-348000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp-348000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp-396000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp-396000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp-396000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp-528000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp-528000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp-528000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp-528000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp-600000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp-600000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp-600000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp-600000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp-792000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp-792000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp-792000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp-924000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 95bdcc8f31c91..7f5cbcd63a258 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra132-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra132", "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -244,6 +246,10 @@ clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { @@ -607,15 +613,20 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc"; + compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; }; sata@70020000 { -- GitLab From 92564257d7af8959eb1d5ba7ead6881c931e8bc3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:19:26 +0100 Subject: [PATCH 712/965] arm64: tegra: Fix Tegra132 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7f5cbcd63a258..0e8903027f04d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -400,7 +400,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -415,7 +415,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -430,7 +430,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -445,7 +445,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -460,7 +460,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -475,7 +475,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; -- GitLab From 9f27a6c421163541bc3354b573283e50f24a7c95 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:20:25 +0100 Subject: [PATCH 713/965] arm64: tegra: Drop unused AHCI clocks on Tegra132 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0e8903027f04d..16673d3bf6f90 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -635,10 +635,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; -- GitLab From fce5d0731616549b9fc2c992b5896f7717fffdd4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:21:18 +0100 Subject: [PATCH 714/965] arm64: tegra: Sort Tegra132 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 16673d3bf6f90..e41671fcd7e38 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -674,8 +674,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -683,7 +683,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, -- GitLab From fe57ff5365c9aef12e80ee51e38d0ea6bb17b255 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:24:20 +0100 Subject: [PATCH 715/965] arm64: tegra: Rename thermal zones nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 11 ++++--- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 14 ++++----- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 27 ++++++++--------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 6 ++-- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 6 ++-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 30 ++++++++----------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++--- 8 files changed, 49 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e41671fcd7e38..3673f79adf1a9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -895,7 +895,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -923,7 +923,8 @@ }; }; }; - mem { + + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -950,7 +951,8 @@ */ }; }; - gpu { + + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -978,7 +980,8 @@ }; }; }; - pllx { + + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 28d59792eaa12..33e707ef883b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -633,7 +633,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -687,28 +687,28 @@ }; }; - gpu { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; trips { - gpu_alert0: critical { - temperature = <99000>; + aux_alert0: critical { + temperature = <90000>; hysteresis = <0>; type = "critical"; }; }; }; - aux { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; trips { - aux_alert0: critical { - temperature = <90000>; + gpu_alert0: critical { + temperature = <99000>; hysteresis = <0>; type = "critical"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 855ae6b705a83..a5c19e4b39c55 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1976,12 +1976,12 @@ }; thermal-zones { - a57 { + /* Cortex-A57 cluster */ + cpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; trips { critical { @@ -1995,12 +1995,12 @@ }; }; - denver { + /* Denver cluster */ + aux-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; trips { critical { @@ -2014,12 +2014,11 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; trips { critical { @@ -2033,12 +2032,11 @@ }; }; - pll { + pll-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; trips { critical { @@ -2052,12 +2050,11 @@ }; }; - always_on { + ao-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; trips { critical { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9f34871b8f60d..b79d7d89cf629 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2097,7 +2097,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2151,7 +2151,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2165,7 +2165,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8d3999cd1af29..76d94ecd1cfec 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2103,7 +2103,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2157,7 +2157,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2171,7 +2171,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9b1900088ad8..0ea613715c6fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2903,39 +2903,33 @@ }; thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; status = "disabled"; }; - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; status = "disabled"; }; - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; + aux-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; status = "disabled"; }; - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; + pllx-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; status = "disabled"; }; - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; + ao-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; status = "disabled"; }; - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 283b50febb6f5..9e60ebf2f5c0a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1684,7 +1684,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu_trip_critical: critical { temperature = <96500>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ccdc0dec4e59b..af9237ad03c15 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1981,7 +1981,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2010,7 +2010,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -2056,7 +2056,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2085,7 +2085,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; -- GitLab From 4b5ae31fb75655d6270a160a3ebafc48474f597d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:25:50 +0100 Subject: [PATCH 716/965] arm64: tegra: Rename power-monitor input nodes Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++------ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 12 ++++++------ .../dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 2883049c4edf7..c4dee05f330c8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -1945,19 +1945,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_MUX"; shunt-resistor-micro-ohms = <20000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_5V0_IO_SYS"; shunt-resistor-micro-ohms = <5000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V3_SYS"; shunt-resistor-micro-ohms = <10000>; @@ -1970,19 +1970,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_3V3_IO_SLP"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_1V8_IO"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_M2_IN"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 4917b43995b0d..3d8878c0ec035 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -73,19 +73,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_SYS_GPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_SOC"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V8_WIFI"; shunt-resistor-micro-ohms = <10000>; @@ -98,19 +98,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_CPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_5V0_DDR"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 33e707ef883b4..6cc51083adb71 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -81,22 +81,22 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5>; }; - channel@1 { + input@1 { reg = <1>; label = "VDD_CPU_GPU"; shunt-resistor-micro-ohms = <5>; }; - channel@2 { + input@2 { reg = <2>; label = "VDD_SOC"; - shunt-resistor-micro-ohms = <>; + shunt-resistor-micro-ohms = <5>; }; }; }; -- GitLab From 548c9c5aaf85bb157b1a87fdc558e3767f5f0bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:27:11 +0100 Subject: [PATCH 717/965] arm64: tegra: Fix Tegra186 compatible string list The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a5c19e4b39c55..21f823ea08c6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -585,7 +585,7 @@ }; gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03160000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -598,7 +598,7 @@ }; cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03180000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -612,7 +612,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03190000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -629,7 +629,7 @@ /* controlled by BPMP, should not be enabled */ pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031a0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -643,7 +643,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -659,7 +659,7 @@ }; gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -672,7 +672,7 @@ }; gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1089,7 +1089,7 @@ }; gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1102,7 +1102,7 @@ }; gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = ; #address-cells = <1>; -- GitLab From 2b14cbd643feea5fc17c6e8bead4e71088c69acd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:28:29 +0100 Subject: [PATCH 718/965] arm64: tegra: Adjust length of CCPLEX cluster MMIO region The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 21f823ea08c6f..c91afff1b7570 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1215,7 +1215,7 @@ ccplex@e000000 { compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; + reg = <0x0 0x0e000000 0x0 0x400000>; nvidia,bpmp = <&bpmp>; }; -- GitLab From e7445ab7dc5160540930912fae02660601b6de80 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:36:35 +0100 Subject: [PATCH 719/965] arm64: tegra: Drop unit-address for audio card graph endpoints Audio graph endpoints don't have a "reg" property, so they shouldn't have a unit-address either. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index b79d7d89cf629..2478ece9e67c2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1031,7 +1031,7 @@ i2s6_port: port@1 { reg = <1>; - i2s6_dap_ep: endpoint@0 { + i2s6_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 76d94ecd1cfec..6d4ed67ffeda4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -989,7 +989,7 @@ i2s5_port: port@1 { reg = <1>; - i2s5_dap_ep: endpoint@0 { + i2s5_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9e60ebf2f5c0a..260de1122aa3e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -688,7 +688,7 @@ i2s4_port: port@1 { reg = <1>; - i2s4_dap_ep: endpoint@0 { + i2s4_dap_ep: endpoint { dai-format = "i2s"; /* Placeholder for external Codec */ }; @@ -706,7 +706,7 @@ port@0 { reg = <0>; - dmic1_cif_ep: endpoint@0 { + dmic1_cif_ep: endpoint { remote-endpoint = <&xbar_dmic1_ep>; }; }; @@ -714,7 +714,7 @@ dmic1_port: port@1 { reg = <1>; - dmic1_dap_ep: endpoint@0 { + dmic1_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; @@ -731,7 +731,7 @@ port@0 { reg = <0>; - dmic2_cif_ep: endpoint@0 { + dmic2_cif_ep: endpoint { remote-endpoint = <&xbar_dmic2_ep>; }; }; @@ -739,7 +739,7 @@ dmic2_port: port@1 { reg = <1>; - dmic2_dap_ep: endpoint@0 { + dmic2_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; -- GitLab From 56797e625910497ef2a2dd40b76be2633a86f726 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:39:20 +0100 Subject: [PATCH 720/965] arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips The standard "jedec," vendor prefix should be used for SPI NOR flash chips. This allows the right DT schema to be picked for validation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 6d4ed67ffeda4..1323fa9b8301c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1878,7 +1878,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <102000000>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 260de1122aa3e..9fc4a8f46250a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1637,7 +1637,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; spi-tx-bus-width = <2>; -- GitLab From 2fcb87970e4282a227e09108d479e860b5b9faf0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:40:59 +0100 Subject: [PATCH 721/965] arm64: tegra: Drop unsupported nvidia,lpdr property The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property, so drop them from the device trees that have listed them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0ea613715c6fa..5e1cbb7889377 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -536,7 +536,6 @@ pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; @@ -548,7 +547,6 @@ clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; -- GitLab From cd6157c1978c84d4fd9b9cedc736fc7b5fce4d09 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:43:20 +0100 Subject: [PATCH 722/965] arm64: tegra: Fix Tegra194 HSP compatible string The HSP instances on Tegra194 are not fully compatible with the version found on Tegra186, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5e1cbb7889377..d7fd6bdd131a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1195,7 +1195,7 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; interrupts = , , @@ -1373,7 +1373,7 @@ }; hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; interrupts = , , -- GitLab From 1ff75059077c0d37edb936d9232f76a74704be41 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:47:47 +0100 Subject: [PATCH 723/965] arm64: tegra: Drop unused properties for Tegra194 PCIe The num-viewport property is never used and can be dropped, whereas the "iommus" property is not needed since we use "iommu-map-mask" and "iommu-map" already. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d7fd6bdd131a7..bb51ccdb324d5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2169,7 +2169,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <1>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; @@ -2202,7 +2201,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE1>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2223,7 +2221,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <2>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; @@ -2256,7 +2253,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE2>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2277,7 +2273,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <3>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; @@ -2310,7 +2305,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE3>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2331,7 +2325,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; - num-viewport = <8>; linux,pci-domain = <4>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; @@ -2364,7 +2357,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2385,7 +2377,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <0>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; @@ -2418,7 +2409,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2439,7 +2429,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <5>; pinctrl-names = "default"; @@ -2476,7 +2465,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2516,7 +2504,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2556,7 +2543,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2599,7 +2585,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; -- GitLab From c453cc9e9e1afbb3c3c2bc2579e4cc2c8ee7641c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:50:44 +0100 Subject: [PATCH 724/965] arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock The "core_m" clock is not documented in the Tegra194 PCIe device tree bindings, so remove it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb51ccdb324d5..bb88d32e553e5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2434,9 +2434,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA194_RESET_PEX1_CORE_5>; -- GitLab From 99d9bde5b4ab05c98f6c2c5e8fb276d3b7072be3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:51:54 +0100 Subject: [PATCH 725/965] arm64: tegra: Rename TCU node to "serial" The TCU is basically a serial port (albeit a fancy one), so it should be named "serial". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb88d32e553e5..abea546cb0722 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2877,7 +2877,7 @@ iommus = <&smmu TEGRA194_SID_APE>; }; - tcu: tcu { + tcu: serial { compatible = "nvidia,tegra194-tcu"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; -- GitLab From 1dcf00ae8205ee2fdbc0c55c41c486f287d20739 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:53:28 +0100 Subject: [PATCH 726/965] arm64: tegra: Remove unsupported regulator properties Remove the unsupported "regulator-disable-ramp-delay" properties which ended up in various DTS files for some reason. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 -- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 34276a84c68a9..21d7e653ea5b8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1588,7 +1588,6 @@ vin-supply = <&vdd_sys_mux>; regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; }; vdd_5v0_io: regulator-vdd-5v0-io { @@ -1610,7 +1609,6 @@ vin-supply = <&vdd_3v3_sys>; regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; }; vdd_dsi_csi: regulator-vdd-dsi-csi { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9fc4a8f46250a..542f51c07781e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -282,7 +281,6 @@ regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -298,7 +296,6 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <350>; regulator-always-on; @@ -314,7 +311,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <360>; regulator-always-on; @@ -330,7 +326,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-always-on; @@ -346,7 +341,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -360,7 +354,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -378,7 +371,6 @@ regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; @@ -403,7 +395,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -417,7 +408,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -1779,7 +1769,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; regulator-always-on; regulator-boot-on; -- GitLab From 635fb5d4cb2590f3f655f05f880cefabf1cb43dd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:54:48 +0100 Subject: [PATCH 727/965] arm64: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 5cfbc0394173c..10347b6e6e847 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1383,7 +1383,7 @@ }; }; - gpio@0 { + hog-0 { gpio-hog; output-high; gpios = <2 GPIO_ACTIVE_HIGH>, -- GitLab From 31bc882c03d447b7ae5c28ed5480467ee714fd91 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:41:53 +0100 Subject: [PATCH 728/965] arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 3 --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 5 ----- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 2e17df6f20ad7..328fbfec4ee8d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -11,11 +11,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 21d7e653ea5b8..4b43b89a9651d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1361,11 +1361,6 @@ dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; -- GitLab From 54215999f30bf7672c302b34c91db76eed525b5e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:43:03 +0100 Subject: [PATCH 729/965] arm64: tegra: smaug: Remove extra PLL power supplies for XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the XUSB controller device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 6d59c28ff2a37..a263d51882ee7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1642,10 +1642,6 @@ dvddio-pex-supply = <&avddio_1v05>; hvddio-pex-supply = <&pp1800>; avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; status = "okay"; }; -- GitLab From 9c1b3ef8e204ca952d0304d4b92fa54de8b9815a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:56:11 +0100 Subject: [PATCH 730/965] arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 542f51c07781e..72c2dc3c14eac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -30,11 +30,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { @@ -446,11 +443,6 @@ avdd-usb-supply = <&vdd_3v3_sys>; dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; }; -- GitLab From 28a44b900e572ecb163cc4e042365b7df6e0fad3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:01:37 +0100 Subject: [PATCH 731/965] arm64: tegra: Add missing TSEC properties on Tegra210 Add missing interrupts, clocks, clock-names, reset and reset-names properties for the TSEC blocks found on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index af9237ad03c15..a49a12fd84b1b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -181,6 +181,12 @@ tsec@54100000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54100000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSEC>; + clock-names = "tsec"; + resets = <&tegra_car 83>; + reset-names = "tsec"; + status = "disabled"; }; dc@54200000 { @@ -283,6 +289,11 @@ tsec@54500000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSECB>; + clock-names = "tsec"; + resets = <&tegra_car 206>; + reset-names = "tsec"; status = "disabled"; }; -- GitLab From f2ef6a9180f38f7b6f633a90126d27e8a669a688 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:05:32 +0100 Subject: [PATCH 732/965] arm64: tegra: Sort Tegra210 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a49a12fd84b1b..aa768ea108fec 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1026,8 +1026,8 @@ <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1035,7 +1035,7 @@ <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, -- GitLab From 02752947367289e8bfd0f09f9c4a5acfb0ac3602 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:06:19 +0100 Subject: [PATCH 733/965] arm64: tegra: Remove unused only-1-8-v properties The only-1-8-v property is not support by an DT schema, so drop it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d3c9368221866..d95a542c0bca1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -11,7 +11,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts index b5d9a55262724..5804acfc428ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -26,7 +26,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { -- GitLab From 553f07360e23b2e17b26be2fcd9ebfc0c14d0e24 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Dec 2021 16:29:11 +0100 Subject: [PATCH 734/965] arm64: tegra: Rename Ethernet PHY nodes Name the Ethernet PHY device tree nodes as expected by the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 3d8878c0ec035..aff857df25cf4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 6cc51083adb71..4631504c3c7a6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio_aon>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index ad217cac2b280..a7d7cfd66379f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -39,7 +39,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index f16b0aa8a374e..0bd66f9c620b9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; -- GitLab From a52280c844c0549b16418dc7e70bdf46a66072eb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 25 Oct 2021 12:08:42 +0100 Subject: [PATCH 735/965] arm64: tegra: Add dma-coherent for Tegra194 VIC DMA operations for the Tegra194 Video Image Compositor (VIC) are coherent and so populate the 'dma-coherent' property. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index abea546cb0722..aeb79660c58e0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1811,6 +1811,7 @@ <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_VIC>; + dma-coherent; }; nvjpg@15380000 { -- GitLab From c2fee44399af4fda2dd8070cfb96cd6de2385442 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Thu, 16 Dec 2021 15:16:10 +0530 Subject: [PATCH 736/965] arm64: tegra: Update SDMMC4 speeds for Tegra194 Add required device-tree properties to populate all speed modes supported by SDMMC4 instance of Tegra194 SDHCI controller. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index aeb79660c58e0..c830f508de426 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -976,6 +976,11 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; supports-cqe; status = "disabled"; }; -- GitLab From cc9396676c1bc4414fa62514daadfece55ef3cfb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:49 +0100 Subject: [PATCH 737/965] arm64: tegra: Add EMC general interrupt on Tegra194 Add the missing EMC general interrupt for the external memory controller on Tegra194. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c830f508de426..3c4acfca459d1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -592,6 +592,7 @@ compatible = "nvidia,tegra194-emc"; reg = <0x0 0x02c60000 0x0 0x90000>, <0x0 0x01780000 0x0 0x80000>; + interrupts = ; clocks = <&bpmp TEGRA194_CLK_EMC>; clock-names = "emc"; -- GitLab From eed280dfe91d84d6b9ad62e47d1b69aa8d9b4db2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:50 +0100 Subject: [PATCH 738/965] arm64: tegra: Add memory controller on Tegra234 This adds the memory controller and the embedded external memory controller found on the Tegra234 SoC. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index b60e4f6f06580..59ad115369bda 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include / { @@ -84,6 +85,54 @@ gpio-controller; }; + mc: memory-controller@2c00000 { + compatible = "nvidia,tegra234-mc"; + reg = <0x02c00000 0x100000>, + <0x02b80000 0x040000>, + <0x01700000 0x100000>; + interrupts = ; + #interconnect-cells = <1>; + status = "okay"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + + /* + * Bit 39 of addresses passing through the memory + * controller selects the XBAR format used when memory + * is accessed. This is used to transparently access + * memory in the XBAR format used by the discrete GPU + * (bit 39 set) or Tegra (bit 39 clear). + * + * As a consequence, the operating system must ensure + * that bit 39 is never used implicitly, for example + * via an I/O virtual address mapping of an IOMMU. If + * devices require access to the XBAR switch, their + * drivers must set this bit explicitly. + * + * Limit the DMA range for memory clients to [38:0]. + */ + dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra234-emc"; + reg = <0x0 0x02c60000 0x0 0x90000>, + <0x0 0x01780000 0x0 0x80000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_EMC>; + clock-names = "emc"; + status = "okay"; + + #interconnect-cells = <0>; + + nvidia,bpmp = <&bpmp>; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; -- GitLab From 6de481e5ab0d69cddbc7c20e8471a950313d4e07 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:51 +0100 Subject: [PATCH 739/965] arm64: tegra: Hook up MMC and BPMP to memory controller Use the interconnects property to hook up the MMC and BPMP to the memory controller. This is needed to set the correct bus-level DMA mask, which is a prerequisite for adding IOMMU support. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 59ad115369bda..6b6f15804a1a5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -156,6 +156,9 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -288,6 +291,11 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; -- GitLab From 73e2b72a3518fb60b6a1c11286715f933bafdec2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:44 +0300 Subject: [PATCH 740/965] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra30 SoC. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- arch/arm/boot/dts/tegra30-ouya.dts | 1 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1224 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 153 +++ 7 files changed, 1395 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index d79a99470ac20..2c2ad2a38f04b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -968,6 +968,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 7c2b70b13cc4d..5ad62b567d328 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1916,6 +1916,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index c2a56eb0b9fa8..ba257ed36d9cd 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -393,6 +393,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 9bf8170fee798..be691a1c33a13 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -767,9 +767,14 @@ vddctrl_reg: vddctrl { regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; reg_1v8_vio: vio { @@ -892,15 +897,20 @@ }; /* SW: +V1.2_VDD_CORE */ - regulator@60 { + vdd_core: regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "tps62362-vout"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; + + nvidia,tegra-core-regulator; }; }; @@ -913,6 +923,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b28c5504e1b19..e604ad08a2c2b 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -2195,6 +2195,7 @@ nvidia,core-pwr-off-time = <458>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index af96404014024..d100a1a8b705e 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,6 +1,56 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1350000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-level = <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt = <1050000 1050000 1350000>; + opp-level = <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1350000>; + opp-level = <1100000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt = <1150000 1150000 1350000>; + opp-level = <1150000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-level = <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt = <1250000 1250000 1350000>; + opp-level = <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1350000>; + opp-level = <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt = <1350000 1350000 1350000>; + opp-level = <1350000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,126 +58,147 @@ opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; }; opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -135,6 +206,7 @@ opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; opp-suspend; }; @@ -142,138 +214,161 @@ opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-500000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-500000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; }; }; @@ -401,4 +496,1133 @@ opp-peak-kBps = <7200000>; }; }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-188000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-222000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <222000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-242000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <242000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-254000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <254000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-216000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-219000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <219000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-267000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-371000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <371000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1150>; + }; + + opp-409000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <409000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-425000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <425000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-470000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <470000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>, <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>, <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>, <&core_opp_1350>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + dsia_dvfs_opp_table: opp-table-dsia { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + dsib_dvfs_opp_table: opp-table-dsib { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-51000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-136000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <136000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-164000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-191000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <191000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-205000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <205000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-216000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1150>; + }; + + opp-227000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <227000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1100>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-334000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <334000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-378000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <378000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-1200000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1350>; + }; + }; + + pll_e_dvfs_opp_table: opp-table-plle { + compatible = "operating-points-v2"; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-228000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-275000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-352000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <352000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-400000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-437000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <437000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + fuse_burn_dvfs_opp_table: opp-table-fuseburn { + compatible = "operating-points-v2"; + + opp-26000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <26000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1150>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-108000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-115000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <115000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-130000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-133000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + }; + + pwm_dvfs_opp_table: opp-table-pwm { + compatible = "operating-points-v2"; + + opp-408000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 46befba0bc72b..83095a467b350 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -55,6 +55,8 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; status = "disabled"; pci@1,0 { @@ -124,6 +126,8 @@ resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; + power-domains = <&pd_heg>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -137,6 +141,8 @@ clocks = <&tegra_car TEGRA30_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; }; @@ -148,6 +154,8 @@ clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; }; @@ -159,6 +167,8 @@ clocks = <&tegra_car TEGRA30_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_heg>; + operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; }; @@ -170,6 +180,7 @@ clocks = <&tegra_car TEGRA30_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; }; @@ -181,6 +192,8 @@ clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_heg>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -194,6 +207,9 @@ resets = <&tegra_car 24>, <&tegra_car 98>; reset-names = "3d", "3d2"; + power-domains = <&pd_3d0>, <&pd_3d1>; + power-domain-names = "3d0", "3d1"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_NV>, <&mc TEGRA_SWGROUP_NV2>; @@ -208,6 +224,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DC>; @@ -238,6 +256,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DCB>; @@ -268,6 +288,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -276,6 +298,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -287,6 +311,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsia_dvfs_opp_table>; status = "disabled"; }; @@ -298,6 +324,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 84>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsib_dvfs_opp_table>; status = "disabled"; }; }; @@ -358,6 +386,34 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; + + pll-c { + compatible = "nvidia,tegra30-pllc"; + clocks = <&tegra_car TEGRA30_CLK_PLL_C>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_c_dvfs_opp_table>; + }; + + pll-e { + compatible = "nvidia,tegra30-plle"; + clocks = <&tegra_car TEGRA30_CLK_PLL_E>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_e_dvfs_opp_table>; + }; + + pll-m { + compatible = "nvidia,tegra30-pllm"; + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_m_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -468,6 +524,8 @@ reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -565,6 +623,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -575,6 +635,8 @@ clocks = <&tegra_car TEGRA30_CLK_PWM>; resets = <&tegra_car 17>; reset-names = "pwm"; + power-domains = <&pd_core>; + operating-points-v2 = <&pwm_dvfs_opp_table>; status = "disabled"; }; @@ -676,6 +738,8 @@ reset-names = "spi"; dmas = <&apbdma 15>, <&apbdma 15>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc1_dvfs_opp_table>; status = "disabled"; }; @@ -690,6 +754,8 @@ reset-names = "spi"; dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc2_dvfs_opp_table>; status = "disabled"; }; @@ -704,6 +770,8 @@ reset-names = "spi"; dmas = <&apbdma 17>, <&apbdma 17>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc3_dvfs_opp_table>; status = "disabled"; }; @@ -718,6 +786,8 @@ reset-names = "spi"; dmas = <&apbdma 18>, <&apbdma 18>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc4_dvfs_opp_table>; status = "disabled"; }; @@ -732,6 +802,8 @@ reset-names = "spi"; dmas = <&apbdma 27>, <&apbdma 27>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc5_dvfs_opp_table>; status = "disabled"; }; @@ -746,6 +818,8 @@ reset-names = "spi"; dmas = <&apbdma 28>, <&apbdma 28>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc6_dvfs_opp_table>; status = "disabled"; }; @@ -765,6 +839,72 @@ clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d0: td { + clocks = <&tegra_car TEGRA30_CLK_GR3D>; + resets = <&mc TEGRA30_MC_RESET_3D>, + <&tegra_car TEGRA30_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d1: td2 { + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; + resets = <&mc TEGRA30_MC_RESET_3D2>, + <&tegra_car TEGRA30_CLK_GR3D2>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car TEGRA30_CLK_VI>, + <&tegra_car TEGRA30_CLK_CSI>; + resets = <&mc TEGRA30_MC_RESET_ISP>, + <&mc TEGRA30_MC_RESET_VI>, + <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA30_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -785,6 +925,7 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; + power-domains = <&pd_core>; nvidia,memory-controller = <&mc>; operating-points-v2 = <&emc_icc_dvfs_opp_table>; @@ -799,6 +940,8 @@ clock-names = "fuse"; resets = <&tegra_car 39>; reset-names = "fuse"; + power-domains = <&pd_core>; + operating-points-v2 = <&fuse_burn_dvfs_opp_table>; }; tsensor: tsensor@70014000 { @@ -921,6 +1064,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -943,6 +1088,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -967,6 +1114,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -1008,6 +1157,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -1048,6 +1199,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; -- GitLab From 1caf3ef4c0febbfe3180da3a57e53ebfa4a0fa3b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:45 +0300 Subject: [PATCH 741/965] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 45fe111705aff..4068952cc6c0f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -40,8 +40,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -98,8 +98,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&gr2d_dvfs_opp_table>; }; @@ -108,8 +108,8 @@ compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; power-domains = <&pd_3d>; operating-points-v2 = <&gr3d_dvfs_opp_table>; }; -- GitLab From 2c16be669291b7be4df37066acc331615f747182 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:46 +0300 Subject: [PATCH 742/965] ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 83095a467b350..b0160883336f1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -123,8 +123,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; power-domains = <&pd_heg>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -190,8 +190,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_heg>; operating-points-v2 = <&gr2d_dvfs_opp_table>; @@ -205,8 +205,10 @@ <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, - <&tegra_car 98>; - reset-names = "3d", "3d2"; + <&tegra_car 98>, + <&mc TEGRA30_MC_RESET_3D>, + <&mc TEGRA30_MC_RESET_3D2>; + reset-names = "3d", "3d2", "mc", "mc2"; power-domains = <&pd_3d0>, <&pd_3d1>; power-domain-names = "3d0", "3d1"; operating-points-v2 = <&gr3d_dvfs_opp_table>; -- GitLab From 279e7aa30424ea900d34ef3a540e2f26a930353d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:47 +0300 Subject: [PATCH 743/965] ARM: tegra20/30: Disable unused host1x hardware MPE, VI, EPP and ISP were never used and we don't have drivers for them. Since these modules are enabled by default in a device-tree, a device is created for them, blocking voltage scaling because there is no driver to bind, and thus, state of PMC driver is never synced. Disable them. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 4068952cc6c0f..c8f2061b927f3 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -59,6 +59,7 @@ reset-names = "mpe"; power-domains = <&pd_mpe>; operating-points-v2 = <&mpe_dvfs_opp_table>; + status = "disabled"; }; vi@54080000 { @@ -70,6 +71,7 @@ reset-names = "vi"; power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; + status = "disabled"; }; epp@540c0000 { @@ -81,6 +83,7 @@ reset-names = "epp"; power-domains = <&pd_core>; operating-points-v2 = <&epp_dvfs_opp_table>; + status = "disabled"; }; isp@54100000 { @@ -91,6 +94,7 @@ resets = <&tegra_car 23>; reset-names = "isp"; power-domains = <&pd_venc>; + status = "disabled"; }; gr2d@54140000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b0160883336f1..dc1f863096723 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -145,6 +145,8 @@ operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; + + status = "disabled"; }; vi@54080000 { @@ -158,6 +160,8 @@ operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; }; epp@540c0000 { @@ -171,6 +175,8 @@ operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; }; isp@54100000 { @@ -183,6 +189,8 @@ power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; }; gr2d@54140000 { -- GitLab From dcbc40848de4f07a0c92a348a57d078e881292c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:22 +0300 Subject: [PATCH 744/965] ARM: tegra: Add S/PDIF node to Tegra20 device-tree Add S/PDIF node to Tegra20 device-tree. It's needed for enabling HDMI audio support. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c8f2061b927f3..2d2f446373b25 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -189,6 +189,7 @@ reset-names = "hdmi"; power-domains = <&pd_core>; operating-points-v2 = <&hdmi_dvfs_opp_table>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -388,6 +389,23 @@ status = "disabled"; }; + tegra_spdif: spdif@70002400 { + compatible = "nvidia,tegra20-spdif"; + reg = <0x70002400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, + <&tegra_car TEGRA20_CLK_SPDIF_IN>; + clock-names = "out", "in"; + resets = <&tegra_car 10>; + dmas = <&apbdma 3>, <&apbdma 3>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; + }; + tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; -- GitLab From dd2cac867a786cb13821f98afd6730761ebc0773 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:23 +0300 Subject: [PATCH 745/965] ARM: tegra: Add HDMI audio graph to Tegra20 device-tree Add HDMI audio graph to Tegra20 device-tree to enable HDMI audio on Tegra20 devices. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2d2f446373b25..1bf5bd5efd93f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -178,7 +178,7 @@ }; }; - hdmi@54280000 { + tegra_hdmi: hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = ; @@ -1040,4 +1040,24 @@ interrupt-affinity = <&{/cpus/cpu@0}>, <&{/cpus/cpu@1}>; }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "NVIDIA Tegra20 HDMI"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + + cpu { + sound-dai = <&tegra_spdif>; + }; + + codec { + sound-dai = <&tegra_hdmi>; + }; + }; + }; }; -- GitLab From 7a53acabf80fc7b3462c52da4eb04daa213c7619 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:24 +0300 Subject: [PATCH 746/965] ARM: tegra: acer-a500: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Acer A500. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 4aa0eb0c50fec..a170a4ba36c15 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -376,8 +376,16 @@ }; }; + tegra_spdif: spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + tegra_i2s1: i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; uartb: serial@70006040 { -- GitLab From 919be27fd0046ed2554f1ff9cbd49d3798446cb5 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:25 +0300 Subject: [PATCH 747/965] ARM: tegra: paz00: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Tested-by: Agneli Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index fe1bffedc266a..d53a175dc17a2 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -264,8 +264,16 @@ }; }; + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; serial@70006000 { -- GitLab From 9ca9a608a787f0f67adea8757fad86d6632c6232 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 26 Jul 2018 17:40:25 +0200 Subject: [PATCH 748/965] ARM: tegra: Add back gpio-ranges properties The properties have been commented out to prevent a regression a while ago. The first regression should be resolved by commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time"). The second regression is probably addressed by commit 494fd7b7ad10 ("PM / core: fix deferred probe breaking suspend resume order") and/or maybe others. Readd the gpio-ranges properties to see whether regressions still get reported. This reverts commit 4f1d841475e1 ("ARM: tegra: Comment out gpio-ranges properties"). Signed-off-by: Stefan Agner Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko [treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 -- arch/arm/boot/dts/tegra124.dtsi | 2 -- arch/arm/boot/dts/tegra20.dtsi | 2 -- arch/arm/boot/dts/tegra30-ouya.dts | 4 ---- arch/arm/boot/dts/tegra30.dtsi | 2 -- 5 files changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ae1be90a9385c..f20be4ca16a14 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -261,9 +261,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 246>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index e87da6c24f7cd..ada152b50ade7 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -308,9 +308,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 251>; - */ }; apbdma: dma@60020000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1bf5bd5efd93f..62bf0b3064721 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -328,9 +328,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 224>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e604ad08a2c2b..a5cfbab5f565f 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -68,10 +68,6 @@ }; }; - gpio: gpio@6000d000 { - gpio-ranges = <&pinmux 0 0 248>; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dc1f863096723..9dab8d2c158a7 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -507,9 +507,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 248>; - */ }; vde@6001a000 { -- GitLab From 38bb8a7264daf0ff5bb3024ae94bc465de78203d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Jun 2021 11:29:51 +0200 Subject: [PATCH 749/965] dt-bindings: clock: starfive: Add JH7100 clock definitions Add all clock outputs for the StarFive JH7100 clock generator. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- include/dt-bindings/clock/starfive-jh7100.h | 202 ++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 include/dt-bindings/clock/starfive-jh7100.h diff --git a/include/dt-bindings/clock/starfive-jh7100.h b/include/dt-bindings/clock/starfive-jh7100.h new file mode 100644 index 0000000000000..aa0863b9728d9 --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7100.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ + +#define JH7100_CLK_CPUNDBUS_ROOT 0 +#define JH7100_CLK_DLA_ROOT 1 +#define JH7100_CLK_DSP_ROOT 2 +#define JH7100_CLK_GMACUSB_ROOT 3 +#define JH7100_CLK_PERH0_ROOT 4 +#define JH7100_CLK_PERH1_ROOT 5 +#define JH7100_CLK_VIN_ROOT 6 +#define JH7100_CLK_VOUT_ROOT 7 +#define JH7100_CLK_AUDIO_ROOT 8 +#define JH7100_CLK_CDECHIFI4_ROOT 9 +#define JH7100_CLK_CDEC_ROOT 10 +#define JH7100_CLK_VOUTBUS_ROOT 11 +#define JH7100_CLK_CPUNBUS_ROOT_DIV 12 +#define JH7100_CLK_DSP_ROOT_DIV 13 +#define JH7100_CLK_PERH0_SRC 14 +#define JH7100_CLK_PERH1_SRC 15 +#define JH7100_CLK_PLL0_TESTOUT 16 +#define JH7100_CLK_PLL1_TESTOUT 17 +#define JH7100_CLK_PLL2_TESTOUT 18 +#define JH7100_CLK_PLL2_REF 19 +#define JH7100_CLK_CPU_CORE 20 +#define JH7100_CLK_CPU_AXI 21 +#define JH7100_CLK_AHB_BUS 22 +#define JH7100_CLK_APB1_BUS 23 +#define JH7100_CLK_APB2_BUS 24 +#define JH7100_CLK_DOM3AHB_BUS 25 +#define JH7100_CLK_DOM7AHB_BUS 26 +#define JH7100_CLK_U74_CORE0 27 +#define JH7100_CLK_U74_CORE1 28 +#define JH7100_CLK_U74_AXI 29 +#define JH7100_CLK_U74RTC_TOGGLE 30 +#define JH7100_CLK_SGDMA2P_AXI 31 +#define JH7100_CLK_DMA2PNOC_AXI 32 +#define JH7100_CLK_SGDMA2P_AHB 33 +#define JH7100_CLK_DLA_BUS 34 +#define JH7100_CLK_DLA_AXI 35 +#define JH7100_CLK_DLANOC_AXI 36 +#define JH7100_CLK_DLA_APB 37 +#define JH7100_CLK_VP6_CORE 38 +#define JH7100_CLK_VP6BUS_SRC 39 +#define JH7100_CLK_VP6_AXI 40 +#define JH7100_CLK_VCDECBUS_SRC 41 +#define JH7100_CLK_VDEC_BUS 42 +#define JH7100_CLK_VDEC_AXI 43 +#define JH7100_CLK_VDECBRG_MAIN 44 +#define JH7100_CLK_VDEC_BCLK 45 +#define JH7100_CLK_VDEC_CCLK 46 +#define JH7100_CLK_VDEC_APB 47 +#define JH7100_CLK_JPEG_AXI 48 +#define JH7100_CLK_JPEG_CCLK 49 +#define JH7100_CLK_JPEG_APB 50 +#define JH7100_CLK_GC300_2X 51 +#define JH7100_CLK_GC300_AHB 52 +#define JH7100_CLK_JPCGC300_AXIBUS 53 +#define JH7100_CLK_GC300_AXI 54 +#define JH7100_CLK_JPCGC300_MAIN 55 +#define JH7100_CLK_VENC_BUS 56 +#define JH7100_CLK_VENC_AXI 57 +#define JH7100_CLK_VENCBRG_MAIN 58 +#define JH7100_CLK_VENC_BCLK 59 +#define JH7100_CLK_VENC_CCLK 60 +#define JH7100_CLK_VENC_APB 61 +#define JH7100_CLK_DDRPLL_DIV2 62 +#define JH7100_CLK_DDRPLL_DIV4 63 +#define JH7100_CLK_DDRPLL_DIV8 64 +#define JH7100_CLK_DDROSC_DIV2 65 +#define JH7100_CLK_DDRC0 66 +#define JH7100_CLK_DDRC1 67 +#define JH7100_CLK_DDRPHY_APB 68 +#define JH7100_CLK_NOC_ROB 69 +#define JH7100_CLK_NOC_COG 70 +#define JH7100_CLK_NNE_AHB 71 +#define JH7100_CLK_NNEBUS_SRC1 72 +#define JH7100_CLK_NNE_BUS 73 +#define JH7100_CLK_NNE_AXI 74 +#define JH7100_CLK_NNENOC_AXI 75 +#define JH7100_CLK_DLASLV_AXI 76 +#define JH7100_CLK_DSPX2C_AXI 77 +#define JH7100_CLK_HIFI4_SRC 78 +#define JH7100_CLK_HIFI4_COREFREE 79 +#define JH7100_CLK_HIFI4_CORE 80 +#define JH7100_CLK_HIFI4_BUS 81 +#define JH7100_CLK_HIFI4_AXI 82 +#define JH7100_CLK_HIFI4NOC_AXI 83 +#define JH7100_CLK_SGDMA1P_BUS 84 +#define JH7100_CLK_SGDMA1P_AXI 85 +#define JH7100_CLK_DMA1P_AXI 86 +#define JH7100_CLK_X2C_AXI 87 +#define JH7100_CLK_USB_BUS 88 +#define JH7100_CLK_USB_AXI 89 +#define JH7100_CLK_USBNOC_AXI 90 +#define JH7100_CLK_USBPHY_ROOTDIV 91 +#define JH7100_CLK_USBPHY_125M 92 +#define JH7100_CLK_USBPHY_PLLDIV25M 93 +#define JH7100_CLK_USBPHY_25M 94 +#define JH7100_CLK_AUDIO_DIV 95 +#define JH7100_CLK_AUDIO_SRC 96 +#define JH7100_CLK_AUDIO_12288 97 +#define JH7100_CLK_VIN_SRC 98 +#define JH7100_CLK_ISP0_BUS 99 +#define JH7100_CLK_ISP0_AXI 100 +#define JH7100_CLK_ISP0NOC_AXI 101 +#define JH7100_CLK_ISPSLV_AXI 102 +#define JH7100_CLK_ISP1_BUS 103 +#define JH7100_CLK_ISP1_AXI 104 +#define JH7100_CLK_ISP1NOC_AXI 105 +#define JH7100_CLK_VIN_BUS 106 +#define JH7100_CLK_VIN_AXI 107 +#define JH7100_CLK_VINNOC_AXI 108 +#define JH7100_CLK_VOUT_SRC 109 +#define JH7100_CLK_DISPBUS_SRC 110 +#define JH7100_CLK_DISP_BUS 111 +#define JH7100_CLK_DISP_AXI 112 +#define JH7100_CLK_DISPNOC_AXI 113 +#define JH7100_CLK_SDIO0_AHB 114 +#define JH7100_CLK_SDIO0_CCLKINT 115 +#define JH7100_CLK_SDIO0_CCLKINT_INV 116 +#define JH7100_CLK_SDIO1_AHB 117 +#define JH7100_CLK_SDIO1_CCLKINT 118 +#define JH7100_CLK_SDIO1_CCLKINT_INV 119 +#define JH7100_CLK_GMAC_AHB 120 +#define JH7100_CLK_GMAC_ROOT_DIV 121 +#define JH7100_CLK_GMAC_PTP_REF 122 +#define JH7100_CLK_GMAC_GTX 123 +#define JH7100_CLK_GMAC_RMII_TX 124 +#define JH7100_CLK_GMAC_RMII_RX 125 +#define JH7100_CLK_GMAC_TX 126 +#define JH7100_CLK_GMAC_TX_INV 127 +#define JH7100_CLK_GMAC_RX_PRE 128 +#define JH7100_CLK_GMAC_RX_INV 129 +#define JH7100_CLK_GMAC_RMII 130 +#define JH7100_CLK_GMAC_TOPHYREF 131 +#define JH7100_CLK_SPI2AHB_AHB 132 +#define JH7100_CLK_SPI2AHB_CORE 133 +#define JH7100_CLK_EZMASTER_AHB 134 +#define JH7100_CLK_E24_AHB 135 +#define JH7100_CLK_E24RTC_TOGGLE 136 +#define JH7100_CLK_QSPI_AHB 137 +#define JH7100_CLK_QSPI_APB 138 +#define JH7100_CLK_QSPI_REF 139 +#define JH7100_CLK_SEC_AHB 140 +#define JH7100_CLK_AES 141 +#define JH7100_CLK_SHA 142 +#define JH7100_CLK_PKA 143 +#define JH7100_CLK_TRNG_APB 144 +#define JH7100_CLK_OTP_APB 145 +#define JH7100_CLK_UART0_APB 146 +#define JH7100_CLK_UART0_CORE 147 +#define JH7100_CLK_UART1_APB 148 +#define JH7100_CLK_UART1_CORE 149 +#define JH7100_CLK_SPI0_APB 150 +#define JH7100_CLK_SPI0_CORE 151 +#define JH7100_CLK_SPI1_APB 152 +#define JH7100_CLK_SPI1_CORE 153 +#define JH7100_CLK_I2C0_APB 154 +#define JH7100_CLK_I2C0_CORE 155 +#define JH7100_CLK_I2C1_APB 156 +#define JH7100_CLK_I2C1_CORE 157 +#define JH7100_CLK_GPIO_APB 158 +#define JH7100_CLK_UART2_APB 159 +#define JH7100_CLK_UART2_CORE 160 +#define JH7100_CLK_UART3_APB 161 +#define JH7100_CLK_UART3_CORE 162 +#define JH7100_CLK_SPI2_APB 163 +#define JH7100_CLK_SPI2_CORE 164 +#define JH7100_CLK_SPI3_APB 165 +#define JH7100_CLK_SPI3_CORE 166 +#define JH7100_CLK_I2C2_APB 167 +#define JH7100_CLK_I2C2_CORE 168 +#define JH7100_CLK_I2C3_APB 169 +#define JH7100_CLK_I2C3_CORE 170 +#define JH7100_CLK_WDTIMER_APB 171 +#define JH7100_CLK_WDT_CORE 172 +#define JH7100_CLK_TIMER0_CORE 173 +#define JH7100_CLK_TIMER1_CORE 174 +#define JH7100_CLK_TIMER2_CORE 175 +#define JH7100_CLK_TIMER3_CORE 176 +#define JH7100_CLK_TIMER4_CORE 177 +#define JH7100_CLK_TIMER5_CORE 178 +#define JH7100_CLK_TIMER6_CORE 179 +#define JH7100_CLK_VP6INTC_APB 180 +#define JH7100_CLK_PWM_APB 181 +#define JH7100_CLK_MSI_APB 182 +#define JH7100_CLK_TEMP_APB 183 +#define JH7100_CLK_TEMP_SENSE 184 +#define JH7100_CLK_SYSERR_APB 185 + +#define JH7100_CLK_PLL0_OUT 186 +#define JH7100_CLK_PLL1_OUT 187 +#define JH7100_CLK_PLL2_OUT 188 + +#define JH7100_CLK_END 189 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */ -- GitLab From af35098f4fcd1f9bfc58dc37479e0786a4d85e96 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 1 Jun 2021 16:02:23 +0200 Subject: [PATCH 750/965] dt-bindings: clock: starfive: Add JH7100 bindings Add bindings for the clock generator on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- .../clock/starfive,jh7100-clkgen.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml new file mode 100644 index 0000000000000..12f17b60ecbeb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Clock Generator + +maintainers: + - Geert Uytterhoeven + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7100-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main clock source (25 MHz) + - description: Application-specific clock source (12-27 MHz) + - description: RMII reference clock (50 MHz) + - description: RGMII RX clock (125 MHz) + + clock-names: + items: + - const: osc_sys + - const: osc_aud + - const: gmac_rmii_ref + - const: gmac_gr_mii_rxclk + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x11800000 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; -- GitLab From 4210be668a09ee20e4e1c7adf61b47d33d05c480 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 1 Jun 2021 15:57:52 +0200 Subject: [PATCH 751/965] clk: starfive: Add JH7100 clock generator driver Add a driver for the StarFive JH7100 clock generator. Reviewed-by: Andy Shevchenko Acked-by: Stephen Boyd Signed-off-by: Geert Uytterhoeven Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing --- MAINTAINERS | 7 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 9 + drivers/clk/starfive/Makefile | 3 + drivers/clk/starfive/clk-starfive-jh7100.c | 689 +++++++++++++++++++++ 6 files changed, 710 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.c diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce85213..2548ef1f82460 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18130,6 +18130,13 @@ M: Ion Badulescu S: Odd Fixes F: drivers/net/ethernet/adaptec/starfire* +STARFIVE JH7100 CLOCK DRIVER +M: Emil Renner Berthing +S: Maintained +F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml +F: drivers/clk/starfive/clk-starfive-jh7100.c +F: include/dt-bindings/clock/starfive-jh7100.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c5b3dc97396a6..c91931c94888e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -412,6 +412,7 @@ source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/socfpga/Kconfig" source "drivers/clk/sprd/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sunxi-ng/Kconfig" source "drivers/clk/tegra/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e42312121e511..a9bb2478fbddd 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -109,6 +109,7 @@ obj-y += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_ARCH_STI) += st/ +obj-$(CONFIG_SOC_STARFIVE) += starfive/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 0000000000000..c0fa9d5e641fe --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_STARFIVE_JH7100 + bool "StarFive JH7100 clock support" + depends on SOC_STARFIVE || COMPILE_TEST + default SOC_STARFIVE + help + Say yes here to support the clock controller on the StarFive JH7100 + SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 0000000000000..09759cc735307 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +# StarFive Clock +obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c new file mode 100644 index 0000000000000..25d31afa0f871 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -0,0 +1,689 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7100 Clock Generator Driver + * + * Copyright 2021 Ahmad Fatoum, Pengutronix + * Copyright (C) 2021 Glider bv + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* external clocks */ +#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0) +#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1) +#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) +#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) + +/* register fields */ +#define JH7100_CLK_ENABLE BIT(31) +#define JH7100_CLK_INVERT BIT(30) +#define JH7100_CLK_MUX_MASK GENMASK(27, 24) +#define JH7100_CLK_MUX_SHIFT 24 +#define JH7100_CLK_DIV_MASK GENMASK(23, 0) + +/* clock data */ +#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT | (_flags), \ + .max = JH7100_CLK_ENABLE, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = _max, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | (_max), \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT, \ + .max = JH7100_CLK_INVERT, \ + .parents = { [0] = _parent }, \ +} + +static const struct { + const char *name; + unsigned long flags; + u32 max; + u8 parents[4]; +} jh7100_clk_data[] __initconst = { + JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT), + JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), + JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT), + JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT), + JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT), + JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT), + JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT), + JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), + JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), + JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_OSC_AUD), + JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE), + JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS), + JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), + JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), + JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), + JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS), + JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI), + JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI), + JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT), + JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS), + JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS), + JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV), + JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT), + JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC), + JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT), + JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC), + JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS), + JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS), + JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), + JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), + JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT), + JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC), + JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS), + JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS), + JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC), + JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS), + JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS), + JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), + JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), + JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT), + JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2), + JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4), + JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS), + JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), + JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), + JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS), + JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), + JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), + JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, + JH7100_CLK_CPU_AXI, + JH7100_CLK_NNEBUS_SRC1), + JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), + JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS), + JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS), + JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), + JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT), + JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC), + JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE), + JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE), + JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS), + JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS), + JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), + JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), + JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS), + JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS), + JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT), + JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), + JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV), + JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_USBPHY_PLLDIV25M), + JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT), + JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), + JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), + JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), + JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC), + JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS), + JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS), + JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS), + JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC), + JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS), + JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS), + JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC), + JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS), + JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS), + JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT), + JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT), + JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC), + JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS), + JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS), + JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC), + JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT), + JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC), + JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT), + JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT), + JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV), + JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), + JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), + JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), + JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, + JH7100_CLK_GMAC_GTX, + JH7100_CLK_GMAC_TX_INV, + JH7100_CLK_GMAC_RMII_TX), + JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), + JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, + JH7100_CLK_GMAC_GR_MII_RX, + JH7100_CLK_GMAC_RMII_RX), + JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), + JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF), + JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV), + JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS), + JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS), + JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB), + JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB), + JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB), + JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC), + JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS), + JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS), + JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS), + JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), +}; + +struct jh7100_clk { + struct clk_hw hw; + unsigned int idx; + unsigned int max_div; +}; + +struct jh7100_clk_priv { + /* protect clk enable and set rate/parent from happening at the same time */ + spinlock_t rmw_lock; + struct device *dev; + void __iomem *base; + struct clk_hw *pll[3]; + struct jh7100_clk reg[JH7100_CLK_PLL0_OUT]; +}; + +static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) +{ + return container_of(hw, struct jh7100_clk, hw); +} + +static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk) +{ + return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]); +} + +static u32 jh7100_clk_reg_get(struct jh7100_clk *clk) +{ + struct jh7100_clk_priv *priv = jh7100_priv_from(clk); + void __iomem *reg = priv->base + 4 * clk->idx; + + return readl_relaxed(reg); +} + +static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) +{ + struct jh7100_clk_priv *priv = jh7100_priv_from(clk); + void __iomem *reg = priv->base + 4 * clk->idx; + unsigned long flags; + + spin_lock_irqsave(&priv->rmw_lock, flags); + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + +static int jh7100_clk_enable(struct clk_hw *hw) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + + jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE); + return 0; +} + +static void jh7100_clk_disable(struct clk_hw *hw) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + + jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0); +} + +static int jh7100_clk_is_enabled(struct clk_hw *hw) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + + return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE); +} + +static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK; + + return div ? parent_rate / div : 0; +} + +static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk, + unsigned long rate, unsigned long parent) +{ + unsigned long max = clk->max_div; + unsigned long div = DIV_ROUND_UP(parent, rate); + + return min(div, max); +} + +static int jh7100_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + unsigned long parent = req->best_parent_rate; + unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); + unsigned long div = jh7100_clk_bestdiv(clk, rate, parent); + unsigned long result = parent / div; + + /* + * we want the result clamped by min_rate and max_rate if possible: + * case 1: div hits the max divider value, which means it's less than + * parent / rate, so the result is greater than rate and min_rate in + * particular. we can't do anything about result > max_rate because the + * divider doesn't go any further. + * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is + * always lower or equal to rate and max_rate. however the result may + * turn out lower than min_rate, but then the next higher rate is fine: + * div - 1 = ceil(parent / rate) - 1 < parent / rate + * and thus + * min_rate <= rate < parent / (div - 1) + */ + if (result < req->min_rate && div > 1) + result = parent / (div - 1); + + req->rate = result; + return 0; +} + +static int jh7100_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate); + + jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); + return 0; +} + +static u8 jh7100_clk_get_parent(struct clk_hw *hw) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 value = jh7100_clk_reg_get(clk); + + return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT; +} + +static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 value = (u32)index << JH7100_CLK_MUX_SHIFT; + + jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value); + return 0; +} + +static int jh7100_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_mux_determine_rate_flags(hw, req, 0); +} + +static int jh7100_clk_get_phase(struct clk_hw *hw) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 value = jh7100_clk_reg_get(clk); + + return (value & JH7100_CLK_INVERT) ? 180 : 0; +} + +static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 value; + + if (degrees == 0) + value = 0; + else if (degrees == 180) + value = JH7100_CLK_INVERT; + else + return -EINVAL; + + jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value); + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + static const struct debugfs_reg32 jh7100_clk_reg = { + .name = "CTRL", + .offset = 0, + }; + struct jh7100_clk *clk = jh7100_clk_from(hw); + struct jh7100_clk_priv *priv = jh7100_priv_from(clk); + struct debugfs_regset32 *regset; + + regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); + if (!regset) + return; + + regset->regs = &jh7100_clk_reg; + regset->nregs = 1; + regset->base = priv->base + 4 * clk->idx; + + debugfs_create_regset32("registers", 0400, dentry, regset); +} +#else +#define jh7100_clk_debug_init NULL +#endif + +static const struct clk_ops jh7100_clk_gate_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_div_ops = { + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gdiv_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_mux_ops = { + .determine_rate = jh7100_clk_mux_determine_rate, + .set_parent = jh7100_clk_set_parent, + .get_parent = jh7100_clk_get_parent, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gmux_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .determine_rate = jh7100_clk_mux_determine_rate, + .set_parent = jh7100_clk_set_parent, + .get_parent = jh7100_clk_get_parent, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_inv_ops = { + .get_phase = jh7100_clk_get_phase, + .set_phase = jh7100_clk_set_phase, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops *__init jh7100_clk_ops(u32 max) +{ + if (max & JH7100_CLK_DIV_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gdiv_ops; + return &jh7100_clk_div_ops; + } + + if (max & JH7100_CLK_MUX_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gmux_ops; + return &jh7100_clk_mux_ops; + } + + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gate_ops; + + return &jh7100_clk_inv_ops; +} + +static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh7100_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7100_CLK_PLL0_OUT) + return &priv->reg[idx].hw; + + if (idx < JH7100_CLK_END) + return priv->pll[idx - JH7100_CLK_PLL0_OUT]; + + return ERR_PTR(-EINVAL); +} + +static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) +{ + struct jh7100_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", + "osc_sys", 0, 40, 1); + if (IS_ERR(priv->pll[0])) + return PTR_ERR(priv->pll[0]); + + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", + "osc_sys", 0, 64, 1); + if (IS_ERR(priv->pll[1])) + return PTR_ERR(priv->pll[1]); + + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", + "pll2_refclk", 0, 55, 1); + if (IS_ERR(priv->pll[2])) + return PTR_ERR(priv->pll[2]); + + for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) { + u32 max = jh7100_clk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7100_clk_data[idx].name, + .ops = jh7100_clk_ops(max), + .parent_data = parents, + .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, + .flags = jh7100_clk_data[idx].flags, + }; + struct jh7100_clk *clk = &priv->reg[idx]; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7100_clk_data[idx].parents[i]; + + if (pidx < JH7100_CLK_PLL0_OUT) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx < JH7100_CLK_END) + parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT]; + else if (pidx == JH7100_CLK_OSC_SYS) + parents[i].fw_name = "osc_sys"; + else if (pidx == JH7100_CLK_OSC_AUD) + parents[i].fw_name = "osc_aud"; + else if (pidx == JH7100_CLK_GMAC_RMII_REF) + parents[i].fw_name = "gmac_rmii_ref"; + else if (pidx == JH7100_CLK_GMAC_GR_MII_RX) + parents[i].fw_name = "gmac_gr_mii_rxclk"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH7100_CLK_DIV_MASK; + + ret = devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv); +} + +static const struct of_device_id clk_starfive_jh7100_match[] = { + { .compatible = "starfive,jh7100-clkgen" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_starfive_jh7100_driver = { + .driver = { + .name = "clk-starfive-jh7100", + .of_match_table = clk_starfive_jh7100_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe); -- GitLab From 810e287e83b69ff8563bde15cae9120c802ac5d7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Jun 2021 11:30:00 +0200 Subject: [PATCH 752/965] dt-bindings: reset: Add StarFive JH7100 reset definitions Add all resets for the StarFive JH7100 reset controller. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Acked-by: Rob Herring Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- include/dt-bindings/reset/starfive-jh7100.h | 126 ++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/reset/starfive-jh7100.h diff --git a/include/dt-bindings/reset/starfive-jh7100.h b/include/dt-bindings/reset/starfive-jh7100.h new file mode 100644 index 0000000000000..540e19254f390 --- /dev/null +++ b/include/dt-bindings/reset/starfive-jh7100.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ + +#define JH7100_RSTN_DOM3AHB_BUS 0 +#define JH7100_RSTN_DOM7AHB_BUS 1 +#define JH7100_RST_U74 2 +#define JH7100_RSTN_U74_AXI 3 +#define JH7100_RSTN_SGDMA2P_AHB 4 +#define JH7100_RSTN_SGDMA2P_AXI 5 +#define JH7100_RSTN_DMA2PNOC_AXI 6 +#define JH7100_RSTN_DLA_AXI 7 +#define JH7100_RSTN_DLANOC_AXI 8 +#define JH7100_RSTN_DLA_APB 9 +#define JH7100_RST_VP6_DRESET 10 +#define JH7100_RST_VP6_BRESET 11 +#define JH7100_RSTN_VP6_AXI 12 +#define JH7100_RSTN_VDECBRG_MAIN 13 +#define JH7100_RSTN_VDEC_AXI 14 +#define JH7100_RSTN_VDEC_BCLK 15 +#define JH7100_RSTN_VDEC_CCLK 16 +#define JH7100_RSTN_VDEC_APB 17 +#define JH7100_RSTN_JPEG_AXI 18 +#define JH7100_RSTN_JPEG_CCLK 19 +#define JH7100_RSTN_JPEG_APB 20 +#define JH7100_RSTN_JPCGC300_MAIN 21 +#define JH7100_RSTN_GC300_2X 22 +#define JH7100_RSTN_GC300_AXI 23 +#define JH7100_RSTN_GC300_AHB 24 +#define JH7100_RSTN_VENC_AXI 25 +#define JH7100_RSTN_VENCBRG_MAIN 26 +#define JH7100_RSTN_VENC_BCLK 27 +#define JH7100_RSTN_VENC_CCLK 28 +#define JH7100_RSTN_VENC_APB 29 +#define JH7100_RSTN_DDRPHY_APB 30 +#define JH7100_RSTN_NOC_ROB 31 +#define JH7100_RSTN_NOC_COG 32 +#define JH7100_RSTN_HIFI4_AXI 33 +#define JH7100_RSTN_HIFI4NOC_AXI 34 +#define JH7100_RST_HIFI4_DRESET 35 +#define JH7100_RST_HIFI4_BRESET 36 +#define JH7100_RSTN_USB_AXI 37 +#define JH7100_RSTN_USBNOC_AXI 38 +#define JH7100_RSTN_SGDMA1P_AXI 39 +#define JH7100_RSTN_DMA1P_AXI 40 +#define JH7100_RSTN_X2C_AXI 41 +#define JH7100_RSTN_NNE_AHB 42 +#define JH7100_RSTN_NNE_AXI 43 +#define JH7100_RSTN_NNENOC_AXI 44 +#define JH7100_RSTN_DLASLV_AXI 45 +#define JH7100_RSTN_DSPX2C_AXI 46 +#define JH7100_RSTN_VIN_SRC 47 +#define JH7100_RSTN_ISPSLV_AXI 48 +#define JH7100_RSTN_VIN_AXI 49 +#define JH7100_RSTN_VINNOC_AXI 50 +#define JH7100_RSTN_ISP0_AXI 51 +#define JH7100_RSTN_ISP0NOC_AXI 52 +#define JH7100_RSTN_ISP1_AXI 53 +#define JH7100_RSTN_ISP1NOC_AXI 54 +#define JH7100_RSTN_VOUT_SRC 55 +#define JH7100_RSTN_DISP_AXI 56 +#define JH7100_RSTN_DISPNOC_AXI 57 +#define JH7100_RSTN_SDIO0_AHB 58 +#define JH7100_RSTN_SDIO1_AHB 59 +#define JH7100_RSTN_GMAC_AHB 60 +#define JH7100_RSTN_SPI2AHB_AHB 61 +#define JH7100_RSTN_SPI2AHB_CORE 62 +#define JH7100_RSTN_EZMASTER_AHB 63 +#define JH7100_RST_E24 64 +#define JH7100_RSTN_QSPI_AHB 65 +#define JH7100_RSTN_QSPI_CORE 66 +#define JH7100_RSTN_QSPI_APB 67 +#define JH7100_RSTN_SEC_AHB 68 +#define JH7100_RSTN_AES 69 +#define JH7100_RSTN_PKA 70 +#define JH7100_RSTN_SHA 71 +#define JH7100_RSTN_TRNG_APB 72 +#define JH7100_RSTN_OTP_APB 73 +#define JH7100_RSTN_UART0_APB 74 +#define JH7100_RSTN_UART0_CORE 75 +#define JH7100_RSTN_UART1_APB 76 +#define JH7100_RSTN_UART1_CORE 77 +#define JH7100_RSTN_SPI0_APB 78 +#define JH7100_RSTN_SPI0_CORE 79 +#define JH7100_RSTN_SPI1_APB 80 +#define JH7100_RSTN_SPI1_CORE 81 +#define JH7100_RSTN_I2C0_APB 82 +#define JH7100_RSTN_I2C0_CORE 83 +#define JH7100_RSTN_I2C1_APB 84 +#define JH7100_RSTN_I2C1_CORE 85 +#define JH7100_RSTN_GPIO_APB 86 +#define JH7100_RSTN_UART2_APB 87 +#define JH7100_RSTN_UART2_CORE 88 +#define JH7100_RSTN_UART3_APB 89 +#define JH7100_RSTN_UART3_CORE 90 +#define JH7100_RSTN_SPI2_APB 91 +#define JH7100_RSTN_SPI2_CORE 92 +#define JH7100_RSTN_SPI3_APB 93 +#define JH7100_RSTN_SPI3_CORE 94 +#define JH7100_RSTN_I2C2_APB 95 +#define JH7100_RSTN_I2C2_CORE 96 +#define JH7100_RSTN_I2C3_APB 97 +#define JH7100_RSTN_I2C3_CORE 98 +#define JH7100_RSTN_WDTIMER_APB 99 +#define JH7100_RSTN_WDT 100 +#define JH7100_RSTN_TIMER0 101 +#define JH7100_RSTN_TIMER1 102 +#define JH7100_RSTN_TIMER2 103 +#define JH7100_RSTN_TIMER3 104 +#define JH7100_RSTN_TIMER4 105 +#define JH7100_RSTN_TIMER5 106 +#define JH7100_RSTN_TIMER6 107 +#define JH7100_RSTN_VP6INTC_APB 108 +#define JH7100_RSTN_PWM_APB 109 +#define JH7100_RSTN_MSI_APB 110 +#define JH7100_RSTN_TEMP_APB 111 +#define JH7100_RSTN_TEMP_SENSE 112 +#define JH7100_RSTN_SYSERR_APB 113 + +#define JH7100_RSTN_END 114 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */ -- GitLab From d7d456a5201d2e707318bbdc4fb69a3407eed29e Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 19 Sep 2021 14:34:34 +0200 Subject: [PATCH 753/965] dt-bindings: reset: Add Starfive JH7100 reset bindings Add bindings for the reset controller on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Emil Renner Berthing --- .../bindings/reset/starfive,jh7100-reset.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml new file mode 100644 index 0000000000000..300359a5e14b4 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 SoC Reset Controller Device Tree Bindings + +maintainers: + - Emil Renner Berthing + +properties: + compatible: + enum: + - starfive,jh7100-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@11840000 { + compatible = "starfive,jh7100-reset"; + reg = <0x11840000 0x10000>; + #reset-cells = <1>; + }; + +... -- GitLab From 0be3a1595bf8c7f39153be02c9aae61dd2108576 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 19 Sep 2021 14:21:05 +0200 Subject: [PATCH 754/965] reset: starfive-jh7100: Add StarFive JH7100 reset driver Add a driver for the StarFive JH7100 reset controller. Reviewed-by: Andy Shevchenko Signed-off-by: Emil Renner Berthing --- MAINTAINERS | 7 ++ drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-starfive-jh7100.c | 172 ++++++++++++++++++++++++++ 4 files changed, 187 insertions(+) create mode 100644 drivers/reset/reset-starfive-jh7100.c diff --git a/MAINTAINERS b/MAINTAINERS index 2548ef1f82460..1152f5d946906 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18137,6 +18137,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml F: drivers/clk/starfive/clk-starfive-jh7100.c F: include/dt-bindings/clock/starfive-jh7100.h +STARFIVE JH7100 RESET CONTROLLER DRIVER +M: Emil Renner Berthing +S: Maintained +F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml +F: drivers/reset/reset-starfive-jh7100.c +F: include/dt-bindings/reset/starfive-jh7100.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 85024eb1d2eac..6f8ba0ddc05fe 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -224,6 +224,13 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. +config RESET_STARFIVE_JH7100 + bool "StarFive JH7100 Reset Driver" + depends on SOC_STARFIVE || COMPILE_TEST + default SOC_STARFIVE + help + This enables the reset controller driver for the StarFive JH7100 SoC. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 21d46d8869ff4..bd0a97be18b50 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c new file mode 100644 index 0000000000000..e28a19d271cbc --- /dev/null +++ b/drivers/reset/reset-starfive-jh7100.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Reset driver for the StarFive JH7100 SoC + * + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* register offsets */ +#define JH7100_RESET_ASSERT0 0x00 +#define JH7100_RESET_ASSERT1 0x04 +#define JH7100_RESET_ASSERT2 0x08 +#define JH7100_RESET_ASSERT3 0x0c +#define JH7100_RESET_STATUS0 0x10 +#define JH7100_RESET_STATUS1 0x14 +#define JH7100_RESET_STATUS2 0x18 +#define JH7100_RESET_STATUS3 0x1c + +/* + * Writing a 1 to the n'th bit of the m'th ASSERT register asserts + * line 32m + n, and writing a 0 deasserts the same line. + * Most reset lines have their status inverted so a 0 bit in the STATUS + * register means the line is asserted and a 1 means it's deasserted. A few + * lines don't though, so store the expected value of the status registers when + * all lines are asserted. + */ +static const u64 jh7100_reset_asserted[2] = { + /* STATUS0 */ + BIT_ULL_MASK(JH7100_RST_U74) | + BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | + BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | + /* STATUS1 */ + BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | + BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), + /* STATUS2 */ + BIT_ULL_MASK(JH7100_RST_E24) | + /* STATUS3 */ + 0, +}; + +struct jh7100_reset { + struct reset_controller_dev rcdev; + /* protect registers against concurrent read-modify-write */ + spinlock_t lock; + void __iomem *base; +}; + +static inline struct jh7100_reset * +jh7100_reset_from(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct jh7100_reset, rcdev); +} + +static int jh7100_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct jh7100_reset *data = jh7100_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); + void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64); + void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); + u64 done = jh7100_reset_asserted[offset] & mask; + u64 value; + unsigned long flags; + int ret; + + if (!assert) + done ^= mask; + + spin_lock_irqsave(&data->lock, flags); + + value = readq(reg_assert); + if (assert) + value |= mask; + else + value &= ~mask; + writeq(value, reg_assert); + + /* if the associated clock is gated, deasserting might otherwise hang forever */ + ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); + + spin_unlock_irqrestore(&data->lock, flags); + return ret; +} + +static int jh7100_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return jh7100_reset_update(rcdev, id, true); +} + +static int jh7100_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return jh7100_reset_update(rcdev, id, false); +} + +static int jh7100_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = jh7100_reset_assert(rcdev, id); + if (ret) + return ret; + + return jh7100_reset_deassert(rcdev, id); +} + +static int jh7100_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct jh7100_reset *data = jh7100_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); + void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); + u64 value = readq(reg_status); + + return !((value ^ jh7100_reset_asserted[offset]) & mask); +} + +static const struct reset_control_ops jh7100_reset_ops = { + .assert = jh7100_reset_assert, + .deassert = jh7100_reset_deassert, + .reset = jh7100_reset_reset, + .status = jh7100_reset_status, +}; + +static int __init jh7100_reset_probe(struct platform_device *pdev) +{ + struct jh7100_reset *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + data->rcdev.ops = &jh7100_reset_ops; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = JH7100_RSTN_END; + data->rcdev.dev = &pdev->dev; + data->rcdev.of_node = pdev->dev.of_node; + spin_lock_init(&data->lock); + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static const struct of_device_id jh7100_reset_dt_ids[] = { + { .compatible = "starfive,jh7100-reset" }, + { /* sentinel */ } +}; + +static struct platform_driver jh7100_reset_driver = { + .driver = { + .name = "jh7100-reset", + .of_match_table = jh7100_reset_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe); -- GitLab From 3021114b3d172cf80c074c81425741f9e26c6679 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 6 Jul 2021 20:19:06 +0200 Subject: [PATCH 755/965] dt-bindings: pinctrl: Add StarFive pinctrl definitions Add definitons for pins and GPIO input, output and output enable signals on the StarFive JH7100 SoC. Acked-by: Rob Herring Signed-off-by: Emil Renner Berthing --- .../dt-bindings/pinctrl/pinctrl-starfive.h | 275 ++++++++++++++++++ 1 file changed, 275 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive.h diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive.h b/include/dt-bindings/pinctrl/pinctrl-starfive.h new file mode 100644 index 0000000000000..de4f75c2c9e85 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Emil Renner Berthing + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_H__ + +#define PAD_GPIO_OFFSET 0 +#define PAD_FUNC_SHARE_OFFSET 64 +#define PAD_GPIO(x) (PAD_GPIO_OFFSET + (x)) +#define PAD_FUNC_SHARE(x) (PAD_FUNC_SHARE_OFFSET + (x)) + +/* + * GPIOMUX bits: + * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | + * | dout | doen | din | dout rev | doen rev | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * dout rev: output signal reverse bit + * doen rev: output enable signal reverse bit + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \ + (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \ + (((din) & 0xff) << 8) | \ + ((n) & 0x3f)) + +#define GPO_REVERSE 0x80000000 + +#define GPO_LOW 0 +#define GPO_HIGH 1 +#define GPO_ENABLE 0 +#define GPO_DISABLE 1 +#define GPO_CLK_GMAC_PAPHYREF 2 +#define GPO_JTAG_TDO 3 +#define GPO_JTAG_TDO_OEN 4 +#define GPO_DMIC_CLK_OUT 5 +#define GPO_DSP_JTDOEN_PAD 6 +#define GPO_DSP_JTDO_PAD 7 +#define GPO_I2C0_PAD_SCK_OE 8 +#define GPO_I2C0_PAD_SCK_OEN (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C0_PAD_SDA_OE 9 +#define GPO_I2C0_PAD_SDA_OEN (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C1_PAD_SCK_OE 10 +#define GPO_I2C1_PAD_SCK_OEN (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C1_PAD_SDA_OE 11 +#define GPO_I2C1_PAD_SDA_OEN (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C2_PAD_SCK_OE 12 +#define GPO_I2C2_PAD_SCK_OEN (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C2_PAD_SDA_OE 13 +#define GPO_I2C2_PAD_SDA_OEN (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C3_PAD_SCK_OE 14 +#define GPO_I2C3_PAD_SCK_OEN (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C3_PAD_SDA_OE 15 +#define GPO_I2C3_PAD_SDA_OEN (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2SRX_BCLK_OUT 16 +#define GPO_I2SRX_BCLK_OUT_OEN 17 +#define GPO_I2SRX_LRCK_OUT 18 +#define GPO_I2SRX_LRCK_OUT_OEN 19 +#define GPO_I2SRX_MCLK_OUT 20 +#define GPO_I2STX_BCLK_OUT 21 +#define GPO_I2STX_BCLK_OUT_OEN 22 +#define GPO_I2STX_LRCK_OUT 23 +#define GPO_I2STX_LRCK_OUT_OEN 24 +#define GPO_I2STX_MCLK_OUT 25 +#define GPO_I2STX_SDOUT0 26 +#define GPO_I2STX_SDOUT1 27 +#define GPO_LCD_PAD_CSM_N 28 +#define GPO_PWM_PAD_OE_N_BIT0 29 +#define GPO_PWM_PAD_OE_N_BIT1 30 +#define GPO_PWM_PAD_OE_N_BIT2 31 +#define GPO_PWM_PAD_OE_N_BIT3 32 +#define GPO_PWM_PAD_OE_N_BIT4 33 +#define GPO_PWM_PAD_OE_N_BIT5 34 +#define GPO_PWM_PAD_OE_N_BIT6 35 +#define GPO_PWM_PAD_OE_N_BIT7 36 +#define GPO_PWM_PAD_OUT_BIT0 37 +#define GPO_PWM_PAD_OUT_BIT1 38 +#define GPO_PWM_PAD_OUT_BIT2 39 +#define GPO_PWM_PAD_OUT_BIT3 40 +#define GPO_PWM_PAD_OUT_BIT4 41 +#define GPO_PWM_PAD_OUT_BIT5 42 +#define GPO_PWM_PAD_OUT_BIT6 43 +#define GPO_PWM_PAD_OUT_BIT7 44 +#define GPO_PWMDAC_LEFT_OUT 45 +#define GPO_PWMDAC_RIGHT_OUT 46 +#define GPO_QSPI_CSN1_OUT 47 +#define GPO_QSPI_CSN2_OUT 48 +#define GPO_QSPI_CSN3_OUT 49 +#define GPO_REGISTER23_SCFG_CMSENSOR_RST0 50 +#define GPO_REGISTER23_SCFG_CMSENSOR_RST1 51 +#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN 52 +#define GPO_SDIO0_PAD_CARD_POWER_EN 53 +#define GPO_SDIO0_PAD_CCLK_OUT 54 +#define GPO_SDIO0_PAD_CCMD_OE 55 +#define GPO_SDIO0_PAD_CCMD_OEN (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE) +#define GPO_SDIO0_PAD_CCMD_OUT 56 +#define GPO_SDIO0_PAD_CDATA_OE_BIT0 57 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT0 (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT1 58 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT1 (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT2 59 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT2 (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT3 60 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT3 (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT4 61 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT4 (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT5 62 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT5 (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT6 63 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT6 (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT7 64 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT7 (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OUT_BIT0 65 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT1 66 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT2 67 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT3 68 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT4 69 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT5 70 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT6 71 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT7 72 +#define GPO_SDIO0_PAD_RST_N 73 +#define GPO_SDIO1_PAD_CARD_POWER_EN 74 +#define GPO_SDIO1_PAD_CCLK_OUT 75 +#define GPO_SDIO1_PAD_CCMD_OE 76 +#define GPO_SDIO1_PAD_CCMD_OEN (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE) +#define GPO_SDIO1_PAD_CCMD_OUT 77 +#define GPO_SDIO1_PAD_CDATA_OE_BIT0 78 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT0 (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT1 79 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT1 (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT2 80 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT2 (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT3 81 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT3 (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT4 82 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT4 (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT5 83 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT5 (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT6 84 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT6 (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT7 85 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT7 (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OUT_BIT0 86 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT1 87 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT2 88 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT3 89 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT4 90 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT5 91 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT6 92 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT7 93 +#define GPO_SDIO1_PAD_RST_N 94 +#define GPO_SPDIF_TX_SDOUT 95 +#define GPO_SPDIF_TX_SDOUT_OEN 96 +#define GPO_SPI0_PAD_OE_N 97 +#define GPO_SPI0_PAD_SCK_OUT 98 +#define GPO_SPI0_PAD_SS_0_N 99 +#define GPO_SPI0_PAD_SS_1_N 100 +#define GPO_SPI0_PAD_TXD 101 +#define GPO_SPI1_PAD_OE_N 102 +#define GPO_SPI1_PAD_SCK_OUT 103 +#define GPO_SPI1_PAD_SS_0_N 104 +#define GPO_SPI1_PAD_SS_1_N 105 +#define GPO_SPI1_PAD_TXD 106 +#define GPO_SPI2_PAD_OE_N 107 +#define GPO_SPI2_PAD_SCK_OUT 108 +#define GPO_SPI2_PAD_SS_0_N 109 +#define GPO_SPI2_PAD_SS_1_N 110 +#define GPO_SPI2_PAD_TXD 111 +#define GPO_SPI2AHB_PAD_OE_N_BIT0 112 +#define GPO_SPI2AHB_PAD_OE_N_BIT1 113 +#define GPO_SPI2AHB_PAD_OE_N_BIT2 114 +#define GPO_SPI2AHB_PAD_OE_N_BIT3 115 +#define GPO_SPI2AHB_PAD_TXD_BIT0 116 +#define GPO_SPI2AHB_PAD_TXD_BIT1 117 +#define GPO_SPI2AHB_PAD_TXD_BIT2 118 +#define GPO_SPI2AHB_PAD_TXD_BIT3 119 +#define GPO_SPI3_PAD_OE_N 120 +#define GPO_SPI3_PAD_SCK_OUT 121 +#define GPO_SPI3_PAD_SS_0_N 122 +#define GPO_SPI3_PAD_SS_1_N 123 +#define GPO_SPI3_PAD_TXD 124 +#define GPO_UART0_PAD_DTRN 125 +#define GPO_UART0_PAD_RTSN 126 +#define GPO_UART0_PAD_SOUT 127 +#define GPO_UART1_PAD_SOUT 128 +#define GPO_UART2_PAD_DTR_N 129 +#define GPO_UART2_PAD_RTS_N 130 +#define GPO_UART2_PAD_SOUT 131 +#define GPO_UART3_PAD_SOUT 132 +#define GPO_USB_DRV_BUS 133 + +#define GPI_CPU_JTAG_TCK 0 +#define GPI_CPU_JTAG_TDI 1 +#define GPI_CPU_JTAG_TMS 2 +#define GPI_CPU_JTAG_TRST 3 +#define GPI_DMIC_SDIN_BIT0 4 +#define GPI_DMIC_SDIN_BIT1 5 +#define GPI_DSP_JTCK_PAD 6 +#define GPI_DSP_JTDI_PAD 7 +#define GPI_DSP_JTMS_PAD 8 +#define GPI_DSP_TRST_PAD 9 +#define GPI_I2C0_PAD_SCK_IN 10 +#define GPI_I2C0_PAD_SDA_IN 11 +#define GPI_I2C1_PAD_SCK_IN 12 +#define GPI_I2C1_PAD_SDA_IN 13 +#define GPI_I2C2_PAD_SCK_IN 14 +#define GPI_I2C2_PAD_SDA_IN 15 +#define GPI_I2C3_PAD_SCK_IN 16 +#define GPI_I2C3_PAD_SDA_IN 17 +#define GPI_I2SRX_BCLK_IN 18 +#define GPI_I2SRX_LRCK_IN 19 +#define GPI_I2SRX_SDIN_BIT0 20 +#define GPI_I2SRX_SDIN_BIT1 21 +#define GPI_I2SRX_SDIN_BIT2 22 +#define GPI_I2STX_BCLK_IN 23 +#define GPI_I2STX_LRCK_IN 24 +#define GPI_SDIO0_PAD_CARD_DETECT_N 25 +#define GPI_SDIO0_PAD_CARD_WRITE_PRT 26 +#define GPI_SDIO0_PAD_CCMD_IN 27 +#define GPI_SDIO0_PAD_CDATA_IN_BIT0 28 +#define GPI_SDIO0_PAD_CDATA_IN_BIT1 29 +#define GPI_SDIO0_PAD_CDATA_IN_BIT2 30 +#define GPI_SDIO0_PAD_CDATA_IN_BIT3 31 +#define GPI_SDIO0_PAD_CDATA_IN_BIT4 32 +#define GPI_SDIO0_PAD_CDATA_IN_BIT5 33 +#define GPI_SDIO0_PAD_CDATA_IN_BIT6 34 +#define GPI_SDIO0_PAD_CDATA_IN_BIT7 35 +#define GPI_SDIO1_PAD_CARD_DETECT_N 36 +#define GPI_SDIO1_PAD_CARD_WRITE_PRT 37 +#define GPI_SDIO1_PAD_CCMD_IN 38 +#define GPI_SDIO1_PAD_CDATA_IN_BIT0 39 +#define GPI_SDIO1_PAD_CDATA_IN_BIT1 40 +#define GPI_SDIO1_PAD_CDATA_IN_BIT2 41 +#define GPI_SDIO1_PAD_CDATA_IN_BIT3 42 +#define GPI_SDIO1_PAD_CDATA_IN_BIT4 43 +#define GPI_SDIO1_PAD_CDATA_IN_BIT5 44 +#define GPI_SDIO1_PAD_CDATA_IN_BIT6 45 +#define GPI_SDIO1_PAD_CDATA_IN_BIT7 46 +#define GPI_SPDIF_RX_SDIN 47 +#define GPI_SPI0_PAD_RXD 48 +#define GPI_SPI0_PAD_SS_IN_N 49 +#define GPI_SPI1_PAD_RXD 50 +#define GPI_SPI1_PAD_SS_IN_N 51 +#define GPI_SPI2_PAD_RXD 52 +#define GPI_SPI2_PAD_SS_IN_N 53 +#define GPI_SPI2AHB_PAD_RXD_BIT0 54 +#define GPI_SPI2AHB_PAD_RXD_BIT1 55 +#define GPI_SPI2AHB_PAD_RXD_BIT2 56 +#define GPI_SPI2AHB_PAD_RXD_BIT3 57 +#define GPI_SPI2AHB_PAD_SS_N 58 +#define GPI_SPI2AHB_SLV_SCLKIN 59 +#define GPI_SPI3_PAD_RXD 60 +#define GPI_SPI3_PAD_SS_IN_N 61 +#define GPI_UART0_PAD_CTSN 62 +#define GPI_UART0_PAD_DCDN 63 +#define GPI_UART0_PAD_DSRN 64 +#define GPI_UART0_PAD_RIN 65 +#define GPI_UART0_PAD_SIN 66 +#define GPI_UART1_PAD_SIN 67 +#define GPI_UART2_PAD_CTS_N 68 +#define GPI_UART2_PAD_DCD_N 69 +#define GPI_UART2_PAD_DSR_N 70 +#define GPI_UART2_PAD_RI_N 71 +#define GPI_UART2_PAD_SIN 72 +#define GPI_UART3_PAD_SIN 73 +#define GPI_USB_OVER_CURRENT 74 + +#define GPI_NONE 0xff + +#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */ -- GitLab From 7431b391df95f5b8d08fd0f9fa1a75cc038ee290 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 27 Jul 2021 14:34:33 +0200 Subject: [PATCH 756/965] dt-bindings: pinctrl: Add StarFive JH7100 bindings Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Emil Renner Berthing --- .../pinctrl/starfive,jh7100-pinctrl.yaml | 307 ++++++++++++++++++ 1 file changed, 307 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml new file mode 100644 index 0000000000000..92963604422f4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Pin Controller Device Tree Bindings + +description: | + Bindings for the JH7100 RISC-V SoC from StarFive Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63] + and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have + configurable bias, drive strength, schmitt trigger etc. The SoC has an + interesting 2-layered approach to pin muxing best illustrated by the diagram + below. + + Signal group 0, 1, ... or 6 + ___|___ + | | + LCD output -----------------| | + CMOS Camera interface ------| |--- PAD_GPIO[0] + Ethernet PHY interface -----| MUX |--- PAD_GPIO[1] + ... | | ... + | |--- PAD_GPIO[63] + -------- GPIO0 ------------| | + | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0] + | | | | | |--- PAD_FUNC_SHARE[1] + | | | | ... | | ... + | | | | | |--- PAD_FUNC_SHARE[141] + | | -----|---|-- GPIO63 ---| | + | | | | | | ------- + UART0 UART1 -- + + + The big MUX in the diagram only has 7 different ways of mapping peripherals + on the left to pins on the right. StarFive calls the 7 configurations "signal + groups". + However some peripherals have their I/O go through the 64 "GPIOs". The + diagram only shows UART0 and UART1, but this also includes a number of other + UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64 + GPIOs such that any GPIO can be set up to be controlled by any of the + peripherals. + Note that signal group 0 doesn't map any of the GPIOs to pins, and only + signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63]. + +maintainers: + - Emil Renner Berthing + - Drew Fustini + +properties: + compatible: + const: starfive,jh7100-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: gpio + - const: padctl + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + starfive,signal-group: + description: | + Select one of the 7 signal groups. If this property is not set it + defaults to the configuration already chosen by the earlier boot stages. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6] + +required: + - compatible + - reg + - reg-names + - clocks + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]+$': + type: object + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: | + The list of pin identifiers that properties in the node apply to. + This should be set using either the PAD_GPIO or PAD_FUNC_SHARE + macros. + Either this or "pinmux" has to be specified, but not both. + $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins" + + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + Either this or "pins" has to be specified, but not both. + $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux" + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 7 + + starfive,strong-pull-up: + description: enable strong pull-up. + type: boolean + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&clkgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + starfive,signal-group = <6>; + + gmac_pins_default: gmac-0 { + gtxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = , + , + , + , + , + , + , + , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + i2c0_pins_default: i2c0-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart3_pins_default: uart3-0 { + rx-pins { + pinmux = ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + tx-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + }; + + gmac { + pinctrl-0 = <&gmac_pins_default>; + pinctrl-names = "default"; + }; + + i2c0 { + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-names = "default"; + }; + + uart3 { + pinctrl-0 = <&uart3_pins_default>; + pinctrl-names = "default"; + }; + }; + +... -- GitLab From ec648f6b7686b716424e8e73eebb4c11ae199187 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 6 Jul 2021 20:19:06 +0200 Subject: [PATCH 757/965] pinctrl: starfive: Add pinctrl driver for StarFive SoCs Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which is said to feature only minor changes to these pinctrl/GPIO parts. For each "GPIO" there are two registers for configuring the output and output enable signals which may come from other peripherals. Among these are two special signals that are constant 0 and constant 1 respectively. Controlling the GPIOs from software is done by choosing one of these signals. In other words the same registers are used for both pin muxing and controlling the GPIOs, which makes it easier to combine the pinctrl and GPIO driver in one. I wrote the pinconf and pinmux parts, but the GPIO part of the code is based on the GPIO driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij Co-developed-by: Huan Feng Signed-off-by: Huan Feng Co-developed-by: Drew Fustini Signed-off-by: Drew Fustini Signed-off-by: Emil Renner Berthing --- MAINTAINERS | 8 + drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-starfive.c | 1354 ++++++++++++++++++++++++++++ 4 files changed, 1380 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index 1152f5d946906..30d6842969e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18137,6 +18137,14 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml F: drivers/clk/starfive/clk-starfive-jh7100.c F: include/dt-bindings/clock/starfive-jh7100.h +STARFIVE JH7100 PINCTRL DRIVER +M: Emil Renner Berthing +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml +F: drivers/pinctrl/pinctrl-starfive.c +F: include/dt-bindings/pinctrl/pinctrl-starfive.h + STARFIVE JH7100 RESET CONTROLLER DRIVER M: Emil Renner Berthing S: Maintained diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6a961d5f8726c..0d5b61e4c21e5 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -281,6 +281,23 @@ config PINCTRL_ST select PINCONF select GPIOLIB_IRQCHIP +config PINCTRL_STARFIVE + tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC" + depends on SOC_STARFIVE || COMPILE_TEST + depends on OF + default SOC_STARFIVE + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + help + Say yes here to support pin control on the StarFive JH7100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STMFX tristate "STMicroelectronics STMFX GPIO expander pinctrl driver" depends on I2C diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 5e63de2ffcf41..f5bdd6b209a6f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/pinctrl-starfive.c new file mode 100644 index 0000000000000..0b912152a405a --- /dev/null +++ b/drivers/pinctrl/pinctrl-starfive.c @@ -0,0 +1,1354 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7100 SoC + * + * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinmux.h" +#include "pinconf.h" + +#define DRIVER_NAME "pinctrl-starfive" + +/* + * Refer to Section 12. GPIO Registers in the JH7100 data sheet: + * https://github.com/starfive-tech/JH7100_Docs + */ +#define NR_GPIOS 64 + +/* + * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts + * are enabled. If set to 0 the GPIO interrupts are disabled. + */ +#define GPIOEN 0x000 + +/* + * The following 32-bit registers come in pairs, but only the offset of the + * first register is defined. The first controls (interrupts for) GPIO 0-31 and + * the second GPIO 32-63. + */ + +/* + * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the + * interrupt is level-triggered. + */ +#define GPIOIS 0x010 + +/* + * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on + * both positive and negative edges. If set to 0 the interrupt is triggered by a + * single edge. + */ +#define GPIOIBE 0x018 + +/* + * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a + * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the + * interrupt is triggered on a falling edge (edge-triggered) or low level + * (level-triggered). + */ +#define GPIOIEV 0x020 + +/* + * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0 + * the interrupt is disabled (masked). Note that the current documentation is + * wrong and says the exct opposite of this. + */ +#define GPIOIE 0x028 + +/* + * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered + * interrupt. + */ +#define GPIOIC 0x030 + +/* + * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected. + */ +#define GPIORIS 0x038 + +/* + * Interrupt Status after Masking. A 1 means the configured edge or level was + * detected and not masked. + */ +#define GPIOMIS 0x040 + +/* + * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is + * a digital 1 and if 0 the pin is a digital 0. + */ +#define GPIODIN 0x048 + +/* + * From the data sheet section 12.2, there are 64 32-bit output data registers + * and 64 output enable registers. Output data and output enable registers for + * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is + * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c. The stride + * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n + * and GPOn_DOEN_CFG is 0x54 + 8n. + */ +#define GPON_DOUT_CFG 0x050 +#define GPON_DOEN_CFG 0x054 + +/* + * From Section 12.3, there are 75 input signal configuration registers which + * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with + * GPI_USB_OVER_CURRENT_CFG 0x378 + */ +#define GPI_CFG_OFFSET 0x250 + +/* + * Pad Control Bits. There are 16 pad control bits for each pin located in 103 + * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by + * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16 + * bit of each register. + */ +#define PAD_SLEW_RATE_MASK GENMASK(11, 9) +#define PAD_SLEW_RATE_POS 9 +#define PAD_BIAS_STRONG_PULL_UP BIT(8) +#define PAD_INPUT_ENABLE BIT(7) +#define PAD_INPUT_SCHMITT_ENABLE BIT(6) +#define PAD_BIAS_DISABLE BIT(5) +#define PAD_BIAS_PULL_DOWN BIT(4) +#define PAD_BIAS_MASK \ + (PAD_BIAS_STRONG_PULL_UP | \ + PAD_BIAS_DISABLE | \ + PAD_BIAS_PULL_DOWN) +#define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0) +#define PAD_DRIVE_STRENGTH_POS 0 + +/* + * From Section 11, the IO_PADSHARE_SEL register can be programmed to select + * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and + * PAD_GPIO pads. This is a global setting. + */ +#define IO_PADSHARE_SEL 0x1a0 + +/* + * This just needs to be some number such that when + * sfp->gpio.pin_base = PAD_INVALID_GPIO then + * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number. + * That is it should underflow and return something >= NR_GPIOS. + */ +#define PAD_INVALID_GPIO 0x10000 + +/* + * The packed pinmux values from the device tree look like this: + * + * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | + * | dout | doen | din | dout rev | doen rev | gpio nr | + * + * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this: + * + * | 31 | 30 - 8 | 7 - 0 | + * | dout/doen rev | unused | dout/doen | + */ +static unsigned int starfive_pinmux_to_gpio(u32 v) +{ + return v & (NR_GPIOS - 1); +} + +static u32 starfive_pinmux_to_dout(u32 v) +{ + return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0)); +} + +static u32 starfive_pinmux_to_doen(u32 v) +{ + return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0)); +} + +static u32 starfive_pinmux_to_din(u32 v) +{ + return (v >> 8) & GENMASK(7, 0); +} + +/* + * The maximum GPIO output current depends on the chosen drive strength: + * + * DS: 0 1 2 3 4 5 6 7 + * mA: 14.2 21.2 28.2 35.2 42.2 49.1 56.0 62.8 + * + * After rounding that is 7*DS + 14 mA + */ +static u32 starfive_drive_strength_to_max_mA(u16 ds) +{ + return 7 * ds + 14; +} + +static u16 starfive_drive_strength_from_max_mA(u32 i) +{ + return (clamp(i, 14U, 63U) - 14) / 7; +} + +struct starfive_pinctrl { + struct gpio_chip gc; + struct pinctrl_gpio_range gpios; + raw_spinlock_t lock; + void __iomem *base; + void __iomem *padctl; + struct pinctrl_dev *pctl; +}; + +static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp, + unsigned int pin) +{ + return pin - sfp->gpios.pin_base; +} + +static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp, + unsigned int gpio) +{ + return sfp->gpios.pin_base + gpio; +} + +static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return container_of(gc, struct starfive_pinctrl, gc); +} + +static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + + return container_of(gc, struct starfive_pinctrl, gc); +} + +static const struct pinctrl_pin_desc starfive_pins[] = { + PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"), + PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"), + PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"), + PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"), + PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"), + PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"), + PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"), + PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"), + PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"), + PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"), + PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"), + PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"), + PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"), + PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"), + PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"), + PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"), + PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"), + PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"), + PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"), + PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"), + PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"), + PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"), + PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"), + PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"), + PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"), + PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"), + PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"), + PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"), + PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"), + PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"), + PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"), + PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"), + PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"), + PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"), + PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"), + PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"), + PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"), + PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"), + PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"), + PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"), + PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"), + PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"), + PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"), + PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"), + PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"), + PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"), + PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"), + PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"), + PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"), + PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"), + PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"), + PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"), + PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"), + PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"), + PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"), + PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"), + PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"), + PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"), + PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"), + PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"), + PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"), + PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"), + PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"), + PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"), + PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"), + PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"), + PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"), + PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"), + PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"), + PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"), + PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"), + PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"), + PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"), + PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"), + PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"), + PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"), + PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"), + PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"), + PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"), + PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"), + PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"), + PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"), + PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"), + PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"), + PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"), + PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"), + PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"), + PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"), + PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"), + PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"), + PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"), + PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"), + PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"), + PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"), + PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"), + PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"), + PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"), + PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"), + PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"), + PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"), + PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"), + PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"), + PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"), + PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"), + PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"), + PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"), + PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"), + PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"), + PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"), + PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"), + PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"), + PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"), + PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"), + PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"), + PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"), + PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"), + PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"), + PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"), + PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"), + PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"), + PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"), + PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"), + PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"), + PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"), + PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"), + PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"), + PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"), + PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"), + PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"), + PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"), + PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"), + PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"), + PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"), + PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"), + PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"), + PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"), + PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"), + PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"), + PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"), + PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"), + PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"), + PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"), + PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"), + PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"), + PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"), + PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"), + PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"), + PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"), + PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"), + PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"), + PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"), + PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"), + PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"), + PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"), + PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"), + PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"), + PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"), + PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"), + PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"), + PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"), + PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"), + PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"), + PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"), + PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"), + PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"), + PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"), + PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"), + PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"), + PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"), + PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"), + PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"), + PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"), + PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"), + PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"), + PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"), + PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"), + PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"), + PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"), + PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"), + PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"), + PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"), + PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"), + PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"), + PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"), + PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"), + PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"), + PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"), + PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"), + PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"), + PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"), + PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"), + PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"), + PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"), + PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"), + PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"), + PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"), + PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"), + PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"), + PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"), + PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"), + PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"), + PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"), + PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"), + PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"), + PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"), + PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"), +}; + +#ifdef CONFIG_DEBUG_FS +static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int pin) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + unsigned int gpio = starfive_pin_to_gpio(sfp, pin); + void __iomem *reg; + u32 dout, doen; + + if (gpio >= NR_GPIOS) + return; + + reg = sfp->base + GPON_DOUT_CFG + 8 * gpio; + dout = readl_relaxed(reg + 0x000); + doen = readl_relaxed(reg + 0x004); + + seq_printf(s, "dout=%lu%s doen=%lu%s", + dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "", + doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : ""); +} +#else +#define starfive_pin_dbg_show NULL +#endif + +static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = sfp->gc.parent; + struct device_node *child; + struct pinctrl_map *map; + const char **pgnames; + const char *grpname; + u32 *pinmux; + int ngroups; + int *pins; + int nmaps; + int ret; + + nmaps = 0; + ngroups = 0; + for_each_child_of_node(np, child) { + int npinmux = of_property_count_u32_elems(child, "pinmux"); + int npins = of_property_count_u32_elems(child, "pins"); + + if (npinmux > 0 && npins > 0) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n", + np, child); + of_node_put(child); + return -EINVAL; + } + if (npinmux == 0 && npins == 0) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n", + np, child); + of_node_put(child); + return -EINVAL; + } + + if (npinmux > 0) + nmaps += 2; + else + nmaps += 1; + ngroups += 1; + } + + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) + return -ENOMEM; + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + ngroups = 0; + for_each_child_of_node(np, child) { + int npins; + int i; + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); + if (!grpname) { + ret = -ENOMEM; + goto put_child; + } + + pgnames[ngroups++] = grpname; + + if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) { + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto put_child; + } + + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); + if (!pinmux) { + ret = -ENOMEM; + goto put_child; + } + + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); + if (ret) + goto put_child; + + for (i = 0; i < npins; i++) { + unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]); + + pins[i] = starfive_gpio_to_pin(sfp, gpio); + } + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) { + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto put_child; + } + + pinmux = NULL; + + for (i = 0; i < npins; i++) { + u32 v; + + ret = of_property_read_u32_index(child, "pins", i, &v); + if (ret) + goto put_child; + pins[i] = v; + } + } else { + ret = -EINVAL; + goto put_child; + } + + ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux); + if (ret < 0) { + dev_err(dev, "error adding group %s: %d\n", grpname, ret); + goto put_child; + } + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "error parsing pin config of group %s: %d\n", + grpname, ret); + goto put_child; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto free_map; + } + + *maps = map; + *num_maps = nmaps; + return 0; + +put_child: + of_node_put(child); +free_map: + pinctrl_utils_free_map(pctldev, map, nmaps); + return ret; +} + +static const struct pinctrl_ops starfive_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = starfive_pin_dbg_show, + .dt_node_to_map = starfive_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int starfive_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = sfp->gc.parent; + const struct group_desc *group; + const u32 *pinmux; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmux = group->data; + for (i = 0; i < group->num_pins; i++) { + u32 v = pinmux[i]; + unsigned int gpio = starfive_pinmux_to_gpio(v); + u32 dout = starfive_pinmux_to_dout(v); + u32 doen = starfive_pinmux_to_doen(v); + u32 din = starfive_pinmux_to_din(v); + void __iomem *reg_dout; + void __iomem *reg_doen; + void __iomem *reg_din; + unsigned long flags; + + dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n", + gpio, dout, doen, din); + + reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; + reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; + if (din != GPI_NONE) + reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din; + else + reg_din = NULL; + + raw_spin_lock_irqsave(&sfp->lock, flags); + writel_relaxed(dout, reg_dout); + writel_relaxed(doen, reg_doen); + if (reg_din) + writel_relaxed(gpio + 2, reg_din); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + } + + return 0; +} + +static const struct pinmux_ops starfive_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = starfive_set_mux, + .strict = true, +}; + +static u16 starfive_padctl_get(struct starfive_pinctrl *sfp, + unsigned int pin) +{ + void __iomem *reg = sfp->padctl + 4 * (pin / 2); + int shift = 16 * (pin % 2); + + return readl_relaxed(reg) >> shift; +} + +static void starfive_padctl_rmw(struct starfive_pinctrl *sfp, + unsigned int pin, + u16 _mask, u16 _value) +{ + void __iomem *reg = sfp->padctl + 4 * (pin / 2); + int shift = 16 * (pin % 2); + u32 mask = (u32)_mask << shift; + u32 value = (u32)_value << shift; + unsigned long flags; + + dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value); + + raw_spin_lock_irqsave(&sfp->lock, flags); + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1) + +static const struct pinconf_generic_params starfive_pinconf_custom_params[] = { + { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 }, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item starfive_pinconf_custom_conf_items[] = { + PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false), +}; + +static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) == + ARRAY_SIZE(starfive_pinconf_custom_params)); +#else +#define starfive_pinconf_custom_conf_items NULL +#endif + +static int starfive_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + u16 value = starfive_padctl_get(sfp, pin); + bool enabled; + u32 arg; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = value & PAD_BIAS_DISABLE; + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = value & PAD_BIAS_PULL_DOWN; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + enabled = !(value & PAD_BIAS_MASK); + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = value & PAD_DRIVE_STRENGTH_MASK; + arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK); + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = value & PAD_INPUT_ENABLE; + arg = enabled; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = value & PAD_INPUT_SCHMITT_ENABLE; + arg = enabled; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = value & PAD_SLEW_RATE_MASK; + arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS; + break; + case PIN_CONFIG_STARFIVE_STRONG_PULL_UP: + enabled = value & PAD_BIAS_STRONG_PULL_UP; + arg = enabled; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, unsigned long *config) +{ + const struct group_desc *group; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + return starfive_pinconf_get(pctldev, group->pins[0], config); +} + +static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + u16 mask, value; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= PAD_BIAS_MASK; + value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= PAD_BIAS_MASK; + value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= PAD_BIAS_MASK; + value = value & ~PAD_BIAS_MASK; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= PAD_DRIVE_STRENGTH_MASK; + value = (value & ~PAD_DRIVE_STRENGTH_MASK) | + starfive_drive_strength_from_max_mA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= PAD_INPUT_ENABLE; + if (arg) + value |= PAD_INPUT_ENABLE; + else + value &= ~PAD_INPUT_ENABLE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= PAD_INPUT_SCHMITT_ENABLE; + if (arg) + value |= PAD_INPUT_SCHMITT_ENABLE; + else + value &= ~PAD_INPUT_SCHMITT_ENABLE; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= PAD_SLEW_RATE_MASK; + value = (value & ~PAD_SLEW_RATE_MASK) | + ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK); + break; + case PIN_CONFIG_STARFIVE_STRONG_PULL_UP: + if (arg) { + mask |= PAD_BIAS_MASK; + value = (value & ~PAD_BIAS_MASK) | + PAD_BIAS_STRONG_PULL_UP; + } else { + mask |= PAD_BIAS_STRONG_PULL_UP; + value = value & ~PAD_BIAS_STRONG_PULL_UP; + } + break; + default: + return -ENOTSUPP; + } + } + + for (i = 0; i < group->num_pins; i++) + starfive_padctl_rmw(sfp, group->pins[i], mask, value); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + u16 value = starfive_padctl_get(sfp, pin); + + seq_printf(s, " (0x%03x)", value); +} +#else +#define starfive_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops starfive_pinconf_ops = { + .pin_config_get = starfive_pinconf_get, + .pin_config_group_get = starfive_pinconf_group_get, + .pin_config_group_set = starfive_pinconf_group_set, + .pin_config_dbg_show = starfive_pinconf_dbg_show, + .is_generic = true, +}; + +static struct pinctrl_desc starfive_desc = { + .name = DRIVER_NAME, + .pins = starfive_pins, + .npins = ARRAY_SIZE(starfive_pins), + .pctlops = &starfive_pinctrl_ops, + .pmxops = &starfive_pinmux_ops, + .confops = &starfive_pinconf_ops, + .owner = THIS_MODULE, + .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params), + .custom_params = starfive_pinconf_custom_params, + .custom_conf_items = starfive_pinconf_custom_conf_items, +}; + +static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio) +{ + return pinctrl_gpio_request(gc->base + gpio); +} + +static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio) +{ + pinctrl_gpio_free(gc->base + gpio); +} + +static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; + + if (readl_relaxed(doen) == GPO_ENABLE) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +} + +static int starfive_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; + unsigned long flags; + + /* enable input and schmitt trigger */ + starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), + PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE, + PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE); + + raw_spin_lock_irqsave(&sfp->lock, flags); + writel_relaxed(GPO_DISABLE, doen); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + return 0; +} + +static int starfive_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; + void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + writel_relaxed(value, dout); + writel_relaxed(GPO_ENABLE, doen); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + + /* disable input, schmitt trigger and bias */ + starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), + PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE, + PAD_BIAS_DISABLE); + + return 0; +} + +static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32); + + return !!(readl_relaxed(din) & BIT(gpio % 32)); +} + +static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio, + int value) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + writel_relaxed(value, dout); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, + unsigned long config) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + u32 arg = pinconf_to_config_argument(config); + u16 value; + u16 mask; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + mask = PAD_BIAS_MASK; + value = PAD_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask = PAD_BIAS_MASK; + value = PAD_BIAS_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask = PAD_BIAS_MASK; + value = 0; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return 0; + case PIN_CONFIG_INPUT_ENABLE: + mask = PAD_INPUT_ENABLE; + value = arg ? PAD_INPUT_ENABLE : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask = PAD_INPUT_SCHMITT_ENABLE; + value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0; + break; + default: + return -ENOTSUPP; + }; + + starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); + return 0; +} + +static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + + sfp->gpios.name = sfp->gc.label; + sfp->gpios.base = sfp->gc.base; + /* + * sfp->gpios.pin_base depends on the chosen signal group + * and is set in starfive_probe() + */ + sfp->gpios.npins = NR_GPIOS; + sfp->gpios.gc = &sfp->gc; + pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); + return 0; +} + +static void starfive_irq_ack(struct irq_data *d) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + writel_relaxed(mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void starfive_irq_mask(struct irq_data *d) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void starfive_irq_mask_ack(struct irq_data *d) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); + void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + writel_relaxed(mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void starfive_irq_unmask(struct irq_data *d) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) | mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *base = sfp->base + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + u32 irq_type, edge_both, polarity; + unsigned long flags; + + switch (trigger) { + case IRQ_TYPE_EDGE_RISING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = mask; /* 1: rising edge */ + break; + case IRQ_TYPE_EDGE_FALLING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = 0; /* 0: falling edge */ + break; + case IRQ_TYPE_EDGE_BOTH: + irq_type = mask; /* 1: edge triggered */ + edge_both = mask; /* 1: both edges */ + polarity = 0; /* 0: ignored */ + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = mask; /* 1: high level */ + break; + case IRQ_TYPE_LEVEL_LOW: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = 0; /* 0: low level */ + break; + default: + return -EINVAL; + } + + if (trigger & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + irq_type |= readl_relaxed(base + GPIOIS) & ~mask; + writel_relaxed(irq_type, base + GPIOIS); + edge_both |= readl_relaxed(base + GPIOIBE) & ~mask; + writel_relaxed(edge_both, base + GPIOIBE); + polarity |= readl_relaxed(base + GPIOIEV) & ~mask; + writel_relaxed(polarity, base + GPIOIEV); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + return 0; +} + +static struct irq_chip starfive_irq_chip = { + .irq_ack = starfive_irq_ack, + .irq_mask = starfive_irq_mask, + .irq_mask_ack = starfive_irq_mask_ack, + .irq_unmask = starfive_irq_unmask, + .irq_set_type = starfive_irq_set_type, + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + +static void starfive_gpio_irq_handler(struct irq_desc *desc) +{ + struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long mis; + unsigned int pin; + + chained_irq_enter(chip, desc); + + mis = readl_relaxed(sfp->base + GPIOMIS + 0); + for_each_set_bit(pin, &mis, 32) + generic_handle_domain_irq(sfp->gc.irq.domain, pin); + + mis = readl_relaxed(sfp->base + GPIOMIS + 4); + for_each_set_bit(pin, &mis, 32) + generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); + + chained_irq_exit(chip, desc); +} + +static int starfive_gpio_init_hw(struct gpio_chip *gc) +{ + struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); + + /* mask all GPIO interrupts */ + writel(0, sfp->base + GPIOIE + 0); + writel(0, sfp->base + GPIOIE + 4); + /* clear edge interrupt flags */ + writel(~0U, sfp->base + GPIOIC + 0); + writel(~0U, sfp->base + GPIOIC + 4); + /* enable GPIO interrupts */ + writel(1, sfp->base + GPIOEN); + return 0; +} + +static void starfive_disable_clock(void *data) +{ + clk_disable_unprepare(data); +} + +static int starfive_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct starfive_pinctrl *sfp; + struct reset_control *rst; + struct clk *clk; + u32 value; + int ret; + + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + if (!sfp) + return -ENOMEM; + + sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); + if (IS_ERR(sfp->base)) + return PTR_ERR(sfp->base); + + sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl"); + if (IS_ERR(sfp->padctl)) + return PTR_ERR(sfp->padctl); + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n"); + + ret = clk_prepare_enable(clk); + if (ret) + return dev_err_probe(dev, ret, "could not enable clock\n"); + + ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk); + if (ret) + return ret; + + /* + * We don't want to assert reset and risk undoing pin muxing for the + * early boot serial console, but let's make sure the reset line is + * deasserted in case someone runs a really minimal bootloader. + */ + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "could not deassert reset\n"); + + platform_set_drvdata(pdev, sfp); + sfp->gc.parent = dev; + raw_spin_lock_init(&sfp->lock); + + ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl); + if (ret) + return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); + + if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) { + if (value > 6) + return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); + writel(value, sfp->padctl + IO_PADSHARE_SEL); + } + + value = readl(sfp->padctl + IO_PADSHARE_SEL); + switch (value) { + case 0: + sfp->gpios.pin_base = PAD_INVALID_GPIO; + goto out_pinctrl_enable; + case 1: + sfp->gpios.pin_base = PAD_GPIO(0); + break; + case 2: + sfp->gpios.pin_base = PAD_FUNC_SHARE(72); + break; + case 3: + sfp->gpios.pin_base = PAD_FUNC_SHARE(70); + break; + case 4: case 5: case 6: + sfp->gpios.pin_base = PAD_FUNC_SHARE(0); + break; + default: + return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); + } + + sfp->gc.label = dev_name(dev); + sfp->gc.owner = THIS_MODULE; + sfp->gc.request = starfive_gpio_request; + sfp->gc.free = starfive_gpio_free; + sfp->gc.get_direction = starfive_gpio_get_direction; + sfp->gc.direction_input = starfive_gpio_direction_input; + sfp->gc.direction_output = starfive_gpio_direction_output; + sfp->gc.get = starfive_gpio_get; + sfp->gc.set = starfive_gpio_set; + sfp->gc.set_config = starfive_gpio_set_config; + sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges; + sfp->gc.base = -1; + sfp->gc.ngpio = NR_GPIOS; + + starfive_irq_chip.parent_device = dev; + starfive_irq_chip.name = sfp->gc.label; + + sfp->gc.irq.chip = &starfive_irq_chip; + sfp->gc.irq.parent_handler = starfive_gpio_irq_handler; + sfp->gc.irq.num_parents = 1; + sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, + sizeof(*sfp->gc.irq.parents), GFP_KERNEL); + if (!sfp->gc.irq.parents) + return -ENOMEM; + sfp->gc.irq.default_type = IRQ_TYPE_NONE; + sfp->gc.irq.handler = handle_bad_irq; + sfp->gc.irq.init_hw = starfive_gpio_init_hw; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + sfp->gc.irq.parents[0] = ret; + + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); + if (ret) + return dev_err_probe(dev, ret, "could not register gpiochip\n"); + +out_pinctrl_enable: + return pinctrl_enable(sfp->pctl); +} + +static const struct of_device_id starfive_of_match[] = { + { .compatible = "starfive,jh7100-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_of_match); + +static struct platform_driver starfive_pinctrl_driver = { + .probe = starfive_probe, + .driver = { + .name = DRIVER_NAME, + .of_match_table = starfive_of_match, + }, +}; +module_platform_driver(starfive_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs"); +MODULE_AUTHOR("Emil Renner Berthing "); +MODULE_LICENSE("GPL v2"); -- GitLab From d0b65b1500973fef840dbc4bb9f9c237db2b761f Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Thu, 7 Oct 2021 14:24:29 +0200 Subject: [PATCH 758/965] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts Add compatibles for the StarFive JH7100 uarts. Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Emil Renner Berthing --- .../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index b49fda5e608f1..12137fe80acff 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -40,6 +40,11 @@ properties: - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - const: snps,dw-apb-uart + - items: + - enum: + - starfive,jh7100-hsuart + - starfive,jh7100-uart + - const: snps,dw-apb-uart - const: snps,dw-apb-uart reg: -- GitLab From b0ad20a3b64bf653a717860819691b262c0b2a2b Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Mon, 4 Oct 2021 19:40:29 +0200 Subject: [PATCH 759/965] serial: 8250_dw: Add StarFive JH7100 quirk On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to skip the clk_set_rate call and rely solely on the UART's internal divisor. Reviewed-by: Andy Shevchenko Reviewed-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- drivers/tty/serial/8250/8250_dw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 53f57c3b9f42c..1769808031c52 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -414,6 +414,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) if (of_device_is_compatible(np, "marvell,armada-38x-uart")) p->serial_out = dw8250_serial_out38x; + if (of_device_is_compatible(np, "starfive,jh7100-uart")) + p->set_termios = dw8250_do_set_termios; } else if (acpi_dev_present("APMC0D08", NULL, -1)) { p->iotype = UPIO_MEM32; @@ -696,6 +698,7 @@ static const struct of_device_id dw8250_of_match[] = { { .compatible = "cavium,octeon-3860-uart" }, { .compatible = "marvell,armada-38x-uart" }, { .compatible = "renesas,rzn1-uart" }, + { .compatible = "starfive,jh7100-uart" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); -- GitLab From ec85362fb121d0297b9f3bb56816ea6282c34fda Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 10 Oct 2021 16:48:27 +0200 Subject: [PATCH 760/965] RISC-V: Add initial StarFive JH7100 device tree Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Acked-by: Palmer Dabbelt Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++ 1 file changed, 230 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi new file mode 100644 index 0000000000000..69f22f9aad9db --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing + */ + +/dts-v1/; +#include +#include + +/ { + compatible = "starfive,jh7100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + osc_sys: osc_sys { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + osc_aud: osc_aud { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac_rmii_ref: gmac_rmii_ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* Should be overridden by the board when needed */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh7100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <127>; + }; + + clkgen: clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x0 0x11800000 0x0 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; + + rstgen: reset-controller@11840000 { + compatible = "starfive,jh7100-reset"; + reg = <0x0 0x11840000 0x0 0x10000>; + #reset-cells = <1>; + }; + + i2c0: i2c@118b0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118b0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C0_CORE>, + <&clkgen JH7100_CLK_I2C0_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C0_APB>; + interrupts = <96>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@118c0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x118c0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C1_CORE>, + <&clkgen JH7100_CLK_I2C1_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C1_APB>; + interrupts = <97>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio: pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&rstgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart2: serial@12430000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12430000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART2_CORE>, + <&clkgen JH7100_CLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART2_APB>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@12440000 { + compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; + reg = <0x0 0x12440000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_UART3_CORE>, + <&clkgen JH7100_CLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&rstgen JH7100_RSTN_UART3_APB>; + interrupts = <73>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c2: i2c@12450000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12450000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C2_CORE>, + <&clkgen JH7100_CLK_I2C2_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C2_APB>; + interrupts = <74>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@12460000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12460000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_I2C3_CORE>, + <&clkgen JH7100_CLK_I2C3_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen JH7100_RSTN_I2C3_APB>; + interrupts = <75>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; -- GitLab From a43676272a6e0b398781bc5337ca4cc187ba923d Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sun, 10 Oct 2021 19:48:36 +0200 Subject: [PATCH 761/965] RISC-V: Add BeagleV Starlight Beta device tree Add initial device tree for the BeagleV Starlight Beta board. About 300 of these boards were sent out as part of a now cancelled BeagleBoard.org project. I2C timing data is based on the device tree in the vendor u-boot port. Heartbeat LED added by Geert. Acked-by: Palmer Dabbelt Co-developed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/starfive/Makefile | 2 + .../dts/starfive/jh7100-beaglev-starlight.dts | 164 ++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/Makefile create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index fe996b88319eb..ff174996cdfd0 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive +subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile new file mode 100644 index 0000000000000..0ea1bc15ab305 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts new file mode 100644 index 0000000000000..c9af67f7a0d20 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing + */ + +/dts-v1/; +#include "jh7100.dtsi" +#include +#include +#include + +/ { + model = "BeagleV Starlight Beta"; + compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <6250000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; + + leds { + compatible = "gpio-leds"; + + led-ack { + gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + label = "ack"; + }; + }; +}; + +&gpio { + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_pins: i2c1-0 { + i2c-pins { + pinmux = , + ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + }; + + i2c2_pins: i2c2-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-0 { + rx-pins { + pinmux = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + tx-pins { + pinmux = ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + pmic@5e { + compatible = "ti,tps65086"; + reg = <0x5e>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <100>; + i2c-scl-falling-time-ns = <100>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&osc_sys { + clock-frequency = <25000000>; +}; + +&osc_aud { + clock-frequency = <27000000>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; -- GitLab From 893d4d9c62ecb32bad7843fc31ec9eb740600758 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Wed, 8 Dec 2021 14:25:23 -0600 Subject: [PATCH 762/965] s390/exit: remove dead reference to do_exit from copy_thread My s390 assembly is not particularly good so I have read the history of the reference to do_exit copy_thread and have been able to verify that do_exit is not used. The general argument is that s390 has been changed to use the generic kernel_thread and kernel_execve and the generic versions do not call do_exit. So it is strange to see a do_exit reference sitting there. The history of the do_exit reference in s390's version of copy_thread seems conclusive that the do_exit reference is something that lingers and should have been removed several years ago. Up through 8d19f15a60be ("[PATCH] s390 update (1/27): arch.") the s390 code made a call to the exit(2) system call when a kernel thread finished. Then kernel_thread_starter was added which branched directly to the value in register 11 when the kernel thread finshed. The value in register 11 was set in kernel_thread to "regs.gprs[11] = (unsigned long) do_exit" In commit 37fe5d41f640 ("s390: fold kernel_thread_helper() into ret_from_fork()") kernel_thread_starter was moved into entry.S and entry64.S unchanged (except for the syntax differences between inline assemly and in the assembly file). In commit f9a7e025dfc2 ("s390: switch to generic kernel_thread()") the assignment to "gprs[11]" was moved into copy_thread from the old kernel_thread. The helper kernel_thread_starter was still being used and was still branching to "%r11" at the end. In commit 30dcb0996e40 ("s390: switch to saner kernel_execve() semantics") kernel_thread_starter was changed to unconditionally branch to sysc_tracenogo instead to %r11 which held the value of do_exit. Unfortunately copy_thread was not updated to stop passing do_exit in "gprs[11]". In commit 56e62a737028 ("s390: convert to generic entry") kernel_thread_starter was replaced by __ret_from_fork. And the code still continued to pass do_exit in "gprs[11]" despite __ret_from_fork not caring in the slightest. Remove this dead reference to do_exit to make it clear that s390 is not doing anything with do_exit in copy_thread. History Tree: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Cc: Vasily Gorbik Cc: Christian Borntraeger Cc: Alexander Gordeev Cc: Al Viro Fixes: 30dcb0996e40 ("s390: switch to saner kernel_execve() semantics") Signed-off-by: "Eric W. Biederman" Link: https://lore.kernel.org/r/20211208202532.16409-1-ebiederm@xmission.com Signed-off-by: Heiko Carstens --- arch/s390/kernel/process.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index e8858b2de24b7..71d86f73b02c9 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -139,7 +139,6 @@ int copy_thread(unsigned long clone_flags, unsigned long new_stackp, (unsigned long)__ret_from_fork; frame->childregs.gprs[9] = new_stackp; /* function */ frame->childregs.gprs[10] = arg; - frame->childregs.gprs[11] = (unsigned long)do_exit; frame->childregs.orig_gpr2 = -1; frame->childregs.last_break = 1; return 0; -- GitLab From b6b486ecef02916af8a430397ccd5a68c5b967b1 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 13 Dec 2021 18:59:02 +0100 Subject: [PATCH 763/965] s390/sclp: fix memblock_phys_free() vs memblock_free() confusion memblock_phys_free() is used on a virtual address. Fix this by using memblock_free(). Note: this doesn't fix a bug currently, since virtual and physical addresses are identical. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- drivers/s390/char/sclp_early.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/s390/char/sclp_early.c b/drivers/s390/char/sclp_early.c index b64feab62caa8..e9943a86c361e 100644 --- a/drivers/s390/char/sclp_early.c +++ b/drivers/s390/char/sclp_early.c @@ -139,7 +139,7 @@ int __init sclp_early_get_core_info(struct sclp_core_info *info) } sclp_fill_core_info(info, sccb); out: - memblock_phys_free((unsigned long)sccb, length); + memblock_free(sccb, length); return rc; } -- GitLab From fcfcba6dfc9a57da9c816667c20614ddfd4def10 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 13 Dec 2021 19:00:57 +0100 Subject: [PATCH 764/965] s390/smp: fix memblock_phys_free() vs memblock_free() confusion memblock_phys_free() is used on a virtual address. Fix this by using memblock_free(). Note: this doesn't fix a bug currently, since virtual and physical addresses are identical. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 2e280e812dfd1..2590c31a8fc30 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -880,7 +880,7 @@ void __init smp_detect_cpus(void) /* Add CPUs present at boot */ __smp_rescan_cpus(info, true); - memblock_phys_free((unsigned long)info, sizeof(*info)); + memblock_free(info, sizeof(*info)); } /* -- GitLab From 15b5c1833afc80b952383502eb06529db2b26219 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 13 Dec 2021 19:16:38 +0100 Subject: [PATCH 765/965] s390/uv: fix memblock virtual vs physical address confusion memblock_alloc_try_nid() returns a virtual address, however in error case the allocated memory is incorrectly freed with memblock_phys_free(). Properly use memblock_free() instead, and pass a physical address to uv_init() to fix this. Note: this doesn't fix a bug currently, since virtual and physical addresses are identical. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/kernel/uv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index 386d4e42b8d36..a5425075dd255 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -30,7 +30,7 @@ int __bootdata_preserved(prot_virt_host); EXPORT_SYMBOL(prot_virt_host); EXPORT_SYMBOL(uv_info); -static int __init uv_init(unsigned long stor_base, unsigned long stor_len) +static int __init uv_init(phys_addr_t stor_base, unsigned long stor_len) { struct uv_cb_init uvcb = { .header.cmd = UVC_CMD_INIT_UV, @@ -49,12 +49,12 @@ static int __init uv_init(unsigned long stor_base, unsigned long stor_len) void __init setup_uv(void) { - unsigned long uv_stor_base; + void *uv_stor_base; if (!is_prot_virt_host()) return; - uv_stor_base = (unsigned long)memblock_alloc_try_nid( + uv_stor_base = memblock_alloc_try_nid( uv_info.uv_base_stor_len, SZ_1M, SZ_2G, MEMBLOCK_ALLOC_ACCESSIBLE, NUMA_NO_NODE); if (!uv_stor_base) { @@ -63,8 +63,8 @@ void __init setup_uv(void) goto fail; } - if (uv_init(uv_stor_base, uv_info.uv_base_stor_len)) { - memblock_phys_free(uv_stor_base, uv_info.uv_base_stor_len); + if (uv_init(__pa(uv_stor_base), uv_info.uv_base_stor_len)) { + memblock_free(uv_stor_base, uv_info.uv_base_stor_len); goto fail; } -- GitLab From 248420797d28c922507f9bfbcc64dbaa0c0a7f53 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 14 Dec 2021 20:41:13 +0100 Subject: [PATCH 766/965] s390/disassembler: update opcode table Sync with binutils: update opcode table to reflect the instruction format update of the lpswey instruction, and add the qpaci instruction. Signed-off-by: Heiko Carstens --- arch/s390/kernel/dis.c | 1 + arch/s390/tools/opcodes.txt | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c index ec5515423f17c..90bbb4ea1d086 100644 --- a/arch/s390/kernel/dis.c +++ b/arch/s390/kernel/dis.c @@ -278,6 +278,7 @@ static const unsigned char formats[][6] = { [INSTR_SIL_RDI] = { D_20, B_16, I16_32, 0, 0, 0 }, [INSTR_SIL_RDU] = { D_20, B_16, U16_32, 0, 0, 0 }, [INSTR_SIY_IRD] = { D20_20, B_16, I8_8, 0, 0, 0 }, + [INSTR_SIY_RD] = { D20_20, B_16, 0, 0, 0, 0 }, [INSTR_SIY_URD] = { D20_20, B_16, U8_8, 0, 0, 0 }, [INSTR_SI_RD] = { D_20, B_16, 0, 0, 0, 0 }, [INSTR_SI_URD] = { D_20, B_16, U8_8, 0, 0, 0 }, diff --git a/arch/s390/tools/opcodes.txt b/arch/s390/tools/opcodes.txt index 6db9820d104a1..5f008e7948987 100644 --- a/arch/s390/tools/opcodes.txt +++ b/arch/s390/tools/opcodes.txt @@ -276,6 +276,7 @@ b285 lpctl S_RD b286 qsi S_RD b287 lsctl S_RD b28e qctri S_RD +b28f qpaci S_RD b299 srnm S_RD b29c stfpc S_RD b29d lfpc S_RD @@ -1098,7 +1099,7 @@ eb61 stric RSY_RDRU eb62 mric RSY_RDRU eb6a asi SIY_IRD eb6e alsi SIY_IRD -eb71 lpswey SIY_URD +eb71 lpswey SIY_RD eb7a agsi SIY_IRD eb7e algsi SIY_IRD eb80 icmh RSY_RURD -- GitLab From cff2d3abc8da078a0447d785736204d8a0ad49b0 Mon Sep 17 00:00:00 2001 From: Juergen Christ Date: Mon, 22 Nov 2021 14:01:34 +0100 Subject: [PATCH 767/965] s390/zcrypt: CCA control CPRB sending When sending a CCA CPRB to a control domain, the CPRB has to be sent via a usage domain. Previous code used the default domain to route this message. If the default domain is not online and ready to send the CPRB, the ioctl will fail even if other usage domains could be used to send the CPRB. To improve this, instead of using the default domain, switch to auto-select of the domain. Signed-off-by: Juergen Christ Reviewed-by: Harald Freudenberger Signed-off-by: Heiko Carstens --- drivers/s390/crypto/zcrypt_api.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/s390/crypto/zcrypt_api.c b/drivers/s390/crypto/zcrypt_api.c index 4c3dcc435e83d..9811ab81f3c43 100644 --- a/drivers/s390/crypto/zcrypt_api.c +++ b/drivers/s390/crypto/zcrypt_api.c @@ -878,14 +878,13 @@ static long _zcrypt_send_cprb(bool userspace, struct ap_perms *perms, /* * If a valid target domain is set and this domain is NOT a usage - * domain but a control only domain, use the default domain as target. + * domain but a control only domain, autoselect target domain. */ tdom = *domain; if (tdom < AP_DOMAINS && !ap_test_config_usage_domain(tdom) && - ap_test_config_ctrl_domain(tdom) && - ap_domain_index >= 0) - tdom = ap_domain_index; + ap_test_config_ctrl_domain(tdom)) + tdom = AUTOSEL_DOM; pref_zc = NULL; pref_zq = NULL; -- GitLab From c7ed509b21b6566990ff39a6744cd5e214b5dca9 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 10 Dec 2021 16:32:11 +0100 Subject: [PATCH 768/965] s390/nmi: disable interrupts on extended save area update Updating of the pointer to machine check extended save area on the IPL CPU needs the lowcore protection to be disabled. Disable interrupts while the protection is off to avoid unnoticed writes to the lowcore. Suggested-by: Heiko Carstens Signed-off-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/include/asm/nmi.h | 6 +++--- arch/s390/kernel/nmi.c | 41 +++++++++++++++---------------------- arch/s390/kernel/setup.c | 2 +- arch/s390/kernel/smp.c | 13 ++++++++---- 4 files changed, 29 insertions(+), 33 deletions(-) diff --git a/arch/s390/include/asm/nmi.h b/arch/s390/include/asm/nmi.h index 2db45d7e68aa7..55c9051dddfdd 100644 --- a/arch/s390/include/asm/nmi.h +++ b/arch/s390/include/asm/nmi.h @@ -98,9 +98,9 @@ struct mcesa { struct pt_regs; -void nmi_alloc_boot_cpu(struct lowcore *lc); -int nmi_alloc_per_cpu(struct lowcore *lc); -void nmi_free_per_cpu(struct lowcore *lc); +void nmi_alloc_mcesa_early(u64 *mcesad); +int nmi_alloc_mcesa(u64 *mcesad); +void nmi_free_mcesa(u64 *mcesad); void s390_handle_mcck(void); void __s390_handle_mcck(void); diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 3f18c1412eba3..1cf1e37553e85 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -58,27 +58,27 @@ static inline unsigned long nmi_get_mcesa_size(void) /* * The initial machine check extended save area for the boot CPU. - * It will be replaced by nmi_init() with an allocated structure. - * The structure is required for machine check happening early in - * the boot process. + * It will be replaced on the boot CPU reinit with an allocated + * structure. The structure is required for machine check happening + * early in the boot process. */ static struct mcesa boot_mcesa __initdata __aligned(MCESA_MAX_SIZE); -void __init nmi_alloc_boot_cpu(struct lowcore *lc) +void __init nmi_alloc_mcesa_early(u64 *mcesad) { if (!nmi_needs_mcesa()) return; - lc->mcesad = __pa(&boot_mcesa); + *mcesad = __pa(&boot_mcesa); if (MACHINE_HAS_GS) - lc->mcesad |= ilog2(MCESA_MAX_SIZE); + *mcesad |= ilog2(MCESA_MAX_SIZE); } -static int __init nmi_init(void) +static void __init nmi_alloc_cache(void) { - unsigned long origin, cr0, size; + unsigned long size; if (!nmi_needs_mcesa()) - return 0; + return; size = nmi_get_mcesa_size(); if (size > MCESA_MIN_SIZE) mcesa_origin_lc = ilog2(size); @@ -86,40 +86,31 @@ static int __init nmi_init(void) mcesa_cache = kmem_cache_create("nmi_save_areas", size, size, 0, NULL); if (!mcesa_cache) panic("Couldn't create nmi save area cache"); - origin = (unsigned long) kmem_cache_alloc(mcesa_cache, GFP_KERNEL); - if (!origin) - panic("Couldn't allocate nmi save area"); - /* The pointer is stored with mcesa_bits ORed in */ - kmemleak_not_leak((void *) origin); - __ctl_store(cr0, 0, 0); - __ctl_clear_bit(0, 28); /* disable lowcore protection */ - /* Replace boot_mcesa on the boot CPU */ - S390_lowcore.mcesad = __pa(origin) | mcesa_origin_lc; - __ctl_load(cr0, 0, 0); - return 0; } -early_initcall(nmi_init); -int nmi_alloc_per_cpu(struct lowcore *lc) +int __ref nmi_alloc_mcesa(u64 *mcesad) { unsigned long origin; + *mcesad = 0; if (!nmi_needs_mcesa()) return 0; + if (!mcesa_cache) + nmi_alloc_cache(); origin = (unsigned long) kmem_cache_alloc(mcesa_cache, GFP_KERNEL); if (!origin) return -ENOMEM; /* The pointer is stored with mcesa_bits ORed in */ kmemleak_not_leak((void *) origin); - lc->mcesad = __pa(origin) | mcesa_origin_lc; + *mcesad = __pa(origin) | mcesa_origin_lc; return 0; } -void nmi_free_per_cpu(struct lowcore *lc) +void nmi_free_mcesa(u64 *mcesad) { if (!nmi_needs_mcesa()) return; - kmem_cache_free(mcesa_cache, __va(lc->mcesad & MCESA_ORIGIN_MASK)); + kmem_cache_free(mcesa_cache, __va(*mcesad & MCESA_ORIGIN_MASK)); } static notrace void s390_handle_damage(void) diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 225ab2d0a4c60..f2c25d113e7be 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -445,7 +445,7 @@ static void __init setup_lowcore_dat_off(void) lc->lpp = LPP_MAGIC; lc->machine_flags = S390_lowcore.machine_flags; lc->preempt_count = S390_lowcore.preempt_count; - nmi_alloc_boot_cpu(lc); + nmi_alloc_mcesa_early(&lc->mcesad); lc->sys_enter_timer = S390_lowcore.sys_enter_timer; lc->exit_timer = S390_lowcore.exit_timer; lc->user_timer = S390_lowcore.user_timer; diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 2590c31a8fc30..1172aaf0b7e21 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -212,7 +212,7 @@ static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); lc->preempt_count = PREEMPT_DISABLED; - if (nmi_alloc_per_cpu(lc)) + if (nmi_alloc_mcesa(&lc->mcesad)) goto out; lowcore_ptr[cpu] = lc; pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); @@ -239,7 +239,7 @@ static void pcpu_free_lowcore(struct pcpu *pcpu) mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); lowcore_ptr[cpu] = NULL; - nmi_free_per_cpu(lc); + nmi_free_mcesa(&lc->mcesad); stack_free(async_stack); stack_free(mcck_stack); free_pages(nodat_stack, THREAD_SIZE_ORDER); @@ -1271,14 +1271,15 @@ static int __init smp_reinit_ipl_cpu(void) { unsigned long async_stack, nodat_stack, mcck_stack; struct lowcore *lc, *lc_ipl; - unsigned long flags; + unsigned long flags, cr0; + u64 mcesad; lc_ipl = lowcore_ptr[0]; lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); async_stack = stack_alloc(); mcck_stack = stack_alloc(); - if (!lc || !nodat_stack || !async_stack || !mcck_stack) + if (!lc || !nodat_stack || !async_stack || !mcck_stack || nmi_alloc_mcesa(&mcesad)) panic("Couldn't allocate memory"); local_irq_save(flags); @@ -1287,6 +1288,10 @@ static int __init smp_reinit_ipl_cpu(void) S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET; S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET; S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET; + __ctl_store(cr0, 0, 0); + __ctl_clear_bit(0, 28); /* disable lowcore protection */ + S390_lowcore.mcesad = mcesad; + __ctl_load(cr0, 0, 0); lowcore_ptr[0] = lc; local_mcck_enable(); local_irq_restore(flags); -- GitLab From cb22cd2d8ff3201f04f167efa86cc561dccffffe Mon Sep 17 00:00:00 2001 From: Alexander Egorenkov Date: Thu, 11 Nov 2021 12:33:59 +0100 Subject: [PATCH 769/965] s390/sclp: release SCLP early buffer after kernel initialization The SCLP early buffer is used only during kernel initialization and can be freed afterwards. The only way to ensure that it is not released while being in use, is to release it in free_initmem(). Acked-by: Heiko Carstens Reviewed-by: Alexander Gordeev Signed-off-by: Alexander Egorenkov [agordeev@linux.ibm.com: added debug output] Signed-off-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c index 8c6f258a61832..86ffd0d51fd59 100644 --- a/arch/s390/mm/init.c +++ b/arch/s390/mm/init.c @@ -215,6 +215,9 @@ void free_initmem(void) __set_memory((unsigned long)_sinittext, (unsigned long)(_einittext - _sinittext) >> PAGE_SHIFT, SET_MEMORY_RW | SET_MEMORY_NX); + free_reserved_area(sclp_early_sccb, + sclp_early_sccb + EXT_SCCB_READ_SCP, + POISON_FREE_INITMEM, "unused early sccb"); free_initmem_default(POISON_FREE_INITMEM); } -- GitLab From c2c224932fd0ee6854d6ebfc8d059c2bcad86606 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Thu, 4 Nov 2021 07:14:44 +0100 Subject: [PATCH 770/965] s390/mm: fix 2KB pgtable release race There is a race on concurrent 2KB-pgtables release paths when both upper and lower halves of the containing parent page are freed, one via page_table_free_rcu() + __tlb_remove_table(), and the other via page_table_free(). The race might lead to a corruption as result of remove of list item in page_table_free() concurrently with __free_page() in __tlb_remove_table(). Let's assume first the lower and next the upper 2KB-pgtables are freed from a page. Since both halves of the page are allocated the tracking byte (bits 24-31 of the page _refcount) has value of 0x03 initially: CPU0 CPU1 ---- ---- page_table_free_rcu() // lower half { // _refcount[31..24] == 0x03 ... atomic_xor_bits(&page->_refcount, 0x11U << (0 + 24)); // _refcount[31..24] <= 0x12 ... table = table | (1U << 0); tlb_remove_table(tlb, table); } ... __tlb_remove_table() { // _refcount[31..24] == 0x12 mask = _table & 3; // mask <= 0x01 ... page_table_free() // upper half { // _refcount[31..24] == 0x12 ... atomic_xor_bits( &page->_refcount, 1U << (1 + 24)); // _refcount[31..24] <= 0x10 // mask <= 0x10 ... atomic_xor_bits(&page->_refcount, mask << (4 + 24)); // _refcount[31..24] <= 0x00 // mask <= 0x00 ... if (mask != 0) // == false break; fallthrough; ... if (mask & 3) // == false ... else __free_page(page); list_del(&page->lru); ^^^^^^^^^^^^^^^^^^ RACE! ^^^^^^^^^^^^^^^^^^^^^ } ... } The problem is page_table_free() releases the page as result of lower nibble unset and __tlb_remove_table() observing zero too early. With this update page_table_free() will use the similar logic as page_table_free_rcu() + __tlb_remove_table(), and mark the fragment as pending for removal in the upper nibble until after the list_del(). In other words, the parent page is considered as unreferenced and safe to release only when the lower nibble is cleared already and unsetting a bit in upper nibble results in that nibble turned zero. Cc: stable@vger.kernel.org Suggested-by: Vlastimil Babka Reviewed-by: Gerald Schaefer Signed-off-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/pgalloc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 82a2617362d58..457c80924542a 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -244,13 +244,15 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) /* Free 2K page table fragment of a 4K page */ bit = ((unsigned long) table & ~PAGE_MASK)/(PTRS_PER_PTE*sizeof(pte_t)); spin_lock_bh(&mm->context.lock); - mask = atomic_xor_bits(&page->_refcount, 1U << (bit + 24)); + mask = atomic_xor_bits(&page->_refcount, 0x11U << (bit + 24)); mask >>= 24; if (mask & 3) list_add(&page->lru, &mm->context.pgtable_list); else list_del(&page->lru); spin_unlock_bh(&mm->context.lock); + mask = atomic_xor_bits(&page->_refcount, 0x10U << (bit + 24)); + mask >>= 24; if (mask != 0) return; } else { -- GitLab From 1194372db6f3c917c9c6f6907e8378cf1076c557 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Thu, 4 Nov 2021 07:14:45 +0100 Subject: [PATCH 771/965] s390/mm: better annotate 2KB pagetable fragments handling Explicitly encode immediate value of pending remove nibble (bits 31-28) and tracking nibble (bits 27-24) of the page refcount whenever these nibbles are tested or changed, for better readability. Also, add some comments describing how the fragments are handled. Reviewed-by: Gerald Schaefer Signed-off-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/mm/pgalloc.c | 127 ++++++++++++++++++++++++++++++++++------- 1 file changed, 107 insertions(+), 20 deletions(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 457c80924542a..5d5549843c5cd 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -176,7 +176,75 @@ void page_table_free_pgste(struct page *page) #endif /* CONFIG_PGSTE */ /* - * page table entry allocation/free routines. + * A 2KB-pgtable is either upper or lower half of a normal page. + * The second half of the page may be unused or used as another + * 2KB-pgtable. + * + * Whenever possible the parent page for a new 2KB-pgtable is picked + * from the list of partially allocated pages mm_context_t::pgtable_list. + * In case the list is empty a new parent page is allocated and added to + * the list. + * + * When a parent page gets fully allocated it contains 2KB-pgtables in both + * upper and lower halves and is removed from mm_context_t::pgtable_list. + * + * When 2KB-pgtable is freed from to fully allocated parent page that + * page turns partially allocated and added to mm_context_t::pgtable_list. + * + * If 2KB-pgtable is freed from the partially allocated parent page that + * page turns unused and gets removed from mm_context_t::pgtable_list. + * Furthermore, the unused parent page is released. + * + * As follows from the above, no unallocated or fully allocated parent + * pages are contained in mm_context_t::pgtable_list. + * + * The upper byte (bits 24-31) of the parent page _refcount is used + * for tracking contained 2KB-pgtables and has the following format: + * + * PP AA + * 01234567 upper byte (bits 24-31) of struct page::_refcount + * || || + * || |+--- upper 2KB-pgtable is allocated + * || +---- lower 2KB-pgtable is allocated + * |+------- upper 2KB-pgtable is pending for removal + * +-------- lower 2KB-pgtable is pending for removal + * + * (See commit 620b4e903179 ("s390: use _refcount for pgtables") on why + * using _refcount is possible). + * + * When 2KB-pgtable is allocated the corresponding AA bit is set to 1. + * The parent page is either: + * - added to mm_context_t::pgtable_list in case the second half of the + * parent page is still unallocated; + * - removed from mm_context_t::pgtable_list in case both hales of the + * parent page are allocated; + * These operations are protected with mm_context_t::lock. + * + * When 2KB-pgtable is deallocated the corresponding AA bit is set to 0 + * and the corresponding PP bit is set to 1 in a single atomic operation. + * Thus, PP and AA bits corresponding to the same 2KB-pgtable are mutually + * exclusive and may never be both set to 1! + * The parent page is either: + * - added to mm_context_t::pgtable_list in case the second half of the + * parent page is still allocated; + * - removed from mm_context_t::pgtable_list in case the second half of + * the parent page is unallocated; + * These operations are protected with mm_context_t::lock. + * + * It is important to understand that mm_context_t::lock only protects + * mm_context_t::pgtable_list and AA bits, but not the parent page itself + * and PP bits. + * + * Releasing the parent page happens whenever the PP bit turns from 1 to 0, + * while both AA bits and the second PP bit are already unset. Then the + * parent page does not contain any 2KB-pgtable fragment anymore, and it has + * also been removed from mm_context_t::pgtable_list. It is safe to release + * the page therefore. + * + * PGSTE memory spaces use full 4KB-pgtables and do not need most of the + * logic described above. Both AA bits are set to 1 to denote a 4KB-pgtable + * while the PP bits are never used, nor such a page is added to or removed + * from mm_context_t::pgtable_list. */ unsigned long *page_table_alloc(struct mm_struct *mm) { @@ -192,14 +260,23 @@ unsigned long *page_table_alloc(struct mm_struct *mm) page = list_first_entry(&mm->context.pgtable_list, struct page, lru); mask = atomic_read(&page->_refcount) >> 24; - mask = (mask | (mask >> 4)) & 3; - if (mask != 3) { + /* + * The pending removal bits must also be checked. + * Failure to do so might lead to an impossible + * value of (i.e 0x13 or 0x23) written to _refcount. + * Such values violate the assumption that pending and + * allocation bits are mutually exclusive, and the rest + * of the code unrails as result. That could lead to + * a whole bunch of races and corruptions. + */ + mask = (mask | (mask >> 4)) & 0x03U; + if (mask != 0x03U) { table = (unsigned long *) page_to_virt(page); bit = mask & 1; /* =1 -> second 2K */ if (bit) table += PTRS_PER_PTE; atomic_xor_bits(&page->_refcount, - 1U << (bit + 24)); + 0x01U << (bit + 24)); list_del(&page->lru); } } @@ -220,12 +297,12 @@ unsigned long *page_table_alloc(struct mm_struct *mm) table = (unsigned long *) page_to_virt(page); if (mm_alloc_pgste(mm)) { /* Return 4K page table with PGSTEs */ - atomic_xor_bits(&page->_refcount, 3 << 24); + atomic_xor_bits(&page->_refcount, 0x03U << 24); memset64((u64 *)table, _PAGE_INVALID, PTRS_PER_PTE); memset64((u64 *)table + PTRS_PER_PTE, 0, PTRS_PER_PTE); } else { /* Return the first 2K fragment of the page */ - atomic_xor_bits(&page->_refcount, 1 << 24); + atomic_xor_bits(&page->_refcount, 0x01U << 24); memset64((u64 *)table, _PAGE_INVALID, 2 * PTRS_PER_PTE); spin_lock_bh(&mm->context.lock); list_add(&page->lru, &mm->context.pgtable_list); @@ -244,19 +321,24 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) /* Free 2K page table fragment of a 4K page */ bit = ((unsigned long) table & ~PAGE_MASK)/(PTRS_PER_PTE*sizeof(pte_t)); spin_lock_bh(&mm->context.lock); + /* + * Mark the page for delayed release. The actual release + * will happen outside of the critical section from this + * function or from __tlb_remove_table() + */ mask = atomic_xor_bits(&page->_refcount, 0x11U << (bit + 24)); mask >>= 24; - if (mask & 3) + if (mask & 0x03U) list_add(&page->lru, &mm->context.pgtable_list); else list_del(&page->lru); spin_unlock_bh(&mm->context.lock); mask = atomic_xor_bits(&page->_refcount, 0x10U << (bit + 24)); mask >>= 24; - if (mask != 0) + if (mask != 0x00U) return; } else { - atomic_xor_bits(&page->_refcount, 3U << 24); + atomic_xor_bits(&page->_refcount, 0x03U << 24); } pgtable_pte_page_dtor(page); @@ -274,43 +356,48 @@ void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table, page = virt_to_page(table); if (mm_alloc_pgste(mm)) { gmap_unlink(mm, table, vmaddr); - table = (unsigned long *) ((unsigned long)table | 3); + table = (unsigned long *) ((unsigned long)table | 0x03U); tlb_remove_table(tlb, table); return; } bit = ((unsigned long) table & ~PAGE_MASK) / (PTRS_PER_PTE*sizeof(pte_t)); spin_lock_bh(&mm->context.lock); + /* + * Mark the page for delayed release. The actual release will happen + * outside of the critical section from __tlb_remove_table() or from + * page_table_free() + */ mask = atomic_xor_bits(&page->_refcount, 0x11U << (bit + 24)); mask >>= 24; - if (mask & 3) + if (mask & 0x03U) list_add_tail(&page->lru, &mm->context.pgtable_list); else list_del(&page->lru); spin_unlock_bh(&mm->context.lock); - table = (unsigned long *) ((unsigned long) table | (1U << bit)); + table = (unsigned long *) ((unsigned long) table | (0x01U << bit)); tlb_remove_table(tlb, table); } void __tlb_remove_table(void *_table) { - unsigned int mask = (unsigned long) _table & 3; + unsigned int mask = (unsigned long) _table & 0x03U; void *table = (void *)((unsigned long) _table ^ mask); struct page *page = virt_to_page(table); switch (mask) { - case 0: /* pmd, pud, or p4d */ + case 0x00U: /* pmd, pud, or p4d */ free_pages((unsigned long) table, 2); break; - case 1: /* lower 2K of a 4K page table */ - case 2: /* higher 2K of a 4K page table */ + case 0x01U: /* lower 2K of a 4K page table */ + case 0x02U: /* higher 2K of a 4K page table */ mask = atomic_xor_bits(&page->_refcount, mask << (4 + 24)); mask >>= 24; - if (mask != 0) + if (mask != 0x00U) break; fallthrough; - case 3: /* 4K page table with pgstes */ - if (mask & 3) - atomic_xor_bits(&page->_refcount, 3 << 24); + case 0x03U: /* 4K page table with pgstes */ + if (mask & 0x03U) + atomic_xor_bits(&page->_refcount, 0x03U << 24); pgtable_pte_page_dtor(page); __free_page(page); break; -- GitLab From 4c88bb96e40b757f4796f70a4a7507df554467c4 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Thu, 4 Nov 2021 07:14:46 +0100 Subject: [PATCH 772/965] s390/mm: check 2KB-fragment page on release When CONFIG_DEBUG_VM is defined check that pending remove and tracking nibbles (bits 31-24 of the page refcount) are cleared. Should the earlier stages of the page lifespan have a race or logical error, such check could help in exposing the issue. Signed-off-by: Alexander Gordeev Reviewed-by: Gerald Schaefer Signed-off-by: Heiko Carstens --- arch/s390/mm/pgalloc.c | 41 ++++++++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/arch/s390/mm/pgalloc.c b/arch/s390/mm/pgalloc.c index 5d5549843c5cd..fd35c1a0213b4 100644 --- a/arch/s390/mm/pgalloc.c +++ b/arch/s390/mm/pgalloc.c @@ -311,10 +311,23 @@ unsigned long *page_table_alloc(struct mm_struct *mm) return table; } +static void page_table_release_check(struct page *page, void *table, + unsigned int half, unsigned int mask) +{ + char msg[128]; + + if (!IS_ENABLED(CONFIG_DEBUG_VM) || !mask) + return; + snprintf(msg, sizeof(msg), + "Invalid pgtable %p release half 0x%02x mask 0x%02x", + table, half, mask); + dump_page(page, msg); +} + void page_table_free(struct mm_struct *mm, unsigned long *table) { + unsigned int mask, bit, half; struct page *page; - unsigned int bit, mask; page = virt_to_page(table); if (!mm_alloc_pgste(mm)) { @@ -337,10 +350,14 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) mask >>= 24; if (mask != 0x00U) return; + half = 0x01U << bit; } else { - atomic_xor_bits(&page->_refcount, 0x03U << 24); + half = 0x03U; + mask = atomic_xor_bits(&page->_refcount, 0x03U << 24); + mask >>= 24; } + page_table_release_check(page, table, half, mask); pgtable_pte_page_dtor(page); __free_page(page); } @@ -380,28 +397,30 @@ void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table, void __tlb_remove_table(void *_table) { - unsigned int mask = (unsigned long) _table & 0x03U; + unsigned int mask = (unsigned long) _table & 0x03U, half = mask; void *table = (void *)((unsigned long) _table ^ mask); struct page *page = virt_to_page(table); - switch (mask) { + switch (half) { case 0x00U: /* pmd, pud, or p4d */ free_pages((unsigned long) table, 2); - break; + return; case 0x01U: /* lower 2K of a 4K page table */ case 0x02U: /* higher 2K of a 4K page table */ mask = atomic_xor_bits(&page->_refcount, mask << (4 + 24)); mask >>= 24; if (mask != 0x00U) - break; - fallthrough; + return; + break; case 0x03U: /* 4K page table with pgstes */ - if (mask & 0x03U) - atomic_xor_bits(&page->_refcount, 0x03U << 24); - pgtable_pte_page_dtor(page); - __free_page(page); + mask = atomic_xor_bits(&page->_refcount, 0x03U << 24); + mask >>= 24; break; } + + page_table_release_check(page, table, half, mask); + pgtable_pte_page_dtor(page); + __free_page(page); } /* -- GitLab From 3951cc6bae4cd252a2efec5bad5d30265d525e0f Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:07 +0100 Subject: [PATCH 773/965] ARM: dts: imx6: phytec: Add PEB-WLBT-05 support The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 85 ++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 90 +++++++++++++++++++ .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 ++++ 10 files changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 8165fae2b1d11..d906a7f05aaad 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index bbf5097ca974f..322f071d972f6 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 95051e18324f2..3f13726c80586 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi new file mode 100644 index 0000000000000..84f884d6e55bc --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_bt>; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_uart3_bt: uart3grp-bt { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ + >; + }; + + pinctrl_usdhc3_wl: usdhc3grp-wl { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 343639cb035ce..a18266598d39f 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index bff98e6769803..607eddc5030f5 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" #include "imx6ul-phytec-segin-peb-av-02.dtsi" +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 0000000000000..04477fd4b9a98 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ + >; + }; + + pinctrl_uart2_bt: uart2grp-bt { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 + >; + }; + + pinctrl_usdhc2_wl: usdhc2grp-wl { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index c8d3eff9ed4ba..1d7362b5ac91b 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" #include "imx6ull-phytec-segin-peb-av-02.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts index e168494e0a6d3..4bcbae024d8d4 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 0000000000000..df25814a33719 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" + +&iomuxc { + /delete-node/ wlgrp; +}; + +&iomuxc_snvs { + pinctrl_wl: wlgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 + >; + }; +}; -- GitLab From e2a6d22f3b48dffcab1dbcb162572ef5a923f24d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:18 -0600 Subject: [PATCH 774/965] soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 8176380b02e6e..a0eab9f41a716 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -841,6 +841,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MN_PGC_GPUMIX), + .keep_clocks = true, }, }; -- GitLab From a0ec8a3a4c8122c1abae04e90c66e79e77eed357 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:19 -0600 Subject: [PATCH 775/965] soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index a0eab9f41a716..3e59d479d001e 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -843,6 +843,31 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .pgc = BIT(IMX8MN_PGC_GPUMIX), .keep_clocks = true, }, + + [IMX8MN_POWER_DOMAIN_DISPMIX] = { + .genpd = { + .name = "dispmix", + }, + .bits = { + .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ, + .map = IMX8MN_DISPMIX_A53_DOMAIN, + .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN, + .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN, + }, + .pgc = BIT(IMX8MN_PGC_DISPMIX), + .keep_clocks = true, + }, + + [IMX8MN_POWER_DOMAIN_MIPI] = { + .genpd = { + .name = "mipi", + }, + .bits = { + .pxx = IMX8MN_MIPI_SW_Pxx_REQ, + .map = IMX8MN_MIPI_A53_DOMAIN, + }, + .pgc = BIT(IMX8MN_PGC_MIPI), + }, }; static const struct regmap_range imx8mn_yes_ranges[] = { -- GitLab From b77beaaee1be62a4623dd7142868c2e1180d8288 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:20 -0600 Subject: [PATCH 776/965] dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Adam Ford Acked-by: Rob Herring Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8mn-power.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h index 102ee85a9b62a..eedd0e581939d 100644 --- a/include/dt-bindings/power/imx8mn-power.h +++ b/include/dt-bindings/power/imx8mn-power.h @@ -12,4 +12,9 @@ #define IMX8MN_POWER_DOMAIN_DISPMIX 3 #define IMX8MN_POWER_DOMAIN_MIPI 4 +#define IMX8MN_DISPBLK_PD_MIPI_DSI 0 +#define IMX8MN_DISPBLK_PD_MIPI_CSI 1 +#define IMX8MN_DISPBLK_PD_LCDIF 2 +#define IMX8MN_DISPBLK_PD_ISI 3 + #endif -- GitLab From 7f511d514e8c34b6dd0c17b5496e48b2a6a2626c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:22 -0600 Subject: [PATCH 777/965] soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl This adds the description for the i.MX8MN disp blk-ctrl. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 77 +++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d96..58a7f11e7e08b 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -14,6 +14,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -498,6 +499,77 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), }; + +static int imx8mn_disp_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* Enable bus clock and deassert bus reset */ + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); + + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + if (action == GENPD_NOTIFY_ON) + udelay(5); + + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { + [IMX8MN_DISPBLK_PD_MIPI_DSI] = { + .name = "dispblk-mipi-dsi", + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, + .num_clks = 2, + .gpc_name = "mipi-dsi", + .rst_mask = BIT(0) | BIT(1), + .clk_mask = BIT(0) | BIT(1), + .mipi_phy_rst_mask = BIT(17), + }, + [IMX8MN_DISPBLK_PD_MIPI_CSI] = { + .name = "dispblk-mipi-csi", + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, + .num_clks = 2, + .gpc_name = "mipi-csi", + .rst_mask = BIT(2) | BIT(3), + .clk_mask = BIT(2) | BIT(3), + .mipi_phy_rst_mask = BIT(16), + }, + [IMX8MN_DISPBLK_PD_LCDIF] = { + .name = "dispblk-lcdif", + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, + .num_clks = 3, + .gpc_name = "lcdif", + .rst_mask = BIT(4) | BIT(5), + .clk_mask = BIT(4) | BIT(5), + }, + [IMX8MN_DISPBLK_PD_ISI] = { + .name = "dispblk-isi", + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", + "disp_apb_root"}, + .num_clks = 4, + .gpc_name = "isi", + .rst_mask = BIT(6) | BIT(7), + .clk_mask = BIT(6) | BIT(7), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { + .max_reg = 0x84, + .power_notifier_fn = imx8mn_disp_power_notifier, + .domains = imx8mn_disp_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -505,7 +577,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mm-disp-blk-ctrl", .data = &imx8mm_disp_blk_ctl_dev_data - } ,{ + }, { + .compatible = "fsl,imx8mn-disp-blk-ctrl", + .data = &imx8mn_disp_blk_ctl_dev_data + }, { /* Sentinel */ } }; -- GitLab From e1e06edd94d5b3171401a1435a17251102cc8494 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:21 -0600 Subject: [PATCH 778/965] dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl Add the DT binding for the i.MX8MN DISP blk-ctrl. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml new file mode 100644 index 0000000000000..fbeaac399c502 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MN DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display and MIPI CSI + peripherals located in the DISP domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mn-disp-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 5 + maxItems: 5 + + power-domain-names: + items: + - const: bus + - const: isi + - const: lcdif + - const: mipi-dsi + - const: mipi-csi + + clocks: + minItems: 11 + maxItems: 11 + + clock-names: + items: + - const: disp_axi + - const: disp_apb + - const: disp_axi_root + - const: disp_apb_root + - const: lcdif-axi + - const: lcdif-apb + - const: lcdif-pix + - const: dsi-pclk + - const: dsi-ref + - const: csi-aclk + - const: csi-pclk + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + disp_blk_ctl: blk_ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", + "dsi-ref", "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; -- GitLab From c9b7011768b5dbb68792b4bacad5ae913059ed74 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Dec 2021 16:04:49 +0100 Subject: [PATCH 779/965] arm64: dts: renesas: Fix pin controller node names Align all pin controller node names with the expectations of the DT bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f89bcc6984206..1e7ed12ebc879 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -87,7 +87,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779a0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index cdf2adea4b10b..19287cccb1f05 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -633,7 +633,7 @@ status = "disabled"; }; - pinctrl: pin-controller@11030000 { + pinctrl: pinctrl@11030000 { compatible = "renesas,r9a07g044-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; -- GitLab From 473dcf0ffc31ce1135cd10578e7e06698cf51f4a Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:22 +0100 Subject: [PATCH 780/965] Documentation, arch: Remove leftovers from raw device Raw device interface was removed so remove all references to configs related to it. Fixes: 603e4922f1c8 ("remove the raw driver") Signed-off-by: Alexandre Ghiti Acked-by: Arnd Bergmann [arch/arm/configs] Signed-off-by: Arnd Bergmann --- Documentation/admin-guide/devices.txt | 8 +------- arch/arm/configs/spear13xx_defconfig | 1 - arch/arm/configs/spear3xx_defconfig | 1 - arch/arm/configs/spear6xx_defconfig | 1 - arch/powerpc/configs/pseries_defconfig | 1 - 5 files changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt index 922c23bb4372a..c07dc0ee860e7 100644 --- a/Documentation/admin-guide/devices.txt +++ b/Documentation/admin-guide/devices.txt @@ -2339,13 +2339,7 @@ disks (see major number 3) except that the limit on partitions is 31. - 162 char Raw block device interface - 0 = /dev/rawctl Raw I/O control device - 1 = /dev/raw/raw1 First raw I/O device - 2 = /dev/raw/raw2 Second raw I/O device - ... - max minor number of raw device is set by kernel config - MAX_RAW_DEVS or raw module parameter 'max_raw_devs' + 162 char Used for (now removed) raw block device interface 163 char diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig index 3b206a31902ff..065553326b391 100644 --- a/arch/arm/configs/spear13xx_defconfig +++ b/arch/arm/configs/spear13xx_defconfig @@ -61,7 +61,6 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index fc5f71c765edc..afca722d6605c 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -41,7 +41,6 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index 52a56b8ce6a71..bc32c02cb86b1 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -36,7 +36,6 @@ CONFIG_INPUT_FF_MEMLESS=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index de7641adb899f..e64f2242abe15 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -189,7 +189,6 @@ CONFIG_HVCS=m CONFIG_VIRTIO_CONSOLE=m CONFIG_IBM_BSR=m CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=1024 CONFIG_I2C_CHARDEV=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y -- GitLab From 2ac7069ad7647cd1d9ca5b08765a1e116e13cdc4 Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:23 +0100 Subject: [PATCH 781/965] Documentation, arch: Remove leftovers from CIFS_WEAK_PW_HASH This config was removed so remove all references to it. Fixes: 76a3c92ec9e0 ("cifs: remove support for NTLM and weaker authentication algorithms") Signed-off-by: Alexandre Ghiti Reviewed-by: Steve French Acked-by: Arnd Bergmann [arch/arm/configs] Acked-by: Thomas Bogendoerfer Signed-off-by: Arnd Bergmann --- Documentation/admin-guide/cifs/usage.rst | 7 +++---- arch/arm/configs/cm_x300_defconfig | 1 - arch/arm/configs/ezx_defconfig | 1 - arch/arm/configs/imote2_defconfig | 1 - arch/arm/configs/nhk8815_defconfig | 1 - arch/arm/configs/pxa_defconfig | 1 - arch/mips/configs/fuloong2e_defconfig | 1 - arch/mips/configs/malta_qemu_32r6_defconfig | 1 - arch/mips/configs/maltaaprp_defconfig | 1 - arch/mips/configs/maltasmvp_defconfig | 1 - arch/mips/configs/maltasmvp_eva_defconfig | 1 - arch/mips/configs/maltaup_defconfig | 1 - arch/powerpc/configs/ppc6xx_defconfig | 1 - arch/sh/configs/titan_defconfig | 1 - 14 files changed, 3 insertions(+), 17 deletions(-) diff --git a/Documentation/admin-guide/cifs/usage.rst b/Documentation/admin-guide/cifs/usage.rst index f170d88202588..3766bf8a1c20e 100644 --- a/Documentation/admin-guide/cifs/usage.rst +++ b/Documentation/admin-guide/cifs/usage.rst @@ -734,10 +734,9 @@ SecurityFlags Flags which control security negotiation and using weaker password hashes is 0x37037 (lanman, plaintext, ntlm, ntlmv2, signing allowed). Some SecurityFlags require the corresponding menuconfig - options to be enabled (lanman and plaintext require - CONFIG_CIFS_WEAK_PW_HASH for example). Enabling - plaintext authentication currently requires also - enabling lanman authentication in the security flags + options to be enabled. Enabling plaintext + authentication currently requires also enabling + lanman authentication in the security flags because the cifs module only supports sending laintext passwords using the older lanman dialect form of the session setup SMB. (e.g. for authentication diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 502a9d870ca44..45769d0ddd4ef 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -146,7 +146,6 @@ CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_ISO8859_1=m diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index a49e699e52de3..ec84d80096b1c 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -314,7 +314,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_SMB_FS=m CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig index 118c4c927f264..6db871d4e0775 100644 --- a/arch/arm/configs/imote2_defconfig +++ b/arch/arm/configs/imote2_defconfig @@ -288,7 +288,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_SMB_FS=m CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 23595fc5a29a9..907d6512821ad 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -127,7 +127,6 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 58f4834289e63..dedaaae3d0d8a 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -699,7 +699,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_DEFAULT="utf8" diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 5c24ac7fdf56d..ba47c5e929b7f 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -206,7 +206,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m CONFIG_CIFS_STATS2=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_CIFS_DEBUG2=y diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig b/arch/mips/configs/malta_qemu_32r6_defconfig index 614af02d83e6e..6fb9bc29f4a03 100644 --- a/arch/mips/configs/malta_qemu_32r6_defconfig +++ b/arch/mips/configs/malta_qemu_32r6_defconfig @@ -165,7 +165,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig index 9c051f8fd3300..eb72df528243a 100644 --- a/arch/mips/configs/maltaaprp_defconfig +++ b/arch/mips/configs/maltaaprp_defconfig @@ -166,7 +166,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig index 2e90d97551d6f..1fb40d310f49c 100644 --- a/arch/mips/configs/maltasmvp_defconfig +++ b/arch/mips/configs/maltasmvp_defconfig @@ -167,7 +167,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig index d1f7fdb27284b..75cb778c61496 100644 --- a/arch/mips/configs/maltasmvp_eva_defconfig +++ b/arch/mips/configs/maltasmvp_eva_defconfig @@ -169,7 +169,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig index 48e5bd4924522..7b4f247dc60cc 100644 --- a/arch/mips/configs/maltaup_defconfig +++ b/arch/mips/configs/maltaup_defconfig @@ -165,7 +165,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 6697c5e6682f1..bb549cb1c3e33 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -1022,7 +1022,6 @@ CONFIG_NFSD=m CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index ba887f1351be6..cd5c58916c65a 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -242,7 +242,6 @@ CONFIG_NFSD=y CONFIG_NFSD_V3=y CONFIG_SMB_FS=m CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_ASCII=m -- GitLab From 5a608e40f9f812fd4bf70b2c044da0ddf4a2552f Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:24 +0100 Subject: [PATCH 782/965] arch: Remove leftovers from mandatory file locking This config was removed so remove all references to it. Fixes: f7e33bdbd6d1 ("fs: remove mandatory file locking support") Signed-off-by: Alexandre Ghiti Reviewed-by: Jeff Layton Acked-by: Thomas Bogendoerfer Signed-off-by: Arnd Bergmann --- arch/mips/configs/decstation_64_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/decstation_r4k_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/mips/configs/decstation_64_defconfig b/arch/mips/configs/decstation_64_defconfig index 85f1955b4b004..e2ed105f8c97c 100644 --- a/arch/mips/configs/decstation_64_defconfig +++ b/arch/mips/configs/decstation_64_defconfig @@ -144,7 +144,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_MANDATORY_FILE_LOCKING is not set CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_PROC_KCORE=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 30a6eafdb1d01..7e987d6f5e344 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -140,7 +140,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_MANDATORY_FILE_LOCKING is not set CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_PROC_KCORE=y diff --git a/arch/mips/configs/decstation_r4k_defconfig b/arch/mips/configs/decstation_r4k_defconfig index e2b58dbf4aa9a..6df5f6f2ac8eb 100644 --- a/arch/mips/configs/decstation_r4k_defconfig +++ b/arch/mips/configs/decstation_r4k_defconfig @@ -140,7 +140,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_MANDATORY_FILE_LOCKING is not set CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_PROC_KCORE=y -- GitLab From e0cb56546d39956cd6c42e690548cafc97e50896 Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:26 +0100 Subject: [PATCH 783/965] arch: Remove leftovers from prism54 wireless driver This driver was removed so remove all references to it. Fixes: d249ff28b1d8 ("intersil: remove obsolete prism54 wireless driver") Signed-off-by: Alexandre Ghiti Acked-by: Thomas Bogendoerfer Signed-off-by: Arnd Bergmann --- arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/malta_kvm_defconfig | 1 - arch/mips/configs/maltaup_xpa_defconfig | 1 - arch/powerpc/configs/pmac32_defconfig | 1 - 5 files changed, 5 deletions(-) diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 638d7cf5ef01d..821630ac1be7f 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -223,7 +223,6 @@ CONFIG_TMD_HERMES=m CONFIG_NORTEL_HERMES=m CONFIG_P54_COMMON=m CONFIG_P54_PCI=m -CONFIG_PRISM54=m CONFIG_LIBERTAS=m CONFIG_LIBERTAS_THINFIRM=m CONFIG_MWL8K=m diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 9cb2cf2595e09..3321bb5769445 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -302,7 +302,6 @@ CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m -CONFIG_PRISM54=m CONFIG_LIBERTAS=m CONFIG_INPUT_MOUSEDEV=y CONFIG_MOUSE_PS2_ELANTECH=y diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig index 5924e48fd3ec6..009b30372226b 100644 --- a/arch/mips/configs/malta_kvm_defconfig +++ b/arch/mips/configs/malta_kvm_defconfig @@ -310,7 +310,6 @@ CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m -CONFIG_PRISM54=m CONFIG_LIBERTAS=m CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig index c0d3156ef6405..e214e136101cd 100644 --- a/arch/mips/configs/maltaup_xpa_defconfig +++ b/arch/mips/configs/maltaup_xpa_defconfig @@ -309,7 +309,6 @@ CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m -CONFIG_PRISM54=m CONFIG_LIBERTAS=m CONFIG_INPUT_MOUSEDEV=y CONFIG_MOUSE_PS2_ELANTECH=y diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig index 7aefac5afab02..13885ec563d15 100644 --- a/arch/powerpc/configs/pmac32_defconfig +++ b/arch/powerpc/configs/pmac32_defconfig @@ -169,7 +169,6 @@ CONFIG_USB_USBNET=m CONFIG_B43=m CONFIG_B43LEGACY=m CONFIG_P54_COMMON=m -CONFIG_PRISM54=m CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set -- GitLab From 733e417518a69b71061c3bafc2bf106109565eee Mon Sep 17 00:00:00 2001 From: Wasin Thonkaew Date: Wed, 3 Nov 2021 19:42:08 +0000 Subject: [PATCH 784/965] asm-generic/error-injection.h: fix a spelling mistake, and a coding style issue Fix a spelling mistake "ganerating" -> "generating". Remove trailing semicolon for a macro ALLOW_ERROR_INJECTION to fix a coding style issue. Signed-off-by: Wasin Thonkaew Acked-by: Masami Hiramatsu Signed-off-by: Arnd Bergmann --- include/asm-generic/error-injection.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/asm-generic/error-injection.h b/include/asm-generic/error-injection.h index 7ddd9dc10ce96..fbca56bd9cbc8 100644 --- a/include/asm-generic/error-injection.h +++ b/include/asm-generic/error-injection.h @@ -20,7 +20,7 @@ struct pt_regs; #ifdef CONFIG_FUNCTION_ERROR_INJECTION /* - * Whitelist ganerating macro. Specify functions which can be + * Whitelist generating macro. Specify functions which can be * error-injectable using this macro. */ #define ALLOW_ERROR_INJECTION(fname, _etype) \ @@ -29,7 +29,7 @@ static struct error_injection_entry __used \ _eil_addr_##fname = { \ .addr = (unsigned long)fname, \ .etype = EI_ETYPE_##_etype, \ - }; + } void override_function_with_return(struct pt_regs *regs); #else -- GitLab From b59e11495b1a0e94d6357ce5df54e24ecbeb8319 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:51:51 +0100 Subject: [PATCH 785/965] ARM: tegra: Add memory client hotflush resets on Tegra114 Add the host1x, gr2d and gr3d memory client hotflush resets on Tegra114. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index f20be4ca16a14..09996acad6399 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -38,8 +38,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA114_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <1>; @@ -52,8 +52,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; + reset-names = "2d", "mc"; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -62,8 +62,8 @@ compatible = "nvidia,tegra114-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; + reset-names = "3d", "mc"; iommus = <&mc TEGRA_SWGROUP_NV>; }; -- GitLab From bd048487af68a9782ebccc3af6606e9e0d7d9f8b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:52:37 +0100 Subject: [PATCH 786/965] ARM: tegra: Add host1x hotflush reset on Tegra124 Add the host1x memory client hotflush reset on Tegra124. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ada152b50ade7..a9ab548781e1c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -94,8 +94,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <2>; -- GitLab From e109c0acb835f81ef228c78d7ae76bbcf9470e20 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:25 +0100 Subject: [PATCH 787/965] dt-bindings: mmc: tegra: Convert to json-schema Convert the NVIDIA Tegra SDHCI bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 -------- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 311 ++++++++++++++++++ 2 files changed, 311 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index 96c0b1440c9c5..0000000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null @@ -1,143 +0,0 @@ -* NVIDIA Tegra Secure Digital Host Controller - -This controller on Tegra family SoCs provides an interface for MMC, SD, -and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-tegra driver. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra20-sdhci": for Tegra20 - - "nvidia,tegra30-sdhci": for Tegra30 - - "nvidia,tegra114-sdhci": for Tegra114 - - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - - "nvidia,tegra210-sdhci": for Tegra210 - - "nvidia,tegra186-sdhci": for Tegra186 - - "nvidia,tegra194-sdhci": for Tegra194 -- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. - One for the module clock and one for the timeout clock. - For all other Tegra devices, must contain a single entry for - the module clock. See ../clocks/clock-bindings.txt for details. -- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the - strings 'sdhci' and 'tmclk' to represent the module and - the timeout clocks, respectively. - For all other Tegra devices must contain the string 'sdhci' - to represent the module clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sdhci - -Optional properties: -- power-gpios : Specify GPIOs for power control - -Example: - -sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = <47>; - clocks = <&tegra_car 14>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <8>; -}; - -Optional properties for Tegra210, Tegra186 and Tegra194: -- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage - configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" - for controllers supporting multiple voltage levels. The order of names - should correspond to the pin configuration states in pinctrl-0 and - pinctrl-1. -- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for - Tegra210 where pad config registers are in the pinmux register domain - for pull-up-strength and pull-down-strength values configuration when - using pads at 3V3 and 1V8 levels. -- nvidia,only-1-8-v : The presence of this property indicates that the - controller operates at a 1.8 V fixed I/O voltage. -- nvidia,pad-autocal-pull-up-offset-3v3, - nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength - calibration offsets for 3.3 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-1v8, - nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength - calibration offsets for 1.8 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-3v3-timeout, - nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 3.3 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-1v8-timeout, - nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 1.8 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-sdr104, - nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength - calibration offsets for SDR104 mode. -- nvidia,pad-autocal-pull-up-offset-hs400, - nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength - calibration offsets for HS400 mode. -- nvidia,default-tap : Specify the default inbound sampling clock - trimmer value for non-tunable modes. -- nvidia,default-trim : Specify the default outbound clock trimmer - value. -- nvidia,dqs-trim : Specify DQS trim value for HS400 timing - - Notes on the pad calibration pull up and pulldown offset values: - - The property values are drive codes which are programmed into the - PD_OFFSET and PU_OFFSET sections of the - SDHCI_TEGRA_AUTO_CAL_CONFIG register. - - A higher value corresponds to higher drive strength. Please refer - to the reference manual of the SoC for correct values. - - The SDR104 and HS400 timing specific values are used in - corresponding modes if specified. - - Notes on tap and trim values: - - The values are used for compensating trace length differences - by adjusting the sampling point. - - The values are programmed to the Vendor Clock Control Register. - Please refer to the reference manual of the SoC for correct - values. - - The DQS trim values are only used on controllers which support - HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports - HS400. - -Example: -sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; - -sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml new file mode 100644 index 0000000000000..f7a9fcc6bbbd1 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Secure Digital Host Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + This controller on Tegra family SoCs provides an interface for MMC, SD, and + SDIO types of memory cards. + + This file documents differences between the core properties described by + mmc-controller.yaml and the properties for the Tegra SDHCI controller. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + - nvidia,tegra210-sdhci + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + + - items: + - const: nvidia,tegra132-sdhci + - const: nvidia,tegra124-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + assigned-clocks: true + assigned-clock-parents: true + assigned-clock-rates: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: sdhci + + power-gpios: + description: specify GPIOs for power control + maxItems: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + + nvidia,default-tap: + description: Specify the default inbound sampling clock trimmer value for + non-tunable modes. + + The values are used for compensating trace length differences by + adjusting the sampling point. The values are programmed to the Vendor + Clock Control Register. Please refer to the reference manual of the SoC + for correct values. + + The DQS trim values are only used on controllers which support HS400 + timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,default-trim: + description: Specify the default outbound clock trimmer value. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,dqs-trim: + description: Specify DQS trim value for HS400 timing. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + + The property values are drive codes which are programmed into the + PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG + register. A higher value corresponds to higher drive strength. Please + refer to the reference manual of the SoC for correct values. The SDR104 + and HS400 timing specific values are used in corresponding modes if + specified. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,only-1-8v: + description: The presence of this property indicates that the controller + operates at a 1.8 V fixed I/O voltage. + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + +allOf: + - $ref: "mmc-controller.yaml" + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + clocks: + items: + - description: module clock + minItems: 1 + maxItems: 1 + else: + properties: + clocks: + items: + - description: module clock + - description: timeout clock + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: sdhci + - const: tmclk + minItems: 2 + maxItems: 2 + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-sdhci + then: + properties: + pinctrl-names: + oneOf: + - items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + then: + properties: + pinctrl-names: + items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mmc@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = <47>; + clocks = <&tegra_car 14>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <8>; + }; + + - | + #include + #include + + mmc@700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; + nvidia,default-tap = <0x2>; + nvidia,default-trim = <0x4>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_C4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; + }; -- GitLab From 068cf93f900267fb4aaf2b14ff369f80aa4b5406 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:26 +0100 Subject: [PATCH 788/965] dt-bindings: mailbox: tegra: Convert to json-schema Convert the NVIDIA Tegra HSP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------ .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 ++++++++++++++++++ 2 files changed, 111 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt deleted file mode 100644 index ff3eafc5a882b..0000000000000 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ /dev/null @@ -1,72 +0,0 @@ -NVIDIA Tegra Hardware Synchronization Primitives (HSP) - -The HSP modules are used for the processors to share resources and communicate -together. It provides a set of hardware synchronization primitives for -interprocessor communication. So the interprocessor communication (IPC) -protocols can use hardware synchronization primitives, when operating between -two processors not in an SMP relationship. - -The features that HSP supported are shared mailboxes, shared semaphores, -arbitrated semaphores and doorbells. - -Required properties: -- name : Should be hsp -- compatible - Array of strings. - one of: - - "nvidia,tegra186-hsp" - - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" -- reg : Offset and length of the register set for the device. -- interrupt-names - Array of strings. - Contains a list of names for the interrupts described by the interrupt - property. May contain the following entries, in any order: - - "doorbell" - - "sharedN", where 'N' is a number from zero up to the number of - external interrupts supported by the HSP instance minus one. - Users of this binding MUST look up entries in the interrupt property - by name, using this interrupt-names property to do so. -- interrupts - Array of interrupt specifiers. - Must contain one entry per entry in the interrupt-names property, - in a matching order. -- #mbox-cells : Should be 2. - -The mbox specifier of the "mboxes" property in the client node should contain -two cells. The first cell determines the HSP type and the second cell is used -to identify the mailbox that the client is going to use. - -For doorbells, the second cell specifies the index of the doorbell to use. - -For shared mailboxes, the second cell is composed of two fields: -- bits 31..24: - A bit mask of flags that further specify how the shared mailbox will be - used. Valid flags are: - - bit 31: - Defines the direction of the mailbox. If set, the mailbox will be used - as a producer (i.e. used to send data). If cleared, the mailbox is the - consumer of data sent by a producer. - -- bits 23.. 0: - The index of the shared mailbox to use. The number of available mailboxes - may vary by instance of the HSP block and SoC generation. - -The following file contains definitions that can be used to construct mailbox -specifiers: - - - -Example: - -hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; -}; - -client { - ... - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml new file mode 100644 index 0000000000000..c43fc4c56f77a --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The HSP modules are used for the processors to share resources and + communicate together. It provides a set of hardware synchronization + primitives for interprocessor communication. So the interprocessor + communication (IPC) protocols can use hardware synchronization + primitives, when operating between two processors not in an SMP + relationship. + + The features that HSP supported are shared mailboxes, shared + semaphores, arbitrated semaphores and doorbells. + + The mbox specifier of the "mboxes" property in the client node should + contain two cells. The first cell determines the HSP type and the + second cell is used to identify the mailbox that the client is going + to use. + + For doorbells, the second cell specifies the index of the doorbell to + use. + + For shared mailboxes, the second cell is composed of two fields: + - bits 31..24: + A bit mask of flags that further specify how the shared mailbox + will be used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox + will be used as a producer (i.e. used to send data). If + cleared, the mailbox is the consumer of data sent by a + producer. + + - bits 23..0: + The index of the shared mailbox to use. The number of available + mailboxes may vary by instance of the HSP block and SoC + generation. + + The following file contains definitions that can be used to + construct mailbox specifiers: + + + +properties: + $nodename: + pattern: "^hsp@[0-9a-f]+$" + + compatible: + oneOf: + - const: nvidia,tegra186-hsp + - const: nvidia,tegra194-hsp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 9 + + interrupt-names: + oneOf: + # shared interrupts are optional + - items: + - const: doorbell + + - items: + - const: doorbell + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + - items: + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + "#mbox-cells": + const: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + client { + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>; + }; -- GitLab From 0637af949a8c75d171a635eb0e41a9104f23bb6b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:27 +0100 Subject: [PATCH 789/965] dt-bindings: mailbox: tegra: Document Tegra234 HSP Add the compatible string for the HSP block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index c43fc4c56f77a..9f7a7296b57ff 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -57,6 +57,9 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - items: + - const: nvidia,tegra234-hsp + - const: nvidia,tegra194-hsp reg: maxItems: 1 -- GitLab From 2f9df754d0c20da8a2f64c461c4567a38b289ef9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:28 +0100 Subject: [PATCH 790/965] dt-bindings: rtc: tegra: Convert to json-schema Convert the NVIDIA Tegra RTC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 -------- .../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e098c..0000000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,-rtc", "nvidia,tegra20-rtc"', where - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml new file mode 100644 index 0000000000000..94266de73cb90 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra real-time clock + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra RTC maintains seconds and milliseconds counters, and five + alarm registers. The alarms and other interrupts may wake the system + from low-power state. + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-rtc + - items: + - enum: + - nvidia,tegra30-rtc + - nvidia,tegra114-rtc + - nvidia,tegra124-rtc + - nvidia,tegra210-rtc + - nvidia,tegra186-rtc + - nvidia,tegra194-rtc + - const: nvidia,tegra20-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + timer@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; + }; -- GitLab From aa8f488fd616e23ce03311f2365ab07eab9bd350 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:29 +0100 Subject: [PATCH 791/965] dt-bindings: rtc: tegra: Document Tegra234 RTC Add the compatible string for the RTC block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml index 94266de73cb90..17d6280e55150 100644 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-rtc - nvidia,tegra186-rtc - nvidia,tegra194-rtc + - nvidia,tegra234-rtc - const: nvidia,tegra20-rtc reg: -- GitLab From 25388844f92f0560961cb7dd374bcdf343d5b1f9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:30 +0100 Subject: [PATCH 792/965] dt-bindings: fuse: tegra: Convert to json-schema Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 --------- .../bindings/fuse/nvidia,tegra20-fuse.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index b109911669e4b..0000000000000 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". - For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain - "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". - For Tegra234 must contain "nvidia,tegra234-efuse". - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml new file mode 100644 index 0000000000000..2bd901dda9766 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra FUSE block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra210-efuse + - nvidia,tegra186-efuse + - nvidia,tegra194-efuse + + - items: + - const: nvidia,tegra132-efuse + - const: nvidia,tegra124-efuse + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fuse + + resets: + maxItems: 1 + + reset-names: + items: + - const: fuse + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra132-efuse + - nvidia,tegra210-efuse +then: + required: + - resets + - reset-names + +examples: + - | + #include + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; -- GitLab From f8dd779bcb4b5a0f891f82a3f23f337ce82da783 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:31 +0100 Subject: [PATCH 793/965] dt-bindings: fuse: tegra: Document Tegra234 FUSE Add the compatible string for the FUSE block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 2bd901dda9766..4819012698722 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -21,6 +21,7 @@ properties: - nvidia,tegra210-efuse - nvidia,tegra186-efuse - nvidia,tegra194-efuse + - nvidia,tegra234-efuse - items: - const: nvidia,tegra132-efuse -- GitLab From d5de8b7608e9e710b18a080b322b11cb40a11efc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:32 +0100 Subject: [PATCH 794/965] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Add the compatible string for the SDHCI block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index f7a9fcc6bbbd1..ce64b34983785 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -33,6 +33,12 @@ properties: - const: nvidia,tegra132-sdhci - const: nvidia,tegra124-sdhci + - items: + - enum: + - nvidia,tegra194-sdhci + - nvidia,tegra234-sdhci + - const: nvidia,tegra186-sdhci + reg: maxItems: 1 -- GitLab From 96b594d2a0932d1c9ae1c48144a63aabc972222d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:33 +0100 Subject: [PATCH 795/965] dt-bindings: serial: 8250: Document Tegra234 UART Add the compatible string for the UART found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/serial/8250.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index fa767440f2816..3bab2f27b970f 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -113,9 +113,10 @@ properties: - nvidia,tegra30-uart - nvidia,tegra114-uart - nvidia,tegra124-uart + - nvidia,tegra210-uart - nvidia,tegra186-uart - nvidia,tegra194-uart - - nvidia,tegra210-uart + - nvidia,tegra234-uart - const: nvidia,tegra20-uart reg: -- GitLab From 5cda3b25cb04222988786ebebe346a7655bde05a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:34 +0100 Subject: [PATCH 796/965] dt-bindings: tegra: pmc: Convert to json-schema Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------ .../arm/tegra/nvidia,tegra186-pmc.yaml | 198 ++++++++++++++++++ 2 files changed, 198 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 576462fae27f5..0000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,133 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 - - "nvidia,tegra234-pmc": for Tegra234 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194 and later) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -Pad configurations are described with pin configuration nodes which -are placed under the pmc node and they are referred to by the pinctrl -client properties. For more information see -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - -The following pads are present on Tegra186: -csia csib dsi mipi-bias -pex-clk-bias pex-clk3 pex-clk2 pex-clk1 -usb0 usb1 usb2 usb-bias -uart audio hsic dbg -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv -sdmmc4 cam dsib dsic -dsid csic csid csie -dsif spi ufs dmic-hv -edp sdmmc1-hv sdmmc3-hv conn -audio-hv ao-hv - -Required pin configuration properties: - - pins: A list of strings, each of which contains the name of a pad - to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the above pads except - for ao-hv. Following pads have software configurable signaling - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, - ao-hv. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@3400000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - - ... - - sor0: sor@15540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml new file mode 100644 index 0000000000000..0faa403f68c87 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + enum: + - nvidia,tegra186-pmc + - nvidia,tegra194-pmc + - nvidia,tegra234-pmc + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + items: + - const: pmc + - const: wake + - const: aotag + - const: scratch + - const: misc + + interrupt-controller: true + + "#interrupt-cells": + description: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + const: 2 + + nvidia,invert-interrupt: + description: If present, inverts the PMU interrupt signal. + $ref: /schemas/types.yaml#/definitions/flag + +if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc +then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 +else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + +patternProperties: + "^[a-z0-9]+-[a-z0-9]+$": + if: + type: object + then: + description: | + These are pad configuration nodes. On Tegra SoCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power + state and signaling voltage. A pad can be either in active or + power down mode. The support for power state and signaling voltage + configuration varies depending on the pad in question. 3.3 V and + 1.8 V signaling voltages are supported on pins where software + controllable signaling voltage switching is available. + + Pad configurations are described with pin configuration nodes + which are placed under the pmc node and they are referred to by + the pinctrl client properties. For more information see + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The following pads are present on Tegra186: + + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv + + The following pads are present on Tegra194: + + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, + audio-hv, ao-hv + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain the name of the pad(s) to be + configured. + + low-power-enable: + description: Configure the pad into power down mode. + $ref: /schemas/types.yaml#/definitions/flag + + low-power-disable: + description: Configure the pad into active mode. + $ref: /schemas/types.yaml#/definitions/flag + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling + voltages. + + The values are defined in + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + The power state can be configured on all of the above pads + except for ao-hv. Following pads have software configurable + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, + audio-hv, ao-hv. + + phandle: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +dependencies: + interrupt-controller: ['#interrupt-cells'] + "#interrupt-cells": + required: + - interrupt-controller + +examples: + - | + #include + #include + #include + #include + #include + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + nvidia,invert-interrupt; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + }; + + sdmmc1: mmc@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; -- GitLab From d289f9de8b952bac7805c82d3f9dfd6440f62c8c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:35 +0100 Subject: [PATCH 797/965] dt-bindings: firmware: tegra: Convert to json-schema Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../firmware/nvidia,tegra186-bpmp.txt | 107 ---------- .../firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++++++++ 2 files changed, 186 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index e44a13bc06ed0..0000000000000 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- -- ../power/power-domain.yaml -- -- .../reset/reset.txt -- - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml new file mode 100644 index 0000000000000..833c07f1685ca --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The BPMP is a specific processor in Tegra chip, which is designed for + booting process handling and offloading the power management, clock + management, and reset control tasks from the CPU. The binding document + defines the resources that would be used by the BPMP firmware driver, + which can create the interprocessor communication (IPC) between the + CPU and BPMP. + + This node is a mailbox consumer. See the following files for details + of the mailbox subsystem, and the specifiers implemented by the + relevant provider(s): + + - .../mailbox/mailbox.txt + - .../mailbox/nvidia,tegra186-hsp.yaml + + This node is a clock, power domain, and reset provider. See the + following files for general documentation of those features, and the + specifiers implemented by this node: + + - .../clock/clock-bindings.txt + - + - ../power/power-domain.yaml + - + - .../reset/reset.txt + - + + The BPMP implements some services which must be represented by + separate nodes. For example, it can provide access to certain I2C + controllers, and the I2C bindings represent each I2C controller as a + device tree node. Such nodes should be nested directly inside the main + BPMP node. + + Software can determine whether a child node of the BPMP node + represents a device by checking for a compatible property. Any node + with a compatible property represents a device that can be + instantiated. Nodes without a compatible property may be used to + provide configuration information regarding the BPMP itself, although + no such configuration nodes are currently defined by this binding. + + The BPMP firmware defines no single global name-/numbering-space for + such services. Put another way, the numbering scheme for I2C buses is + distinct from the numbering scheme for any other service the BPMP may + provide (e.g. a future hypothetical SPI bus service). As such, child + device nodes will have no reg property, and the BPMP node will have no + "#address-cells" or "#size-cells" property. + + The shared memory area for the IPC TX and RX between CPU and BPMP are + predefined and work on top of sysram, which is an SRAM inside the + chip. See ".../sram/sram.yaml" for the bindings. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra194-bpmp + - nvidia,tegra234-bpmp + - const: nvidia,tegra186-bpmp + - const: nvidia,tegra186-bpmp + + mboxes: + description: A phandle and channel specifier for the mailbox used to + communicate with the BPMP. + maxItems: 1 + + shmem: + description: List of the phandle to the TX and RX shared memory area + that the IPC between CPU and BPMP is based on. + minItems: 2 + maxItems: 2 + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + - description: DMA read client + - description: DMA write client + + interconnect-names: + items: + - const: read + - const: write + - const: dma-mem # dma-read + - const: dma-write + + iommus: + maxItems: 1 + + i2c: + type: object + + thermal: + type: object + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + - "#clock-cells" + - "#power-domain-cells" + - "#reset-cells" + +examples: + - | + #include + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + sram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x30000000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000000 0x50000>; + + cpu_bpmp_tx: sram@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: sram@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; -- GitLab From a12e1b7812ff81236732abf0f361d59c32890f9a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:37 +0100 Subject: [PATCH 798/965] dt-bindings: thermal: tegra186-bpmp: Convert to json-schema Convert the Tegra186 (and later) BPMP thermal device tree bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 --------------- .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt deleted file mode 100644 index fc87f6aa1b8f5..0000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ /dev/null @@ -1,33 +0,0 @@ -NVIDIA Tegra186 BPMP thermal sensor - -In Tegra186, the BPMP (Boot and Power Management Processor) implements an -interface that is used to read system temperatures, including CPU cluster -and GPU temperatures. This binding describes the thermal sensor that is -exposed by BPMP. - -The BPMP thermal node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the -core thermal binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-thermal" - - "nvidia,tegra194-bpmp-thermal" -- #thermal-sensor-cells: Cell for sensor index. - Single-cell integer. - Must be <1>. - -Example: - -bpmp { - ... - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml new file mode 100644 index 0000000000000..c91fd07e4061d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) BPMP thermal sensor + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + In Tegra186, the BPMP (Boot and Power Management Processor) implements + an interface that is used to read system temperatures, including CPU + cluster and GPU temperatures. This binding describes the thermal + sensor that is exposed by BPMP. + + The BPMP thermal node must be located directly inside the main BPMP + node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the + BPMP binding. + + This node represents a thermal sensor. See + + Documentation/devicetree/bindings/thermal/thermal-sensor.yaml + + for details of the core thermal binding. + +properties: + compatible: + enum: + - nvidia,tegra186-bpmp-thermal + - nvidia,tegra194-bpmp-thermal + + '#thermal-sensor-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of cells needed in the phandle specifier to + identify a given sensor. Must be 1 and the single cell specifies + the sensor index. + const: 1 + +additionalProperties: false -- GitLab From 8461fe3e443b28dc44773c98c642d094caa1976d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:38 +0100 Subject: [PATCH 799/965] dt-bindings: serial: tegra-tcu: Convert to json-schema Convert the Tegra TCU device tree bindings to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------ .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt deleted file mode 100644 index 085a8591accd6..0000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt +++ /dev/null @@ -1,35 +0,0 @@ -NVIDIA Tegra Combined UART (TCU) - -The TCU is a system for sharing a hardware UART instance among multiple -systems within the Tegra SoC. It is implemented through a mailbox- -based protocol where each "virtual UART" has a pair of mailboxes, one -for transmitting and one for receiving, that is used to communicate -with the hardware implementing the TCU. - -Required properties: -- name : Should be tcu -- compatible - Array of strings - One of: - - "nvidia,tegra194-tcu" -- mbox-names: - "rx" - Mailbox for receiving data from hardware UART - "tx" - Mailbox for transmitting data to hardware UART -- mboxes: Mailboxes corresponding to the mbox-names. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -Example bindings: ------------------ - -tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; - mbox-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml new file mode 100644 index 0000000000000..7987eca0bb526 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Combined UART (TCU) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: + The TCU is a system for sharing a hardware UART instance among multiple + systems within the Tegra SoC. It is implemented through a mailbox- + based protocol where each "virtual UART" has a pair of mailboxes, one + for transmitting and one for receiving, that is used to communicate + with the hardware implementing the TCU. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + const: nvidia,tegra194-tcu + + mbox-names: + items: + - const: rx + - const: tx + + mboxes: + description: | + List of phandles to mailbox channels used for receiving and + transmitting data from and to the hardware UART. + items: + - description: mailbox for receiving data from hardware UART + - description: mailbox for transmitting data to hardware UART + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include + + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; -- GitLab From cd1fe47862c71994390e810182785a4f4d371875 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:39 +0100 Subject: [PATCH 800/965] dt-bindings: serial: Document Tegra234 TCU Add the compatible string for the TCU found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml index 7987eca0bb526..e2d111b3e0b01 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -22,7 +22,12 @@ properties: pattern: "^serial(@.*)?$" compatible: - const: nvidia,tegra194-tcu + oneOf: + - const: nvidia,tegra194-tcu + - items: + - enum: + - nvidia,tegra234-tcu + - const: nvidia,tegra194-tcu mbox-names: items: -- GitLab From a90901a5a373b364d1495dbd853d31f391c021a8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 16:55:59 +0100 Subject: [PATCH 801/965] dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties Add the interconnects, interconnect-names and iommus properties to the device tree bindings for the Tegra XUDC controller. These are used to describe the device's paths to and from memory. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index 8428415896ce5..a39c76b894849 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -59,6 +59,19 @@ properties: - const: fs_src - const: hs_src + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + power-domains: items: - description: XUSBB(device) power-domain -- GitLab From b58db7135a1279ca77db9444701dbee02fa29fb7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:45 +0300 Subject: [PATCH 802/965] dt-bindings: ARM: tegra: Document ASUS Transformers Document Tegra20/30/114-based ASUS Transformer Series tablet devices. This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG Infinity TF700T, TF701T. Signed-off-by: David Heidelberg Signed-off-by: Anton Bambura Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 3bd0920da2744..64b7b770a0dca 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,6 +36,9 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 + - items: + - const: asus,tf101 + - const: nvidia,tegra20 - items: - const: acer,picasso - const: nvidia,tegra20 @@ -49,6 +52,18 @@ properties: - nvidia,cardhu-a04 - const: nvidia,cardhu - const: nvidia,tegra30 + - items: + - const: asus,tf201 + - const: nvidia,tegra30 + - items: + - const: asus,tf300t + - const: nvidia,tegra30 + - items: + - const: asus,tf300tg + - const: nvidia,tegra30 + - items: + - const: asus,tf700t + - const: nvidia,tegra30 - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 @@ -76,6 +91,7 @@ properties: - const: nvidia,tegra30 - items: - enum: + - asus,tf701t - nvidia,dalmore - nvidia,roth - nvidia,tn7 -- GitLab From f64de71a9383457345ca6cd653c02f5b80a695e3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:13:46 +0300 Subject: [PATCH 803/965] dt-bindings: ARM: tegra: Document Pegatron Chagall Document Pegatron Chagall, which is Tegra30-based tablet device. Acked-by: Rob Herring Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 64b7b770a0dca..49841ca272ee9 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -89,6 +89,9 @@ properties: - items: - const: ouya,ouya - const: nvidia,tegra30 + - items: + - const: pegatron,chagall + - const: nvidia,tegra30 - items: - enum: - asus,tf701t -- GitLab From d0e70d13048419913c4723793c9f600acd861b36 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:11 +0300 Subject: [PATCH 804/965] dt-bindings: clock: tegra-car: Document new clock sub-nodes Document sub-nodes which describe Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher clock rates. Each node contains a phandle to OPP table and power domain. The root PLLs and system clocks don't have any specific device dedicated to them, clock controller is in charge of managing power for them. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra20-car.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml index 459d2a5253935..f832abb7f11ae 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -42,6 +42,36 @@ properties: "#reset-cells": const: 1 +patternProperties: + "^(sclk)|(pll-[cem])$": + type: object + properties: + compatible: + enum: + - nvidia,tegra20-sclk + - nvidia,tegra30-sclk + - nvidia,tegra30-pllc + - nvidia,tegra30-plle + - nvidia,tegra30-pllm + + operating-points-v2: true + + clocks: + items: + - description: node's clock + + power-domains: + maxItems: 1 + description: phandle to the core SoC power domain + + required: + - compatible + - operating-points-v2 + - clocks + - power-domains + + additionalProperties: false + required: - compatible - reg @@ -59,6 +89,13 @@ examples: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + operating-points-v2 = <&opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&domain>; + }; }; usb-controller@c5004000 { -- GitLab From 425a68a963698867a9b6a8d82fcd41354a01f0ab Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:13 +0300 Subject: [PATCH 805/965] dt-bindings: host1x: Document OPP and power domain properties Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-host1x.txt | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee306a..62861a8fb5c68 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +303,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +335,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +439,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +454,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +464,7 @@ Example: interrupts = ; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +546,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +566,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +576,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +589,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +615,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +642,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +651,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +663,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; -- GitLab From 0c41e287f7541aee58c5a0c4437524fbdbf63bd9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:14 +0300 Subject: [PATCH 806/965] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 62861a8fb5c68..e61999ce54e96 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -19,6 +19,7 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - host1x + - mc Optional properties: - operating-points-v2: See ../bindings/opp/opp.txt for details. @@ -198,6 +199,7 @@ of the following host1x client modules: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 2d + - mc Optional properties: - interconnects: Must contain entry for the GR2D memory clients. @@ -224,6 +226,8 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + - mc + - mc2 (Only required on SoCs with two 3D clocks) Optional properties: - interconnects: Must contain entry for the GR3D memory clients. -- GitLab From ccc3016261edc37d66123946ede157f8c22205da Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:32 +0300 Subject: [PATCH 807/965] media: dt: bindings: tegra-vde: Convert to schema Convert NVIDIA Tegra video decoder binding to schema. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/media/nvidia,tegra-vde.txt | 64 ----------- .../bindings/media/nvidia,tegra-vde.yaml | 107 ++++++++++++++++++ 2 files changed, 107 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt deleted file mode 100644 index 602169b8aa198..0000000000000 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra Video Decoder Engine - -Required properties: -- compatible : Must contain one of the following values: - - "nvidia,tegra20-vde" - - "nvidia,tegra30-vde" - - "nvidia,tegra114-vde" - - "nvidia,tegra124-vde" - - "nvidia,tegra132-vde" -- reg : Must contain an entry for each entry in reg-names. -- reg-names : Must include the following entries: - - sxe - - bsev - - mbe - - ppe - - mce - - tfe - - ppb - - vdma - - frameid -- iram : Must contain phandle to the mmio-sram device node that represents - IRAM region used by VDE. -- interrupts : Must contain an entry for each entry in interrupt-names. -- interrupt-names : Must include the following entries: - - sync-token - - bsev - - sxe -- clocks : Must include the following entries: - - vde -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Should include the following entries: - - vde - -Optional properties: -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Must include the following entries: - - mc -- iommus: Must contain phandle to the IOMMU device node. - -Example: - -video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300 /* Video frame controls */>; - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; -}; diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml new file mode 100644 index 0000000000000..c143aaa063468 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Decoder Engine + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra132-vde + - nvidia,tegra124-vde + - nvidia,tegra114-vde + - items: + - const: nvidia,tegra30-vde + - const: nvidia,tegra20-vde + - items: + - const: nvidia,tegra20-vde + + reg: + maxItems: 9 + + reg-names: + items: + - const: sxe + - const: bsev + - const: mbe + - const: ppe + - const: mce + - const: tfe + - const: ppb + - const: vdma + - const: frameid + + clocks: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: vde + - const: mc + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: sync-token + - const: bsev + - const: sxe + + iommus: + maxItems: 1 + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the SRAM MMIO node. + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - reset-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x300>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&iram>; /* IRAM MMIO region */ + interrupts = <0 9 4>, /* Sync token */ + <0 10 4>, /* BSE-V */ + <0 12 4>; /* SXE */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&clk 61>; + reset-names = "vde", "mc"; + resets = <&rst 61>, <&mem 13>; + iommus = <&mem 15>; + }; -- GitLab From c9059a6bb993db31cd85f3a4081766af9e61be40 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:33 +0300 Subject: [PATCH 808/965] media: dt: bindings: tegra-vde: Document OPP and power domain Document new OPP table and power domain properties of the video decoder hardware. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml index c143aaa063468..4ecdee1be37e7 100644 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -68,6 +68,16 @@ properties: description: Phandle of the SRAM MMIO node. + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, + which is a bitfield indicating SoC speedo or process ID mask. + + power-domains: + maxItems: 1 + description: + Phandle to the SoC core power domain. + required: - compatible - reg @@ -104,4 +114,6 @@ examples: reset-names = "vde", "mc"; resets = <&rst 61>, <&mem 13>; iommus = <&mem 15>; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; -- GitLab From 914ed1f56581f99094035f1cc989ab4498104e94 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:53:08 +0100 Subject: [PATCH 809/965] arm64: tegra: Add host1x hotflush reset on Tegra210 Add the host1x memory client hotflush reset on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index aa768ea108fec..218a2b32200f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -93,8 +93,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA210_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; + reset-names = "host1x", "mc"; #address-cells = <2>; #size-cells = <2>; -- GitLab From dd73d18e7fc7adc7e70711ff2c92373ce8862c3f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 17 Dec 2021 16:20:45 +0000 Subject: [PATCH 810/965] arm64: Ensure that the 'bti' macro is defined where linkage.h is included Not all .S files include asm/assembler.h, however the SYM_FUNC_* definitions invoke the 'bti' macro. Include asm/assembler.h in asm/linkage.h. Fixes: 9be34be87cc8 ("arm64: Add macro version of the BTI instruction") Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/linkage.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/linkage.h b/arch/arm64/include/asm/linkage.h index 9065e4749b42a..b77e9b3f5371c 100644 --- a/arch/arm64/include/asm/linkage.h +++ b/arch/arm64/include/asm/linkage.h @@ -1,6 +1,10 @@ #ifndef __ASM_LINKAGE_H #define __ASM_LINKAGE_H +#ifdef __ASSEMBLY__ +#include +#endif + #define __ALIGN .align 2 #define __ALIGN_STR ".align 2" -- GitLab From 3b2e5d74e25fe6aae6e9427cdbdc2d82586ddc16 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 17:37:44 +0200 Subject: [PATCH 811/965] ARM: configs: at91: sama7: Enable SPI NOR and QSPI controller sama7g5ek comes with a SPI NOR flash connected to the QSPI controller. Enable the SPI NOR subsystem and the QSPI controller. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209153744.357465-2-tudor.ambarus@microchip.com --- arch/arm/configs/sama7_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 938aae4bd80bf..0368068e04d96 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -33,7 +33,6 @@ CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_EFI_PARTITION is not set # CONFIG_COREDUMP is not set @@ -83,6 +82,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_NETDEVICES=y CONFIG_MACB=y CONFIG_MICREL_PHY=y @@ -104,8 +105,8 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_AT91=y CONFIG_SPI=y -CONFIG_SPI_MEM=y CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y CONFIG_SPI_GPIO=y CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91PIO4=y -- GitLab From e1137bcefa025ec4c583e85d6c86c9ba11133224 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 15 Dec 2021 15:43:11 +0200 Subject: [PATCH 812/965] ARM: configs: at91: Enable crypto software implementations Enable at least the same amount of algs as the hardware IPs are supporting so that they are able to fallback to the software implementations in case they need it. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211215134311.304427-1-tudor.ambarus@microchip.com --- arch/arm/configs/at91_dt_defconfig | 9 ++++++++- arch/arm/configs/sama5_defconfig | 8 ++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index a6310c8abcc3e..549d01be0b474 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -216,7 +216,14 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y -CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index fe0d7ccc8fb24..03dd80c2a19e0 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -232,6 +232,14 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y -- GitLab From 572a0a647b9b491729d24c083c8410c55bf16326 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Sat, 4 Dec 2021 22:23:55 +0200 Subject: [PATCH 813/965] selftests/sgx: Fix corrupted cpuid macro invocation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SGX selftest fails to build on tip/x86/sgx: main.c: In function ‘get_total_epc_mem’: main.c:296:17: error: implicit declaration of function ‘__cpuid’ [-Werror=implicit-function-declaration] 296 | __cpuid(&eax, &ebx, &ecx, &edx); | ^~~~~~~ Include cpuid.h and use __cpuid_count() macro in order to fix the compilation issue. [ dhansen: tweak commit message ] Fixes: f0ff2447b861 ("selftests/sgx: Add a new kselftest: Unclobbered_vdso_oversubscribed") Signed-off-by: Jarkko Sakkinen Signed-off-by: Dave Hansen Acked-by: Reinette Chatre Link: https://lkml.kernel.org/r/20211204202355.23005-1-jarkko@kernel.org Cc: Shuah Khan --- tools/testing/selftests/sgx/main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/sgx/main.c b/tools/testing/selftests/sgx/main.c index 7e912db4c6c5e..370c4995f7c4a 100644 --- a/tools/testing/selftests/sgx/main.c +++ b/tools/testing/selftests/sgx/main.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2016-20 Intel Corporation. */ +#include #include #include #include @@ -291,9 +292,7 @@ static unsigned long get_total_epc_mem(void) int section = 0; while (true) { - eax = SGX_CPUID; - ecx = section + SGX_CPUID_EPC; - __cpuid(&eax, &ebx, &ecx, &edx); + __cpuid_count(SGX_CPUID, section + SGX_CPUID_EPC, eax, ebx, ecx, edx); type = eax & SGX_CPUID_EPC_MASK; if (type == SGX_CPUID_EPC_INVALID) -- GitLab From 1f1cb308abc5272551b7db9c0d31733478f829bf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 6 Dec 2021 11:56:17 +1300 Subject: [PATCH 814/965] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a number of the peripheral devices to function. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 505ae69289f6d..c491e33794054 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -17,6 +17,8 @@ ethernet0 = &cp0_eth0; ethernet1 = &cp0_eth1; ethernet2 = &cp0_eth2; + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; }; memory@0 { @@ -114,6 +116,14 @@ }; }; +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; + &cp0_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&cp0_i2c0_pins>; -- GitLab From 35d544a273eafc3d00074973771ebaa7e358d0fd Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 6 Dec 2021 11:56:18 +1300 Subject: [PATCH 815/965] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add the necessary dts nodes and properties for this. Signed-off-by: Chris Packham Reviewed-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 130 ++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index c491e33794054..d9f9f2c197408 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -73,6 +73,17 @@ enable-active-high; regulator-always-on; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&cp0_i2c1>; + mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>; + los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + status = "okay"; + }; }; &uart0 { @@ -195,6 +206,125 @@ phy0: ethernet-phy@0 { reg = <0>; }; + + switch6: switch0@6 { + /* Actual device is MV88E6393X */ + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + interrupt-parent = <&cp0_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "p1"; + phy-handle = <&switch0phy1>; + }; + + port@2 { + reg = <2>; + label = "p2"; + phy-handle = <&switch0phy2>; + }; + + port@3 { + reg = <3>; + label = "p3"; + phy-handle = <&switch0phy3>; + }; + + port@4 { + reg = <4>; + label = "p4"; + phy-handle = <&switch0phy4>; + }; + + port@5 { + reg = <5>; + label = "p5"; + phy-handle = <&switch0phy5>; + }; + + port@6 { + reg = <6>; + label = "p6"; + phy-handle = <&switch0phy6>; + }; + + port@7 { + reg = <7>; + label = "p7"; + phy-handle = <&switch0phy7>; + }; + + port@8 { + reg = <8>; + label = "p8"; + phy-handle = <&switch0phy8>; + }; + + port@9 { + reg = <9>; + label = "p9"; + phy-mode = "10gbase-r"; + sfp = <&sfp>; + managed = "in-band-status"; + }; + + port@a { + reg = <10>; + label = "cpu"; + ethernet = <&cp0_eth0>; + }; + + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: switch0phy1@1 { + reg = <0x1>; + }; + + switch0phy2: switch0phy2@2 { + reg = <0x2>; + }; + + switch0phy3: switch0phy3@3 { + reg = <0x3>; + }; + + switch0phy4: switch0phy4@4 { + reg = <0x4>; + }; + + switch0phy5: switch0phy5@5 { + reg = <0x5>; + }; + + switch0phy6: switch0phy6@6 { + reg = <0x6>; + }; + + switch0phy7: switch0phy7@7 { + reg = <0x7>; + }; + + switch0phy8: switch0phy8@8 { + reg = <0x8>; + }; + }; + }; }; &cp0_xmdio { -- GitLab From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 8 Dec 2021 03:40:35 +0100 Subject: [PATCH 816/965] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the reference xtal clock. So add missing xtal clock source into comphy device tree node. If the property is not present, the driver defaults to 25 MHz xtal rate (which, as far as we know, is used by all the existing boards). Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 9acc5d2b5a002..673f4906eef90 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -265,6 +265,8 @@ "lane2_sata_usb3"; #address-cells = <1>; #size-cells = <0>; + clocks = <&xtalclk>; + clock-names = "xtal"; comphy0: phy@0 { reg = <0>; -- GitLab From effd42600b987c1e95f946b14fefc1c7639e7439 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 12 Nov 2021 14:44:02 +0100 Subject: [PATCH 817/965] arm64: dts: marvell: cn9130: add GPIO and SPI aliases CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI controllers built-in. However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required aliases as both the Orion SPI driver and MVEBU GPIO drivers require the aliases to be present. So add the required aliases for GPIO and SPI controllers. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi index a2b7e5ec979d3..71769ac7f0585 100644 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -11,6 +11,13 @@ model = "Marvell Armada CN9130 SoC"; compatible = "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + aliases { + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; + }; }; /* -- GitLab From 0734f8311ce72c9041e5142769eff2083889c172 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 12 Nov 2021 14:44:03 +0100 Subject: [PATCH 818/965] arm64: dts: marvell: cn9130: enable CP0 GPIO controllers CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in Armada 7k and 8k both are left disabled by the SoC DTSI. This first of all makes no sense as they are always present due to being SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2 pins for regulators and SD card support without enabling them first. So, enable both of them like Armada 7k and 8k do. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi index 71769ac7f0585..327b04134134f 100644 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -42,3 +42,11 @@ #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE #undef CP11X_PCIE2_BASE + +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; -- GitLab From 62480772263ab6b52e758f2346c70a526abd1d28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 9 Nov 2021 17:46:04 +0100 Subject: [PATCH 819/965] ARM: dts: armada-38x: Add generic compatible to UART nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic compatible string "ns16550a" to serial port nodes of Armada 38x. This makes it possible to use earlycon. Fixes: 0d3d96ab0059 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 9b1a24cc5e91f..df3c8d1d8f641 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -168,7 +168,7 @@ }; uart0: serial@12000 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = ; @@ -178,7 +178,7 @@ }; uart1: serial@12100 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = ; -- GitLab From 0706a78f31c4217ca144f630063ec9561a21548d Mon Sep 17 00:00:00 2001 From: Magnus Karlsson Date: Fri, 17 Dec 2021 15:56:46 +0100 Subject: [PATCH 820/965] Revert "xsk: Do not sleep in poll() when need_wakeup set" This reverts commit bd0687c18e635b63233dc87f38058cd728802ab4. This patch causes a Tx only workload to go to sleep even when it does not have to, leading to misserable performance in skb mode. It fixed one rare problem but created a much worse one, so this need to be reverted while I try to craft a proper solution to the original problem. Fixes: bd0687c18e63 ("xsk: Do not sleep in poll() when need_wakeup set") Signed-off-by: Magnus Karlsson Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20211217145646.26449-1-magnus.karlsson@gmail.com --- net/xdp/xsk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c index 7a466ea962c57..f16074eb53c72 100644 --- a/net/xdp/xsk.c +++ b/net/xdp/xsk.c @@ -677,6 +677,8 @@ static __poll_t xsk_poll(struct file *file, struct socket *sock, struct xdp_sock *xs = xdp_sk(sk); struct xsk_buff_pool *pool; + sock_poll_wait(file, sock, wait); + if (unlikely(!xsk_is_bound(xs))) return mask; @@ -688,8 +690,6 @@ static __poll_t xsk_poll(struct file *file, struct socket *sock, else /* Poll needs to drive Tx also in copy mode */ __xsk_sendmsg(sk); - } else { - sock_poll_wait(file, sock, wait); } if (xs->rx && !xskq_prod_is_empty(xs->rx)) -- GitLab From 819d11507f6637731947836e6308f5966d64cf9d Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 17 Dec 2021 18:24:00 +0000 Subject: [PATCH 821/965] bpf, selftests: Fix spelling mistake "tained" -> "tainted" There appears to be a spelling mistake in a bpf test message. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20211217182400.39296-1-colin.i.king@gmail.com --- tools/testing/selftests/bpf/verifier/value_ptr_arith.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/bpf/verifier/value_ptr_arith.c b/tools/testing/selftests/bpf/verifier/value_ptr_arith.c index 4d347bc53aa28..359f3e8f8b604 100644 --- a/tools/testing/selftests/bpf/verifier/value_ptr_arith.c +++ b/tools/testing/selftests/bpf/verifier/value_ptr_arith.c @@ -1078,7 +1078,7 @@ .errstr_unpriv = "R0 pointer -= pointer prohibited", }, { - "map access: trying to leak tained dst reg", + "map access: trying to leak tainted dst reg", .insns = { BPF_MOV64_IMM(BPF_REG_0, 0), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), -- GitLab From b603377e408fb41dbb0971635c57e123edbb5bf8 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 21:57:54 +0200 Subject: [PATCH 822/965] soc: samsung: Add USI driver USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204195757.8600-3-semen.protsenko@linaro.org Tested-by: Chanho Park Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/Kconfig | 14 ++ drivers/soc/samsung/Makefile | 2 + drivers/soc/samsung/exynos-usi.c | 285 +++++++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/soc/samsung/exynos-usi.c diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index e2cedef1e8d16..a9f8b224322e4 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -23,6 +23,20 @@ config EXYNOS_CHIPID Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. This driver can also be built as module (exynos_chipid). +config EXYNOS_USI + tristate "Exynos USI (Universal Serial Interface) driver" + default ARCH_EXYNOS && ARM64 + depends on ARCH_EXYNOS || COMPILE_TEST + select MFD_SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV0. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + config EXYNOS_PMU bool "Exynos PMU controller driver" if COMPILE_TEST depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST) diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 2ae4bea804cf0..9f59d1905ab01 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -4,6 +4,8 @@ obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o exynos_chipid-y += exynos-chipid.o exynos-asv.o +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o + obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index 0000000000000..114352695ac2b --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* USIv2: System Register: SW_CONF register bits */ +#define USI_V2_SW_CONF_NONE 0x0 +#define USI_V2_SW_CONF_UART BIT(0) +#define USI_V2_SW_CONF_SPI BIT(1) +#define USI_V2_SW_CONF_I2C BIT(2) +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \ + USI_V2_SW_CONF_I2C) + +/* USIv2: USI register offsets */ +#define USI_CON 0x04 +#define USI_OPTION 0x08 + +/* USIv2: USI register bits */ +#define USI_CON_RESET BIT(0) +#define USI_OPTION_CLKREQ_ON BIT(1) +#define USI_OPTION_CLKSTOP_ON BIT(2) + +enum exynos_usi_ver { + USI_VER2 = 2, +}; + +struct exynos_usi_variant { + enum exynos_usi_ver ver; /* USI IP-core version */ + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */ + size_t min_mode; /* first index in exynos_usi_modes[] */ + size_t max_mode; /* last index in exynos_usi_modes[] */ + size_t num_clks; /* number of clocks to assert */ + const char * const *clk_names; /* clock names to assert */ +}; + +struct exynos_usi { + struct device *dev; + void __iomem *regs; /* USI register map */ + struct clk_bulk_data *clks; /* USI clocks */ + + size_t mode; /* current USI SW_CONF mode index */ + bool clkreq_on; /* always provide clock to IP */ + + /* System Register */ + struct regmap *sysreg; /* System Register map */ + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ + + const struct exynos_usi_variant *data; +}; + +struct exynos_usi_mode { + const char *name; /* mode name */ + unsigned int val; /* mode register value */ +}; + +static const struct exynos_usi_mode exynos_usi_modes[] = { + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, +}; + +static const char * const exynos850_usi_clk_names[] = { "pclk", "ipclk" }; +static const struct exynos_usi_variant exynos850_usi_data = { + .ver = USI_VER2, + .sw_conf_mask = USI_V2_SW_CONF_MASK, + .min_mode = USI_V2_NONE, + .max_mode = USI_V2_I2C, + .num_clks = ARRAY_SIZE(exynos850_usi_clk_names), + .clk_names = exynos850_usi_clk_names, +}; + +static const struct of_device_id exynos_usi_dt_match[] = { + { + .compatible = "samsung,exynos850-usi", + .data = &exynos850_usi_data, + }, + { } /* sentinel */ +}; +MODULE_DEVICE_TABLE(of, exynos_usi_dt_match); + +/** + * exynos_usi_set_sw_conf - Set USI block configuration mode + * @usi: USI driver object + * @mode: Mode index + * + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. + * + * Return: 0 on success, or negative error code on failure. + */ +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) +{ + unsigned int val; + int ret; + + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + + val = exynos_usi_modes[mode].val; + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, + usi->data->sw_conf_mask, val); + if (ret) + return ret; + + usi->mode = mode; + dev_dbg(usi->dev, "protocol: %s\n", exynos_usi_modes[usi->mode].name); + + return 0; +} + +/** + * exynos_usi_enable - Initialize USI block + * @usi: USI driver object + * + * USI IP-core start state is "reset" (on startup and after CPU resume). This + * routine enables the USI block by clearing the reset flag. It also configures + * HWACG behavior (needed e.g. for UART Rx). It should be performed before + * underlying protocol becomes functional. + * + * Return: 0 on success, or negative error code on failure. + */ +static int exynos_usi_enable(const struct exynos_usi *usi) +{ + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(usi->data->num_clks, usi->clks); + if (ret) + return ret; + + /* Enable USI block */ + val = readl(usi->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, usi->regs + USI_CON); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating */ + if (usi->clkreq_on) { + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKSTOP_ON; + val |= USI_OPTION_CLKREQ_ON; + writel(val, usi->regs + USI_OPTION); + } + + clk_bulk_disable_unprepare(usi->data->num_clks, usi->clks); + + return ret; +} + +static int exynos_usi_configure(struct exynos_usi *usi) +{ + int ret; + + ret = exynos_usi_set_sw_conf(usi, usi->mode); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) + return exynos_usi_enable(usi); + + return 0; +} + +static int exynos_usi_parse_dt(struct device_node *np, struct exynos_usi *usi) +{ + int ret; + u32 mode; + + ret = of_property_read_u32(np, "samsung,mode", &mode); + if (ret) + return ret; + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + usi->mode = mode; + + usi->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); + if (IS_ERR(usi->sysreg)) + return PTR_ERR(usi->sysreg); + + ret = of_property_read_u32_index(np, "samsung,sysreg", 1, + &usi->sw_conf); + if (ret) + return ret; + + usi->clkreq_on = of_property_read_bool(np, "samsung,clkreq-on"); + + return 0; +} + +static int exynos_usi_get_clocks(struct exynos_usi *usi) +{ + const size_t num = usi->data->num_clks; + struct device *dev = usi->dev; + size_t i; + + if (num == 0) + return 0; + + usi->clks = devm_kcalloc(dev, num, sizeof(*usi->clks), GFP_KERNEL); + if (!usi->clks) + return -ENOMEM; + + for (i = 0; i < num; ++i) + usi->clks[i].id = usi->data->clk_names[i]; + + return devm_clk_bulk_get(dev, num, usi->clks); +} + +static int exynos_usi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct exynos_usi *usi; + int ret; + + usi = devm_kzalloc(dev, sizeof(*usi), GFP_KERNEL); + if (!usi) + return -ENOMEM; + + usi->dev = dev; + platform_set_drvdata(pdev, usi); + + usi->data = of_device_get_match_data(dev); + if (!usi->data) + return -EINVAL; + + ret = exynos_usi_parse_dt(np, usi); + if (ret) + return ret; + + ret = exynos_usi_get_clocks(usi); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) { + usi->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(usi->regs)) + return PTR_ERR(usi->regs); + } + + ret = exynos_usi_configure(usi); + if (ret) + return ret; + + /* Make it possible to embed protocol nodes into USI np */ + return of_platform_populate(np, NULL, NULL, dev); +} + +static int __maybe_unused exynos_usi_resume_noirq(struct device *dev) +{ + struct exynos_usi *usi = dev_get_drvdata(dev); + + return exynos_usi_configure(usi); +} + +static const struct dev_pm_ops exynos_usi_pm = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, exynos_usi_resume_noirq) +}; + +static struct platform_driver exynos_usi_driver = { + .driver = { + .name = "exynos-usi", + .pm = &exynos_usi_pm, + .of_match_table = exynos_usi_dt_match, + }, + .probe = exynos_usi_probe, +}; +module_platform_driver(exynos_usi_driver); + +MODULE_DESCRIPTION("Samsung USI driver"); +MODULE_AUTHOR("Sam Protsenko "); +MODULE_LICENSE("GPL"); -- GitLab From 96c8bddb6cdefb029cc7e411a5ee2183477368ea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 13 Dec 2021 12:20:57 +0100 Subject: [PATCH 823/965] dt-bindings: soc: samsung: keep SoC driver bindings together Recently added Samsung Exynos USI driver devicetree bindings were added under ../bindings/soc/samsung/exynos-usi.yaml, so move there also two other bindings for Exynos SoC drivers: the PMU and ChipID. Update Samsung Exynos MAINTAINERS entry to include this new path. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211213112057.16709-1-krzysztof.kozlowski@canonical.com --- .../devicetree/bindings/{arm => soc}/samsung/exynos-chipid.yaml | 2 +- .../{arm/samsung/pmu.yaml => soc/samsung/exynos-pmu.yaml} | 2 +- MAINTAINERS | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{arm => soc}/samsung/exynos-chipid.yaml (93%) rename Documentation/devicetree/bindings/{arm/samsung/pmu.yaml => soc/samsung/exynos-pmu.yaml} (97%) diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-chipid.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml rename to Documentation/devicetree/bindings/soc/samsung/exynos-chipid.yaml index bfc352a2fdd66..4bb8efb83ac15 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-chipid.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml# +$id: http://devicetree.org/schemas/soc/samsung/exynos-chipid.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos SoC series Chipid driver diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml similarity index 97% rename from Documentation/devicetree/bindings/arm/samsung/pmu.yaml rename to Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 0bbd89265b28c..c30a6437030d7 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml# +$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos SoC series Power Management Unit (PMU) diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce85213..bdab70cad1970 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2542,6 +2542,7 @@ Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/ F: Documentation/arm/samsung/ F: Documentation/devicetree/bindings/arm/samsung/ F: Documentation/devicetree/bindings/power/pd-samsung.yaml +F: Documentation/devicetree/bindings/soc/samsung/ F: arch/arm/boot/dts/exynos* F: arch/arm/boot/dts/s3c* F: arch/arm/boot/dts/s5p* -- GitLab From eafba51c545a165b29777cde1fc8b04781a0a8db Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 15 Dec 2021 10:44:49 +0100 Subject: [PATCH 824/965] dt-bindings: soc: bcm: Convert brcm,bcm2835-vchiq to json-schema This converts the VCHIQ bindings to YAML format. Signed-off-by: Stefan Wahren Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211215094448.280796-1-nsaenz@kernel.org --- .../bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 17 ------ .../bindings/soc/bcm/brcm,bcm2835-vchiq.yaml | 53 +++++++++++++++++++ 2 files changed, 53 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt deleted file mode 100644 index f331316183f64..0000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ /dev/null @@ -1,17 +0,0 @@ -Broadcom VCHIQ firmware services - -Required properties: - -- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise - "brcm,bcm2836-vchiq". -- reg: Physical base address and length of the doorbell register pair -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Example: - -mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; -}; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml new file mode 100644 index 0000000000000..e04439b3355b2 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom VCHIQ firmware services + +maintainers: + - Nicolas Saenz Julienne + +description: + The VCHIQ communication channel can be provided by BCM283x and Capri SoCs, + to communicate with the VPU-side OS services. + +properties: + compatible: + oneOf: + - description: BCM2835 based boards + items: + - enum: + - brcm,bcm2835-vchiq + + - description: BCM2836/BCM2837 based boards + items: + - enum: + - brcm,bcm2836-vchiq + - const: brcm,bcm2835-vchiq + + reg: + description: Physical base address and length of the doorbell register pair + minItems: 1 + + interrupts: + description: Interrupt number of the doorbell interrupt + minItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + }; + +... -- GitLab From 13391025039fe86c68741e45a8b7bc158c69d68e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:14:13 -0800 Subject: [PATCH 825/965] ARM: dts: Cygnus: Fixed iProc PCIe controller properties Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce106..e73a19409d711 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- GitLab From 89b9492c113c4a22361f32639c6af041bcada2b6 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 16:06:22 -0800 Subject: [PATCH 826/965] ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d711..ad65be8719389 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; -- GitLab From d2b820bb16c509b313b87f616dcf6aa612d01fb9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:15:27 -0800 Subject: [PATCH 827/965] ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a23..33e6ba63a1eee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- GitLab From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:16:27 -0800 Subject: [PATCH 828/965] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa188585..f242763c3bde1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- GitLab From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 10:19:09 -0800 Subject: [PATCH 829/965] ARM: dts: NSP: Rename SATA unit name Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index f242763c3bde1..5b1dc58d40ba2 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; -- GitLab From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 17 Dec 2021 00:03:19 +0800 Subject: [PATCH 830/965] ARM: dts: BCM5301X: correct RX delay and enable flow control on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current 'rx-internal-delay-ps' property value on the Realtek switch node, 2000, will be divided by 300, resulting in 6.66, which will be rounded to the closest step value, 7. Change it to 2100 to be accurate. See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns") for reference. Flow control needs to be enabled on both sides of the internal and external switch. It is already enabled on the CPU port of the Realtek switch so we also enable it on the external switch port of the Broadcom switch as well. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 16dea851719f2..df8199fd4eb46 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -138,7 +138,7 @@ ethernet = <&sw0_p5>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; fixed-link { speed = <1000>; @@ -213,6 +213,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; -- GitLab From 39d02827ed40fd421a758a36264c255d69f5d035 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 16 Dec 2021 19:28:20 +0100 Subject: [PATCH 831/965] s390/crypto: fix compile error for ChaCha20 module The clgfi instruction used within the ChaCha20 assembly is only available for z9-109 and newer machines, and therefore this will generate a compile error if compiled e.g. with MARCH_Z900. Given that the assembler code will only be executed on machines with vector instructions, which became much later available than z9-109, use insn notation to generate the clgfi instruction, and avoid compile errors due to unknown instructions. Fixes: b087dfab4d39 ("s390/crypto: add SIMD implementation for ChaCha20") Reported-by: kernel test robot Reviewed-by: Harald Freudenberger Signed-off-by: Heiko Carstens --- arch/s390/crypto/chacha-s390.S | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/s390/crypto/chacha-s390.S b/arch/s390/crypto/chacha-s390.S index 9b033622191ca..badf5c49717da 100644 --- a/arch/s390/crypto/chacha-s390.S +++ b/arch/s390/crypto/chacha-s390.S @@ -312,7 +312,7 @@ ENTRY(chacha20_vx_4x) VPERM XC0,XC0,XC0,BEPERM VPERM XD0,XD0,XD0,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_4x VLM XT0,XT3,0,INP,0 @@ -339,7 +339,7 @@ ENTRY(chacha20_vx_4x) VPERM XC0,XC0,XC0,BEPERM VPERM XD0,XD0,XD0,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_4x VLM XT0,XT3,0,INP,0 @@ -366,7 +366,7 @@ ENTRY(chacha20_vx_4x) VPERM XC0,XC0,XC0,BEPERM VPERM XD0,XD0,XD0,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_4x VLM XT0,XT3,0,INP,0 @@ -472,7 +472,7 @@ ENDPROC(chacha20_vx_4x) #define T3 %v30 ENTRY(chacha20_vx) - clgfi LEN,256 + .insn rilu,0xc20e00000000,LEN,256 # clgfi LEN,256 jle chacha20_vx_4x stmg %r6,%r7,6*8(SP) @@ -725,7 +725,7 @@ ENTRY(chacha20_vx) VPERM C0,C0,C0,BEPERM VPERM D0,D0,D0,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VAF D2,D2,T2 # +K[3]+2 @@ -754,7 +754,7 @@ ENTRY(chacha20_vx) VPERM C0,C1,C1,BEPERM VPERM D0,D1,D1,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VLM A1,D1,0,INP,0 @@ -780,7 +780,7 @@ ENTRY(chacha20_vx) VPERM C0,C2,C2,BEPERM VPERM D0,D2,D2,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VLM A1,D1,0,INP,0 @@ -807,7 +807,7 @@ ENTRY(chacha20_vx) VPERM C0,C3,C3,BEPERM VPERM D0,D3,D3,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VAF D3,D2,T1 # K[3]+4 @@ -837,7 +837,7 @@ ENTRY(chacha20_vx) VPERM C0,C4,C4,BEPERM VPERM D0,D4,D4,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VLM A1,D1,0,INP,0 @@ -864,7 +864,7 @@ ENTRY(chacha20_vx) VPERM C0,C5,C5,BEPERM VPERM D0,D5,D5,BEPERM - clgfi LEN,0x40 + .insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40 jl .Ltail_vx VLM A1,D1,0,INP,0 -- GitLab From a0e45d40d5f8461aeee9374c0ffa7b1da87c203c Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 16 Dec 2021 13:27:10 +0100 Subject: [PATCH 832/965] s390/crash_dump: fix virtual vs physical address handling Signal processor STORE STATUS requires a physical address where register contents are supposed to be written to, however the kernel must read the data via the corresponding virtual address. Also the allocated save_area, where register contents are copied to, resides in virtual address space. Fix this by using proper __pa() conversion, or correct memblock_alloc() invocation. Reviewed-by: Alexander Gordeev Signed-off-by: Heiko Carstens --- arch/s390/kernel/crash_dump.c | 2 +- arch/s390/kernel/smp.c | 18 +++++++----------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c index 785d54c9350c4..af82021216423 100644 --- a/arch/s390/kernel/crash_dump.c +++ b/arch/s390/kernel/crash_dump.c @@ -60,7 +60,7 @@ struct save_area * __init save_area_alloc(bool is_boot_cpu) { struct save_area *sa; - sa = (void *) memblock_phys_alloc(sizeof(*sa), 8); + sa = memblock_alloc(sizeof(*sa), 8); if (!sa) panic("Failed to allocate save area\n"); diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 1172aaf0b7e21..2bad902d84373 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -658,26 +658,22 @@ int smp_store_status(int cpu) * deactivates the elfcorehdr= kernel parameter */ static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, - bool is_boot_cpu, unsigned long page) + bool is_boot_cpu, __vector128 *vxrs) { - __vector128 *vxrs = (__vector128 *) page; - if (is_boot_cpu) vxrs = boot_cpu_vector_save_area; else - __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); + __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, __pa(vxrs)); save_area_add_vxrs(sa, vxrs); } static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, - bool is_boot_cpu, unsigned long page) + bool is_boot_cpu, void *regs) { - void *regs = (void *) page; - if (is_boot_cpu) copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); else - __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); + __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, __pa(regs)); save_area_add_regs(sa, regs); } @@ -685,14 +681,14 @@ void __init smp_save_dump_cpus(void) { int addr, boot_cpu_addr, max_cpu_addr; struct save_area *sa; - unsigned long page; bool is_boot_cpu; + void *page; if (!(oldmem_data.start || is_ipl_type_dump())) /* No previous system present, normal boot. */ return; /* Allocate a page as dumping area for the store status sigps */ - page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31); + page = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE); if (!page) panic("ERROR: Failed to allocate %lx bytes below %lx\n", PAGE_SIZE, 1UL << 31); @@ -723,7 +719,7 @@ void __init smp_save_dump_cpus(void) /* Get the CPU registers */ smp_save_cpu_regs(sa, addr, is_boot_cpu, page); } - memblock_phys_free(page, PAGE_SIZE); + memblock_free(page, PAGE_SIZE); diag_amode31_ops.diag308_reset(); pcpu_set_smt(0); } -- GitLab From 2d6a1c7d57723efcb23a345d0ea5a10d76350390 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:45 +0200 Subject: [PATCH 833/965] dt-bindings: Add vendor prefix for WinLink WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211217161549.24836-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd7812..95a847dfd29a9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1318,6 +1318,8 @@ patternProperties: description: Wiligear, Ltd. "^winbond,.*": description: Winbond Electronics corp. + "^winlink,.*": + description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. "^wits,.*": -- GitLab From e1ba2f940ba4c4c3b4d0a520301a920591c421f9 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:46 +0200 Subject: [PATCH 834/965] dt-bindings: arm: samsung: Document E850-96 board binding Add binding for the WinLink E850-96 board, which is based on Samsung Exynos850 SoC. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211217161549.24836-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index d885712027134..052cd94113d44 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -205,6 +205,12 @@ properties: - samsung,jackpotlte # Samsung Galaxy A8 (2018) - const: samsung,exynos7885 + - description: Exynos850 based boards + items: + - enum: + - winlink,e850-96 # WinLink E850-96 + - const: samsung,exynos850 + - description: Exynos Auto v9 based boards items: - enum: -- GitLab From 51b1a5729469cef57a3c97aa014aa6e1d2b8d864 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:47 +0200 Subject: [PATCH 835/965] dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 All Exynos850 GPIO blocks can use EXYNOS5420_PIN_DRV* definitions, except GPIO_HSI block. Add pin drive strength definitions for GPIO_HSI block correspondingly. Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211217161549.24836-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/pinctrl/samsung.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index b1832506b9239..950970634dfe4 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -36,7 +36,10 @@ #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 @@ -56,6 +59,14 @@ #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 -- GitLab From 299e6f788eab0b0aef97efb29ddc6971e7d0daf3 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Mon, 20 Dec 2021 13:17:59 +0100 Subject: [PATCH 836/965] reset: starfive-jh7100: Fix 32bit compilation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't be defined when compiling on 32bit architectures: On i386: ../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’: ../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration] value = readq(reg_assert); ^~~~~ ../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration] writeq(value, reg_assert); ^~~~~~ On m68k: drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration] drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1 make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2 make[1]: *** [Makefile:1969: drivers] Error 2 make: *** [Makefile:226: __sub-make] Error 2 Fixes: 0be3a1595bf8 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver") Reported-by: Randy Dunlap Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20211220121800.760846-1-kernel@esmil.dk' Signed-off-by: Arnd Bergmann --- drivers/reset/reset-starfive-jh7100.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c index e28a19d271cbc..fc44b2fb3e031 100644 --- a/drivers/reset/reset-starfive-jh7100.c +++ b/drivers/reset/reset-starfive-jh7100.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include -- GitLab From 8a3804c030e44335890bc9ca70cfa987488d9ec6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Dec 2021 16:12:32 -0600 Subject: [PATCH 837/965] ARM: dts: Remove "spidev" nodes "spidev" is not a real device, but a Linux implementation detail. It has never been documented either. The kernel has WARNed on the use of it for over 6 years. Time to remove its usage from the tree. Signed-off-by: Rob Herring Acked-by: Nicolas Ferre Acked-by: Viresh Kumar Cc: Mark Brown Link: https://lore.kernel.org/r/20211217221232.3664417-1-robh@kernel.org' Reviwed-by: Mark Brown Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/at91-q5xr5.dts | 18 ---------- arch/arm/boot/dts/at91-wb50n.dts | 6 ---- arch/arm/boot/dts/imx28-tx28.dts | 36 ------------------- arch/arm/boot/dts/imx53-tx53.dtsi | 11 ------ arch/arm/boot/dts/imx6qdl-tx6.dtsi | 12 ------- .../boot/dts/imx6ul-imx6ull-opos6uldev.dtsi | 12 ------- arch/arm/boot/dts/imx6ul-prti6g.dts | 6 ---- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 24 ------------- arch/arm/boot/dts/omap3-tao3530.dtsi | 14 -------- .../dts/qcom-mdm9615-wp8548-mangoh-green.dts | 2 +- arch/arm/boot/dts/spear1310-evb.dts | 16 --------- arch/arm/boot/dts/spear1340-evb.dts | 16 --------- 12 files changed, 1 insertion(+), 172 deletions(-) diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts index 5827383b181b0..47a00062f01f1 100644 --- a/arch/arm/boot/dts/at91-q5xr5.dts +++ b/arch/arm/boot/dts/at91-q5xr5.dts @@ -147,12 +147,6 @@ reg = <0x8000 0x3E000>; }; }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &spi1 { @@ -160,18 +154,6 @@ pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; status = "okay"; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <0>; - }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &usart0 { diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index a5e45bb95c04e..89f0f717f7ed3 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -90,12 +90,6 @@ &spi1 { status = "okay"; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <8000000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 164254c28f8eb..9e5651c7ea6b7 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -239,24 +239,6 @@ >; /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; }; @@ -700,24 +682,6 @@ pinctrl-0 = <&spi3_pins_a>; clock-frequency = <57600000>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7c9730f3f8207..81c2726a328a1 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -192,17 +192,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &esdhc1 { diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 362e65ccaa784..bcc5bbcce7697 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -259,18 +259,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &fec { diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi index 935a77d717a6d..18cac19aa9b0f 100644 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi @@ -114,18 +114,6 @@ pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; status = "okay"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <5000000>; - }; }; &i2c1 { diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts index d62015701d0a4..c18390f238e1e 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/imx6ul-prti6g.dts @@ -78,12 +78,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 938a32ced88d6..c485d058e0790 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -227,18 +227,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <660000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <660000>; - }; }; sound { @@ -290,18 +278,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <60000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <60000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 580bfa1931c80..7f440d11f7e75 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -197,25 +197,11 @@ &mcspi1 { pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; &mcspi3 { pinctrl-names = "default"; pinctrl-0 = <&mcspi3_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; #include "twl4030.dtsi" diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts index 942e3a2cac357..0827de5426c1d 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -103,7 +103,7 @@ &gsbi3_spi { spi@0 { - compatible = "swir,mangoh-iotport-spi", "spidev"; + compatible = "swir,mangoh-iotport-spi"; spi-max-frequency = <24000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index 8fcb6be6e7c79..4cbadcb410841 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -395,22 +395,6 @@ pl022,wait-state = <0>; pl022,duplex = <0>; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; wdt@ec800620 { diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts index f70ff56d45423..fd194ebeedc92 100644 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -489,22 +489,6 @@ ts,i-drive = <1>; }; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; timer@ec800600 { -- GitLab From 2e8f2d3a691e521fa49f825010759192e86cf102 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 19 Nov 2021 22:39:51 +0100 Subject: [PATCH 838/965] dt-bindings: soc: qcom: stats: Document compatibles with fixed offset Document additional compatibles that can be used similarly to qcom,rpm-stats for older RPM firmware versions that have the sleep stats at a fixed offset rather than a dynamic one. The exact offset might vary depending on the SoC so use SoC-specific compatible names to avoid confusion. Cc: Maulik Shah Signed-off-by: Stephan Gerhold Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211119213953.31970-2-stephan@gerhold.net --- Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml index 99dff7d73b7ec..473adca4e973c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml @@ -21,6 +21,11 @@ properties: enum: - qcom,rpmh-stats - qcom,rpm-stats + # For older RPM firmware versions with fixed offset for the sleep stats + - qcom,apq8084-rpm-stats + - qcom,msm8226-rpm-stats + - qcom,msm8916-rpm-stats + - qcom,msm8974-rpm-stats reg: maxItems: 1 -- GitLab From 708dbf4490c8ddf55d79b9f3855219b92d108760 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 19 Nov 2021 22:39:52 +0100 Subject: [PATCH 839/965] soc: qcom: stats: Add fixed sleep stats offset for older RPM firmwares Not all RPM firmware versions have the dynamic sleep stats offset available. Most older versions use a fixed offset of 0xdba0. Add support for this using new SoC-specific compatibles for APQ8084, MSM8226, MSM8916 and MSM8974. Even older SoCs seem to use a different offset and stats format. If needed those could be supported in the future by adding separate compatibles for those with a different stats_config. Cc: Maulik Shah Signed-off-by: Stephan Gerhold Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211119213953.31970-3-stephan@gerhold.net --- drivers/soc/qcom/qcom_stats.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 131d24caabf8d..d6bfd1bbdc2a8 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -237,6 +237,15 @@ static const struct stats_config rpm_data = { .subsystem_stats_in_smem = false, }; +/* Older RPM firmwares have the stats at a fixed offset instead */ +static const struct stats_config rpm_data_dba0 = { + .stats_offset = 0xdba0, + .num_records = 2, + .appended_stats_avail = true, + .dynamic_offset = false, + .subsystem_stats_in_smem = false, +}; + static const struct stats_config rpmh_data = { .stats_offset = 0x48, .num_records = 3, @@ -246,6 +255,10 @@ static const struct stats_config rpmh_data = { }; static const struct of_device_id qcom_stats_table[] = { + { .compatible = "qcom,apq8084-rpm-stats", .data = &rpm_data_dba0 }, + { .compatible = "qcom,msm8226-rpm-stats", .data = &rpm_data_dba0 }, + { .compatible = "qcom,msm8916-rpm-stats", .data = &rpm_data_dba0 }, + { .compatible = "qcom,msm8974-rpm-stats", .data = &rpm_data_dba0 }, { .compatible = "qcom,rpm-stats", .data = &rpm_data }, { .compatible = "qcom,rpmh-stats", .data = &rpmh_data }, { } -- GitLab From 6fc61c39ee1adb5f4115d288c876772fcd8b6979 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 21 Nov 2021 01:20:46 +0100 Subject: [PATCH 840/965] soc: qcom: llcc: Add configuration data for SM8350 Add LLCC configuration data for SM8350 SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org --- drivers/soc/qcom/llcc-qcom.c | 28 ++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 6bf2f1d1f2c55..ec52f29c88673 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -195,6 +195,28 @@ static const struct llcc_slice_config sm8250_data[] = { { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, }; +static const struct llcc_slice_config sm8350_data[] = { + { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, + { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, + { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, + { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), @@ -228,6 +250,11 @@ static const struct qcom_llcc_config sm8250_cfg = { .size = ARRAY_SIZE(sm8250_data), }; +static const struct qcom_llcc_config sm8350_cfg = { + .sct_data = sm8350_data, + .size = ARRAY_SIZE(sm8350_data), +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -644,6 +671,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, + { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 437c9df132296..9e8fd92c96b73 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -33,6 +33,9 @@ #define LLCC_MODPE 29 #define LLCC_APTCM 30 #define LLCC_WRCACHE 31 +#define LLCC_CVPFW 32 +#define LLCC_CPUSS1 33 +#define LLCC_CPUHWT 36 /** * struct llcc_slice_desc - Cache slice descriptor -- GitLab From 92c550f9ffd2884bb5def52b5c0485a35e452784 Mon Sep 17 00:00:00 2001 From: Changcheng Deng Date: Thu, 25 Nov 2021 01:43:11 +0000 Subject: [PATCH 841/965] PM: AVS: qcom-cpr: Use div64_ul instead of do_div do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot Signed-off-by: Changcheng Deng Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211125014311.45942-1-deng.changcheng@zte.com.cn --- drivers/soc/qcom/cpr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/cpr.c b/drivers/soc/qcom/cpr.c index 1d818a8ba2089..e9b854ed1bdfd 100644 --- a/drivers/soc/qcom/cpr.c +++ b/drivers/soc/qcom/cpr.c @@ -1010,7 +1010,7 @@ static int cpr_interpolate(const struct corner *corner, int step_volt, return corner->uV; temp = f_diff * (uV_high - uV_low); - do_div(temp, f_high - f_low); + temp = div64_ul(temp, f_high - f_low); /* * max_volt_scale has units of uV/MHz while freq values -- GitLab From 3925b909f75800e69bd1a65130a0440191a9e60a Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Sun, 28 Nov 2021 22:03:17 +0100 Subject: [PATCH 842/965] soc: qcom: aoss: constify static struct thermal_cooling_device_ops The only usage of qmp_cooling_device_ops is to pass its address to devm_thermal_of_cooling_device_register() which takes a pointer to const struct thermal_cooling_device_ops as argument. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211128210317.25504-1-rikard.falkeborn@gmail.com --- drivers/soc/qcom/qcom_aoss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 34acf58bbb0d6..cbe5e39fdaeb0 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -352,7 +352,7 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, return ret; } -static struct thermal_cooling_device_ops qmp_cooling_device_ops = { +static const struct thermal_cooling_device_ops qmp_cooling_device_ops = { .get_max_state = qmp_cdev_get_max_state, .get_cur_state = qmp_cdev_get_cur_state, .set_cur_state = qmp_cdev_set_cur_state, -- GitLab From 8712107740ad272bd89c873ec850146ac3d8832a Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:29 +0100 Subject: [PATCH 843/965] dt-bindings: qcom-rpmpd: Add sm6125 power domains Add dt-bindings for sm6125 SoC RPM Power Domains Signed-off-by: Martin Botka [bjorn: Added compatible to binding as well] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-1-martin.botka@somainline.org --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index a6d51d51d2c77..8b5d641104b19 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -33,6 +33,7 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm6115-rpmpd + - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 340b0ffe5eb80..5b64059ef43ef 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -219,6 +219,14 @@ #define SM6115_VDD_LPI_CX 6 #define SM6115_VDD_LPI_MX 7 +/* SM6125 Power Domains */ +#define SM6125_VDDCX 0 +#define SM6125_VDDCX_AO 1 +#define SM6125_VDDCX_VFL 2 +#define SM6125_VDDMX 3 +#define SM6125_VDDMX_AO 4 +#define SM6125_VDDMX_VFL 5 + /* QCM2290 Power Domains */ #define QCM2290_VDDCX 0 #define QCM2290_VDDCX_AO 1 -- GitLab From 82c6bf7585cdb5e1bc8f8b1a2925ad692585e1f4 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:30 +0100 Subject: [PATCH 844/965] soc: qcom: rpmpd: Add support for sm6125 Add RPM power domains located in Qualcomm SM6125 SoC. Signed-off-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-2-martin.botka@somainline.org --- drivers/soc/qcom/rpmpd.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 36b2381039e62..0a8d8d24bfb77 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -395,6 +395,28 @@ static const struct rpmpd_desc sm6115_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; +/* sm6125 RPM Power domains */ +DEFINE_RPMPD_PAIR(sm6125, vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6125, vddcx_vfl, RWCX, 0); + +DEFINE_RPMPD_PAIR(sm6125, vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6125, vddmx_vfl, RWMX, 0); + +static struct rpmpd *sm6125_rpmpds[] = { + [SM6125_VDDCX] = &sm6125_vddcx, + [SM6125_VDDCX_AO] = &sm6125_vddcx_ao, + [SM6125_VDDCX_VFL] = &sm6125_vddcx_vfl, + [SM6125_VDDMX] = &sm6125_vddmx, + [SM6125_VDDMX_AO] = &sm6125_vddmx_ao, + [SM6125_VDDMX_VFL] = &sm6125_vddmx_vfl, +}; + +static const struct rpmpd_desc sm6125_desc = { + .rpmpds = sm6125_rpmpds, + .num_pds = ARRAY_SIZE(sm6125_rpmpds), + .max_state = RPM_SMD_LEVEL_BINNING, +}; + static struct rpmpd *qcm2290_rpmpds[] = { [QCM2290_VDDCX] = &sm6115_vddcx, [QCM2290_VDDCX_AO] = &sm6115_vddcx_ao, @@ -425,6 +447,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, + { .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmpd_match_table); -- GitLab From 71ca61c4d009ef914bab95b875ef4411c6cb7b2f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:57:39 +0530 Subject: [PATCH 845/965] dt-bindings: arm: cpus: Add kryo780 compatible Kryo780 is found in SM8450, so add it to the list of cpu compatibles Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-2-vkoul@kernel.org --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index f2ab6423b4af1..dfa28e3525cb1 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -174,6 +174,7 @@ properties: - qcom,kryo560 - qcom,kryo570 - qcom,kryo685 + - qcom,kryo780 - qcom,scorpion enable-method: -- GitLab From 028e4c664906331fb6623982b8486cd86efa14b3 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:57:40 +0530 Subject: [PATCH 846/965] dt-bindings: firmware: scm: Add SM8450 compatible Add compatible for SM8450 SoCs. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-3-vkoul@kernel.org --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index d7e3cda8924e2..548733388497c 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -29,6 +29,7 @@ Required properties: * "qcom,scm-sm8150" * "qcom,scm-sm8250" * "qcom,scm-sm8350" + * "qcom,scm-sm8450" and: * "qcom,scm" - clocks: Specifies clocks needed by the SCM interface, if any: -- GitLab From 0e57fe4d11e59a9625b30be18b84aa69e32f0c37 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:57:41 +0530 Subject: [PATCH 847/965] dt-bindings: arm: qcom: Document SM8450 SoC and boards Document the SM8450 SoC binding and also the boards using it. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-4-vkoul@kernel.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64b..29a0bd3adac2f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -50,6 +50,7 @@ description: | sm8150 sm8250 sm8350 + sm8450 The 'board' element must be one of the following strings: @@ -257,6 +258,11 @@ properties: - qcom,sm8350-mtp - const: qcom,sm8350 + - items: + - enum: + - qcom,sm8450-qrd + - const: qcom,sm8450 + additionalProperties: true ... -- GitLab From aa9fc2c7e5777ae44a2f03e041d3f4b3e4a02860 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 12:57:42 +0530 Subject: [PATCH 848/965] soc: qcom: smem: Update max processor count Update max processor count to reflect the number of co-processors on SM8450 SoCs. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-5-vkoul@kernel.org --- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index c7e519bfdc8ae..e2057d8f1effb 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -85,7 +85,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 14 +#define SMEM_HOST_COUNT 15 /** * struct smem_proc_comm - proc_comm communication struct (legacy) -- GitLab From 22c755708c2395c58eb7670357baa110ba1ca2e0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 12:57:43 +0530 Subject: [PATCH 849/965] dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-6-vkoul@kernel.org --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 8b5d641104b19..f48bc41d81ec0 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -38,6 +38,7 @@ properties: - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd + - qcom,sm8450-rpmhpd '#power-domain-cells': const: 1 diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 5b64059ef43ef..edfc1ff2acb3d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -68,6 +68,21 @@ #define SM8350_MXC_AO 11 #define SM8350_MSS 12 +/* SM8450 Power Domain Indexes */ +#define SM8450_CX 0 +#define SM8450_CX_AO 1 +#define SM8450_EBI 2 +#define SM8450_GFX 3 +#define SM8450_LCX 4 +#define SM8450_LMX 5 +#define SM8450_MMCX 6 +#define SM8450_MMCX_AO 7 +#define SM8450_MX 8 +#define SM8450_MX_AO 9 +#define SM8450_MXC 10 +#define SM8450_MXC_AO 11 +#define SM8450_MSS 12 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 -- GitLab From 5d12289516d943dd6f348826a9f56f84199af0b1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 12:57:44 +0530 Subject: [PATCH 850/965] soc: qcom: rpmhpd: Add SM8450 power domains Add the power domains exposed by RPMH in the Qualcomm SM8450 platform. Unlike previous generations CX domain is not a child of MX domain. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-7-vkoul@kernel.org --- drivers/soc/qcom/rpmhpd.c | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 1118345d8824e..e7e150ce1b1a0 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -253,6 +253,57 @@ static const struct rpmhpd_desc sm8350_desc = { .num_pds = ARRAY_SIZE(sm8350_rpmhpds), }; +/* SM8450 RPMH powerdomains */ +static struct rpmhpd sm8450_cx_ao; +static struct rpmhpd sm8450_cx = { + .pd = { .name = "cx", }, + .peer = &sm8450_cx_ao, + .res_name = "cx.lvl", +}; + +static struct rpmhpd sm8450_cx_ao = { + .pd = { .name = "cx_ao", }, + .active_only = true, + .res_name = "cx.lvl", +}; + +static struct rpmhpd sm8450_mmcx_ao; +static struct rpmhpd sm8450_mmcx = { + .pd = { .name = "mmcx", }, + .peer = &sm8450_mmcx_ao, + .parent = &sm8450_cx.pd, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd sm8450_mmcx_ao = { + .pd = { .name = "mmcx_ao", }, + .active_only = true, + .peer = &sm8450_mmcx, + .parent = &sm8450_cx_ao.pd, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd *sm8450_rpmhpds[] = { + [SM8450_CX] = &sm8450_cx, + [SM8450_CX_AO] = &sm8450_cx_ao, + [SM8450_EBI] = &sdm845_ebi, + [SM8450_GFX] = &sdm845_gfx, + [SM8450_LCX] = &sdm845_lcx, + [SM8450_LMX] = &sdm845_lmx, + [SM8450_MMCX] = &sm8450_mmcx, + [SM8450_MMCX_AO] = &sm8450_mmcx_ao, + [SM8450_MX] = &sdm845_mx, + [SM8450_MX_AO] = &sdm845_mx_ao, + [SM8450_MXC] = &sm8350_mxc, + [SM8450_MXC_AO] = &sm8350_mxc_ao, + [SM8450_MSS] = &sdm845_mss, +}; + +static const struct rpmhpd_desc sm8450_desc = { + .rpmhpds = sm8450_rpmhpds, + .num_pds = ARRAY_SIZE(sm8450_rpmhpds), +}; + /* SC7180 RPMH powerdomains */ static struct rpmhpd *sc7180_rpmhpds[] = { [SC7180_CX] = &sdm845_cx, @@ -318,6 +369,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, + { .compatible = "qcom,sm8450-rpmhpd", .data = &sm8450_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmhpd_match_table); -- GitLab From 9e4cdb4ca7e1fc4cca021cd8fefc4488c6c63bfa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 12:57:45 +0530 Subject: [PATCH 851/965] soc: qcom: socinfo: add SM8450 ID Add the ID for the Qualcomm SM8450 SoC. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072745.3969077-8-vkoul@kernel.org --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 9a0eb59405e83..113dc57b74c38 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -315,6 +315,7 @@ static const struct soc_id soc_id[] = { { 425, "SC7180" }, { 453, "IPQ6005" }, { 455, "QRB5165" }, + { 457, "SM8450" }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) -- GitLab From 84e3b09292a481df5afe8a6b6fff8ded746506e3 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 9 Dec 2021 21:01:54 +0530 Subject: [PATCH 852/965] soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao sm8450_cx and sm8450_cx_ao should be peers of each other, add the missing .peer entry for sm8450_cx_ao Cc: Dmitry Baryshkov Cc: Vinod Koul Signed-off-by: Rajendra Nayak Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1639063917-9011-2-git-send-email-quic_rjendra@quicinc.com --- drivers/soc/qcom/rpmhpd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index e7e150ce1b1a0..2032cf355e52a 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -264,6 +264,7 @@ static struct rpmhpd sm8450_cx = { static struct rpmhpd sm8450_cx_ao = { .pd = { .name = "cx_ao", }, .active_only = true, + .peer = &sm8450_cx, .res_name = "cx.lvl", }; -- GitLab From 09bb67c104b5d27718a7191eff057ee7a45fc035 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 9 Dec 2021 21:01:55 +0530 Subject: [PATCH 853/965] soc: qcom: rpmhpd: Rename rpmhpd struct names The rpmhpd structs were named with a SoC-name prefix, but then they got reused across multiple SoC families making things confusing. Rename all the struct names to remove SoC-name prefixes. While we do this we end up with some power-domains without parents, and some with and at times different parents across SoCs. use a _w__parent suffix for such cases. No functional change as part of this patch. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1639063917-9011-3-git-send-email-quic_rjendra@quicinc.com --- drivers/soc/qcom/rpmhpd.c | 341 +++++++++++++++++++------------------- 1 file changed, 171 insertions(+), 170 deletions(-) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 2032cf355e52a..a12db32433c52 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -63,73 +63,132 @@ struct rpmhpd_desc { static DEFINE_MUTEX(rpmhpd_lock); -/* SDM845 RPMH powerdomains */ +/* RPMH powerdomains */ -static struct rpmhpd sdm845_ebi = { +static struct rpmhpd ebi = { .pd = { .name = "ebi", }, .res_name = "ebi.lvl", }; -static struct rpmhpd sdm845_lmx = { +static struct rpmhpd lmx = { .pd = { .name = "lmx", }, .res_name = "lmx.lvl", }; -static struct rpmhpd sdm845_lcx = { +static struct rpmhpd lcx = { .pd = { .name = "lcx", }, .res_name = "lcx.lvl", }; -static struct rpmhpd sdm845_gfx = { +static struct rpmhpd gfx = { .pd = { .name = "gfx", }, .res_name = "gfx.lvl", }; -static struct rpmhpd sdm845_mss = { +static struct rpmhpd mss = { .pd = { .name = "mss", }, .res_name = "mss.lvl", }; -static struct rpmhpd sdm845_mx_ao; -static struct rpmhpd sdm845_mx = { +static struct rpmhpd mx_ao; +static struct rpmhpd mx = { .pd = { .name = "mx", }, - .peer = &sdm845_mx_ao, + .peer = &mx_ao, .res_name = "mx.lvl", }; -static struct rpmhpd sdm845_mx_ao = { +static struct rpmhpd mx_ao = { .pd = { .name = "mx_ao", }, .active_only = true, - .peer = &sdm845_mx, + .peer = &mx, .res_name = "mx.lvl", }; -static struct rpmhpd sdm845_cx_ao; -static struct rpmhpd sdm845_cx = { +static struct rpmhpd cx_ao; +static struct rpmhpd cx = { + .pd = { .name = "cx", }, + .peer = &cx_ao, + .res_name = "cx.lvl", +}; + +static struct rpmhpd cx_ao = { + .pd = { .name = "cx_ao", }, + .active_only = true, + .peer = &cx, + .res_name = "cx.lvl", +}; + +static struct rpmhpd cx_ao_w_mx_parent; +static struct rpmhpd cx_w_mx_parent = { .pd = { .name = "cx", }, - .peer = &sdm845_cx_ao, - .parent = &sdm845_mx.pd, + .peer = &cx_ao_w_mx_parent, + .parent = &mx.pd, .res_name = "cx.lvl", }; -static struct rpmhpd sdm845_cx_ao = { +static struct rpmhpd cx_ao_w_mx_parent = { .pd = { .name = "cx_ao", }, .active_only = true, - .peer = &sdm845_cx, - .parent = &sdm845_mx_ao.pd, + .peer = &cx_w_mx_parent, + .parent = &mx_ao.pd, .res_name = "cx.lvl", }; +static struct rpmhpd mmcx_ao; +static struct rpmhpd mmcx = { + .pd = { .name = "mmcx", }, + .peer = &mmcx_ao, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd mmcx_ao = { + .pd = { .name = "mmcx_ao", }, + .active_only = true, + .peer = &mmcx, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd mmcx_ao_w_cx_parent; +static struct rpmhpd mmcx_w_cx_parent = { + .pd = { .name = "mmcx", }, + .peer = &mmcx_ao_w_cx_parent, + .parent = &cx.pd, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd mmcx_ao_w_cx_parent = { + .pd = { .name = "mmcx_ao", }, + .active_only = true, + .peer = &mmcx_w_cx_parent, + .parent = &cx_ao.pd, + .res_name = "mmcx.lvl", +}; + +static struct rpmhpd mxc_ao; +static struct rpmhpd mxc = { + .pd = { .name = "mxc", }, + .peer = &mxc_ao, + .res_name = "mxc.lvl", +}; + +static struct rpmhpd mxc_ao = { + .pd = { .name = "mxc_ao", }, + .active_only = true, + .peer = &mxc, + .res_name = "mxc.lvl", +}; + +/* SDM845 RPMH powerdomains */ static struct rpmhpd *sdm845_rpmhpds[] = { - [SDM845_EBI] = &sdm845_ebi, - [SDM845_MX] = &sdm845_mx, - [SDM845_MX_AO] = &sdm845_mx_ao, - [SDM845_CX] = &sdm845_cx, - [SDM845_CX_AO] = &sdm845_cx_ao, - [SDM845_LMX] = &sdm845_lmx, - [SDM845_LCX] = &sdm845_lcx, - [SDM845_GFX] = &sdm845_gfx, - [SDM845_MSS] = &sdm845_mss, + [SDM845_EBI] = &ebi, + [SDM845_MX] = &mx, + [SDM845_MX_AO] = &mx_ao, + [SDM845_CX] = &cx_w_mx_parent, + [SDM845_CX_AO] = &cx_ao_w_mx_parent, + [SDM845_LMX] = &lmx, + [SDM845_LCX] = &lcx, + [SDM845_GFX] = &gfx, + [SDM845_MSS] = &mss, }; static const struct rpmhpd_desc sdm845_desc = { @@ -139,9 +198,9 @@ static const struct rpmhpd_desc sdm845_desc = { /* SDX55 RPMH powerdomains */ static struct rpmhpd *sdx55_rpmhpds[] = { - [SDX55_MSS] = &sdm845_mss, - [SDX55_MX] = &sdm845_mx, - [SDX55_CX] = &sdm845_cx, + [SDX55_MSS] = &mss, + [SDX55_MX] = &mx, + [SDX55_CX] = &cx_w_mx_parent, }; static const struct rpmhpd_desc sdx55_desc = { @@ -151,12 +210,12 @@ static const struct rpmhpd_desc sdx55_desc = { /* SM6350 RPMH powerdomains */ static struct rpmhpd *sm6350_rpmhpds[] = { - [SM6350_CX] = &sdm845_cx, - [SM6350_GFX] = &sdm845_gfx, - [SM6350_LCX] = &sdm845_lcx, - [SM6350_LMX] = &sdm845_lmx, - [SM6350_MSS] = &sdm845_mss, - [SM6350_MX] = &sdm845_mx, + [SM6350_CX] = &cx_w_mx_parent, + [SM6350_GFX] = &gfx, + [SM6350_LCX] = &lcx, + [SM6350_LMX] = &lmx, + [SM6350_MSS] = &mss, + [SM6350_MX] = &mx, }; static const struct rpmhpd_desc sm6350_desc = { @@ -165,33 +224,18 @@ static const struct rpmhpd_desc sm6350_desc = { }; /* SM8150 RPMH powerdomains */ - -static struct rpmhpd sm8150_mmcx_ao; -static struct rpmhpd sm8150_mmcx = { - .pd = { .name = "mmcx", }, - .peer = &sm8150_mmcx_ao, - .res_name = "mmcx.lvl", -}; - -static struct rpmhpd sm8150_mmcx_ao = { - .pd = { .name = "mmcx_ao", }, - .active_only = true, - .peer = &sm8150_mmcx, - .res_name = "mmcx.lvl", -}; - static struct rpmhpd *sm8150_rpmhpds[] = { - [SM8150_MSS] = &sdm845_mss, - [SM8150_EBI] = &sdm845_ebi, - [SM8150_LMX] = &sdm845_lmx, - [SM8150_LCX] = &sdm845_lcx, - [SM8150_GFX] = &sdm845_gfx, - [SM8150_MX] = &sdm845_mx, - [SM8150_MX_AO] = &sdm845_mx_ao, - [SM8150_CX] = &sdm845_cx, - [SM8150_CX_AO] = &sdm845_cx_ao, - [SM8150_MMCX] = &sm8150_mmcx, - [SM8150_MMCX_AO] = &sm8150_mmcx_ao, + [SM8150_MSS] = &mss, + [SM8150_EBI] = &ebi, + [SM8150_LMX] = &lmx, + [SM8150_LCX] = &lcx, + [SM8150_GFX] = &gfx, + [SM8150_MX] = &mx, + [SM8150_MX_AO] = &mx_ao, + [SM8150_CX] = &cx_w_mx_parent, + [SM8150_CX_AO] = &cx_ao_w_mx_parent, + [SM8150_MMCX] = &mmcx, + [SM8150_MMCX_AO] = &mmcx_ao, }; static const struct rpmhpd_desc sm8150_desc = { @@ -199,17 +243,18 @@ static const struct rpmhpd_desc sm8150_desc = { .num_pds = ARRAY_SIZE(sm8150_rpmhpds), }; +/* SM8250 RPMH powerdomains */ static struct rpmhpd *sm8250_rpmhpds[] = { - [SM8250_CX] = &sdm845_cx, - [SM8250_CX_AO] = &sdm845_cx_ao, - [SM8250_EBI] = &sdm845_ebi, - [SM8250_GFX] = &sdm845_gfx, - [SM8250_LCX] = &sdm845_lcx, - [SM8250_LMX] = &sdm845_lmx, - [SM8250_MMCX] = &sm8150_mmcx, - [SM8250_MMCX_AO] = &sm8150_mmcx_ao, - [SM8250_MX] = &sdm845_mx, - [SM8250_MX_AO] = &sdm845_mx_ao, + [SM8250_CX] = &cx_w_mx_parent, + [SM8250_CX_AO] = &cx_ao_w_mx_parent, + [SM8250_EBI] = &ebi, + [SM8250_GFX] = &gfx, + [SM8250_LCX] = &lcx, + [SM8250_LMX] = &lmx, + [SM8250_MMCX] = &mmcx, + [SM8250_MMCX_AO] = &mmcx_ao, + [SM8250_MX] = &mx, + [SM8250_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sm8250_desc = { @@ -218,34 +263,20 @@ static const struct rpmhpd_desc sm8250_desc = { }; /* SM8350 Power domains */ -static struct rpmhpd sm8350_mxc_ao; -static struct rpmhpd sm8350_mxc = { - .pd = { .name = "mxc", }, - .peer = &sm8350_mxc_ao, - .res_name = "mxc.lvl", -}; - -static struct rpmhpd sm8350_mxc_ao = { - .pd = { .name = "mxc_ao", }, - .active_only = true, - .peer = &sm8350_mxc, - .res_name = "mxc.lvl", -}; - static struct rpmhpd *sm8350_rpmhpds[] = { - [SM8350_CX] = &sdm845_cx, - [SM8350_CX_AO] = &sdm845_cx_ao, - [SM8350_EBI] = &sdm845_ebi, - [SM8350_GFX] = &sdm845_gfx, - [SM8350_LCX] = &sdm845_lcx, - [SM8350_LMX] = &sdm845_lmx, - [SM8350_MMCX] = &sm8150_mmcx, - [SM8350_MMCX_AO] = &sm8150_mmcx_ao, - [SM8350_MX] = &sdm845_mx, - [SM8350_MX_AO] = &sdm845_mx_ao, - [SM8350_MXC] = &sm8350_mxc, - [SM8350_MXC_AO] = &sm8350_mxc_ao, - [SM8350_MSS] = &sdm845_mss, + [SM8350_CX] = &cx_w_mx_parent, + [SM8350_CX_AO] = &cx_ao_w_mx_parent, + [SM8350_EBI] = &ebi, + [SM8350_GFX] = &gfx, + [SM8350_LCX] = &lcx, + [SM8350_LMX] = &lmx, + [SM8350_MMCX] = &mmcx, + [SM8350_MMCX_AO] = &mmcx_ao, + [SM8350_MX] = &mx, + [SM8350_MX_AO] = &mx_ao, + [SM8350_MXC] = &mxc, + [SM8350_MXC_AO] = &mxc_ao, + [SM8350_MSS] = &mss, }; static const struct rpmhpd_desc sm8350_desc = { @@ -254,50 +285,20 @@ static const struct rpmhpd_desc sm8350_desc = { }; /* SM8450 RPMH powerdomains */ -static struct rpmhpd sm8450_cx_ao; -static struct rpmhpd sm8450_cx = { - .pd = { .name = "cx", }, - .peer = &sm8450_cx_ao, - .res_name = "cx.lvl", -}; - -static struct rpmhpd sm8450_cx_ao = { - .pd = { .name = "cx_ao", }, - .active_only = true, - .peer = &sm8450_cx, - .res_name = "cx.lvl", -}; - -static struct rpmhpd sm8450_mmcx_ao; -static struct rpmhpd sm8450_mmcx = { - .pd = { .name = "mmcx", }, - .peer = &sm8450_mmcx_ao, - .parent = &sm8450_cx.pd, - .res_name = "mmcx.lvl", -}; - -static struct rpmhpd sm8450_mmcx_ao = { - .pd = { .name = "mmcx_ao", }, - .active_only = true, - .peer = &sm8450_mmcx, - .parent = &sm8450_cx_ao.pd, - .res_name = "mmcx.lvl", -}; - static struct rpmhpd *sm8450_rpmhpds[] = { - [SM8450_CX] = &sm8450_cx, - [SM8450_CX_AO] = &sm8450_cx_ao, - [SM8450_EBI] = &sdm845_ebi, - [SM8450_GFX] = &sdm845_gfx, - [SM8450_LCX] = &sdm845_lcx, - [SM8450_LMX] = &sdm845_lmx, - [SM8450_MMCX] = &sm8450_mmcx, - [SM8450_MMCX_AO] = &sm8450_mmcx_ao, - [SM8450_MX] = &sdm845_mx, - [SM8450_MX_AO] = &sdm845_mx_ao, - [SM8450_MXC] = &sm8350_mxc, - [SM8450_MXC_AO] = &sm8350_mxc_ao, - [SM8450_MSS] = &sdm845_mss, + [SM8450_CX] = &cx, + [SM8450_CX_AO] = &cx_ao, + [SM8450_EBI] = &ebi, + [SM8450_GFX] = &gfx, + [SM8450_LCX] = &lcx, + [SM8450_LMX] = &lmx, + [SM8450_MMCX] = &mmcx_w_cx_parent, + [SM8450_MMCX_AO] = &mmcx_ao_w_cx_parent, + [SM8450_MX] = &mx, + [SM8450_MX_AO] = &mx_ao, + [SM8450_MXC] = &mxc, + [SM8450_MXC_AO] = &mxc_ao, + [SM8450_MSS] = &mss, }; static const struct rpmhpd_desc sm8450_desc = { @@ -307,14 +308,14 @@ static const struct rpmhpd_desc sm8450_desc = { /* SC7180 RPMH powerdomains */ static struct rpmhpd *sc7180_rpmhpds[] = { - [SC7180_CX] = &sdm845_cx, - [SC7180_CX_AO] = &sdm845_cx_ao, - [SC7180_GFX] = &sdm845_gfx, - [SC7180_MX] = &sdm845_mx, - [SC7180_MX_AO] = &sdm845_mx_ao, - [SC7180_LMX] = &sdm845_lmx, - [SC7180_LCX] = &sdm845_lcx, - [SC7180_MSS] = &sdm845_mss, + [SC7180_CX] = &cx_w_mx_parent, + [SC7180_CX_AO] = &cx_ao_w_mx_parent, + [SC7180_GFX] = &gfx, + [SC7180_MX] = &mx, + [SC7180_MX_AO] = &mx_ao, + [SC7180_LMX] = &lmx, + [SC7180_LCX] = &lcx, + [SC7180_MSS] = &mss, }; static const struct rpmhpd_desc sc7180_desc = { @@ -324,15 +325,15 @@ static const struct rpmhpd_desc sc7180_desc = { /* SC7280 RPMH powerdomains */ static struct rpmhpd *sc7280_rpmhpds[] = { - [SC7280_CX] = &sdm845_cx, - [SC7280_CX_AO] = &sdm845_cx_ao, - [SC7280_EBI] = &sdm845_ebi, - [SC7280_GFX] = &sdm845_gfx, - [SC7280_MX] = &sdm845_mx, - [SC7280_MX_AO] = &sdm845_mx_ao, - [SC7280_LMX] = &sdm845_lmx, - [SC7280_LCX] = &sdm845_lcx, - [SC7280_MSS] = &sdm845_mss, + [SC7280_CX] = &cx_w_mx_parent, + [SC7280_CX_AO] = &cx_ao_w_mx_parent, + [SC7280_EBI] = &ebi, + [SC7280_GFX] = &gfx, + [SC7280_MX] = &mx, + [SC7280_MX_AO] = &mx_ao, + [SC7280_LMX] = &lmx, + [SC7280_LCX] = &lcx, + [SC7280_MSS] = &mss, }; static const struct rpmhpd_desc sc7280_desc = { @@ -342,17 +343,17 @@ static const struct rpmhpd_desc sc7280_desc = { /* SC8180x RPMH powerdomains */ static struct rpmhpd *sc8180x_rpmhpds[] = { - [SC8180X_CX] = &sdm845_cx, - [SC8180X_CX_AO] = &sdm845_cx_ao, - [SC8180X_EBI] = &sdm845_ebi, - [SC8180X_GFX] = &sdm845_gfx, - [SC8180X_LCX] = &sdm845_lcx, - [SC8180X_LMX] = &sdm845_lmx, - [SC8180X_MMCX] = &sm8150_mmcx, - [SC8180X_MMCX_AO] = &sm8150_mmcx_ao, - [SC8180X_MSS] = &sdm845_mss, - [SC8180X_MX] = &sdm845_mx, - [SC8180X_MX_AO] = &sdm845_mx_ao, + [SC8180X_CX] = &cx_w_mx_parent, + [SC8180X_CX_AO] = &cx_ao_w_mx_parent, + [SC8180X_EBI] = &ebi, + [SC8180X_GFX] = &gfx, + [SC8180X_LCX] = &lcx, + [SC8180X_LMX] = &lmx, + [SC8180X_MMCX] = &mmcx, + [SC8180X_MMCX_AO] = &mmcx_ao, + [SC8180X_MSS] = &mss, + [SC8180X_MX] = &mx, + [SC8180X_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sc8180x_desc = { -- GitLab From 7d6a0a4dcf148681bb7760f9aad100ee3d3ce836 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 9 Dec 2021 21:01:56 +0530 Subject: [PATCH 854/965] soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 The requirement to specify the active + sleep and active-only MX power-domains as the parents of the corresponding CX power domains is not applicable on sc7280. Fix it by using the cx/cx_ao structs for sc7280 instead of the _w_mx_parent ones. Signed-off-by: Rajendra Nayak Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1639063917-9011-4-git-send-email-quic_rjendra@quicinc.com --- drivers/soc/qcom/rpmhpd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index a12db32433c52..63602049eaa0c 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -325,8 +325,8 @@ static const struct rpmhpd_desc sc7180_desc = { /* SC7280 RPMH powerdomains */ static struct rpmhpd *sc7280_rpmhpds[] = { - [SC7280_CX] = &cx_w_mx_parent, - [SC7280_CX_AO] = &cx_ao_w_mx_parent, + [SC7280_CX] = &cx, + [SC7280_CX_AO] = &cx_ao, [SC7280_EBI] = &ebi, [SC7280_GFX] = &gfx, [SC7280_MX] = &mx, -- GitLab From 90c74c1c2574e9454fb3a7ae2cddc9433aa89d49 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 9 Dec 2021 21:01:57 +0530 Subject: [PATCH 855/965] soc: qcom: rpmhpd: Sort power-domain definitions and lists Sort all power-domain defines and the SoC specific lists in alphabetical order for better readability. No functional changes. Signed-off-by: Rajendra Nayak Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1639063917-9011-5-git-send-email-quic_rjendra@quicinc.com --- drivers/soc/qcom/rpmhpd.c | 122 +++++++++++++++++++------------------- 1 file changed, 62 insertions(+), 60 deletions(-) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 63602049eaa0c..58f1dc9b9cb73 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -65,46 +65,9 @@ static DEFINE_MUTEX(rpmhpd_lock); /* RPMH powerdomains */ -static struct rpmhpd ebi = { - .pd = { .name = "ebi", }, - .res_name = "ebi.lvl", -}; - -static struct rpmhpd lmx = { - .pd = { .name = "lmx", }, - .res_name = "lmx.lvl", -}; - -static struct rpmhpd lcx = { - .pd = { .name = "lcx", }, - .res_name = "lcx.lvl", -}; - -static struct rpmhpd gfx = { - .pd = { .name = "gfx", }, - .res_name = "gfx.lvl", -}; - -static struct rpmhpd mss = { - .pd = { .name = "mss", }, - .res_name = "mss.lvl", -}; - -static struct rpmhpd mx_ao; -static struct rpmhpd mx = { - .pd = { .name = "mx", }, - .peer = &mx_ao, - .res_name = "mx.lvl", -}; - -static struct rpmhpd mx_ao = { - .pd = { .name = "mx_ao", }, - .active_only = true, - .peer = &mx, - .res_name = "mx.lvl", -}; - static struct rpmhpd cx_ao; +static struct rpmhpd mx; +static struct rpmhpd mx_ao; static struct rpmhpd cx = { .pd = { .name = "cx", }, .peer = &cx_ao, @@ -134,6 +97,26 @@ static struct rpmhpd cx_ao_w_mx_parent = { .res_name = "cx.lvl", }; +static struct rpmhpd ebi = { + .pd = { .name = "ebi", }, + .res_name = "ebi.lvl", +}; + +static struct rpmhpd gfx = { + .pd = { .name = "gfx", }, + .res_name = "gfx.lvl", +}; + +static struct rpmhpd lcx = { + .pd = { .name = "lcx", }, + .res_name = "lcx.lvl", +}; + +static struct rpmhpd lmx = { + .pd = { .name = "lmx", }, + .res_name = "lmx.lvl", +}; + static struct rpmhpd mmcx_ao; static struct rpmhpd mmcx = { .pd = { .name = "mmcx", }, @@ -164,6 +147,25 @@ static struct rpmhpd mmcx_ao_w_cx_parent = { .res_name = "mmcx.lvl", }; +static struct rpmhpd mss = { + .pd = { .name = "mss", }, + .res_name = "mss.lvl", +}; + +static struct rpmhpd mx_ao; +static struct rpmhpd mx = { + .pd = { .name = "mx", }, + .peer = &mx_ao, + .res_name = "mx.lvl", +}; + +static struct rpmhpd mx_ao = { + .pd = { .name = "mx_ao", }, + .active_only = true, + .peer = &mx, + .res_name = "mx.lvl", +}; + static struct rpmhpd mxc_ao; static struct rpmhpd mxc = { .pd = { .name = "mxc", }, @@ -180,15 +182,15 @@ static struct rpmhpd mxc_ao = { /* SDM845 RPMH powerdomains */ static struct rpmhpd *sdm845_rpmhpds[] = { - [SDM845_EBI] = &ebi, - [SDM845_MX] = &mx, - [SDM845_MX_AO] = &mx_ao, [SDM845_CX] = &cx_w_mx_parent, [SDM845_CX_AO] = &cx_ao_w_mx_parent, - [SDM845_LMX] = &lmx, - [SDM845_LCX] = &lcx, + [SDM845_EBI] = &ebi, [SDM845_GFX] = &gfx, + [SDM845_LCX] = &lcx, + [SDM845_LMX] = &lmx, [SDM845_MSS] = &mss, + [SDM845_MX] = &mx, + [SDM845_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sdm845_desc = { @@ -198,9 +200,9 @@ static const struct rpmhpd_desc sdm845_desc = { /* SDX55 RPMH powerdomains */ static struct rpmhpd *sdx55_rpmhpds[] = { + [SDX55_CX] = &cx_w_mx_parent, [SDX55_MSS] = &mss, [SDX55_MX] = &mx, - [SDX55_CX] = &cx_w_mx_parent, }; static const struct rpmhpd_desc sdx55_desc = { @@ -225,17 +227,17 @@ static const struct rpmhpd_desc sm6350_desc = { /* SM8150 RPMH powerdomains */ static struct rpmhpd *sm8150_rpmhpds[] = { - [SM8150_MSS] = &mss, - [SM8150_EBI] = &ebi, - [SM8150_LMX] = &lmx, - [SM8150_LCX] = &lcx, - [SM8150_GFX] = &gfx, - [SM8150_MX] = &mx, - [SM8150_MX_AO] = &mx_ao, [SM8150_CX] = &cx_w_mx_parent, [SM8150_CX_AO] = &cx_ao_w_mx_parent, + [SM8150_EBI] = &ebi, + [SM8150_GFX] = &gfx, + [SM8150_LCX] = &lcx, + [SM8150_LMX] = &lmx, [SM8150_MMCX] = &mmcx, [SM8150_MMCX_AO] = &mmcx_ao, + [SM8150_MSS] = &mss, + [SM8150_MX] = &mx, + [SM8150_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sm8150_desc = { @@ -272,11 +274,11 @@ static struct rpmhpd *sm8350_rpmhpds[] = { [SM8350_LMX] = &lmx, [SM8350_MMCX] = &mmcx, [SM8350_MMCX_AO] = &mmcx_ao, + [SM8350_MSS] = &mss, [SM8350_MX] = &mx, [SM8350_MX_AO] = &mx_ao, [SM8350_MXC] = &mxc, [SM8350_MXC_AO] = &mxc_ao, - [SM8350_MSS] = &mss, }; static const struct rpmhpd_desc sm8350_desc = { @@ -294,11 +296,11 @@ static struct rpmhpd *sm8450_rpmhpds[] = { [SM8450_LMX] = &lmx, [SM8450_MMCX] = &mmcx_w_cx_parent, [SM8450_MMCX_AO] = &mmcx_ao_w_cx_parent, + [SM8450_MSS] = &mss, [SM8450_MX] = &mx, [SM8450_MX_AO] = &mx_ao, [SM8450_MXC] = &mxc, [SM8450_MXC_AO] = &mxc_ao, - [SM8450_MSS] = &mss, }; static const struct rpmhpd_desc sm8450_desc = { @@ -311,11 +313,11 @@ static struct rpmhpd *sc7180_rpmhpds[] = { [SC7180_CX] = &cx_w_mx_parent, [SC7180_CX_AO] = &cx_ao_w_mx_parent, [SC7180_GFX] = &gfx, - [SC7180_MX] = &mx, - [SC7180_MX_AO] = &mx_ao, - [SC7180_LMX] = &lmx, [SC7180_LCX] = &lcx, + [SC7180_LMX] = &lmx, [SC7180_MSS] = &mss, + [SC7180_MX] = &mx, + [SC7180_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sc7180_desc = { @@ -329,11 +331,11 @@ static struct rpmhpd *sc7280_rpmhpds[] = { [SC7280_CX_AO] = &cx_ao, [SC7280_EBI] = &ebi, [SC7280_GFX] = &gfx, - [SC7280_MX] = &mx, - [SC7280_MX_AO] = &mx_ao, - [SC7280_LMX] = &lmx, [SC7280_LCX] = &lcx, + [SC7280_LMX] = &lmx, [SC7280_MSS] = &mss, + [SC7280_MX] = &mx, + [SC7280_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sc7280_desc = { -- GitLab From 492c995ab1ed1a149d5e8808953ce8837e310c06 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Dec 2021 09:26:02 +0100 Subject: [PATCH 856/965] dt-bindings: arm: msm: Add LLCC for SM6350 Add LLCC compatible for SM6350 SoC. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-2-luca.weiss@fairphone.com --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 62fcbd8833923..e12fc7999356a 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -24,6 +24,7 @@ properties: - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sdm845-llcc + - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc -- GitLab From bd0d04d4144d3db5b461b21d528607fe994d9afa Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:26:03 +0100 Subject: [PATCH 857/965] dt-bindings: firmware: scm: Add SM6350 compatible Add devicetree compatible for SCM on SM6350 SoC. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-3-luca.weiss@fairphone.com --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 548733388497c..b1cd4ad1889ae 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -26,6 +26,7 @@ Required properties: * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sdx55" + * "qcom,scm-sm6350" * "qcom,scm-sm8150" * "qcom,scm-sm8250" * "qcom,scm-sm8350" -- GitLab From 1e20b28d2e0e3e2996841df92f3af9050303f864 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:26:09 +0100 Subject: [PATCH 858/965] dt-bindings: arm: msm: Don't mark LLCC interrupt as required Newer SoCs like SM6350 or SM8250 don't provide an interrupt for LLCC. Signed-off-by: Luca Weiss Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-9-luca.weiss@fairphone.com --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index e12fc7999356a..03882aac8d2dd 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -45,7 +45,6 @@ required: - compatible - reg - reg-names - - interrupts additionalProperties: false -- GitLab From d39cec003ab0d6b91f9709c59daa6f0480d232e2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:11:11 +0100 Subject: [PATCH 859/965] soc: qcom: socinfo: Add SM6350 and SM7225 Both SoCs are known as 'lagoon' downstream. Add their ids to the socinfo driver. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213081111.20217-1-luca.weiss@fairphone.com --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 113dc57b74c38..6dc0f39c0ec3b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -313,9 +313,11 @@ static const struct soc_id soc_id[] = { { 421, "IPQ6000" }, { 422, "IPQ6010" }, { 425, "SC7180" }, + { 434, "SM6350" }, { 453, "IPQ6005" }, { 455, "QRB5165" }, { 457, "SM8450" }, + { 459, "SM7225" }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) -- GitLab From e395f021ccebc239e4fec02fec47f5f0eef44ebd Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sat, 11 Dec 2021 17:06:26 +0800 Subject: [PATCH 860/965] soc: qcom: rpmh-rsc: Fix typo in a comment The double `for' in the comment in line 694 is repeated. Remove one of them from the comment. Signed-off-by: Jason Wang Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211211090626.248801-1-wangborong@cdjrlc.com --- drivers/soc/qcom/rpmh-rsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 3a12a482f6b2f..01c2f50cb97ef 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -691,7 +691,7 @@ static int find_slots(struct tcs_group *tcs, const struct tcs_request *msg, * @drv: The controller. * @msg: The data to be written to the controller. * - * This should only be called for for sleep/wake state, never active-only + * This should only be called for sleep/wake state, never active-only * state. * * The caller must ensure that no other RPMH actions are happening and the -- GitLab From bc9fd597b3009d3412022c7beb3fbb01c9d27b31 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:04 +0800 Subject: [PATCH 861/965] dt-bindings: aspeed: Add Secure Boot Controller bindings The secure boot controller was first introduced in the AST2600. Signed-off-by: Joel Stanley Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211117035106.321454-2-joel@jms.id.au Signed-off-by: Joel Stanley --- .../bindings/arm/aspeed/aspeed,sbc.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml new file mode 100644 index 0000000000000..c72aab7064848 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +# Copyright 2021 Joel Stanley, IBM Corp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ASPEED Secure Boot Controller + +maintainers: + - Joel Stanley + - Andrew Jeffery + +description: | + The ASPEED SoCs have a register bank for interacting with the secure boot + controller. + +properties: + compatible: + items: + - const: aspeed,ast2600-sbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; -- GitLab From fea289467608ffddb2f8d3a740912047974bb183 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:05 +0800 Subject: [PATCH 862/965] ARM: dts: aspeed: Add secure boot controller node The ast2600 has a secure boot controller. Signed-off-by: Joel Stanley Reviewed-by: Ryan Chen Link: https://lore.kernel.org/r/20211117035106.321454-3-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 5106a424f1ced..16b36c13695af 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -384,6 +384,11 @@ status = "disabled"; }; + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; -- GitLab From 0720caa3f81d6b8c1ee5d51d3d251dc43030e687 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:34:43 +0800 Subject: [PATCH 863/965] ARM: dts: Add openbmc-flash-layout-64-alt.dtsi Add openbmc-flash-layout-64-alt.dtsi to describe the partitions of the secondary flash for OpenBMC's 64M static layout. The layout is the same as openbmc-flash-layout-64.dtsi and the labels are prepended with "alt-" for the partitions. Signed-off-by: Lei YU Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20211210093443.2140557-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- .../boot/dts/openbmc-flash-layout-64-alt.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi new file mode 100644 index 0000000000000..6505258675612 --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "alt-u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "alt-u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "alt-kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "alt-rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "alt-rwfs"; + }; +}; -- GitLab From b26965e99788ea163fc217bdca1c2b17a5d70c90 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:36:23 +0800 Subject: [PATCH 864/965] ARM: dts: aspeed: g220a: Enable secondary flash Enable the secondary flash of the g220a's BMC and the wdt2. Signed-off-by: Lei YU Link: https://lore.kernel.org/r/20211210093623.2140640-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 01dace8f5e5f7..0d1fb5ccfd36b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -260,6 +260,13 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; }; &spi1 { @@ -278,6 +285,11 @@ status = "okay"; }; +&wdt2 { + status = "okay"; + aspeed,alt-boot; +}; + &gpio { status = "okay"; gpio-line-names = -- GitLab From a8c729e966c4e9d033242d948b0e53c2a62d32e2 Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Tue, 7 Dec 2021 17:49:24 +0800 Subject: [PATCH 865/965] ARM: dts: aspeed: Adding Facebook Bletchley BMC Initial introduction of Facebook Bletchley equipped with Aspeed 2600 BMC SoC. Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/20211207094923.422422-1-howard.chiu@quantatw.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../dts/aspeed-bmc-facebook-bletchley.dts | 756 ++++++++++++++++++ 2 files changed, 757 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 78b71e02624c6..6ff97305200d5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1482,6 +1482,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-elbert.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts new file mode 100644 index 0000000000000..f973ea883b97c --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Bletchley BMC"; + compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; + + switchphy: ethernet-phy@0 { + // Fixed link + }; + + leds { + compatible = "gpio-leds"; + + sys_log_id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; + }; + fan0_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; + }; + fan1_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; + }; + fan2_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; + }; + fan3_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; + }; + fan0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; + }; + fan1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; + }; + fan2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; + }; + fan3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; + }; + sled0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; + }; + sled0_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; + }; + sled1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; + }; + sled1_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; + }; + sled2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; + }; + sled2_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; + }; + sled3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; + }; + sled3_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; + }; + sled4_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; + }; + sled4_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; + }; + sled5_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; + }; + sled5_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&switchphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&i2c0 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled0_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", + "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", + "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", + "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; + }; + + sled0_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled0_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled1_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; + }; + + sled1_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled1_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled2_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; + }; + + sled2_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled2_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c3 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled3_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; + }; + + sled3_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled3_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c4 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled4_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; + }; + + sled4_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled4_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c5 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled5_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; + }; + + sled5_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled5_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + hdc1080@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + front_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-fault-identify","power-p5v-stby-good", + "power-p1v0-dvdd-good","power-p1v0-avdd-good", + "","","","", + "","","","", + "","","",""; + }; +}; + +&i2c12 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + + fan_ioexp: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-fan0","presence-fan1", + "presence-fan2","presence-fan3", + "power-fan0-good","power-fan1-good", + "power-fan2-good","power-fan3-good", + "","","","", + "","","",""; + }; +}; + +&i2c13 { + multi-master; + aspeed,hw-timeout-ms = <1000>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", + /*H0-H7*/ "presence-riser1","presence-riser2", + "presence-sled0","presence-sled1", + "presence-sled2","presence-sled3", + "presence-sled4","presence-sled5", + /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", + "","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", + "ALERT_SLED2","ALERT_SLED3", + "ALERT_SLED4","ALERT_SLED5", + "P12V_AUX_ALERT1","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","", + "","BOARD_ID0","BOARD_ID1","BOARD_ID2", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","BAT_DETECT", + "BMC_BT_WP0","BMC_BT_WP1","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","RST_BMC_MVL","","", + "USB2_SEL0_A","USB2_SEL1_A", + "USB2_SEL0_B","USB2_SEL1_B", + /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&adc0 { + vref = <1800>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; -- GitLab From 4fcbe1f5b6ba71e0c464a303e3769bf1ce1fe54c Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Tue, 30 Nov 2021 13:48:55 -0500 Subject: [PATCH 866/965] ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config Configure the vuart in such a way that it does not inhibit the SuperIO's UART from functioning correctly. This allows the same DTS to be used for both configurations with SuperIO and VUART (depending on the BIOS build). The decision on whether to actually enable VUART can then be made at runtime. This change also enables the new uart_routing driver for the SuperIO case. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211130184855.1779353-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 60ac6d3f03b56..aff27c1d4b06d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -3,6 +3,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "Tyan S7106 BMC"; @@ -127,8 +128,23 @@ status = "okay"; }; +&uart_routing { + status = "okay"; +}; + &vuart { status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; }; &lpc_ctrl { -- GitLab From 30daf3cd8997d0ba4bda2b4a7f7c5122c81216f1 Mon Sep 17 00:00:00 2001 From: Ali El-Haj-Mahmoud Date: Tue, 30 Nov 2021 13:01:10 -0500 Subject: [PATCH 867/965] ARM: dts: aspeed: Add TYAN S8036 BMC machine The TYAN S8036 is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Ali El-Haj-Mahmoud Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211130180110.2217042-1-aaelhaj@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 470 ++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6ff97305200d5..25005a7b5b846 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1521,6 +1521,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts new file mode 100644 index 0000000000000..708ee78e4b830 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Tyan S8036 BMC"; + compatible = "tyan,s8036-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + p2a_memory: region@987f0000 { + no-map; + reg = <0x987f0000 0x00010000>; /* 64KB */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; /* 16M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + label = "bmc"; + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* RS-232 connector on header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + /* Alternative to vuart to internally connect (route) to uart1 + * when vuart cannot be used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart4 { + /* Alternative to vuart to internally connect (route) to the + * external port usually used by uart1 when vuart cannot be + * used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart5 { + /* BMC "debug" (console) UART; connected to RS-232 connector + * on header; selectable via jumpers as alternative to uart2 + */ + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&vuart { + status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&p2a { + status = "okay"; + memory-region = <&p2a_memory>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + /* CPU fan */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* PWM group for chassis fans #1, #2, #3 and #4 */ + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + /* PWM group for chassis fans #5 and #6 */ + fan@6 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c0 { + /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ + status = "okay"; +}; + +&i2c1 { + /* Directly connected to IPMB HDR. */ + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* BMC EEPROM, incl. mainboard FRU */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + /* Also connected to: + * - BCM5720 + * - FPGA + * - FAN HDR + * - FPIO HDR + */ +}; + +&i2c3 { + status = "okay"; + + /* PSU1 FRU @ 0xA0 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* PSU2 FRU @ 0xA2 */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* PSU1 @ 0xB0 */ + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + /* PSU2 @ 0xB2 */ + power-supply@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + /* Hardware monitor with temperature sensors */ + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + status = "okay"; + sensor-type = "temperature"; + }; + }; + + /* Also connected to: + * - PCA9544 + * - CLK BUFF + * - OCP FRU + */ +}; + +&i2c6 { + status = "okay"; + /* Connected to: + * - PCA9548 @0xE0 + * - PCA9548 @0xE2 + * - PCA9544 @0xE4 + */ +}; + +&i2c7 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #4 + */ +}; + +&i2c8 { + status = "okay"; + + /* Not connected */ +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&ibt { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +/* We're following the GPIO naming as defined at + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. + * + * Notes on led-identify and id-button: + * - A physical button is connected to id-button which + * triggers the clock on a D flip-flop. The /Q output of the + * flip-flop drives its D input. + * - The flip-flop's Q output drives led-identify which is + * connected to LEDs. + * - With that, every button press toggles the LED between on and off. + * + * Notes on power-, reset- and nmi- button and control: + * - The -button signals can be used to monitor physical buttons. + * - The -control signals can be used to actuate the specific + * operation. + * - In hardware, the -button signals are connected to the -control + * signals through drivers with the -control signals being + * protected through diodes. + */ +&gpio { + status = "okay"; + gpio-line-names = + /*A0*/ "", + /*A1*/ "", + /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ + /*A3*/ "", + /*A4*/ "", + /*A5*/ "", + /*A6*/ "", + /*A7*/ "", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0*/ "", + /*D1*/ "", + /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ + /*D3*/ "platform-reset", /* in: RESET_LED_L */ + /*D4*/ "", + /*D5*/ "", + /*D6*/ "", + /*D7*/ "", + /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ + /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ + /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ + /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ + /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ + /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ + /*E6*/ "TSI_RESERT", + /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ + /*F0*/ "", + /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ + /*F2*/ "", + /*F3*/ "", + /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ + /*F5*/ "BMC_SYS_FAULT_LED_L", + /*F6*/ "BMC_ASSERT_BIOS_WP_L", + /*F7*/ "", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0*/ "", + /*Q1*/ "", + /*Q2*/ "", + /*Q3*/ "", + /*Q4*/ "", + /*Q5*/ "", + /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ + /*Q7*/ "", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z2*/ "","","", + /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ + /*Z4-Z7*/ "","","","", + /*AA0*/ "", + /*AA1*/ "", + /*AA2*/ "", + /*AA3*/ "", + /*AA4*/ "", + /*AA5*/ "", + /*AA6*/ "", + /*AA7*/ "BMC_ASSERT_BMC_READY", + /*AB0*/ "BMC_SPD_SEL", + /*AB1-AB7*/ "","","","","","",""; +}; -- GitLab From 1fe5c05c7c25b5ffa66d623c790f39babd2f5e7f Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 11:06:40 -0600 Subject: [PATCH 868/965] ARM: dts: aspeed: p10: Enable USB host ports Ensure both controllers are enabled on, and add GPIO hog for USB power control to set the USB power to always on. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208170641.13322-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 12 +++++++++++- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index f42e2d776ba85..3e9edc893f558 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -280,7 +280,7 @@ /*L0-L7*/ "","","","","","","","", /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", @@ -292,6 +292,12 @@ /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &i2c0 { @@ -2375,6 +2381,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 866f32cdccea8..cb7d86a2862cf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -275,6 +275,12 @@ output-high; line-name = "I2C3_MUX_OE_N"; }; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &emmc_controller { -- GitLab From 62589e873d8e7cef7efd583ace1bb6ec90f252b7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 13:17:57 -0600 Subject: [PATCH 869/965] ARM: dts: aspeed: p10: Add TPM device Add the Nuvoton NPCT75X, a TIS I2C TPM. Modified Eddie's change to include the general compatible string, and combine the rainier and everest patches. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208191758.20517-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 5 +++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3e9edc893f558..22c06ff7a7ed2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -1887,6 +1887,11 @@ &i2c12 { status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c13 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index cb7d86a2862cf..c479742198328 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -2067,6 +2067,11 @@ &i2c12 { status = "okay"; + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; -- GitLab From a350dc623e3678b9bc6c6385df72a66a1ee69c7f Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:55 -0800 Subject: [PATCH 870/965] ARM: dts: aspeed: add LCLK setting into LPC IBT node If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC IBT node as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-2-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + arch/arm/boot/dts/aspeed-g6.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b313a1cf5f73f..f14dace34c5aa 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -381,6 +381,7 @@ compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index c7049454c7cbd..d0cc4be2de59f 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -507,6 +507,7 @@ compatible = "aspeed,ast2500-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 16b36c13695af..539edbd7aaeef 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -586,6 +586,7 @@ compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; -- GitLab From 002c42d37e45ff5b5248576c77437ccafb651454 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:56 -0800 Subject: [PATCH 871/965] dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtsi change in this patch series should be applied along with, and dtbs should be re-compiled after applying this series since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211108190200.290957-3-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- .../devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt index c9902fd4b38b7..25f86da804b72 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt @@ -11,6 +11,7 @@ Required properties: "aspeed,ast2500-ibt-bmc" "aspeed,ast2600-ibt-bmc" - reg: physical address and size of the registers +- clocks: clock for the device Optional properties: @@ -23,4 +24,5 @@ Example: compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x1e789140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; }; -- GitLab From 45cd8bbaaa18ab1c4f4387529db72b33be463197 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:58 -0800 Subject: [PATCH 872/965] ARM: dts: aspeed: add LCLK setting into LPC KCS nodes If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC KCS node as one of required properties to enable the LCLK by the LPC KCS driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-5-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++++ arch/arm/boot/dts/aspeed-g6.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d0cc4be2de59f..7495f93c5069f 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -446,6 +446,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -453,6 +454,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -460,6 +462,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -467,6 +470,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 539edbd7aaeef..c32e87fad4dc9 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -525,6 +525,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; kcs_chan = <1>; status = "disabled"; }; @@ -533,6 +534,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -540,6 +542,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -547,6 +550,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; -- GitLab From 19fd04fb9247fb5dce01919fa83ed037ec569247 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 16 Dec 2021 16:38:12 +0530 Subject: [PATCH 873/965] arm64: dts: qcom: sm8450: Add usb nodes SM8450 features a single USB controller which connects to both HS and SS phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216110813.658384-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 62082ed5335dd..10c25ad2d0c74 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -626,6 +626,52 @@ #hwlock-cells = <1>; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8450-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sm8450-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -1013,6 +1059,49 @@ #clock-cells = <0>; }; }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; timer { -- GitLab From 27a0d0b846d9add93a65c25149aae14ec3f75524 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 16 Dec 2021 16:38:13 +0530 Subject: [PATCH 874/965] arm64: dts: qcom: sm8450-qrd: Enable USB nodes Enable the usb phy and usb controller in peripheral mode. This helps to get the adb working with the QRD board. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216110813.658384-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 4b7ad190d538f..b68ab247e6aeb 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -373,3 +373,26 @@ vdda-max-microamp = <173000>; vdda-pll-max-microamp = <24900>; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p91>; +}; -- GitLab From 0d2589aa5ca99821486be8b7ff9c747665b9c2c9 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 20 Dec 2021 17:50:03 +0100 Subject: [PATCH 875/965] arm64: defconfig: Enable Samsung I2C driver i2c-s3c2410 driver is needed for some arm64 Exynos SoCs, e.g. Exynos850. Signed-off-by: Sam Protsenko Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20211121150558.21801-1-semen.protsenko@linaro.org Link: https://lore.kernel.org/r/20211220165004.17005-1-krzysztof.kozlowski@canonical.com' Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a9850dd877207..30516dc0b70ec 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -463,6 +463,7 @@ CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y CONFIG_I2C_RIIC=y CONFIG_I2C_RK3X=y +CONFIG_I2C_S3C2410=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_TEGRA=y CONFIG_I2C_UNIPHIER_F=y -- GitLab From ce96a964682ac11a7f6823397dfdb5026d459f37 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 20 Dec 2021 17:50:04 +0100 Subject: [PATCH 876/965] arm64: exynos: Enable Exynos Multi-Core Timer driver Some ARM64 Exynos SoCs have MCT timer block, e.g. Exynos850 and Exynos5433. CLKSRC_EXYNOS_MCT option is not visible unless COMPILE_TEST is enabled. Select CLKSRC_EXYNOS_MCT option for ARM64 ARCH_EXYNOS like it's done in arch/arm/mach-exynos/Kconfig, to enable MCT timer support for ARM64 Exynos SoCs. Even though ARM architected timer is available on all ARM64 SoCs, and used for managing timer hardware and clock source events, MCT timer still can be used as a wakeup source, as stated in commitae460fd9164b ("clocksource/drivers/exynos_mct: Prioritise Arm arch timer on arm64"). It's also nice to be able to test available MCT IP-core. Signed-off-by: Marek Szyprowski Signed-off-by: Sam Protsenko Signed-off-by: Krzysztof Kozlowski Tested-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20211101193531.15078-3-semen.protsenko@linaro.org Link: https://lore.kernel.org/r/20211220165004.17005-2-krzysztof.kozlowski@canonical.com' Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 1aa8b70732186..91f5e95681226 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,7 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG + select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select PINCTRL -- GitLab From d5624bb29f49b849ac8d1e9783dbf9c65cf33457 Mon Sep 17 00:00:00 2001 From: Xiongfeng Wang Date: Tue, 21 Dec 2021 11:55:56 +0800 Subject: [PATCH 877/965] asm-generic: introduce io_stop_wc() and add implementation for ARM64 For memory accesses with write-combining attributes (e.g. those returned by ioremap_wc()), the CPU may wait for prior accesses to be merged with subsequent ones. But in some situation, such wait is bad for the performance. We introduce io_stop_wc() to prevent the merging of write-combining memory accesses before this macro with those after it. We add implementation for ARM64 using DGH instruction and provide NOP implementation for other architectures. Signed-off-by: Xiongfeng Wang Suggested-by: Will Deacon Suggested-by: Catalin Marinas Acked-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211221035556.60346-1-wangxiongfeng2@huawei.com Signed-off-by: Catalin Marinas --- Documentation/memory-barriers.txt | 8 ++++++++ arch/arm64/include/asm/barrier.h | 9 +++++++++ include/asm-generic/barrier.h | 11 +++++++++++ 3 files changed, 28 insertions(+) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 7367ada13208c..b12df9137e1c1 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1950,6 +1950,14 @@ There are some more advanced barrier functions: For load from persistent memory, existing read memory barriers are sufficient to ensure read ordering. + (*) io_stop_wc(); + + For memory accesses with write-combining attributes (e.g. those returned + by ioremap_wc(), the CPU may wait for prior accesses to be merged with + subsequent ones. io_stop_wc() can be used to prevent the merging of + write-combining memory accesses before this macro with those after it when + such wait has performance implications. + =============================== IMPLICIT KERNEL MEMORY BARRIERS =============================== diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 1c5a005984582..62217be362173 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -26,6 +26,14 @@ #define __tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") +/* + * Data Gathering Hint: + * This instruction prevents merging memory accesses with Normal-NC or + * Device-GRE attributes before the hint instruction with any memory accesses + * appearing after the hint instruction. + */ +#define dgh() asm volatile("hint #6" : : : "memory") + #ifdef CONFIG_ARM64_PSEUDO_NMI #define pmr_sync() \ do { \ @@ -46,6 +54,7 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) +#define io_stop_wc() dgh() #define tsb_csync() \ do { \ diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h index 640f09479bdf7..4c2c1b8303442 100644 --- a/include/asm-generic/barrier.h +++ b/include/asm-generic/barrier.h @@ -251,5 +251,16 @@ do { \ #define pmem_wmb() wmb() #endif +/* + * ioremap_wc() maps I/O memory as memory with write-combining attributes. For + * this kind of memory accesses, the CPU may wait for prior accesses to be + * merged with subsequent ones. In some situation, such wait is bad for the + * performance. io_stop_wc() can be used to prevent the merging of + * write-combining memory accesses before this macro with those after it. + */ +#ifndef io_stop_wc +#define io_stop_wc do { } while (0) +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_GENERIC_BARRIER_H */ -- GitLab From b64dfcde1ca9cb82e38e573753f0c0db8fb841c2 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Fri, 17 Dec 2021 16:48:29 +0100 Subject: [PATCH 878/965] x86/mm: Prevent early boot triple-faults with instrumentation Commit in Fixes added a global TLB flush on the early boot path, after the kernel switches off of the trampoline page table. Compiler profiling options enabled with GCOV_PROFILE add additional measurement code on clang which needs to be initialized prior to use. The global flush in x86_64_start_kernel() happens before those initializations can happen, leading to accessing invalid memory. GCOV_PROFILE builds with gcc are still ok so this is clang-specific. The second issue this fixes is with KASAN: for a similar reason, kasan_early_init() needs to have happened before KASAN-instrumented functions are called. Therefore, reorder the flush to happen after the KASAN early init and prevent the compilers from adding profiling instrumentation to native_write_cr4(). Fixes: f154f290855b ("x86/mm/64: Flush global TLB on boot and AP bringup") Reported-by: "J. Bruce Fields" Reported-by: kernel test robot Signed-off-by: Borislav Petkov Tested-by: Carel Si Tested-by: "J. Bruce Fields" Link: https://lore.kernel.org/r/20211209144141.GC25654@xsang-OptiPlex-9020 --- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/head64.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0083464de5e31..79b3d67addcc3 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -384,7 +384,7 @@ set_register: } EXPORT_SYMBOL(native_write_cr0); -void native_write_cr4(unsigned long val) +void __no_profile native_write_cr4(unsigned long val) { unsigned long bits_changed = 0; diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 75acb6027a87a..f5e80a8377ad6 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -483,10 +483,12 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data) /* Kill off the identity-map trampoline */ reset_early_page_tables(); - __native_tlb_flush_global(native_read_cr4()); - clear_bss(); + /* + * This needs to happen *before* kasan_early_init() because latter maps stuff + * into that page. + */ clear_page(init_top_pgt); /* @@ -498,6 +500,16 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data) kasan_early_init(); + /* + * Flush global TLB entries which could be left over from the trampoline page + * table. + * + * This needs to happen *after* kasan_early_init() as KASAN-enabled .configs + * instrument native_write_cr4() so KASAN must be initialized for that + * instrumentation to work. + */ + __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); + idt_setup_early_handler(); copy_bootdata(__va(real_mode_data)); -- GitLab From 31e833b2031232493f2c30e53401e1f5ba293f97 Mon Sep 17 00:00:00 2001 From: "Guilherme G. Piccoli" Date: Tue, 21 Dec 2021 12:52:30 -0300 Subject: [PATCH 879/965] arm64: Unhash early pointer print plus improve comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When facing a really early issue on DT parsing we have currently a message that shows both the physical and virtual address of the FDT. The printk pointer modifier for the virtual address shows a hashed address there unless the user provides "no_hash_pointers" parameter in the command-line. The situation in which this message shows-up is a bit more serious though: the boot process is broken, nothing can be done (even an oops is too much for this early stage) so we have this message as a last resort in order to help debug bootloader issues, for example. Hence, we hereby change that to "%px" in order to make debugging easy, there's not much information leak risk in such early boot failure. Also, we tried to improve a bit the commenting on that function, given that if kernel fails there, it just hangs forever in a cpu_relax() loop. The reason we cannot BUG/panic is that is too early to do so; thanks to Mark Brown for pointing that on IRC and thanks Robin Murphy for the good pointer hash discussion in the mailing-list. Cc: Mark Brown Cc: Robin Murphy Signed-off-by: Guilherme G. Piccoli Reviewed-by: Robin Murphy Acked-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20211221155230.1532850-1-gpiccoli@igalia.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/setup.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index be5f85b0a24de..a80430550a737 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -189,11 +189,16 @@ static void __init setup_machine_fdt(phys_addr_t dt_phys) if (!dt_virt || !early_init_dt_scan(dt_virt)) { pr_crit("\n" - "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" + "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n" "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" "\nPlease check your bootloader.", &dt_phys, dt_virt); + /* + * Note that in this _really_ early stage we cannot even BUG() + * or oops, so the least terrible thing to do is cpu_relax(), + * or else we could end-up printing non-initialized data, etc. + */ while (true) cpu_relax(); } -- GitLab From c23f1b77358c173a25ef21303d2a8cc893e9ce22 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 22 Dec 2021 09:08:13 -0600 Subject: [PATCH 880/965] arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX The SM6125_VDDCX constant is introduced through a separate branch and is not available in the dts branch. Temporarily replace the constant with it's value to avoid the build breakage. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index e81b2a7794fb7..49e6bca646c23 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -449,7 +449,7 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd 0>; bus-width = <8>; non-removable; @@ -474,7 +474,7 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd 0>; bus-width = <4>; status = "disabled"; -- GitLab From 38e0257e0e6f4fef2aa2966b089b56a8b1cfb75c Mon Sep 17 00:00:00 2001 From: D Scott Phillips Date: Mon, 20 Dec 2021 15:41:14 -0800 Subject: [PATCH 881/965] arm64: errata: Fix exec handling in erratum 1418040 workaround The erratum 1418040 workaround enables CNTVCT_EL1 access trapping in EL0 when executing compat threads. The workaround is applied when switching between tasks, but the need for the workaround could also change at an exec(), when a non-compat task execs a compat binary or vice versa. Apply the workaround in arch_setup_new_exec(). This leaves a small window of time between SET_PERSONALITY and arch_setup_new_exec where preemption could occur and confuse the old workaround logic that compares TIF_32BIT between prev and next. Instead, we can just read cntkctl to make sure it's in the state that the next task needs. I measured cntkctl read time to be about the same as a mov from a general-purpose register on N1. Update the workaround logic to examine the current value of cntkctl instead of the previous task's compat state. Fixes: d49f7d7376d0 ("arm64: Move handling of erratum 1418040 into C code") Cc: # 5.9.x Signed-off-by: D Scott Phillips Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20211220234114.3926-1-scott@os.amperecomputing.com Signed-off-by: Catalin Marinas --- arch/arm64/kernel/process.c | 39 +++++++++++++++---------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index aacf2f5559a8b..271d4bbf468e3 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -439,34 +439,26 @@ static void entry_task_switch(struct task_struct *next) /* * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. - * Assuming the virtual counter is enabled at the beginning of times: - * - * - disable access when switching from a 64bit task to a 32bit task - * - enable access when switching from a 32bit task to a 64bit task + * Ensure access is disabled when switching to a 32bit task, ensure + * access is enabled when switching to a 64bit task. */ -static void erratum_1418040_thread_switch(struct task_struct *prev, - struct task_struct *next) +static void erratum_1418040_thread_switch(struct task_struct *next) { - bool prev32, next32; - u64 val; - - if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040)) - return; - - prev32 = is_compat_thread(task_thread_info(prev)); - next32 = is_compat_thread(task_thread_info(next)); - - if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) + if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) || + !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) return; - val = read_sysreg(cntkctl_el1); - - if (!next32) - val |= ARCH_TIMER_USR_VCT_ACCESS_EN; + if (is_compat_thread(task_thread_info(next))) + sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0); else - val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN; + sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN); +} - write_sysreg(val, cntkctl_el1); +static void erratum_1418040_new_exec(void) +{ + preempt_disable(); + erratum_1418040_thread_switch(current); + preempt_enable(); } /* @@ -501,7 +493,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, contextidr_thread_switch(next); entry_task_switch(next); ssbs_thread_switch(next); - erratum_1418040_thread_switch(prev, next); + erratum_1418040_thread_switch(next); ptrauth_thread_switch_user(next); /* @@ -611,6 +603,7 @@ void arch_setup_new_exec(void) current->mm->context.flags = mmflags; ptrauth_thread_init_user(); mte_thread_init_user(); + erratum_1418040_new_exec(); if (task_spec_ssb_noexec(current)) { arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS, -- GitLab From 4d5cff69fbddbbefef2903faa48263cc5d3ca382 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 15 Dec 2021 17:56:11 +0100 Subject: [PATCH 882/965] x86/mtrr: Remove the mtrr_bp_init() stub Add an IS_ENABLED() check in setup_arch() and call pat_disable() directly if MTRRs are not supported. This allows to remove the include in , which pull in lowlevel x86 headers that should not be included for UML builds and will cause build warnings with a following patch. Signed-off-by: Christoph Hellwig Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211215165612.554426-2-hch@lst.de --- arch/x86/include/asm/mtrr.h | 8 +------- arch/x86/kernel/setup.c | 7 ++++++- arch/x86/kvm/mmu/spte.c | 1 + 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 829df26fd7a3e..76d726074c163 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -24,8 +24,8 @@ #define _ASM_X86_MTRR_H #include -#include +void mtrr_bp_init(void); /* * The following functions are for use by other drivers that cannot use @@ -43,7 +43,6 @@ extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_ap_init(void); -extern void mtrr_bp_init(void); extern void set_mtrr_aps_delayed_init(void); extern void mtrr_aps_init(void); extern void mtrr_bp_restore(void); @@ -84,11 +83,6 @@ static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) { } -static inline void mtrr_bp_init(void) -{ - pat_disable("PAT support disabled because CONFIG_MTRR is disabled in the kernel."); -} - #define mtrr_ap_init() do {} while (0) #define set_mtrr_aps_delayed_init() do {} while (0) #define mtrr_aps_init() do {} while (0) diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 6a190c7f4d71b..2f5129bd49dc4 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -979,7 +980,11 @@ void __init setup_arch(char **cmdline_p) max_pfn = e820__end_of_ram_pfn(); /* update e820 for memory not covered by WB MTRRs */ - mtrr_bp_init(); + if (IS_ENABLED(CONFIG_MTRR)) + mtrr_bp_init(); + else + pat_disable("PAT support disabled because CONFIG_MTRR is disabled in the kernel."); + if (mtrr_trim_uncached_memory(max_pfn)) max_pfn = e820__end_of_ram_pfn(); diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index 0c76c45fdb686..fad546df0bbac 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -16,6 +16,7 @@ #include "spte.h" #include +#include #include static bool __read_mostly enable_mmio_caching = true; -- GitLab From 983d8e60f50806f90534cc5373d0ce867e5aaf79 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Wed, 22 Dec 2021 14:19:18 -0800 Subject: [PATCH 883/965] xfs: map unwritten blocks in XFS_IOC_{ALLOC,FREE}SP just like fallocate The old ALLOCSP/FREESP ioctls in XFS can be used to preallocate space at the end of files, just like fallocate and RESVSP. Make the behavior consistent with the other ioctls. Reported-by: Kirill Tkhai Signed-off-by: Darrick J. Wong Signed-off-by: Darrick J. Wong Reviewed-by: Dave Chinner Reviewed-by: Eric Sandeen --- fs/xfs/xfs_ioctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/xfs/xfs_ioctl.c b/fs/xfs/xfs_ioctl.c index 174cd8950cb67..bc85e045845d1 100644 --- a/fs/xfs/xfs_ioctl.c +++ b/fs/xfs/xfs_ioctl.c @@ -687,7 +687,8 @@ xfs_ioc_space( if (bf->l_start > XFS_ISIZE(ip)) { error = xfs_alloc_file_space(ip, XFS_ISIZE(ip), - bf->l_start - XFS_ISIZE(ip), 0); + bf->l_start - XFS_ISIZE(ip), + XFS_BMAPI_PREALLOC); if (error) goto out_unlock; } -- GitLab From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 23 Dec 2021 00:17:17 +0100 Subject: [PATCH 884/965] Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused a build regression: arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value Reported-by: Stephen Rothwell Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 -------------------- 1 file changed, 77 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index df8199fd4eb46..249476fdad7a6 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,83 +93,6 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; - - switch { - compatible = "realtek,rtl8365mb"; - /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ - mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - phy-handle = <ðphy0>; - }; - - port@1 { - reg = <1>; - label = "lan6"; - phy-handle = <ðphy1>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <ðphy2>; - }; - - port@3 { - reg = <3>; - label = "lan8"; - phy-handle = <ðphy3>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&sw0_p5>; - phy-mode = "rgmii"; - tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2100>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - }; - }; }; &srab { -- GitLab From 5fe392ff9d1f7254a1fbb3f72d9893088e4d23eb Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 22 Dec 2021 09:30:41 -0700 Subject: [PATCH 885/965] x86/boot/compressed: Move CLANG_FLAGS to beginning of KBUILD_CFLAGS When cross compiling i386_defconfig on an arm64 host with clang, there are a few instances of '-Waddress-of-packed-member' and '-Wgnu-variable-sized-type-not-at-end' in arch/x86/boot/compressed/, which should both be disabled with the cc-disable-warning calls in that directory's Makefile, which indicates that cc-disable-warning is failing at the point of testing these flags. The cc-disable-warning calls fail because at the point that the flags are tested, KBUILD_CFLAGS has '-march=i386' without $(CLANG_FLAGS), which has the '--target=' flag to tell clang what architecture it is targeting. Without the '--target=' flag, the host architecture (arm64) is used and i386 is not a valid value for '-march=' in that case. This error can be seen by adding some logging to try-run: clang-14: error: the clang compiler does not support '-march=i386' Invoking the compiler has to succeed prior to calling cc-option or cc-disable-warning in order to accurately test whether or not the flag is supported; if it doesn't, the requested flag can never be added to the compiler flags. Move $(CLANG_FLAGS) to the beginning of KBUILD_FLAGS so that any new flags that might be added in the future can be accurately tested. Fixes: d5cbd80e302d ("x86/boot: Add $(CLANG_FLAGS) to compressed KBUILD_CFLAGS") Signed-off-by: Nathan Chancellor Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211222163040.1961481-1-nathan@kernel.org --- arch/x86/boot/compressed/Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 431bf7f846c3c..e118136460518 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -28,7 +28,11 @@ KCOV_INSTRUMENT := n targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \ vmlinux.bin.xz vmlinux.bin.lzo vmlinux.bin.lz4 vmlinux.bin.zst -KBUILD_CFLAGS := -m$(BITS) -O2 +# CLANG_FLAGS must come before any cc-disable-warning or cc-option calls in +# case of cross compiling, as it has the '--target=' flag, which is needed to +# avoid errors with '-march=i386', and future flags may depend on the target to +# be valid. +KBUILD_CFLAGS := -m$(BITS) -O2 $(CLANG_FLAGS) KBUILD_CFLAGS += -fno-strict-aliasing -fPIE KBUILD_CFLAGS += -Wundef KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING @@ -47,7 +51,6 @@ KBUILD_CFLAGS += -D__DISABLE_EXPORTS # Disable relocation relaxation in case the link is not PIE. KBUILD_CFLAGS += $(call as-option,-Wa$(comma)-mrelax-relocations=no) KBUILD_CFLAGS += -include $(srctree)/include/linux/hidden.h -KBUILD_CFLAGS += $(CLANG_FLAGS) # sev.c indirectly inludes inat-table.h which is generated during # compilation and stored in $(objtree). Add the directory to the includes so -- GitLab From f34e8875ae244462711e31fcc4a82db13a16d36f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 22 Nov 2021 09:54:00 -0600 Subject: [PATCH 886/965] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" The QSPI controller on Intel's SoCFPGA platform does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash. Introduce the dts compatible "intel,socfpga-qspi" to differentiate the hardware. Acked-by: Pratyush Yadav Reviewed-by: Rob Herring Signed-off-by: Dinh Nguyen --- v3: revert to "intel,socfpga-qspi" v2: change binding to "cdns,qspi-nor-0010" to be more generic for other platforms --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index ca155abbda7a3..037f41f58503c 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -29,6 +29,7 @@ properties: - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi - const: cdns,qspi-nor - const: cdns,qspi-nor -- GitLab From 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 22 Nov 2021 09:10:03 -0600 Subject: [PATCH 887/965] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash! So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts compatible "intel,socfpga-qspi" that is specific for versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented. Signed-off-by: Dinh Nguyen --- v3: revert back to "intel,socfpga-qspi" v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010" --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 0b021eef0b538..7c1d6423d7f8c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -782,7 +782,7 @@ }; qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a574ea91d9d3f..3ba431dfa8c94 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -756,7 +756,7 @@ }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index d301ac0d406bf..3ec301bd08a91 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -594,7 +594,7 @@ }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 163f33b46e4f7..0dd2d2ee765aa 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -628,7 +628,7 @@ }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, -- GitLab From 0be4838f018c10d7f138a213c006d345db35ef5b Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 7 Dec 2021 18:50:01 +0000 Subject: [PATCH 888/965] x86/events/amd/iommu: Remove redundant assignment to variable shift Variable shift is being initialized with a value that is never read, it is being re-assigned later inside a loop. The assignment is redundant and can be removed. Signed-off-by: Colin Ian King Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211207185001.1412413-1-colin.i.king@gmail.com --- arch/x86/events/amd/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 913745f1419ba..b15f7b950d2e0 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -161,7 +161,7 @@ static int get_next_avail_iommu_bnk_cntr(struct perf_event *event) raw_spin_lock_irqsave(&piommu->lock, flags); - for (bank = 0, shift = 0; bank < max_banks; bank++) { + for (bank = 0; bank < max_banks; bank++) { for (cntr = 0; cntr < max_cntrs; cntr++) { shift = bank + (bank*3) + cntr; if (piommu->cntr_assign_mask & BIT_ULL(shift)) { -- GitLab From c4538d0f19010f22854360d99551eb293228b946 Mon Sep 17 00:00:00 2001 From: Guo Ren Date: Tue, 28 Dec 2021 14:47:26 +0800 Subject: [PATCH 889/965] s390: remove unused TASK_SIZE_OF This macro isn't used in Linux sched, now. Delete in include/linux/sched.h and arch's include/asm. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211228064730.2882351-6-guoren@kernel.org Signed-off-by: Heiko Carstens --- arch/s390/include/asm/processor.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index f54c152bf2bf9..5581b64a42364 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -88,11 +88,10 @@ extern void __bpon(void); * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. */ -#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \ +#define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \ _REGION3_SIZE : TASK_SIZE_MAX) #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1)) -#define TASK_SIZE TASK_SIZE_OF(current) #define TASK_SIZE_MAX (-PAGE_SIZE) #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ -- GitLab From 244122b4d2e5221e6abd6e21d6a58170104db781 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Thu, 16 Dec 2021 09:24:31 -0800 Subject: [PATCH 890/965] x86/lib: Add fast-short-rep-movs check to copy_user_enhanced_fast_string() Commit f444a5ff95dc ("x86/cpufeatures: Add support for fast short REP; MOVSB") fixed memmove() with an ALTERNATIVE that will use REP MOVSB for all string lengths. copy_user_enhanced_fast_string() has a similar run time check to avoid using REP MOVSB for copies less that 64 bytes. Add an ALTERNATIVE to patch out the short length check and always use REP MOVSB on X86_FEATURE_FSRM CPUs. Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20211216172431.1396371-1-tony.luck@intel.com --- arch/x86/lib/copy_user_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S index 2797e630b9b1c..1c429f0489ddc 100644 --- a/arch/x86/lib/copy_user_64.S +++ b/arch/x86/lib/copy_user_64.S @@ -200,8 +200,8 @@ EXPORT_SYMBOL(copy_user_generic_string) */ SYM_FUNC_START(copy_user_enhanced_fast_string) ASM_STAC - cmpl $64,%edx - jb .L_copy_short_string /* less then 64 bytes, avoid the costly 'rep' */ + /* CPUs without FSRM should avoid rep movsb for short copies */ + ALTERNATIVE "cmpl $64, %edx; jb .L_copy_short_string", "", X86_FEATURE_FSRM movl %edx,%ecx 1: rep movsb -- GitLab From a41f5b78ac5ba65986b31ddc6325a0b8cc8b8864 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 8 Nov 2021 01:26:40 +0900 Subject: [PATCH 891/965] x86/vdso: Remove -nostdlib compiler flag The -nostdlib option requests the compiler to not use the standard system startup files or libraries when linking. It is effective only when $(CC) is used as a linker driver. Since 379d98ddf413 ("x86: vdso: Use $LD instead of $CC to link") $(LD) is directly used, hence -nostdlib is unneeded. Signed-off-by: Masahiro Yamada Signed-off-by: Borislav Petkov Reviewed-by: Nick Desaulniers Link: https://lore.kernel.org/r/20211107162641.324688-1-masahiroy@kernel.org --- arch/x86/entry/vdso/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/entry/vdso/Makefile b/arch/x86/entry/vdso/Makefile index a2dddcc189f69..693f8b9031fb8 100644 --- a/arch/x86/entry/vdso/Makefile +++ b/arch/x86/entry/vdso/Makefile @@ -172,7 +172,7 @@ $(obj)/vdso32.so.dbg: $(obj)/vdso32/vdso32.lds $(vobjs32) FORCE # The DSO images are built using a special linker script. # quiet_cmd_vdso = VDSO $@ - cmd_vdso = $(LD) -nostdlib -o $@ \ + cmd_vdso = $(LD) -o $@ \ $(VDSO_LDFLAGS) $(VDSO_LDFLAGS_$(filter %.lds,$(^F))) \ -T $(filter %.lds,$^) $(filter %.o,$^) && \ sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' -- GitLab From 9102fa34604159642625f42d7f801f1e04d9ca12 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 8 Nov 2021 01:26:41 +0900 Subject: [PATCH 892/965] x86/purgatory: Remove -nostdlib compiler flag The -nostdlib option requests the compiler to not use the standard system startup files or libraries when linking. It is effective only when $(CC) is used as a linker driver. $(LD) is directly used for linking purgatory.{ro,chk} here, hence -nostdlib is unneeded. Signed-off-by: Masahiro Yamada Signed-off-by: Borislav Petkov Reviewed-by: Nick Desaulniers Link: https://lore.kernel.org/r/20211107162641.324688-2-masahiroy@kernel.org --- arch/x86/purgatory/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile index 95ea17a9d20cb..ae53d54d79593 100644 --- a/arch/x86/purgatory/Makefile +++ b/arch/x86/purgatory/Makefile @@ -16,7 +16,7 @@ CFLAGS_sha256.o := -D__DISABLE_EXPORTS # When linking purgatory.ro with -r unresolved symbols are not checked, # also link a purgatory.chk binary without -r to check for unresolved symbols. -PURGATORY_LDFLAGS := -e purgatory_start -nostdlib -z nodefaultlib +PURGATORY_LDFLAGS := -e purgatory_start -z nodefaultlib LDFLAGS_purgatory.ro := -r $(PURGATORY_LDFLAGS) LDFLAGS_purgatory.chk := $(PURGATORY_LDFLAGS) targets += purgatory.ro purgatory.chk -- GitLab From eaa090538e8d21801c6d5f94590c3799e6a528b5 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 30 Dec 2021 17:53:54 +0800 Subject: [PATCH 893/965] drm/amd/pm: keep the BACO feature enabled for suspend To pair with the workaround which always reset the ASIC in suspend. Otherwise, the reset which relies on BACO will fail. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 8a817932acdfc..9d7d64fdf410e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1400,8 +1400,14 @@ static int smu_disable_dpms(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; int ret = 0; + /* + * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair + * the workaround which always reset the asic in suspend. + * It's likely that workaround will be dropped in the future. + * Then the change here should be dropped together. + */ bool use_baco = !smu->is_apu && - ((amdgpu_in_reset(adev) && + (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); -- GitLab From 9a45ac2320d0a6ae01880a30d4b86025fce4061b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Dec 2021 22:41:18 -0500 Subject: [PATCH 894/965] fbdev: fbmem: add a helper to determine if an aperture is used by a fw fb Add a function for drivers to check if the a firmware initialized fb is corresponds to their aperture. This allows drivers to check if the device corresponds to what the firmware set up as the display device. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215203 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1840 Signed-off-by: Alex Deucher --- drivers/video/fbdev/core/fbmem.c | 47 ++++++++++++++++++++++++++++++++ include/linux/fb.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 826175ad88a2f..0fa7ede94fa61 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -1762,6 +1762,53 @@ int remove_conflicting_framebuffers(struct apertures_struct *a, } EXPORT_SYMBOL(remove_conflicting_framebuffers); +/** + * is_firmware_framebuffer - detect if firmware-configured framebuffer matches + * @a: memory range, users of which are to be checked + * + * This function checks framebuffer devices (initialized by firmware/bootloader) + * which use memory range described by @a. If @a matchesm the function returns + * true, otherwise false. + */ +bool is_firmware_framebuffer(struct apertures_struct *a) +{ + bool do_free = false; + bool found = false; + int i; + + if (!a) { + a = alloc_apertures(1); + if (!a) + return false; + + a->ranges[0].base = 0; + a->ranges[0].size = ~0; + do_free = true; + } + + mutex_lock(®istration_lock); + /* check all firmware fbs and kick off if the base addr overlaps */ + for_each_registered_fb(i) { + struct apertures_struct *gen_aper; + + if (!(registered_fb[i]->flags & FBINFO_MISC_FIRMWARE)) + continue; + + gen_aper = registered_fb[i]->apertures; + if (fb_do_apertures_overlap(gen_aper, a)) { + found = true; + break; + } + } + mutex_unlock(®istration_lock); + + if (do_free) + kfree(a); + + return found; +} +EXPORT_SYMBOL(is_firmware_framebuffer); + /** * remove_conflicting_pci_framebuffers - remove firmware-configured framebuffers for PCI devices * @pdev: PCI device diff --git a/include/linux/fb.h b/include/linux/fb.h index 6f3db99ab990a..3da95842b2075 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -610,6 +610,7 @@ extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); extern int remove_conflicting_framebuffers(struct apertures_struct *a, const char *name, bool primary); +extern bool is_firmware_framebuffer(struct apertures_struct *a); extern int fb_prepare_logo(struct fb_info *fb_info, int rotate); extern int fb_show_logo(struct fb_info *fb_info, int rotate); extern char* fb_get_buffer_offset(struct fb_info *info, struct fb_pixmap *buf, u32 size); -- GitLab From b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Dec 2021 22:57:16 -0500 Subject: [PATCH 895/965] drm/amdgpu: disable runpm if we are the primary adapter If we are the primary adapter (i.e., the one used by the firwmare framebuffer), disable runtime pm. This fixes a regression caused by commit 55285e21f045 which results in the displays waking up shortly after they go to sleep due to the device coming out of runtime suspend and sending a hotplug uevent. v2: squash in reworked fix from Evan Fixes: 55285e21f045 ("fbdev/efifb: Release PCI device's runtime PM ref during FB destroy") Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215203 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1840 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 28 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b85b67a88a3d3..7d67aec6f4a2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1077,6 +1077,7 @@ struct amdgpu_device { bool runpm; bool in_runpm; bool has_pr3; + bool is_fw_fb; bool pm_sysfs_en; bool ucode_sysfs_en; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 86ca80da9eea8..99370bdd8c5b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_irq.h" @@ -1890,6 +1891,26 @@ MODULE_DEVICE_TABLE(pci, pciidlist); static const struct drm_driver amdgpu_kms_driver; +static bool amdgpu_is_fw_framebuffer(resource_size_t base, + resource_size_t size) +{ + bool found = false; +#if IS_REACHABLE(CONFIG_FB) + struct apertures_struct *a; + + a = alloc_apertures(1); + if (!a) + return false; + + a->ranges[0].base = base; + a->ranges[0].size = size; + + found = is_firmware_framebuffer(a); + kfree(a); +#endif + return found; +} + static int amdgpu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -1898,6 +1919,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, unsigned long flags = ent->driver_data; int ret, retry = 0, i; bool supports_atomic = false; + bool is_fw_fb; + resource_size_t base, size; /* skip devices which are owned by radeon */ for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { @@ -1966,6 +1989,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, } #endif + base = pci_resource_start(pdev, 0); + size = pci_resource_len(pdev, 0); + is_fw_fb = amdgpu_is_fw_framebuffer(base, size); + /* Get rid of things like offb */ ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); if (ret) @@ -1978,6 +2005,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->dev = &pdev->dev; adev->pdev = pdev; ddev = adev_to_drm(adev); + adev->is_fw_fb = is_fw_fb; if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 651c7abfde036..09ad17944eb2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -206,6 +206,12 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) adev->runpm = true; break; } + /* XXX: disable runtime pm if we are the primary adapter + * to avoid displays being re-enabled after DPMS. + * This needs to be sorted out and fixed properly. + */ + if (adev->is_fw_fb) + adev->runpm = false; if (adev->runpm) dev_info(adev->dev, "Using BACO for runtime pm\n"); } -- GitLab From 7a3429bace0e08d94c39245631ea6bc109dafa49 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Thu, 30 Dec 2021 17:36:31 -0700 Subject: [PATCH 896/965] ipv4: Check attribute length for RTA_GATEWAY in multipath route syzbot reported uninit-value: ============================================================ BUG: KMSAN: uninit-value in fib_get_nhs+0xac4/0x1f80 net/ipv4/fib_semantics.c:708 fib_get_nhs+0xac4/0x1f80 net/ipv4/fib_semantics.c:708 fib_create_info+0x2411/0x4870 net/ipv4/fib_semantics.c:1453 fib_table_insert+0x45c/0x3a10 net/ipv4/fib_trie.c:1224 inet_rtm_newroute+0x289/0x420 net/ipv4/fib_frontend.c:886 Add helper to validate RTA_GATEWAY length before using the attribute. Fixes: 4e902c57417c ("[IPv4]: FIB configuration using struct fib_config") Reported-by: syzbot+d4b9a2851cc3ce998741@syzkaller.appspotmail.com Signed-off-by: David Ahern Cc: Thomas Graf Signed-off-by: David S. Miller --- net/ipv4/fib_semantics.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c index fde7797b58069..f1caa2c1c0410 100644 --- a/net/ipv4/fib_semantics.c +++ b/net/ipv4/fib_semantics.c @@ -662,6 +662,19 @@ static int fib_count_nexthops(struct rtnexthop *rtnh, int remaining, return nhs; } +static int fib_gw_from_attr(__be32 *gw, struct nlattr *nla, + struct netlink_ext_ack *extack) +{ + if (nla_len(nla) < sizeof(*gw)) { + NL_SET_ERR_MSG(extack, "Invalid IPv4 address in RTA_GATEWAY"); + return -EINVAL; + } + + *gw = nla_get_in_addr(nla); + + return 0; +} + /* only called when fib_nh is integrated into fib_info */ static int fib_get_nhs(struct fib_info *fi, struct rtnexthop *rtnh, int remaining, struct fib_config *cfg, @@ -704,7 +717,11 @@ static int fib_get_nhs(struct fib_info *fi, struct rtnexthop *rtnh, return -EINVAL; } if (nla) { - fib_cfg.fc_gw4 = nla_get_in_addr(nla); + ret = fib_gw_from_attr(&fib_cfg.fc_gw4, nla, + extack); + if (ret) + goto errout; + if (fib_cfg.fc_gw4) fib_cfg.fc_gw_family = AF_INET; } else if (nlav) { @@ -902,6 +919,7 @@ int fib_nh_match(struct net *net, struct fib_config *cfg, struct fib_info *fi, attrlen = rtnh_attrlen(rtnh); if (attrlen > 0) { struct nlattr *nla, *nlav, *attrs = rtnh_attrs(rtnh); + int err; nla = nla_find(attrs, attrlen, RTA_GATEWAY); nlav = nla_find(attrs, attrlen, RTA_VIA); @@ -912,12 +930,17 @@ int fib_nh_match(struct net *net, struct fib_config *cfg, struct fib_info *fi, } if (nla) { + __be32 gw; + + err = fib_gw_from_attr(&gw, nla, extack); + if (err) + return err; + if (nh->fib_nh_gw_family != AF_INET || - nla_get_in_addr(nla) != nh->fib_nh_gw4) + gw != nh->fib_nh_gw4) return 1; } else if (nlav) { struct fib_config cfg2; - int err; err = fib_gw_from_via(&cfg2, nlav, extack); if (err) -- GitLab From 664b9c4b7392ce723b013201843264bf95481ce5 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Thu, 30 Dec 2021 17:36:32 -0700 Subject: [PATCH 897/965] ipv4: Check attribute length for RTA_FLOW in multipath route Make sure RTA_FLOW is at least 4B before using. Fixes: 4e902c57417c ("[IPv4]: FIB configuration using struct fib_config") Signed-off-by: David Ahern Signed-off-by: David S. Miller --- net/ipv4/fib_semantics.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c index f1caa2c1c0410..36bc429f1635e 100644 --- a/net/ipv4/fib_semantics.c +++ b/net/ipv4/fib_semantics.c @@ -731,8 +731,13 @@ static int fib_get_nhs(struct fib_info *fi, struct rtnexthop *rtnh, } nla = nla_find(attrs, attrlen, RTA_FLOW); - if (nla) + if (nla) { + if (nla_len(nla) < sizeof(u32)) { + NL_SET_ERR_MSG(extack, "Invalid RTA_FLOW"); + return -EINVAL; + } fib_cfg.fc_flow = nla_get_u32(nla); + } fib_cfg.fc_encap = nla_find(attrs, attrlen, RTA_ENCAP); nla = nla_find(attrs, attrlen, RTA_ENCAP_TYPE); @@ -963,8 +968,14 @@ int fib_nh_match(struct net *net, struct fib_config *cfg, struct fib_info *fi, #ifdef CONFIG_IP_ROUTE_CLASSID nla = nla_find(attrs, attrlen, RTA_FLOW); - if (nla && nla_get_u32(nla) != nh->nh_tclassid) - return 1; + if (nla) { + if (nla_len(nla) < sizeof(u32)) { + NL_SET_ERR_MSG(extack, "Invalid RTA_FLOW"); + return -EINVAL; + } + if (nla_get_u32(nla) != nh->nh_tclassid) + return 1; + } #endif } -- GitLab From 4619bcf91399f00a40885100fb61d594d8454033 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Thu, 30 Dec 2021 17:36:33 -0700 Subject: [PATCH 898/965] ipv6: Check attribute length for RTA_GATEWAY in multipath route Commit referenced in the Fixes tag used nla_memcpy for RTA_GATEWAY as does the current nla_get_in6_addr. nla_memcpy protects against accessing memory greater than what is in the attribute, but there is no check requiring the attribute to have an IPv6 address. Add it. Fixes: 51ebd3181572 ("ipv6: add support of equal cost multipath (ECMP)") Signed-off-by: David Ahern Cc: Nicolas Dichtel Signed-off-by: David S. Miller --- net/ipv6/route.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/net/ipv6/route.c b/net/ipv6/route.c index 42d60c76d30a0..d16599c225b87 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -5224,6 +5224,19 @@ out: return should_notify; } +static int fib6_gw_from_attr(struct in6_addr *gw, struct nlattr *nla, + struct netlink_ext_ack *extack) +{ + if (nla_len(nla) < sizeof(*gw)) { + NL_SET_ERR_MSG(extack, "Invalid IPv6 address in RTA_GATEWAY"); + return -EINVAL; + } + + *gw = nla_get_in6_addr(nla); + + return 0; +} + static int ip6_route_multipath_add(struct fib6_config *cfg, struct netlink_ext_ack *extack) { @@ -5264,7 +5277,13 @@ static int ip6_route_multipath_add(struct fib6_config *cfg, nla = nla_find(attrs, attrlen, RTA_GATEWAY); if (nla) { - r_cfg.fc_gateway = nla_get_in6_addr(nla); + int ret; + + ret = fib6_gw_from_attr(&r_cfg.fc_gateway, nla, + extack); + if (ret) + return ret; + r_cfg.fc_flags |= RTF_GATEWAY; } r_cfg.fc_encap = nla_find(attrs, attrlen, RTA_ENCAP); -- GitLab From 1ff15a710a862db1101b97810af14aedc835a86a Mon Sep 17 00:00:00 2001 From: David Ahern Date: Thu, 30 Dec 2021 17:36:34 -0700 Subject: [PATCH 899/965] ipv6: Check attribute length for RTA_GATEWAY when deleting multipath route Make sure RTA_GATEWAY for IPv6 multipath route has enough bytes to hold an IPv6 address. Fixes: 6b9ea5a64ed5 ("ipv6: fix multipath route replace error recovery") Signed-off-by: David Ahern Cc: Roopa Prabhu Signed-off-by: David S. Miller --- net/ipv6/route.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/net/ipv6/route.c b/net/ipv6/route.c index d16599c225b87..b311c0bc9983e 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -5453,7 +5453,11 @@ static int ip6_route_multipath_del(struct fib6_config *cfg, nla = nla_find(attrs, attrlen, RTA_GATEWAY); if (nla) { - nla_memcpy(&r_cfg.fc_gateway, nla, 16); + err = fib6_gw_from_attr(&r_cfg.fc_gateway, nla, + extack); + if (err) + return err; + r_cfg.fc_flags |= RTF_GATEWAY; } } -- GitLab From 8bda81a4d400cf8a72e554012f0d8c45e07a3904 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Thu, 30 Dec 2021 17:36:35 -0700 Subject: [PATCH 900/965] lwtunnel: Validate RTA_ENCAP_TYPE attribute length lwtunnel_valid_encap_type_attr is used to validate encap attributes within a multipath route. Add length validation checking to the type. lwtunnel_valid_encap_type_attr is called converting attributes to fib{6,}_config struct which means it is used before fib_get_nhs, ip6_route_multipath_add, and ip6_route_multipath_del - other locations that use rtnh_ok and then nla_get_u16 on RTA_ENCAP_TYPE attribute. Fixes: 9ed59592e3e3 ("lwtunnel: fix autoload of lwt modules") Signed-off-by: David Ahern Signed-off-by: David S. Miller --- net/core/lwtunnel.c | 4 ++++ net/ipv4/fib_semantics.c | 3 +++ net/ipv6/route.c | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/net/core/lwtunnel.c b/net/core/lwtunnel.c index 2820aca2173a8..9ccd64e8a666a 100644 --- a/net/core/lwtunnel.c +++ b/net/core/lwtunnel.c @@ -197,6 +197,10 @@ int lwtunnel_valid_encap_type_attr(struct nlattr *attr, int remaining, nla_entype = nla_find(attrs, attrlen, RTA_ENCAP_TYPE); if (nla_entype) { + if (nla_len(nla_entype) < sizeof(u16)) { + NL_SET_ERR_MSG(extack, "Invalid RTA_ENCAP_TYPE"); + return -EINVAL; + } encap_type = nla_get_u16(nla_entype); if (lwtunnel_valid_encap_type(encap_type, diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c index 36bc429f1635e..92c29ab3d0428 100644 --- a/net/ipv4/fib_semantics.c +++ b/net/ipv4/fib_semantics.c @@ -740,6 +740,9 @@ static int fib_get_nhs(struct fib_info *fi, struct rtnexthop *rtnh, } fib_cfg.fc_encap = nla_find(attrs, attrlen, RTA_ENCAP); + /* RTA_ENCAP_TYPE length checked in + * lwtunnel_valid_encap_type_attr + */ nla = nla_find(attrs, attrlen, RTA_ENCAP_TYPE); if (nla) fib_cfg.fc_encap_type = nla_get_u16(nla); diff --git a/net/ipv6/route.c b/net/ipv6/route.c index b311c0bc9983e..d2ff8a7e17094 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -5287,6 +5287,10 @@ static int ip6_route_multipath_add(struct fib6_config *cfg, r_cfg.fc_flags |= RTF_GATEWAY; } r_cfg.fc_encap = nla_find(attrs, attrlen, RTA_ENCAP); + + /* RTA_ENCAP_TYPE length checked in + * lwtunnel_valid_encap_type_attr + */ nla = nla_find(attrs, attrlen, RTA_ENCAP_TYPE); if (nla) r_cfg.fc_encap_type = nla_get_u16(nla); -- GitLab From 5e75d0b215b868337e7a193f28a543ec00e858b1 Mon Sep 17 00:00:00 2001 From: Jianguo Wu Date: Fri, 31 Dec 2021 10:01:08 +0800 Subject: [PATCH 901/965] selftests: net: udpgro_fwd.sh: explicitly checking the available ping feature As Paolo pointed out, the result of ping IPv6 address depends on the running distro. So explicitly checking the available ping feature, as e.g. do the bareudp.sh self-tests. Fixes: 8b3170e07539 ("selftests: net: using ping6 for IPv6 in udpgro_fwd.sh") Signed-off-by: Jianguo Wu Link: https://lore.kernel.org/r/825ee22b-4245-dbf7-d2f7-a230770d6e21@163.com Signed-off-by: Jakub Kicinski --- tools/testing/selftests/net/udpgro_fwd.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/net/udpgro_fwd.sh b/tools/testing/selftests/net/udpgro_fwd.sh index 3ea73013d9568..6f05e06f67613 100755 --- a/tools/testing/selftests/net/udpgro_fwd.sh +++ b/tools/testing/selftests/net/udpgro_fwd.sh @@ -193,7 +193,8 @@ for family in 4 6; do SUFFIX="64 nodad" VXDEV=vxlan6 IPT=ip6tables - PING="ping6" + # Use ping6 on systems where ping doesn't handle IPv6 + ping -w 1 -c 1 ::1 > /dev/null 2>&1 || PING="ping6" fi echo "IPv$family" -- GitLab From d6d86830705f173fca6087a3e67ceaf68db80523 Mon Sep 17 00:00:00 2001 From: Haimin Zhang Date: Fri, 31 Dec 2021 10:35:23 +0800 Subject: [PATCH 902/965] net ticp:fix a kernel-infoleak in __tipc_sendmsg() struct tipc_socket_addr.ref has a 4-byte hole,and __tipc_getname() currently copying it to user space,causing kernel-infoleak. BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:121 [inline] BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:121 [inline] lib/usercopy.c:33 BUG: KMSAN: kernel-infoleak in _copy_to_user+0x1c9/0x270 lib/usercopy.c:33 lib/usercopy.c:33 instrument_copy_to_user include/linux/instrumented.h:121 [inline] instrument_copy_to_user include/linux/instrumented.h:121 [inline] lib/usercopy.c:33 _copy_to_user+0x1c9/0x270 lib/usercopy.c:33 lib/usercopy.c:33 copy_to_user include/linux/uaccess.h:209 [inline] copy_to_user include/linux/uaccess.h:209 [inline] net/socket.c:287 move_addr_to_user+0x3f6/0x600 net/socket.c:287 net/socket.c:287 __sys_getpeername+0x470/0x6b0 net/socket.c:1987 net/socket.c:1987 __do_sys_getpeername net/socket.c:1997 [inline] __se_sys_getpeername net/socket.c:1994 [inline] __do_sys_getpeername net/socket.c:1997 [inline] net/socket.c:1994 __se_sys_getpeername net/socket.c:1994 [inline] net/socket.c:1994 __x64_sys_getpeername+0xda/0x120 net/socket.c:1994 net/socket.c:1994 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_x64 arch/x86/entry/common.c:51 [inline] arch/x86/entry/common.c:82 do_syscall_64+0x54/0xd0 arch/x86/entry/common.c:82 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x44/0xae Uninit was stored to memory at: tipc_getname+0x575/0x5e0 net/tipc/socket.c:757 net/tipc/socket.c:757 __sys_getpeername+0x3b3/0x6b0 net/socket.c:1984 net/socket.c:1984 __do_sys_getpeername net/socket.c:1997 [inline] __se_sys_getpeername net/socket.c:1994 [inline] __do_sys_getpeername net/socket.c:1997 [inline] net/socket.c:1994 __se_sys_getpeername net/socket.c:1994 [inline] net/socket.c:1994 __x64_sys_getpeername+0xda/0x120 net/socket.c:1994 net/socket.c:1994 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_x64 arch/x86/entry/common.c:51 [inline] arch/x86/entry/common.c:82 do_syscall_64+0x54/0xd0 arch/x86/entry/common.c:82 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x44/0xae Uninit was stored to memory at: msg_set_word net/tipc/msg.h:212 [inline] msg_set_destport net/tipc/msg.h:619 [inline] msg_set_word net/tipc/msg.h:212 [inline] net/tipc/socket.c:1486 msg_set_destport net/tipc/msg.h:619 [inline] net/tipc/socket.c:1486 __tipc_sendmsg+0x44fa/0x5890 net/tipc/socket.c:1486 net/tipc/socket.c:1486 tipc_sendmsg+0xeb/0x140 net/tipc/socket.c:1402 net/tipc/socket.c:1402 sock_sendmsg_nosec net/socket.c:704 [inline] sock_sendmsg net/socket.c:724 [inline] sock_sendmsg_nosec net/socket.c:704 [inline] net/socket.c:2409 sock_sendmsg net/socket.c:724 [inline] net/socket.c:2409 ____sys_sendmsg+0xe11/0x12c0 net/socket.c:2409 net/socket.c:2409 ___sys_sendmsg net/socket.c:2463 [inline] ___sys_sendmsg net/socket.c:2463 [inline] net/socket.c:2492 __sys_sendmsg+0x704/0x840 net/socket.c:2492 net/socket.c:2492 __do_sys_sendmsg net/socket.c:2501 [inline] __se_sys_sendmsg net/socket.c:2499 [inline] __do_sys_sendmsg net/socket.c:2501 [inline] net/socket.c:2499 __se_sys_sendmsg net/socket.c:2499 [inline] net/socket.c:2499 __x64_sys_sendmsg+0xe2/0x120 net/socket.c:2499 net/socket.c:2499 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_x64 arch/x86/entry/common.c:51 [inline] arch/x86/entry/common.c:82 do_syscall_64+0x54/0xd0 arch/x86/entry/common.c:82 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x44/0xae Local variable skaddr created at: __tipc_sendmsg+0x2d0/0x5890 net/tipc/socket.c:1419 net/tipc/socket.c:1419 tipc_sendmsg+0xeb/0x140 net/tipc/socket.c:1402 net/tipc/socket.c:1402 Bytes 4-7 of 16 are uninitialized Memory access of size 16 starts at ffff888113753e00 Data copied to user address 0000000020000280 Reported-by: syzbot+cdbd40e0c3ca02cae3b7@syzkaller.appspotmail.com Signed-off-by: Haimin Zhang Acked-by: Jon Maloy Link: https://lore.kernel.org/r/1640918123-14547-1-git-send-email-tcs.kernel@gmail.com Signed-off-by: Jakub Kicinski --- net/tipc/socket.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/tipc/socket.c b/net/tipc/socket.c index ad570c2450be8..3e63c83e641c5 100644 --- a/net/tipc/socket.c +++ b/net/tipc/socket.c @@ -1461,6 +1461,8 @@ static int __tipc_sendmsg(struct socket *sock, struct msghdr *m, size_t dlen) msg_set_syn(hdr, 1); } + memset(&skaddr, 0, sizeof(skaddr)); + /* Determine destination */ if (atype == TIPC_SERVICE_RANGE) { return tipc_sendmcast(sock, ua, m, dlen, timeout); -- GitLab From 938f2e0b57ffe8a6df71e1e177b2978b1b33fe5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Linus=20L=C3=BCssing?= Date: Sat, 1 Jan 2022 06:27:13 +0100 Subject: [PATCH 903/965] batman-adv: mcast: don't send link-local multicast to mcast routers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The addition of routable multicast TX handling introduced a bug/regression for packets with a link-local multicast destination: These packets would be sent to all batman-adv nodes with a multicast router and to all batman-adv nodes with an old version without multicast router detection. This even disregards the batman-adv multicast fanout setting, which can potentially lead to an unwanted, high number of unicast transmissions or even congestion. Fixing this by avoiding to send link-local multicast packets to nodes in the multicast router list. Fixes: 11d458c1cb9b ("batman-adv: mcast: apply optimizations for routable packets, too") Signed-off-by: Linus Lüssing Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich --- net/batman-adv/multicast.c | 15 ++++++++++----- net/batman-adv/multicast.h | 10 ++++++---- net/batman-adv/soft-interface.c | 7 +++++-- 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/net/batman-adv/multicast.c b/net/batman-adv/multicast.c index 433901dcf0c37..f4004cf0ff6fb 100644 --- a/net/batman-adv/multicast.c +++ b/net/batman-adv/multicast.c @@ -1339,6 +1339,7 @@ batadv_mcast_forw_rtr_node_get(struct batadv_priv *bat_priv, * @bat_priv: the bat priv with all the soft interface information * @skb: The multicast packet to check * @orig: an originator to be set to forward the skb to + * @is_routable: stores whether the destination is routable * * Return: the forwarding mode as enum batadv_forw_mode and in case of * BATADV_FORW_SINGLE set the orig to the single originator the skb @@ -1346,17 +1347,16 @@ batadv_mcast_forw_rtr_node_get(struct batadv_priv *bat_priv, */ enum batadv_forw_mode batadv_mcast_forw_mode(struct batadv_priv *bat_priv, struct sk_buff *skb, - struct batadv_orig_node **orig) + struct batadv_orig_node **orig, int *is_routable) { int ret, tt_count, ip_count, unsnoop_count, total_count; bool is_unsnoopable = false; unsigned int mcast_fanout; struct ethhdr *ethhdr; - int is_routable = 0; int rtr_count = 0; ret = batadv_mcast_forw_mode_check(bat_priv, skb, &is_unsnoopable, - &is_routable); + is_routable); if (ret == -ENOMEM) return BATADV_FORW_NONE; else if (ret < 0) @@ -1369,7 +1369,7 @@ batadv_mcast_forw_mode(struct batadv_priv *bat_priv, struct sk_buff *skb, ip_count = batadv_mcast_forw_want_all_ip_count(bat_priv, ethhdr); unsnoop_count = !is_unsnoopable ? 0 : atomic_read(&bat_priv->mcast.num_want_all_unsnoopables); - rtr_count = batadv_mcast_forw_rtr_count(bat_priv, is_routable); + rtr_count = batadv_mcast_forw_rtr_count(bat_priv, *is_routable); total_count = tt_count + ip_count + unsnoop_count + rtr_count; @@ -1689,6 +1689,7 @@ batadv_mcast_forw_want_rtr(struct batadv_priv *bat_priv, * @bat_priv: the bat priv with all the soft interface information * @skb: the multicast packet to transmit * @vid: the vlan identifier + * @is_routable: stores whether the destination is routable * * Sends copies of a frame with multicast destination to any node that signaled * interest in it, that is either via the translation table or the according @@ -1701,7 +1702,7 @@ batadv_mcast_forw_want_rtr(struct batadv_priv *bat_priv, * is neither IPv4 nor IPv6. NET_XMIT_SUCCESS otherwise. */ int batadv_mcast_forw_send(struct batadv_priv *bat_priv, struct sk_buff *skb, - unsigned short vid) + unsigned short vid, int is_routable) { int ret; @@ -1717,12 +1718,16 @@ int batadv_mcast_forw_send(struct batadv_priv *bat_priv, struct sk_buff *skb, return ret; } + if (!is_routable) + goto skip_mc_router; + ret = batadv_mcast_forw_want_rtr(bat_priv, skb, vid); if (ret != NET_XMIT_SUCCESS) { kfree_skb(skb); return ret; } +skip_mc_router: consume_skb(skb); return ret; } diff --git a/net/batman-adv/multicast.h b/net/batman-adv/multicast.h index 9fee5da083113..8aec818d0bf63 100644 --- a/net/batman-adv/multicast.h +++ b/net/batman-adv/multicast.h @@ -43,7 +43,8 @@ enum batadv_forw_mode { enum batadv_forw_mode batadv_mcast_forw_mode(struct batadv_priv *bat_priv, struct sk_buff *skb, - struct batadv_orig_node **mcast_single_orig); + struct batadv_orig_node **mcast_single_orig, + int *is_routable); int batadv_mcast_forw_send_orig(struct batadv_priv *bat_priv, struct sk_buff *skb, @@ -51,7 +52,7 @@ int batadv_mcast_forw_send_orig(struct batadv_priv *bat_priv, struct batadv_orig_node *orig_node); int batadv_mcast_forw_send(struct batadv_priv *bat_priv, struct sk_buff *skb, - unsigned short vid); + unsigned short vid, int is_routable); void batadv_mcast_init(struct batadv_priv *bat_priv); @@ -68,7 +69,8 @@ void batadv_mcast_purge_orig(struct batadv_orig_node *orig_node); static inline enum batadv_forw_mode batadv_mcast_forw_mode(struct batadv_priv *bat_priv, struct sk_buff *skb, - struct batadv_orig_node **mcast_single_orig) + struct batadv_orig_node **mcast_single_orig, + int *is_routable) { return BATADV_FORW_ALL; } @@ -85,7 +87,7 @@ batadv_mcast_forw_send_orig(struct batadv_priv *bat_priv, static inline int batadv_mcast_forw_send(struct batadv_priv *bat_priv, struct sk_buff *skb, - unsigned short vid) + unsigned short vid, int is_routable) { kfree_skb(skb); return NET_XMIT_DROP; diff --git a/net/batman-adv/soft-interface.c b/net/batman-adv/soft-interface.c index 7ee09337fc401..2dbbe6c196093 100644 --- a/net/batman-adv/soft-interface.c +++ b/net/batman-adv/soft-interface.c @@ -198,6 +198,7 @@ static netdev_tx_t batadv_interface_tx(struct sk_buff *skb, int gw_mode; enum batadv_forw_mode forw_mode = BATADV_FORW_SINGLE; struct batadv_orig_node *mcast_single_orig = NULL; + int mcast_is_routable = 0; int network_offset = ETH_HLEN; __be16 proto; @@ -300,7 +301,8 @@ static netdev_tx_t batadv_interface_tx(struct sk_buff *skb, send: if (do_bcast && !is_broadcast_ether_addr(ethhdr->h_dest)) { forw_mode = batadv_mcast_forw_mode(bat_priv, skb, - &mcast_single_orig); + &mcast_single_orig, + &mcast_is_routable); if (forw_mode == BATADV_FORW_NONE) goto dropped; @@ -359,7 +361,8 @@ send: ret = batadv_mcast_forw_send_orig(bat_priv, skb, vid, mcast_single_orig); } else if (forw_mode == BATADV_FORW_SOME) { - ret = batadv_mcast_forw_send(bat_priv, skb, vid); + ret = batadv_mcast_forw_send(bat_priv, skb, vid, + mcast_is_routable); } else { if (batadv_dat_snoop_outgoing_arp_request(bat_priv, skb)) -- GitLab From ae81de737885820616f9c67c2e7935998b523d58 Mon Sep 17 00:00:00 2001 From: Gagan Kumar Date: Sat, 1 Jan 2022 11:11:25 +0530 Subject: [PATCH 904/965] mctp: Remove only static neighbour on RTM_DELNEIGH Add neighbour source flag in mctp_neigh_remove(...) to allow removal of only static neighbours. This should be a no-op change and might be useful later when mctp can have MCTP_NEIGH_DISCOVER neighbours. Signed-off-by: Gagan Kumar Signed-off-by: David S. Miller --- net/mctp/neigh.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/net/mctp/neigh.c b/net/mctp/neigh.c index 5cc0421214938..6ad3e33bd4d47 100644 --- a/net/mctp/neigh.c +++ b/net/mctp/neigh.c @@ -85,8 +85,8 @@ void mctp_neigh_remove_dev(struct mctp_dev *mdev) mutex_unlock(&net->mctp.neigh_lock); } -// TODO: add a "source" flag so netlink can only delete static neighbours? -static int mctp_neigh_remove(struct mctp_dev *mdev, mctp_eid_t eid) +static int mctp_neigh_remove(struct mctp_dev *mdev, mctp_eid_t eid, + enum mctp_neigh_source source) { struct net *net = dev_net(mdev->dev); struct mctp_neigh *neigh, *tmp; @@ -94,7 +94,8 @@ static int mctp_neigh_remove(struct mctp_dev *mdev, mctp_eid_t eid) mutex_lock(&net->mctp.neigh_lock); list_for_each_entry_safe(neigh, tmp, &net->mctp.neighbours, list) { - if (neigh->dev == mdev && neigh->eid == eid) { + if (neigh->dev == mdev && neigh->eid == eid && + neigh->source == source) { list_del_rcu(&neigh->list); /* TODO: immediate RTM_DELNEIGH */ call_rcu(&neigh->rcu, __mctp_neigh_free); @@ -202,7 +203,7 @@ static int mctp_rtm_delneigh(struct sk_buff *skb, struct nlmsghdr *nlh, if (!mdev) return -ENODEV; - return mctp_neigh_remove(mdev, eid); + return mctp_neigh_remove(mdev, eid, MCTP_NEIGH_STATIC); } static int mctp_fill_neigh(struct sk_buff *skb, u32 portid, u32 seq, int event, -- GitLab From c255a34e02efb1393d23ffb205ba1a11320aeffb Mon Sep 17 00:00:00 2001 From: Arthur Kiyanovski Date: Sun, 2 Jan 2022 07:37:26 +0000 Subject: [PATCH 905/965] net: ena: Fix undefined state when tx request id is out of bounds ena_com_tx_comp_req_id_get() checks the req_id of a received completion, and if it is out of bounds returns -EINVAL. This is a sign that something is wrong with the device and it needs to be reset. The current code does not reset the device in this case, which leaves the driver in an undefined state, where this completion is not properly handled. This commit adds a call to handle_invalid_req_id() in ena_clean_tx_irq() and ena_clean_xdp_irq() which resets the device to fix the issue. This commit also removes unnecessary request id checks from validate_tx_req_id() and validate_xdp_req_id(). This check is unneeded because it was already performed in ena_com_tx_comp_req_id_get(), which is called right before these functions. Fixes: 548c4940b9f1 ("net: ena: Implement XDP_TX action") Signed-off-by: Shay Agroskin Signed-off-by: Arthur Kiyanovski Signed-off-by: David S. Miller --- drivers/net/ethernet/amazon/ena/ena_netdev.c | 34 ++++++++++++-------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c index 7d5d885d85d5e..2274063e34cc4 100644 --- a/drivers/net/ethernet/amazon/ena/ena_netdev.c +++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c @@ -1288,26 +1288,22 @@ static int handle_invalid_req_id(struct ena_ring *ring, u16 req_id, static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) { - struct ena_tx_buffer *tx_info = NULL; + struct ena_tx_buffer *tx_info; - if (likely(req_id < tx_ring->ring_size)) { - tx_info = &tx_ring->tx_buffer_info[req_id]; - if (likely(tx_info->skb)) - return 0; - } + tx_info = &tx_ring->tx_buffer_info[req_id]; + if (likely(tx_info->skb)) + return 0; return handle_invalid_req_id(tx_ring, req_id, tx_info, false); } static int validate_xdp_req_id(struct ena_ring *xdp_ring, u16 req_id) { - struct ena_tx_buffer *tx_info = NULL; + struct ena_tx_buffer *tx_info; - if (likely(req_id < xdp_ring->ring_size)) { - tx_info = &xdp_ring->tx_buffer_info[req_id]; - if (likely(tx_info->xdpf)) - return 0; - } + tx_info = &xdp_ring->tx_buffer_info[req_id]; + if (likely(tx_info->xdpf)) + return 0; return handle_invalid_req_id(xdp_ring, req_id, tx_info, true); } @@ -1332,9 +1328,14 @@ static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget) rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id); - if (rc) + if (rc) { + if (unlikely(rc == -EINVAL)) + handle_invalid_req_id(tx_ring, req_id, NULL, + false); break; + } + /* validate that the request id points to a valid skb */ rc = validate_tx_req_id(tx_ring, req_id); if (rc) break; @@ -1896,9 +1897,14 @@ static int ena_clean_xdp_irq(struct ena_ring *xdp_ring, u32 budget) rc = ena_com_tx_comp_req_id_get(xdp_ring->ena_com_io_cq, &req_id); - if (rc) + if (rc) { + if (unlikely(rc == -EINVAL)) + handle_invalid_req_id(xdp_ring, req_id, NULL, + true); break; + } + /* validate that the request id points to a valid xdp_frame */ rc = validate_xdp_req_id(xdp_ring, req_id); if (rc) break; -- GitLab From cb3d4f98f0b26eafa0b913ac3716e4714254a747 Mon Sep 17 00:00:00 2001 From: Arthur Kiyanovski Date: Sun, 2 Jan 2022 07:37:27 +0000 Subject: [PATCH 906/965] net: ena: Fix wrong rx request id by resetting device A wrong request id received from the device is a sign that something is wrong with it, therefore trigger a device reset. Also add some debug info to the "Page is NULL" print to make it easier to debug. Fixes: 1738cd3ed342 ("net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)") Signed-off-by: Arthur Kiyanovski Signed-off-by: David S. Miller --- drivers/net/ethernet/amazon/ena/ena_netdev.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c index 2274063e34cc4..52a8c60b7e290 100644 --- a/drivers/net/ethernet/amazon/ena/ena_netdev.c +++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c @@ -1428,6 +1428,7 @@ static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring, u16 *next_to_clean) { struct ena_rx_buffer *rx_info; + struct ena_adapter *adapter; u16 len, req_id, buf = 0; struct sk_buff *skb; void *page_addr; @@ -1440,8 +1441,14 @@ static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring, rx_info = &rx_ring->rx_buffer_info[req_id]; if (unlikely(!rx_info->page)) { - netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, - "Page is NULL\n"); + adapter = rx_ring->adapter; + netif_err(adapter, rx_err, rx_ring->netdev, + "Page is NULL. qid %u req_id %u\n", rx_ring->qid, req_id); + ena_increase_stat(&rx_ring->rx_stats.bad_req_id, 1, &rx_ring->syncp); + adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; + /* Make sure reset reason is set before triggering the reset */ + smp_mb__before_atomic(); + set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); return NULL; } -- GitLab From 5055dc0348b8b7c168e3296044bccd724e1ae6cd Mon Sep 17 00:00:00 2001 From: Arthur Kiyanovski Date: Sun, 2 Jan 2022 07:37:28 +0000 Subject: [PATCH 907/965] net: ena: Fix error handling when calculating max IO queues number The role of ena_calc_max_io_queue_num() is to return the number of queues supported by the device, which means the return value should be >=0. The function that calls ena_calc_max_io_queue_num(), checks the return value. If it is 0, it means the device reported it supports 0 IO queues. This case is considered an error and is handled by the calling function accordingly. However the current implementation of ena_calc_max_io_queue_num() is wrong, since when it detects the device supports 0 IO queues, it returns -EFAULT. In such a case the calling function doesn't detect the error, and therefore doesn't handle it. This commit changes ena_calc_max_io_queue_num() to return 0 in case the device reported it supports 0 queues, allowing the calling function to properly handle the error case. Fixes: 736ce3f414cc ("net: ena: make ethtool -l show correct max number of queues") Signed-off-by: Shay Agroskin Signed-off-by: Arthur Kiyanovski Signed-off-by: David S. Miller --- drivers/net/ethernet/amazon/ena/ena_netdev.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c index 52a8c60b7e290..c72f0c7ff4aa3 100644 --- a/drivers/net/ethernet/amazon/ena/ena_netdev.c +++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c @@ -4026,10 +4026,6 @@ static u32 ena_calc_max_io_queue_num(struct pci_dev *pdev, max_num_io_queues = min_t(u32, max_num_io_queues, io_tx_cq_num); /* 1 IRQ for mgmnt and 1 IRQs for each IO direction */ max_num_io_queues = min_t(u32, max_num_io_queues, pci_msix_vec_count(pdev) - 1); - if (unlikely(!max_num_io_queues)) { - dev_err(&pdev->dev, "The device doesn't have io queues\n"); - return -EFAULT; - } return max_num_io_queues; } -- GitLab From f9d31c4cf4c11ff10317f038b9c6f7c3bda6cdd4 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Fri, 31 Dec 2021 18:37:37 -0500 Subject: [PATCH 908/965] sctp: hold endpoint before calling cb in sctp_transport_lookup_process The same fix in commit 5ec7d18d1813 ("sctp: use call_rcu to free endpoint") is also needed for dumping one asoc and sock after the lookup. Fixes: 86fdb3448cc1 ("sctp: ensure ep is not destroyed before doing the dump") Signed-off-by: Xin Long Signed-off-by: David S. Miller --- include/net/sctp/sctp.h | 3 +-- net/sctp/diag.c | 46 +++++++++++++++++++---------------------- net/sctp/socket.c | 22 +++++++++++++------- 3 files changed, 37 insertions(+), 34 deletions(-) diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index d314a180ab93d..3ae61ce2eabd0 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -112,8 +112,7 @@ struct sctp_transport *sctp_transport_get_next(struct net *net, struct rhashtable_iter *iter); struct sctp_transport *sctp_transport_get_idx(struct net *net, struct rhashtable_iter *iter, int pos); -int sctp_transport_lookup_process(int (*cb)(struct sctp_transport *, void *), - struct net *net, +int sctp_transport_lookup_process(sctp_callback_t cb, struct net *net, const union sctp_addr *laddr, const union sctp_addr *paddr, void *p); int sctp_transport_traverse_process(sctp_callback_t cb, sctp_callback_t cb_done, diff --git a/net/sctp/diag.c b/net/sctp/diag.c index a7d6231715013..034e2c74497df 100644 --- a/net/sctp/diag.c +++ b/net/sctp/diag.c @@ -245,48 +245,44 @@ static size_t inet_assoc_attr_size(struct sctp_association *asoc) + 64; } -static int sctp_tsp_dump_one(struct sctp_transport *tsp, void *p) +static int sctp_sock_dump_one(struct sctp_endpoint *ep, struct sctp_transport *tsp, void *p) { struct sctp_association *assoc = tsp->asoc; - struct sock *sk = tsp->asoc->base.sk; struct sctp_comm_param *commp = p; - struct sk_buff *in_skb = commp->skb; + struct sock *sk = ep->base.sk; const struct inet_diag_req_v2 *req = commp->r; - const struct nlmsghdr *nlh = commp->nlh; - struct net *net = sock_net(in_skb->sk); + struct sk_buff *skb = commp->skb; struct sk_buff *rep; int err; err = sock_diag_check_cookie(sk, req->id.idiag_cookie); if (err) - goto out; + return err; - err = -ENOMEM; rep = nlmsg_new(inet_assoc_attr_size(assoc), GFP_KERNEL); if (!rep) - goto out; + return -ENOMEM; lock_sock(sk); - if (sk != assoc->base.sk) { - release_sock(sk); - sk = assoc->base.sk; - lock_sock(sk); + if (ep != assoc->ep) { + err = -EAGAIN; + goto out; } - err = inet_sctp_diag_fill(sk, assoc, rep, req, - sk_user_ns(NETLINK_CB(in_skb).sk), - NETLINK_CB(in_skb).portid, - nlh->nlmsg_seq, 0, nlh, - commp->net_admin); - release_sock(sk); + + err = inet_sctp_diag_fill(sk, assoc, rep, req, sk_user_ns(NETLINK_CB(skb).sk), + NETLINK_CB(skb).portid, commp->nlh->nlmsg_seq, 0, + commp->nlh, commp->net_admin); if (err < 0) { WARN_ON(err == -EMSGSIZE); - kfree_skb(rep); goto out; } + release_sock(sk); - err = nlmsg_unicast(net->diag_nlsk, rep, NETLINK_CB(in_skb).portid); + return nlmsg_unicast(sock_net(skb->sk)->diag_nlsk, rep, NETLINK_CB(skb).portid); out: + release_sock(sk); + kfree_skb(rep); return err; } @@ -429,15 +425,15 @@ static void sctp_diag_get_info(struct sock *sk, struct inet_diag_msg *r, static int sctp_diag_dump_one(struct netlink_callback *cb, const struct inet_diag_req_v2 *req) { - struct sk_buff *in_skb = cb->skb; - struct net *net = sock_net(in_skb->sk); + struct sk_buff *skb = cb->skb; + struct net *net = sock_net(skb->sk); const struct nlmsghdr *nlh = cb->nlh; union sctp_addr laddr, paddr; struct sctp_comm_param commp = { - .skb = in_skb, + .skb = skb, .r = req, .nlh = nlh, - .net_admin = netlink_net_capable(in_skb, CAP_NET_ADMIN), + .net_admin = netlink_net_capable(skb, CAP_NET_ADMIN), }; if (req->sdiag_family == AF_INET) { @@ -460,7 +456,7 @@ static int sctp_diag_dump_one(struct netlink_callback *cb, paddr.v6.sin6_family = AF_INET6; } - return sctp_transport_lookup_process(sctp_tsp_dump_one, + return sctp_transport_lookup_process(sctp_sock_dump_one, net, &laddr, &paddr, &commp); } diff --git a/net/sctp/socket.c b/net/sctp/socket.c index ad5028a07b183..da08671a3f801 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -5317,23 +5317,31 @@ int sctp_for_each_endpoint(int (*cb)(struct sctp_endpoint *, void *), } EXPORT_SYMBOL_GPL(sctp_for_each_endpoint); -int sctp_transport_lookup_process(int (*cb)(struct sctp_transport *, void *), - struct net *net, +int sctp_transport_lookup_process(sctp_callback_t cb, struct net *net, const union sctp_addr *laddr, const union sctp_addr *paddr, void *p) { struct sctp_transport *transport; - int err; + struct sctp_endpoint *ep; + int err = -ENOENT; rcu_read_lock(); transport = sctp_addrs_lookup_transport(net, laddr, paddr); + if (!transport) { + rcu_read_unlock(); + return err; + } + ep = transport->asoc->ep; + if (!sctp_endpoint_hold(ep)) { /* asoc can be peeled off */ + sctp_transport_put(transport); + rcu_read_unlock(); + return err; + } rcu_read_unlock(); - if (!transport) - return -ENOENT; - err = cb(transport, p); + err = cb(ep, transport, p); + sctp_endpoint_put(ep); sctp_transport_put(transport); - return err; } EXPORT_SYMBOL_GPL(sctp_transport_lookup_process); -- GitLab From 29262e1f773b4b6a43711120be564c57fca07cfb Mon Sep 17 00:00:00 2001 From: Thomas Toye Date: Sat, 1 Jan 2022 18:22:07 +0100 Subject: [PATCH 909/965] rndis_host: support Hytera digital radios Hytera makes a range of digital (DMR) radios. These radios can be programmed to a allow a computer to control them over Ethernet over USB, either using NCM or RNDIS. This commit adds support for RNDIS for Hytera radios. I tested with a Hytera PD785 and a Hytera MD785G. When these radios are programmed to set up a Radio to PC Network using RNDIS, an USB interface will be added with class 2 (Communications), subclass 2 (Abstract Modem Control) and an interface protocol of 255 ("vendor specific" - lsusb even hints "MSFT RNDIS?"). This patch is similar to the solution of this StackOverflow user, but that only works for the Hytera MD785: https://stackoverflow.com/a/53550858 To use the "Radio to PC Network" functionality of Hytera DMR radios, the radios need to be programmed correctly in CPS (Hytera's Customer Programming Software). "Forward to PC" should be checked in "Network" (under "General Setting" in "Conventional") and the "USB Network Communication Protocol" should be set to RNDIS. Signed-off-by: Thomas Toye Signed-off-by: David S. Miller --- drivers/net/usb/rndis_host.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c index 4a84f90e377c4..247f58cb0f84e 100644 --- a/drivers/net/usb/rndis_host.c +++ b/drivers/net/usb/rndis_host.c @@ -608,6 +608,11 @@ static const struct usb_device_id products [] = { USB_DEVICE_AND_INTERFACE_INFO(0x1630, 0x0042, USB_CLASS_COMM, 2 /* ACM */, 0x0ff), .driver_info = (unsigned long) &rndis_poll_status_info, +}, { + /* Hytera Communications DMR radios' "Radio to PC Network" */ + USB_VENDOR_AND_INTERFACE_INFO(0x238b, + USB_CLASS_COMM, 2 /* ACM */, 0x0ff), + .driver_info = (unsigned long)&rndis_info, }, { /* RNDIS is MSFT's un-official variant of CDC ACM */ USB_INTERFACE_INFO(USB_CLASS_COMM, 2 /* ACM */, 0x0ff), -- GitLab From 1ef5e1d0dca5b4ffd49d7dec4a83660882f1fda4 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Sun, 2 Jan 2022 17:54:08 +0100 Subject: [PATCH 910/965] net/fsl: Remove leftover definition in xgmac_mdio commit 26eee0210ad7 ("net/fsl: fix a bug in xgmac_mdio") fixed a bug in the QorIQ mdio driver but left the (now unused) incorrect bit definition for MDIO_DATA_BSY in the code. This commit removes it. Signed-off-by: Markus Koch Signed-off-by: David S. Miller --- drivers/net/ethernet/freescale/xgmac_mdio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/freescale/xgmac_mdio.c b/drivers/net/ethernet/freescale/xgmac_mdio.c index 0b68852379da5..5b8b9bcf41a25 100644 --- a/drivers/net/ethernet/freescale/xgmac_mdio.c +++ b/drivers/net/ethernet/freescale/xgmac_mdio.c @@ -47,7 +47,6 @@ struct tgec_mdio_controller { #define MDIO_CTL_READ BIT(15) #define MDIO_DATA(x) (x & 0xffff) -#define MDIO_DATA_BSY BIT(31) struct mdio_fsl_priv { struct tgec_mdio_controller __iomem *mdio_base; -- GitLab From e5a7431f5a2d6dcff7d516ee9d178a3254b17b87 Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Tue, 14 Dec 2021 12:02:38 +0800 Subject: [PATCH 911/965] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins). The hwirq base for each sgpio bank should be multiples of 64 rather than multiples of 32. Signed-off-by: Steven Lee Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-aspeed-sgpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index 3d6ef37a7702a..b3a9b8488f11d 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc) reg = ioread32(bank_reg(data, bank, reg_irq_status)); for_each_set_bit(p, ®, 32) - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2); + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); } chained_irq_exit(ic, desc); -- GitLab From 32e246b02f53b2fdaa81ea9f2ca6ff068c017fcb Mon Sep 17 00:00:00 2001 From: Gregory Fong Date: Mon, 3 Jan 2022 10:53:02 +0100 Subject: [PATCH 912/965] MAINTAINERS: update gpio-brcmstb maintainers Add Doug and Florian as maintainers for gpio-brcmstb, and remove myself. Signed-off-by: Gregory Fong Signed-off-by: Bartosz Golaszewski --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fb18ce7168aa7..dd36acc87ce62 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3769,7 +3769,8 @@ S: Supported F: drivers/net/wireless/broadcom/brcm80211/ BROADCOM BRCMSTB GPIO DRIVER -M: Gregory Fong +M: Doug Berger +M: Florian Fainelli L: bcm-kernel-feedback-list@broadcom.com S: Supported F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt -- GitLab From e30a845b0376eb51c9c94f56bbd53b2e08ba822f Mon Sep 17 00:00:00 2001 From: David Ahern Date: Mon, 3 Jan 2022 10:19:11 -0700 Subject: [PATCH 913/965] ipv6: Continue processing multipath route even if gateway attribute is invalid ip6_route_multipath_del loop continues processing the multipath attribute even if delete of a nexthop path fails. For consistency, do the same if the gateway attribute is invalid. Fixes: 1ff15a710a86 ("ipv6: Check attribute length for RTA_GATEWAY when deleting multipath route") Signed-off-by: David Ahern Acked-by: Nicolas Dichtel Link: https://lore.kernel.org/r/20220103171911.94739-1-dsahern@kernel.org Signed-off-by: Jakub Kicinski --- net/ipv6/route.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/ipv6/route.c b/net/ipv6/route.c index d2ff8a7e17094..087df86c15d18 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -5459,8 +5459,10 @@ static int ip6_route_multipath_del(struct fib6_config *cfg, if (nla) { err = fib6_gw_from_attr(&r_cfg.fc_gateway, nla, extack); - if (err) - return err; + if (err) { + last_err = err; + goto next_rtnh; + } r_cfg.fc_flags |= RTF_GATEWAY; } @@ -5469,6 +5471,7 @@ static int ip6_route_multipath_del(struct fib6_config *cfg, if (err) last_err = err; +next_rtnh: rtnh = rtnh_next(rtnh, &remaining); } -- GitLab From 95bdba23b5b4aa75fe3e6c84335e638641c707bb Mon Sep 17 00:00:00 2001 From: David Ahern Date: Mon, 3 Jan 2022 10:05:55 -0700 Subject: [PATCH 914/965] ipv6: Do cleanup if attribute validation fails in multipath route As Nicolas noted, if gateway validation fails walking the multipath attribute the code should jump to the cleanup to free previously allocated memory. Fixes: 1ff15a710a86 ("ipv6: Check attribute length for RTA_GATEWAY when deleting multipath route") Signed-off-by: David Ahern Acked-by: Nicolas Dichtel Link: https://lore.kernel.org/r/20220103170555.94638-1-dsahern@kernel.org Signed-off-by: Jakub Kicinski --- net/ipv6/route.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/net/ipv6/route.c b/net/ipv6/route.c index 087df86c15d18..1deb6297aab66 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -5277,12 +5277,10 @@ static int ip6_route_multipath_add(struct fib6_config *cfg, nla = nla_find(attrs, attrlen, RTA_GATEWAY); if (nla) { - int ret; - - ret = fib6_gw_from_attr(&r_cfg.fc_gateway, nla, + err = fib6_gw_from_attr(&r_cfg.fc_gateway, nla, extack); - if (ret) - return ret; + if (err) + goto cleanup; r_cfg.fc_flags |= RTF_GATEWAY; } -- GitLab From 46669e8616c649c71c4cfcd712fd3d107e771380 Mon Sep 17 00:00:00 2001 From: Song Liu Date: Mon, 3 Jan 2022 13:49:36 -0800 Subject: [PATCH 915/965] md/raid1: fix missing bitmap update w/o WriteMostly devices commit [1] causes missing bitmap updates when there isn't any WriteMostly devices. Detailed steps to reproduce by Norbert (which somehow didn't make to lore): # setup md10 (raid1) with two drives (1 GByte sparse files) dd if=/dev/zero of=disk1 bs=1024k seek=1024 count=0 dd if=/dev/zero of=disk2 bs=1024k seek=1024 count=0 losetup /dev/loop11 disk1 losetup /dev/loop12 disk2 mdadm --create /dev/md10 --level=1 --raid-devices=2 /dev/loop11 /dev/loop12 # add bitmap (aka write-intent log) mdadm /dev/md10 --grow --bitmap=internal echo check > /sys/block/md10/md/sync_action root:# cat /sys/block/md10/md/mismatch_cnt 0 root:# # remove member drive disk2 (loop12) mdadm /dev/md10 -f loop12 ; mdadm /dev/md10 -r loop12 # modify degraded md device dd if=/dev/urandom of=/dev/md10 bs=512 count=1 # no blocks recorded as out of sync on the remaining member disk1/loop11 root:# mdadm -X /dev/loop11 | grep Bitmap Bitmap : 16 bits (chunks), 0 dirty (0.0%) root:# # re-add disk2, nothing synced because of empty bitmap mdadm /dev/md10 --re-add /dev/loop12 # check integrity again echo check > /sys/block/md10/md/sync_action # disk1 and disk2 are no longer in sync, reads return differend data root:# cat /sys/block/md10/md/mismatch_cnt 128 root:# # clean up mdadm -S /dev/md10 losetup -d /dev/loop11 losetup -d /dev/loop12 rm disk1 disk2 Fix this by moving the WriteMostly check to the if condition for alloc_behind_master_bio(). [1] commit fd3b6975e9c1 ("md/raid1: only allocate write behind bio for WriteMostly device") Fixes: fd3b6975e9c1 ("md/raid1: only allocate write behind bio for WriteMostly device") Cc: stable@vger.kernel.org # v5.12+ Cc: Guoqing Jiang Cc: Jens Axboe Reported-by: Norbert Warmuth Suggested-by: Linus Torvalds Signed-off-by: Song Liu --- drivers/md/raid1.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index 7dc8026cf6ee0..85505424f7a48 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -1496,12 +1496,13 @@ static void raid1_write_request(struct mddev *mddev, struct bio *bio, if (!r1_bio->bios[i]) continue; - if (first_clone && test_bit(WriteMostly, &rdev->flags)) { + if (first_clone) { /* do behind I/O ? * Not if there are too many, or cannot * allocate memory, or a reader on WriteMostly * is waiting for behind writes to flush */ if (bitmap && + test_bit(WriteMostly, &rdev->flags) && (atomic_read(&bitmap->behind_writes) < mddev->bitmap_info.max_write_behind) && !waitqueue_active(&bitmap->behind_wait)) { -- GitLab From 065e1ae02fbe5f56f4aa118414d45fc30647acd4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 3 Jan 2022 11:34:52 -0800 Subject: [PATCH 916/965] Revert "net: phy: fixed_phy: Fix NULL vs IS_ERR() checking in __fixed_phy_register" This reverts commit b45396afa4177f2b1ddfeff7185da733fade1dc3 ("net: phy: fixed_phy: Fix NULL vs IS_ERR() checking in __fixed_phy_register") since it prevents any system that uses a fixed PHY without a GPIO descriptor from properly working: [ 5.971952] brcm-systemport 9300000.ethernet: failed to register fixed PHY [ 5.978854] brcm-systemport: probe of 9300000.ethernet failed with error -22 [ 5.986047] brcm-systemport 9400000.ethernet: failed to register fixed PHY [ 5.992947] brcm-systemport: probe of 9400000.ethernet failed with error -22 Fixes: b45396afa417 ("net: phy: fixed_phy: Fix NULL vs IS_ERR() checking in __fixed_phy_register") Signed-off-by: Florian Fainelli Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20220103193453.1214961-1-f.fainelli@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/phy/fixed_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/fixed_phy.c b/drivers/net/phy/fixed_phy.c index a0c256bd54417..c65fb5f5d2dc5 100644 --- a/drivers/net/phy/fixed_phy.c +++ b/drivers/net/phy/fixed_phy.c @@ -239,8 +239,8 @@ static struct phy_device *__fixed_phy_register(unsigned int irq, /* Check if we have a GPIO associated with this fixed phy */ if (!gpiod) { gpiod = fixed_phy_get_gpiod(np); - if (!gpiod) - return ERR_PTR(-EINVAL); + if (IS_ERR(gpiod)) + return ERR_CAST(gpiod); } /* Get the next available PHY address, up to PHY_MAX_ADDR */ -- GitLab From fa55a7d745de2d10489295b0674a403e2a5d490d Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 3 Jan 2022 18:11:30 +0100 Subject: [PATCH 917/965] seg6: export get_srh() for ICMP handling An ICMP error message can contain in its message body part of an IPv6 packet which invoked the error. Such a packet might contain a segment router header. Export get_srh() so the ICMP code can make use of it. Since his changes the scope of the function from local to global, add the seg6_ prefix to keep the namespace clean. And move it into seg6.c so it is always available, not just when IPV6_SEG6_LWTUNNEL is enabled. Signed-off-by: Andrew Lunn Reviewed-by: David Ahern Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller --- include/net/seg6.h | 1 + net/ipv6/seg6.c | 29 +++++++++++++++++++++++++++++ net/ipv6/seg6_local.c | 33 ++------------------------------- 3 files changed, 32 insertions(+), 31 deletions(-) diff --git a/include/net/seg6.h b/include/net/seg6.h index 9d19c15e8545c..a6f25983670aa 100644 --- a/include/net/seg6.h +++ b/include/net/seg6.h @@ -58,6 +58,7 @@ extern int seg6_local_init(void); extern void seg6_local_exit(void); extern bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced); +extern struct ipv6_sr_hdr *seg6_get_srh(struct sk_buff *skb, int flags); extern int seg6_do_srh_encap(struct sk_buff *skb, struct ipv6_sr_hdr *osrh, int proto); extern int seg6_do_srh_inline(struct sk_buff *skb, struct ipv6_sr_hdr *osrh); diff --git a/net/ipv6/seg6.c b/net/ipv6/seg6.c index a8b5784afb1ae..5bc9bf8921992 100644 --- a/net/ipv6/seg6.c +++ b/net/ipv6/seg6.c @@ -75,6 +75,35 @@ bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced) return true; } +struct ipv6_sr_hdr *seg6_get_srh(struct sk_buff *skb, int flags) +{ + struct ipv6_sr_hdr *srh; + int len, srhoff = 0; + + if (ipv6_find_hdr(skb, &srhoff, IPPROTO_ROUTING, NULL, &flags) < 0) + return NULL; + + if (!pskb_may_pull(skb, srhoff + sizeof(*srh))) + return NULL; + + srh = (struct ipv6_sr_hdr *)(skb->data + srhoff); + + len = (srh->hdrlen + 1) << 3; + + if (!pskb_may_pull(skb, srhoff + len)) + return NULL; + + /* note that pskb_may_pull may change pointers in header; + * for this reason it is necessary to reload them when needed. + */ + srh = (struct ipv6_sr_hdr *)(skb->data + srhoff); + + if (!seg6_validate_srh(srh, len, true)) + return NULL; + + return srh; +} + static struct genl_family seg6_genl_family; static const struct nla_policy seg6_genl_policy[SEG6_ATTR_MAX + 1] = { diff --git a/net/ipv6/seg6_local.c b/net/ipv6/seg6_local.c index 2dc40b3f373ef..ef88489c71f52 100644 --- a/net/ipv6/seg6_local.c +++ b/net/ipv6/seg6_local.c @@ -150,40 +150,11 @@ static struct seg6_local_lwt *seg6_local_lwtunnel(struct lwtunnel_state *lwt) return (struct seg6_local_lwt *)lwt->data; } -static struct ipv6_sr_hdr *get_srh(struct sk_buff *skb, int flags) -{ - struct ipv6_sr_hdr *srh; - int len, srhoff = 0; - - if (ipv6_find_hdr(skb, &srhoff, IPPROTO_ROUTING, NULL, &flags) < 0) - return NULL; - - if (!pskb_may_pull(skb, srhoff + sizeof(*srh))) - return NULL; - - srh = (struct ipv6_sr_hdr *)(skb->data + srhoff); - - len = (srh->hdrlen + 1) << 3; - - if (!pskb_may_pull(skb, srhoff + len)) - return NULL; - - /* note that pskb_may_pull may change pointers in header; - * for this reason it is necessary to reload them when needed. - */ - srh = (struct ipv6_sr_hdr *)(skb->data + srhoff); - - if (!seg6_validate_srh(srh, len, true)) - return NULL; - - return srh; -} - static struct ipv6_sr_hdr *get_and_validate_srh(struct sk_buff *skb) { struct ipv6_sr_hdr *srh; - srh = get_srh(skb, IP6_FH_F_SKIP_RH); + srh = seg6_get_srh(skb, IP6_FH_F_SKIP_RH); if (!srh) return NULL; @@ -200,7 +171,7 @@ static bool decap_and_validate(struct sk_buff *skb, int proto) struct ipv6_sr_hdr *srh; unsigned int off = 0; - srh = get_srh(skb, 0); + srh = seg6_get_srh(skb, 0); if (srh && srh->segments_left > 0) return false; -- GitLab From e41294408c56c68ea0f269d757527bf33b39118a Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 3 Jan 2022 18:11:31 +0100 Subject: [PATCH 918/965] icmp: ICMPV6: Examine invoking packet for Segment Route Headers. RFC8754 says: ICMP error packets generated within the SR domain are sent to source nodes within the SR domain. The invoking packet in the ICMP error message may contain an SRH. Since the destination address of a packet with an SRH changes as each segment is processed, it may not be the destination used by the socket or application that generated the invoking packet. For the source of an invoking packet to process the ICMP error message, the ultimate destination address of the IPv6 header may be required. The following logic is used to determine the destination address for use by protocol-error handlers. * Walk all extension headers of the invoking IPv6 packet to the routing extension header preceding the upper-layer header. - If routing header is type 4 Segment Routing Header (SRH) o The SID at Segment List[0] may be used as the destination address of the invoking packet. Mangle the skb so the network header points to the invoking packet inside the ICMP packet. The seg6 helpers can then be used on the skb to find any segment routing headers. If found, mark this fact in the IPv6 control block of the skb, and store the offset into the packet of the SRH. Then restore the skb back to its old state. Signed-off-by: Andrew Lunn Reviewed-by: David Ahern Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller --- include/linux/ipv6.h | 2 ++ include/net/seg6.h | 1 + net/ipv6/icmp.c | 6 +++++- net/ipv6/seg6.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 20c1f968da7c1..a59d25f193857 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -133,6 +133,7 @@ struct inet6_skb_parm { __u16 dsthao; #endif __u16 frag_max_size; + __u16 srhoff; #define IP6SKB_XFRM_TRANSFORMED 1 #define IP6SKB_FORWARDED 2 @@ -142,6 +143,7 @@ struct inet6_skb_parm { #define IP6SKB_HOPBYHOP 32 #define IP6SKB_L3SLAVE 64 #define IP6SKB_JUMBOGRAM 128 +#define IP6SKB_SEG6 256 }; #if defined(CONFIG_NET_L3_MASTER_DEV) diff --git a/include/net/seg6.h b/include/net/seg6.h index a6f25983670aa..02b0cd3057876 100644 --- a/include/net/seg6.h +++ b/include/net/seg6.h @@ -59,6 +59,7 @@ extern void seg6_local_exit(void); extern bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced); extern struct ipv6_sr_hdr *seg6_get_srh(struct sk_buff *skb, int flags); +extern void seg6_icmp_srh(struct sk_buff *skb, struct inet6_skb_parm *opt); extern int seg6_do_srh_encap(struct sk_buff *skb, struct ipv6_sr_hdr *osrh, int proto); extern int seg6_do_srh_inline(struct sk_buff *skb, struct ipv6_sr_hdr *osrh); diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index a7c31ab67c5d6..96c5cc0f30ceb 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -820,6 +821,7 @@ out_bh_enable: void icmpv6_notify(struct sk_buff *skb, u8 type, u8 code, __be32 info) { + struct inet6_skb_parm *opt = IP6CB(skb); const struct inet6_protocol *ipprot; int inner_offset; __be16 frag_off; @@ -829,6 +831,8 @@ void icmpv6_notify(struct sk_buff *skb, u8 type, u8 code, __be32 info) if (!pskb_may_pull(skb, sizeof(struct ipv6hdr))) goto out; + seg6_icmp_srh(skb, opt); + nexthdr = ((struct ipv6hdr *)skb->data)->nexthdr; if (ipv6_ext_hdr(nexthdr)) { /* now skip over extension headers */ @@ -853,7 +857,7 @@ void icmpv6_notify(struct sk_buff *skb, u8 type, u8 code, __be32 info) ipprot = rcu_dereference(inet6_protos[nexthdr]); if (ipprot && ipprot->err_handler) - ipprot->err_handler(skb, NULL, type, code, inner_offset, info); + ipprot->err_handler(skb, opt, type, code, inner_offset, info); raw6_icmp_error(skb, nexthdr, type, code, inner_offset, info); return; diff --git a/net/ipv6/seg6.c b/net/ipv6/seg6.c index 5bc9bf8921992..73aaabf0e9665 100644 --- a/net/ipv6/seg6.c +++ b/net/ipv6/seg6.c @@ -104,6 +104,36 @@ struct ipv6_sr_hdr *seg6_get_srh(struct sk_buff *skb, int flags) return srh; } +/* Determine if an ICMP invoking packet contains a segment routing + * header. If it does, extract the offset to the true destination + * address, which is in the first segment address. + */ +void seg6_icmp_srh(struct sk_buff *skb, struct inet6_skb_parm *opt) +{ + __u16 network_header = skb->network_header; + struct ipv6_sr_hdr *srh; + + /* Update network header to point to the invoking packet + * inside the ICMP packet, so we can use the seg6_get_srh() + * helper. + */ + skb_reset_network_header(skb); + + srh = seg6_get_srh(skb, 0); + if (!srh) + goto out; + + if (srh->type != IPV6_SRCRT_TYPE_4) + goto out; + + opt->flags |= IP6SKB_SEG6; + opt->srhoff = (unsigned char *)srh - skb->data; + +out: + /* Restore the network header back to the ICMP packet */ + skb->network_header = network_header; +} + static struct genl_family seg6_genl_family; static const struct nla_policy seg6_genl_policy[SEG6_ATTR_MAX + 1] = { -- GitLab From 222a011efc839ca1f51bf89fe7a2b3705fa55ccd Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 3 Jan 2022 18:11:32 +0100 Subject: [PATCH 919/965] udp6: Use Segment Routing Header for dest address if present When finding the socket to report an error on, if the invoking packet is using Segment Routing, the IPv6 destination address is that of an intermediate router, not the end destination. Extract the ultimate destination address from the segment address. This change allows traceroute to function in the presence of Segment Routing. Signed-off-by: Andrew Lunn Reviewed-by: David Ahern Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller --- include/net/seg6.h | 19 +++++++++++++++++++ net/ipv6/udp.c | 3 ++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/include/net/seg6.h b/include/net/seg6.h index 02b0cd3057876..af668f17b3988 100644 --- a/include/net/seg6.h +++ b/include/net/seg6.h @@ -65,4 +65,23 @@ extern int seg6_do_srh_encap(struct sk_buff *skb, struct ipv6_sr_hdr *osrh, extern int seg6_do_srh_inline(struct sk_buff *skb, struct ipv6_sr_hdr *osrh); extern int seg6_lookup_nexthop(struct sk_buff *skb, struct in6_addr *nhaddr, u32 tbl_id); + +/* If the packet which invoked an ICMP error contains an SRH return + * the true destination address from within the SRH, otherwise use the + * destination address in the IP header. + */ +static inline const struct in6_addr *seg6_get_daddr(struct sk_buff *skb, + struct inet6_skb_parm *opt) +{ + struct ipv6_sr_hdr *srh; + + if (opt->flags & IP6SKB_SEG6) { + srh = (struct ipv6_sr_hdr *)(skb->data + opt->srhoff); + return &srh->segments[0]; + } + + return NULL; +} + + #endif diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index 8cde9efd79198..a0871c212741c 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -561,7 +562,7 @@ int __udp6_lib_err(struct sk_buff *skb, struct inet6_skb_parm *opt, struct ipv6_pinfo *np; const struct ipv6hdr *hdr = (const struct ipv6hdr *)skb->data; const struct in6_addr *saddr = &hdr->saddr; - const struct in6_addr *daddr = &hdr->daddr; + const struct in6_addr *daddr = seg6_get_daddr(skb, opt) ? : &hdr->daddr; struct udphdr *uh = (struct udphdr *)(skb->data+offset); bool tunnel = false; struct sock *sk; -- GitLab From 3087a6f36ee028ec095c04a8531d7d33899b7fed Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 4 Jan 2022 10:21:26 +0100 Subject: [PATCH 920/965] netrom: fix copying in user data in nr_setsockopt This code used to copy in an unsigned long worth of data before the sockptr_t conversion, so restore that. Fixes: a7b75c5a8c41 ("net: pass a sockptr_t into ->setsockopt") Reported-by: Dan Carpenter Signed-off-by: Christoph Hellwig Signed-off-by: David S. Miller --- net/netrom/af_netrom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netrom/af_netrom.c b/net/netrom/af_netrom.c index 775064cdd0ee4..f1ba7dd3d253d 100644 --- a/net/netrom/af_netrom.c +++ b/net/netrom/af_netrom.c @@ -306,7 +306,7 @@ static int nr_setsockopt(struct socket *sock, int level, int optname, if (optlen < sizeof(unsigned int)) return -EINVAL; - if (copy_from_sockptr(&opt, optval, sizeof(unsigned int))) + if (copy_from_sockptr(&opt, optval, sizeof(unsigned long))) return -EFAULT; switch (optname) { -- GitLab From 7d18a07897d07495ee140dd319b0e9265c0f68ba Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 4 Jan 2022 01:45:08 -0800 Subject: [PATCH 921/965] sch_qfq: prevent shift-out-of-bounds in qfq_init_qdisc tx_queue_len can be set to ~0U, we need to be more careful about overflows. __fls(0) is undefined, as this report shows: UBSAN: shift-out-of-bounds in net/sched/sch_qfq.c:1430:24 shift exponent 51770272 is too large for 32-bit type 'int' CPU: 0 PID: 25574 Comm: syz-executor.0 Not tainted 5.16.0-rc7-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x201/0x2d8 lib/dump_stack.c:106 ubsan_epilogue lib/ubsan.c:151 [inline] __ubsan_handle_shift_out_of_bounds+0x494/0x530 lib/ubsan.c:330 qfq_init_qdisc+0x43f/0x450 net/sched/sch_qfq.c:1430 qdisc_create+0x895/0x1430 net/sched/sch_api.c:1253 tc_modify_qdisc+0x9d9/0x1e20 net/sched/sch_api.c:1660 rtnetlink_rcv_msg+0x934/0xe60 net/core/rtnetlink.c:5571 netlink_rcv_skb+0x200/0x470 net/netlink/af_netlink.c:2496 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline] netlink_unicast+0x814/0x9f0 net/netlink/af_netlink.c:1345 netlink_sendmsg+0xaea/0xe60 net/netlink/af_netlink.c:1921 sock_sendmsg_nosec net/socket.c:704 [inline] sock_sendmsg net/socket.c:724 [inline] ____sys_sendmsg+0x5b9/0x910 net/socket.c:2409 ___sys_sendmsg net/socket.c:2463 [inline] __sys_sendmsg+0x280/0x370 net/socket.c:2492 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x44/0xd0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x44/0xae Fixes: 462dbc9101ac ("pkt_sched: QFQ Plus: fair-queueing service at DRR cost") Signed-off-by: Eric Dumazet Reported-by: syzbot Signed-off-by: David S. Miller --- net/sched/sch_qfq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index 0b7f9ba28deb0..d4ce58c90f9fb 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -1421,10 +1421,8 @@ static int qfq_init_qdisc(struct Qdisc *sch, struct nlattr *opt, if (err < 0) return err; - if (qdisc_dev(sch)->tx_queue_len + 1 > QFQ_MAX_AGG_CLASSES) - max_classes = QFQ_MAX_AGG_CLASSES; - else - max_classes = qdisc_dev(sch)->tx_queue_len + 1; + max_classes = min_t(u64, (u64)qdisc_dev(sch)->tx_queue_len + 1, + QFQ_MAX_AGG_CLASSES); /* max_cl_shift = floor(log_2(max_classes)) */ max_cl_shift = __fls(max_classes); q->max_agg_classes = 1< Date: Tue, 4 Jan 2022 13:34:12 +0000 Subject: [PATCH 922/965] perf/smmuv3: Fix unused variable warning when CONFIG_OF=n The kbuild robot reports that building the SMMUv3 PMU driver with CONFIG_OF=n results in a warning for W=1 builds: >> drivers/perf/arm_smmuv3_pmu.c:889:34: warning: unused variable 'smmu_pmu_of_match' [-Wunused-const-variable] static const struct of_device_id smmu_pmu_of_match[] = { ^ Guard the match table with #ifdef CONFIG_OF. Link: https://lore.kernel.org/r/202201041700.01KZEzhb-lkp@intel.com Fixes: 3f7be4356176 ("perf/smmuv3: Add devicetree support") Reported-by: kernel test robot Signed-off-by: Will Deacon --- drivers/perf/arm_smmuv3_pmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 598d6978280d8..1ae19f7301b29 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -939,11 +939,13 @@ static void smmu_pmu_shutdown(struct platform_device *pdev) smmu_pmu_disable(&smmu_pmu->pmu); } +#ifdef CONFIG_OF static const struct of_device_id smmu_pmu_of_match[] = { { .compatible = "arm,smmu-v3-pmcg" }, {} }; MODULE_DEVICE_TABLE(of, smmu_pmu_of_match); +#endif static struct platform_driver smmu_pmu_driver = { .driver = { -- GitLab From 2da56881a7f8fdd887e6c2d250db58f1abdad0b6 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 17 Dec 2021 17:59:08 +0300 Subject: [PATCH 923/965] drivers: perf: marvell_cn10k: fix an IS_ERR() vs NULL check The devm_ioremap() function does not return error pointers. It returns NULL. Fixes: 036a7584bede ("drivers: perf: Add LLC-TAD perf counter support") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20211217145907.GA16611@kili Signed-off-by: Will Deacon --- drivers/perf/marvell_cn10k_tad_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c index 250dd4c52d705..7f4d292658e32 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -312,7 +312,7 @@ static int tad_pmu_probe(struct platform_device *pdev) regions[i].base = devm_ioremap(&pdev->dev, res->start, tad_pmu_page_size); - if (IS_ERR(regions[i].base)) { + if (!regions[i].base) { dev_err(&pdev->dev, "TAD%d ioremap fail\n", i); return -ENOMEM; } -- GitLab From 68a18ad71378a56858141c4449e02a30c829763e Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Thu, 23 Dec 2021 08:28:48 -0800 Subject: [PATCH 924/965] mac80211: initialize variable have_higher_than_11mbit Clang static analysis reports this warnings mlme.c:5332:7: warning: Branch condition evaluates to a garbage value have_higher_than_11mbit) ^~~~~~~~~~~~~~~~~~~~~~~ have_higher_than_11mbit is only set to true some of the time in ieee80211_get_rates() but is checked all of the time. So have_higher_than_11mbit needs to be initialized to false. Fixes: 5d6a1b069b7f ("mac80211: set basic rates earlier") Signed-off-by: Tom Rix Reviewed-by: Nick Desaulniers Link: https://lore.kernel.org/r/20211223162848.3243702-1-trix@redhat.com Signed-off-by: Johannes Berg --- net/mac80211/mlme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 37f7d975f3dac..3147ca89f608e 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -5265,7 +5265,7 @@ static int ieee80211_prep_connection(struct ieee80211_sub_if_data *sdata, */ if (new_sta) { u32 rates = 0, basic_rates = 0; - bool have_higher_than_11mbit; + bool have_higher_than_11mbit = false; int min_rate = INT_MAX, min_rate_index = -1; const struct cfg80211_bss_ies *ies; int shift = ieee80211_vif_get_shift(&sdata->vif); -- GitLab From 8b5cb7e41d9d77ffca036b0239177de123394a55 Mon Sep 17 00:00:00 2001 From: Pavel Skripkin Date: Thu, 30 Dec 2021 22:55:47 +0300 Subject: [PATCH 925/965] mac80211: mesh: embedd mesh_paths and mpp_paths into ieee80211_if_mesh Syzbot hit NULL deref in rhashtable_free_and_destroy(). The problem was in mesh_paths and mpp_paths being NULL. mesh_pathtbl_init() could fail in case of memory allocation failure, but nobody cared, since ieee80211_mesh_init_sdata() returns void. It led to leaving 2 pointers as NULL. Syzbot has found null deref on exit path, but it could happen anywhere else, because code assumes these pointers are valid. Since all ieee80211_*_setup_sdata functions are void and do not fail, let's embedd mesh_paths and mpp_paths into parent struct to avoid adding error handling on higher levels and follow the pattern of others setup_sdata functions Fixes: 60854fd94573 ("mac80211: mesh: convert path table to rhashtable") Reported-and-tested-by: syzbot+860268315ba86ea6b96b@syzkaller.appspotmail.com Signed-off-by: Pavel Skripkin Link: https://lore.kernel.org/r/20211230195547.23977-1-paskripkin@gmail.com Signed-off-by: Johannes Berg --- net/mac80211/ieee80211_i.h | 24 +++++++++- net/mac80211/mesh.h | 22 +-------- net/mac80211/mesh_pathtbl.c | 89 +++++++++++++------------------------ 3 files changed, 54 insertions(+), 81 deletions(-) diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h index 5666bbb8860bb..482c98ede19bb 100644 --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h @@ -647,6 +647,26 @@ struct mesh_csa_settings { struct cfg80211_csa_settings settings; }; +/** + * struct mesh_table + * + * @known_gates: list of known mesh gates and their mpaths by the station. The + * gate's mpath may or may not be resolved and active. + * @gates_lock: protects updates to known_gates + * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr + * @walk_head: linked list containing all mesh_path objects + * @walk_lock: lock protecting walk_head + * @entries: number of entries in the table + */ +struct mesh_table { + struct hlist_head known_gates; + spinlock_t gates_lock; + struct rhashtable rhead; + struct hlist_head walk_head; + spinlock_t walk_lock; + atomic_t entries; /* Up to MAX_MESH_NEIGHBOURS */ +}; + struct ieee80211_if_mesh { struct timer_list housekeeping_timer; struct timer_list mesh_path_timer; @@ -721,8 +741,8 @@ struct ieee80211_if_mesh { /* offset from skb->data while building IE */ int meshconf_offset; - struct mesh_table *mesh_paths; - struct mesh_table *mpp_paths; /* Store paths for MPP&MAP */ + struct mesh_table mesh_paths; + struct mesh_table mpp_paths; /* Store paths for MPP&MAP */ int mesh_paths_generation; int mpp_paths_generation; }; diff --git a/net/mac80211/mesh.h b/net/mac80211/mesh.h index 77080b4f87b8a..b2b717a78114f 100644 --- a/net/mac80211/mesh.h +++ b/net/mac80211/mesh.h @@ -127,26 +127,6 @@ struct mesh_path { u32 path_change_count; }; -/** - * struct mesh_table - * - * @known_gates: list of known mesh gates and their mpaths by the station. The - * gate's mpath may or may not be resolved and active. - * @gates_lock: protects updates to known_gates - * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr - * @walk_head: linked list containing all mesh_path objects - * @walk_lock: lock protecting walk_head - * @entries: number of entries in the table - */ -struct mesh_table { - struct hlist_head known_gates; - spinlock_t gates_lock; - struct rhashtable rhead; - struct hlist_head walk_head; - spinlock_t walk_lock; - atomic_t entries; /* Up to MAX_MESH_NEIGHBOURS */ -}; - /* Recent multicast cache */ /* RMC_BUCKETS must be a power of 2, maximum 256 */ #define RMC_BUCKETS 256 @@ -308,7 +288,7 @@ int mesh_path_error_tx(struct ieee80211_sub_if_data *sdata, void mesh_path_assign_nexthop(struct mesh_path *mpath, struct sta_info *sta); void mesh_path_flush_pending(struct mesh_path *mpath); void mesh_path_tx_pending(struct mesh_path *mpath); -int mesh_pathtbl_init(struct ieee80211_sub_if_data *sdata); +void mesh_pathtbl_init(struct ieee80211_sub_if_data *sdata); void mesh_pathtbl_unregister(struct ieee80211_sub_if_data *sdata); int mesh_path_del(struct ieee80211_sub_if_data *sdata, const u8 *addr); void mesh_path_timer(struct timer_list *t); diff --git a/net/mac80211/mesh_pathtbl.c b/net/mac80211/mesh_pathtbl.c index 7cab1cf09bf1a..acc1c299f1ae5 100644 --- a/net/mac80211/mesh_pathtbl.c +++ b/net/mac80211/mesh_pathtbl.c @@ -47,32 +47,24 @@ static void mesh_path_rht_free(void *ptr, void *tblptr) mesh_path_free_rcu(tbl, mpath); } -static struct mesh_table *mesh_table_alloc(void) +static void mesh_table_init(struct mesh_table *tbl) { - struct mesh_table *newtbl; + INIT_HLIST_HEAD(&tbl->known_gates); + INIT_HLIST_HEAD(&tbl->walk_head); + atomic_set(&tbl->entries, 0); + spin_lock_init(&tbl->gates_lock); + spin_lock_init(&tbl->walk_lock); - newtbl = kmalloc(sizeof(struct mesh_table), GFP_ATOMIC); - if (!newtbl) - return NULL; - - INIT_HLIST_HEAD(&newtbl->known_gates); - INIT_HLIST_HEAD(&newtbl->walk_head); - atomic_set(&newtbl->entries, 0); - spin_lock_init(&newtbl->gates_lock); - spin_lock_init(&newtbl->walk_lock); - if (rhashtable_init(&newtbl->rhead, &mesh_rht_params)) { - kfree(newtbl); - return NULL; - } - - return newtbl; + /* rhashtable_init() may fail only in case of wrong + * mesh_rht_params + */ + WARN_ON(rhashtable_init(&tbl->rhead, &mesh_rht_params)); } static void mesh_table_free(struct mesh_table *tbl) { rhashtable_free_and_destroy(&tbl->rhead, mesh_path_rht_free, tbl); - kfree(tbl); } /** @@ -238,13 +230,13 @@ static struct mesh_path *mpath_lookup(struct mesh_table *tbl, const u8 *dst, struct mesh_path * mesh_path_lookup(struct ieee80211_sub_if_data *sdata, const u8 *dst) { - return mpath_lookup(sdata->u.mesh.mesh_paths, dst, sdata); + return mpath_lookup(&sdata->u.mesh.mesh_paths, dst, sdata); } struct mesh_path * mpp_path_lookup(struct ieee80211_sub_if_data *sdata, const u8 *dst) { - return mpath_lookup(sdata->u.mesh.mpp_paths, dst, sdata); + return mpath_lookup(&sdata->u.mesh.mpp_paths, dst, sdata); } static struct mesh_path * @@ -281,7 +273,7 @@ __mesh_path_lookup_by_idx(struct mesh_table *tbl, int idx) struct mesh_path * mesh_path_lookup_by_idx(struct ieee80211_sub_if_data *sdata, int idx) { - return __mesh_path_lookup_by_idx(sdata->u.mesh.mesh_paths, idx); + return __mesh_path_lookup_by_idx(&sdata->u.mesh.mesh_paths, idx); } /** @@ -296,7 +288,7 @@ mesh_path_lookup_by_idx(struct ieee80211_sub_if_data *sdata, int idx) struct mesh_path * mpp_path_lookup_by_idx(struct ieee80211_sub_if_data *sdata, int idx) { - return __mesh_path_lookup_by_idx(sdata->u.mesh.mpp_paths, idx); + return __mesh_path_lookup_by_idx(&sdata->u.mesh.mpp_paths, idx); } /** @@ -309,7 +301,7 @@ int mesh_path_add_gate(struct mesh_path *mpath) int err; rcu_read_lock(); - tbl = mpath->sdata->u.mesh.mesh_paths; + tbl = &mpath->sdata->u.mesh.mesh_paths; spin_lock_bh(&mpath->state_lock); if (mpath->is_gate) { @@ -418,7 +410,7 @@ struct mesh_path *mesh_path_add(struct ieee80211_sub_if_data *sdata, if (!new_mpath) return ERR_PTR(-ENOMEM); - tbl = sdata->u.mesh.mesh_paths; + tbl = &sdata->u.mesh.mesh_paths; spin_lock_bh(&tbl->walk_lock); mpath = rhashtable_lookup_get_insert_fast(&tbl->rhead, &new_mpath->rhash, @@ -460,7 +452,7 @@ int mpp_path_add(struct ieee80211_sub_if_data *sdata, return -ENOMEM; memcpy(new_mpath->mpp, mpp, ETH_ALEN); - tbl = sdata->u.mesh.mpp_paths; + tbl = &sdata->u.mesh.mpp_paths; spin_lock_bh(&tbl->walk_lock); ret = rhashtable_lookup_insert_fast(&tbl->rhead, @@ -489,7 +481,7 @@ int mpp_path_add(struct ieee80211_sub_if_data *sdata, void mesh_plink_broken(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - struct mesh_table *tbl = sdata->u.mesh.mesh_paths; + struct mesh_table *tbl = &sdata->u.mesh.mesh_paths; static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; struct mesh_path *mpath; @@ -548,7 +540,7 @@ static void __mesh_path_del(struct mesh_table *tbl, struct mesh_path *mpath) void mesh_path_flush_by_nexthop(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - struct mesh_table *tbl = sdata->u.mesh.mesh_paths; + struct mesh_table *tbl = &sdata->u.mesh.mesh_paths; struct mesh_path *mpath; struct hlist_node *n; @@ -563,7 +555,7 @@ void mesh_path_flush_by_nexthop(struct sta_info *sta) static void mpp_flush_by_proxy(struct ieee80211_sub_if_data *sdata, const u8 *proxy) { - struct mesh_table *tbl = sdata->u.mesh.mpp_paths; + struct mesh_table *tbl = &sdata->u.mesh.mpp_paths; struct mesh_path *mpath; struct hlist_node *n; @@ -597,8 +589,8 @@ static void table_flush_by_iface(struct mesh_table *tbl) */ void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata) { - table_flush_by_iface(sdata->u.mesh.mesh_paths); - table_flush_by_iface(sdata->u.mesh.mpp_paths); + table_flush_by_iface(&sdata->u.mesh.mesh_paths); + table_flush_by_iface(&sdata->u.mesh.mpp_paths); } /** @@ -644,7 +636,7 @@ int mesh_path_del(struct ieee80211_sub_if_data *sdata, const u8 *addr) /* flush relevant mpp entries first */ mpp_flush_by_proxy(sdata, addr); - err = table_path_del(sdata->u.mesh.mesh_paths, sdata, addr); + err = table_path_del(&sdata->u.mesh.mesh_paths, sdata, addr); sdata->u.mesh.mesh_paths_generation++; return err; } @@ -682,7 +674,7 @@ int mesh_path_send_to_gates(struct mesh_path *mpath) struct mesh_path *gate; bool copy = false; - tbl = sdata->u.mesh.mesh_paths; + tbl = &sdata->u.mesh.mesh_paths; rcu_read_lock(); hlist_for_each_entry_rcu(gate, &tbl->known_gates, gate_list) { @@ -762,29 +754,10 @@ void mesh_path_fix_nexthop(struct mesh_path *mpath, struct sta_info *next_hop) mesh_path_tx_pending(mpath); } -int mesh_pathtbl_init(struct ieee80211_sub_if_data *sdata) +void mesh_pathtbl_init(struct ieee80211_sub_if_data *sdata) { - struct mesh_table *tbl_path, *tbl_mpp; - int ret; - - tbl_path = mesh_table_alloc(); - if (!tbl_path) - return -ENOMEM; - - tbl_mpp = mesh_table_alloc(); - if (!tbl_mpp) { - ret = -ENOMEM; - goto free_path; - } - - sdata->u.mesh.mesh_paths = tbl_path; - sdata->u.mesh.mpp_paths = tbl_mpp; - - return 0; - -free_path: - mesh_table_free(tbl_path); - return ret; + mesh_table_init(&sdata->u.mesh.mesh_paths); + mesh_table_init(&sdata->u.mesh.mpp_paths); } static @@ -806,12 +779,12 @@ void mesh_path_tbl_expire(struct ieee80211_sub_if_data *sdata, void mesh_path_expire(struct ieee80211_sub_if_data *sdata) { - mesh_path_tbl_expire(sdata, sdata->u.mesh.mesh_paths); - mesh_path_tbl_expire(sdata, sdata->u.mesh.mpp_paths); + mesh_path_tbl_expire(sdata, &sdata->u.mesh.mesh_paths); + mesh_path_tbl_expire(sdata, &sdata->u.mesh.mpp_paths); } void mesh_pathtbl_unregister(struct ieee80211_sub_if_data *sdata) { - mesh_table_free(sdata->u.mesh.mesh_paths); - mesh_table_free(sdata->u.mesh.mpp_paths); + mesh_table_free(&sdata->u.mesh.mesh_paths); + mesh_table_free(&sdata->u.mesh.mpp_paths); } -- GitLab From 8ff5f5d9d8cfce6a1e368a6daa7123be133a6c35 Mon Sep 17 00:00:00 2001 From: Li Zhijian Date: Tue, 28 Dec 2021 09:44:06 +0800 Subject: [PATCH 926/965] RDMA/rxe: Prevent double freeing rxe_map_set() The same rxe_map_set could be freed twice: rxe_reg_user_mr() -> rxe_mr_init_user() -> rxe_mr_free_map_set() # 1st -> rxe_drop_ref() ... -> rxe_mr_cleanup() -> rxe_mr_free_map_set() # 2nd Follow normal convection and put resource cleanup either in the error unwind of the allocator, or the overall free function. Leave the object unchanged with a NULL cur_map_set on failure and remove the unncessary free in rxe_mr_init_user(). Link: https://lore.kernel.org/r/20211228014406.1033444-1-lizhijian@cn.fujitsu.com Signed-off-by: Li Zhijian Acked-by: Zhu Yanjun Signed-off-by: Jason Gunthorpe --- drivers/infiniband/sw/rxe/rxe_mr.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/infiniband/sw/rxe/rxe_mr.c b/drivers/infiniband/sw/rxe/rxe_mr.c index 53271df10e47e..bcf717bcf0b3f 100644 --- a/drivers/infiniband/sw/rxe/rxe_mr.c +++ b/drivers/infiniband/sw/rxe/rxe_mr.c @@ -135,19 +135,19 @@ static int rxe_mr_alloc(struct rxe_mr *mr, int num_buf, int both) ret = rxe_mr_alloc_map_set(num_map, &mr->cur_map_set); if (ret) - goto err_out; + return -ENOMEM; if (both) { ret = rxe_mr_alloc_map_set(num_map, &mr->next_map_set); - if (ret) { - rxe_mr_free_map_set(mr->num_map, mr->cur_map_set); - goto err_out; - } + if (ret) + goto err_free; } return 0; -err_out: +err_free: + rxe_mr_free_map_set(mr->num_map, mr->cur_map_set); + mr->cur_map_set = NULL; return -ENOMEM; } @@ -214,7 +214,7 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, pr_warn("%s: Unable to get virtual address\n", __func__); err = -ENOMEM; - goto err_cleanup_map; + goto err_release_umem; } buf->addr = (uintptr_t)vaddr; @@ -237,8 +237,6 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, return 0; -err_cleanup_map: - rxe_mr_free_map_set(mr->num_map, mr->cur_map_set); err_release_umem: ib_umem_release(umem); err_out: -- GitLab From 3da4390bcdf4dcea5eb7961f1ba05f75c642a39d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 4 Jan 2022 14:57:14 +0000 Subject: [PATCH 927/965] arm64: perf: Don't register user access sysctl handler multiple times Commit e2012600810c ("arm64: perf: Add userspace counter access disable switch") introduced a new 'perf_user_access' sysctl file to enable and disable direct userspace access to the PMU counters. Sadly, Geert reports that on his big.LITTLE SoC ('Renesas Salvator-XS w/ R-Car H3'), the file is created for each PMU type probed, resulting in a splat during boot: | hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available | sysctl duplicate entry: /kernel//perf_user_access | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.16.0-rc3-arm64-renesas-00003-ge2012600810c #1420 | Hardware name: Renesas Salvator-X 2nd version board based on r8a77951 (DT) | Call trace: | dump_backtrace+0x0/0x190 | show_stack+0x14/0x20 | dump_stack_lvl+0x88/0xb0 | dump_stack+0x14/0x2c | __register_sysctl_table+0x384/0x818 | register_sysctl+0x20/0x28 | armv8_pmu_init.constprop.0+0x118/0x150 | armv8_a57_pmu_init+0x1c/0x28 | arm_pmu_device_probe+0x1b4/0x558 | armv8_pmu_device_probe+0x18/0x20 | platform_probe+0x64/0xd0 | hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 counters available Introduce a state variable to track creation of the sysctl file and ensure that it is only created once. Reported-by: Geert Uytterhoeven Fixes: e2012600810c ("arm64: perf: Add userspace counter access disable switch") Link: https://lore.kernel.org/r/CAMuHMdVcDxR9sGzc5pcnORiotonERBgc6dsXZXMd6wTvLGA9iw@mail.gmail.com Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4c5c8d731fbb9..cab678ed66183 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1214,6 +1214,14 @@ static struct ctl_table armv8_pmu_sysctl_table[] = { { } }; +static void armv8_pmu_register_sysctl_table(void) +{ + static u32 tbl_registered = 0; + + if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) + register_sysctl("kernel", armv8_pmu_sysctl_table); +} + static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, int (*map_event)(struct perf_event *event), const struct attribute_group *events, @@ -1248,8 +1256,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ? caps : &armv8_pmuv3_caps_attr_group; - register_sysctl("kernel", armv8_pmu_sysctl_table); - + armv8_pmu_register_sysctl_table(); return 0; } -- GitLab From c370baa328022cbd46c59c821d1b467a97f047be Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Fri, 24 Dec 2021 04:11:26 -0500 Subject: [PATCH 928/965] EDAC/i10nm: Release mdev/mbase when failing to detect HBM On systems without HBM (High Bandwidth Memory) mdev/mbase are not released/unmapped. Add the code to release mdev/mbase when failing to detect HBM. [Tony: re-word commit message] Cc: Fixes: c945088384d0 ("EDAC/i10nm: Add support for high bandwidth memory") Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://lore.kernel.org/r/20211224091126.1246-1-qiuxu.zhuo@intel.com --- drivers/edac/i10nm_base.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index 83345bfac246f..6cf50ee0b77c5 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -358,6 +358,9 @@ static int i10nm_get_hbm_munits(void) mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE); if (!mbase) { + pci_dev_put(d->imc[lmc].mdev); + d->imc[lmc].mdev = NULL; + i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n", base + off); return -ENOMEM; @@ -368,6 +371,12 @@ static int i10nm_get_hbm_munits(void) mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0); if (!I10NM_IS_HBM_IMC(mcmtr)) { + iounmap(d->imc[lmc].mbase); + d->imc[lmc].mbase = NULL; + d->imc[lmc].hbm_mc = false; + pci_dev_put(d->imc[lmc].mdev); + d->imc[lmc].mdev = NULL; + i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n"); return -ENODEV; } -- GitLab From 754e4382354f7908923a1949d8dc8d05f82f09cb Mon Sep 17 00:00:00 2001 From: Pavel Skripkin Date: Tue, 4 Jan 2022 21:28:06 +0300 Subject: [PATCH 929/965] ieee802154: atusb: fix uninit value in atusb_set_extended_addr Alexander reported a use of uninitialized value in atusb_set_extended_addr(), that is caused by reading 0 bytes via usb_control_msg(). Fix it by validating if the number of bytes transferred is actually correct, since usb_control_msg() may read less bytes, than was requested by caller. Fail log: BUG: KASAN: uninit-cmp in ieee802154_is_valid_extended_unicast_addr include/linux/ieee802154.h:310 [inline] BUG: KASAN: uninit-cmp in atusb_set_extended_addr drivers/net/ieee802154/atusb.c:1000 [inline] BUG: KASAN: uninit-cmp in atusb_probe.cold+0x29f/0x14db drivers/net/ieee802154/atusb.c:1056 Uninit value used in comparison: 311daa649a2003bd stack handle: 000000009a2003bd ieee802154_is_valid_extended_unicast_addr include/linux/ieee802154.h:310 [inline] atusb_set_extended_addr drivers/net/ieee802154/atusb.c:1000 [inline] atusb_probe.cold+0x29f/0x14db drivers/net/ieee802154/atusb.c:1056 usb_probe_interface+0x314/0x7f0 drivers/usb/core/driver.c:396 Fixes: 7490b008d123 ("ieee802154: add support for atusb transceiver") Reported-by: Alexander Potapenko Acked-by: Alexander Aring Signed-off-by: Pavel Skripkin Link: https://lore.kernel.org/r/20220104182806.7188-1-paskripkin@gmail.com Signed-off-by: Stefan Schmidt --- drivers/net/ieee802154/atusb.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ieee802154/atusb.c b/drivers/net/ieee802154/atusb.c index 23ee0b14cbfa1..2f5e7b31032aa 100644 --- a/drivers/net/ieee802154/atusb.c +++ b/drivers/net/ieee802154/atusb.c @@ -93,7 +93,9 @@ static int atusb_control_msg(struct atusb *atusb, unsigned int pipe, ret = usb_control_msg(usb_dev, pipe, request, requesttype, value, index, data, size, timeout); - if (ret < 0) { + if (ret < size) { + ret = ret < 0 ? ret : -ENODATA; + atusb->err = ret; dev_err(&usb_dev->dev, "%s: req 0x%02x val 0x%x idx 0x%x, error %d\n", @@ -861,9 +863,9 @@ static int atusb_get_and_show_build(struct atusb *atusb) if (!build) return -ENOMEM; - ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0), - ATUSB_BUILD, ATUSB_REQ_FROM_DEV, 0, 0, - build, ATUSB_BUILD_SIZE, 1000); + /* We cannot call atusb_control_msg() here, since this request may read various length data */ + ret = usb_control_msg(atusb->usb_dev, usb_rcvctrlpipe(usb_dev, 0), ATUSB_BUILD, + ATUSB_REQ_FROM_DEV, 0, 0, build, ATUSB_BUILD_SIZE, 1000); if (ret >= 0) { build[ret] = 0; dev_info(&usb_dev->dev, "Firmware: build %s\n", build); -- GitLab From 01cbf50877e602e2376af89e4a51c30bc574c618 Mon Sep 17 00:00:00 2001 From: Mateusz Palczewski Date: Wed, 3 Mar 2021 11:45:33 +0000 Subject: [PATCH 930/965] i40e: Fix to not show opcode msg on unsuccessful VF MAC change Hide i40e opcode information sent during response to VF in case when untrusted VF tried to change MAC on the VF interface. This is implemented by adding an additional parameter 'hide' to the response sent to VF function that hides the display of error information, but forwards the error code to VF. Previously it was not possible to send response with some error code to VF without displaying opcode information. Fixes: 5c3c48ac6bf5 ("i40e: implement virtual device interface") Signed-off-by: Grzegorz Szczurek Signed-off-by: Mateusz Palczewski Reviewed-by: Paul M Stillwell Jr Reviewed-by: Aleksandr Loktionov Tested-by: Tony Brelinski Signed-off-by: Tony Nguyen --- .../ethernet/intel/i40e/i40e_virtchnl_pf.c | 40 +++++++++++++++---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c index 2ea4deb8fc44c..048f1678ab8ac 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c @@ -1877,17 +1877,19 @@ sriov_configure_out: /***********************virtual channel routines******************/ /** - * i40e_vc_send_msg_to_vf + * i40e_vc_send_msg_to_vf_ex * @vf: pointer to the VF info * @v_opcode: virtual channel opcode * @v_retval: virtual channel return value * @msg: pointer to the msg buffer * @msglen: msg length + * @is_quiet: true for not printing unsuccessful return values, false otherwise * * send msg to VF **/ -static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode, - u32 v_retval, u8 *msg, u16 msglen) +static int i40e_vc_send_msg_to_vf_ex(struct i40e_vf *vf, u32 v_opcode, + u32 v_retval, u8 *msg, u16 msglen, + bool is_quiet) { struct i40e_pf *pf; struct i40e_hw *hw; @@ -1903,7 +1905,7 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode, abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id; /* single place to detect unsuccessful return values */ - if (v_retval) { + if (v_retval && !is_quiet) { vf->num_invalid_msgs++; dev_info(&pf->pdev->dev, "VF %d failed opcode %d, retval: %d\n", vf->vf_id, v_opcode, v_retval); @@ -1933,6 +1935,23 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode, return 0; } +/** + * i40e_vc_send_msg_to_vf + * @vf: pointer to the VF info + * @v_opcode: virtual channel opcode + * @v_retval: virtual channel return value + * @msg: pointer to the msg buffer + * @msglen: msg length + * + * send msg to VF + **/ +static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode, + u32 v_retval, u8 *msg, u16 msglen) +{ + return i40e_vc_send_msg_to_vf_ex(vf, v_opcode, v_retval, + msg, msglen, false); +} + /** * i40e_vc_send_resp_to_vf * @vf: pointer to the VF info @@ -2695,6 +2714,7 @@ error_param: * i40e_check_vf_permission * @vf: pointer to the VF info * @al: MAC address list from virtchnl + * @is_quiet: set true for printing msg without opcode info, false otherwise * * Check that the given list of MAC addresses is allowed. Will return -EPERM * if any address in the list is not valid. Checks the following conditions: @@ -2709,13 +2729,15 @@ error_param: * addresses might not be accurate. **/ static inline int i40e_check_vf_permission(struct i40e_vf *vf, - struct virtchnl_ether_addr_list *al) + struct virtchnl_ether_addr_list *al, + bool *is_quiet) { struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = pf->vsi[vf->lan_vsi_idx]; int mac2add_cnt = 0; int i; + *is_quiet = false; for (i = 0; i < al->num_elements; i++) { struct i40e_mac_filter *f; u8 *addr = al->list[i].addr; @@ -2739,6 +2761,7 @@ static inline int i40e_check_vf_permission(struct i40e_vf *vf, !ether_addr_equal(addr, vf->default_lan_addr.addr)) { dev_err(&pf->pdev->dev, "VF attempting to override administratively set MAC address, bring down and up the VF interface to resume normal operation\n"); + *is_quiet = true; return -EPERM; } @@ -2775,6 +2798,7 @@ static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg) (struct virtchnl_ether_addr_list *)msg; struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = NULL; + bool is_quiet = false; i40e_status ret = 0; int i; @@ -2791,7 +2815,7 @@ static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg) */ spin_lock_bh(&vsi->mac_filter_hash_lock); - ret = i40e_check_vf_permission(vf, al); + ret = i40e_check_vf_permission(vf, al, &is_quiet); if (ret) { spin_unlock_bh(&vsi->mac_filter_hash_lock); goto error_param; @@ -2829,8 +2853,8 @@ static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg) error_param: /* send the response to the VF */ - return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR, - ret); + return i40e_vc_send_msg_to_vf_ex(vf, VIRTCHNL_OP_ADD_ETH_ADDR, + ret, NULL, 0, is_quiet); } /** -- GitLab From 3116f59c12bd24c513194cd3acb3ec1f7d468954 Mon Sep 17 00:00:00 2001 From: Di Zhu Date: Mon, 29 Nov 2021 19:52:01 +0600 Subject: [PATCH 931/965] i40e: fix use-after-free in i40e_sync_filters_subtask() Using ifconfig command to delete the ipv6 address will cause the i40e network card driver to delete its internal mac_filter and i40e_service_task kernel thread will concurrently access the mac_filter. These two processes are not protected by lock so causing the following use-after-free problems. print_address_description+0x70/0x360 ? vprintk_func+0x5e/0xf0 kasan_report+0x1b2/0x330 i40e_sync_vsi_filters+0x4f0/0x1850 [i40e] i40e_sync_filters_subtask+0xe3/0x130 [i40e] i40e_service_task+0x195/0x24c0 [i40e] process_one_work+0x3f5/0x7d0 worker_thread+0x61/0x6c0 ? process_one_work+0x7d0/0x7d0 kthread+0x1c3/0x1f0 ? kthread_park+0xc0/0xc0 ret_from_fork+0x35/0x40 Allocated by task 2279810: kasan_kmalloc+0xa0/0xd0 kmem_cache_alloc_trace+0xf3/0x1e0 i40e_add_filter+0x127/0x2b0 [i40e] i40e_add_mac_filter+0x156/0x190 [i40e] i40e_addr_sync+0x2d/0x40 [i40e] __hw_addr_sync_dev+0x154/0x210 i40e_set_rx_mode+0x6d/0xf0 [i40e] __dev_set_rx_mode+0xfb/0x1f0 __dev_mc_add+0x6c/0x90 igmp6_group_added+0x214/0x230 __ipv6_dev_mc_inc+0x338/0x4f0 addrconf_join_solict.part.7+0xa2/0xd0 addrconf_dad_work+0x500/0x980 process_one_work+0x3f5/0x7d0 worker_thread+0x61/0x6c0 kthread+0x1c3/0x1f0 ret_from_fork+0x35/0x40 Freed by task 2547073: __kasan_slab_free+0x130/0x180 kfree+0x90/0x1b0 __i40e_del_filter+0xa3/0xf0 [i40e] i40e_del_mac_filter+0xf3/0x130 [i40e] i40e_addr_unsync+0x85/0xa0 [i40e] __hw_addr_sync_dev+0x9d/0x210 i40e_set_rx_mode+0x6d/0xf0 [i40e] __dev_set_rx_mode+0xfb/0x1f0 __dev_mc_del+0x69/0x80 igmp6_group_dropped+0x279/0x510 __ipv6_dev_mc_dec+0x174/0x220 addrconf_leave_solict.part.8+0xa2/0xd0 __ipv6_ifa_notify+0x4cd/0x570 ipv6_ifa_notify+0x58/0x80 ipv6_del_addr+0x259/0x4a0 inet6_addr_del+0x188/0x260 addrconf_del_ifaddr+0xcc/0x130 inet6_ioctl+0x152/0x190 sock_do_ioctl+0xd8/0x2b0 sock_ioctl+0x2e5/0x4c0 do_vfs_ioctl+0x14e/0xa80 ksys_ioctl+0x7c/0xa0 __x64_sys_ioctl+0x42/0x50 do_syscall_64+0x98/0x2c0 entry_SYSCALL_64_after_hwframe+0x65/0xca Fixes: 41c445ff0f48 ("i40e: main driver core") Signed-off-by: Di Zhu Signed-off-by: Rui Zhang Tested-by: Gurucharan G Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/i40e/i40e_main.c | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index e118cf9265c79..e0c4d6113c022 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -99,6 +99,24 @@ MODULE_LICENSE("GPL v2"); static struct workqueue_struct *i40e_wq; +static void netdev_hw_addr_refcnt(struct i40e_mac_filter *f, + struct net_device *netdev, int delta) +{ + struct netdev_hw_addr *ha; + + if (!f || !netdev) + return; + + netdev_for_each_mc_addr(ha, netdev) { + if (ether_addr_equal(ha->addr, f->macaddr)) { + ha->refcount += delta; + if (ha->refcount <= 0) + ha->refcount = 1; + break; + } + } +} + /** * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code * @hw: pointer to the HW structure @@ -2036,6 +2054,7 @@ static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi, hlist_for_each_entry_safe(new, h, from, hlist) { /* We can simply free the wrapper structure */ hlist_del(&new->hlist); + netdev_hw_addr_refcnt(new->f, vsi->netdev, -1); kfree(new); } } @@ -2383,6 +2402,10 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) &tmp_add_list, &tmp_del_list, vlan_filters); + + hlist_for_each_entry(new, &tmp_add_list, hlist) + netdev_hw_addr_refcnt(new->f, vsi->netdev, 1); + if (retval) goto err_no_memory_locked; @@ -2515,6 +2538,7 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) if (new->f->state == I40E_FILTER_NEW) new->f->state = new->state; hlist_del(&new->hlist); + netdev_hw_addr_refcnt(new->f, vsi->netdev, -1); kfree(new); } spin_unlock_bh(&vsi->mac_filter_hash_lock); -- GitLab From 40feded8a247f95957a0de9abd100085fb320a2f Mon Sep 17 00:00:00 2001 From: Mateusz Palczewski Date: Thu, 9 Dec 2021 11:04:35 +0100 Subject: [PATCH 932/965] i40e: Fix for displaying message regarding NVM version When loading the i40e driver, it prints a message like: 'The driver for the device detected a newer version of the NVM image v1.x than expected v1.y. Please install the most recent version of the network driver.' This is misleading as the driver is working as expected. Fix that by removing the second part of message and changing it from dev_info to dev_dbg. Fixes: 4fb29bddb57f ("i40e: The driver now prints the API version in error message") Signed-off-by: Mateusz Palczewski Tested-by: Gurucharan G Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/i40e/i40e_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index e0c4d6113c022..17c3f6d697401 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -15475,8 +15475,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) - dev_info(&pdev->dev, - "The driver for the device detected a newer version of the NVM image v%u.%u than expected v%u.%u. Please install the most recent version of the network driver.\n", + dev_dbg(&pdev->dev, + "The driver for the device detected a newer version of the NVM image v%u.%u than v%u.%u.\n", hw->aq.api_maj_ver, hw->aq.api_min_ver, I40E_FW_API_VERSION_MAJOR, -- GitLab From e738451d78b2f8a9635d66c6a87f304b4d965f7a Mon Sep 17 00:00:00 2001 From: Jedrzej Jagielski Date: Fri, 17 Dec 2021 14:29:05 +0000 Subject: [PATCH 933/965] i40e: Fix incorrect netdev's real number of RX/TX queues There was a wrong queues representation in sysfs during driver's reinitialization in case of online cpus number is less than combined queues. It was caused by stopped NetworkManager, which is responsible for calling vsi_open function during driver's initialization. In specific situation (ex. 12 cpus online) there were 16 queues in /sys/class/net//queues. In case of modifying queues with value higher, than number of online cpus, then it caused write errors and other errors. Add updating of sysfs's queues representation during driver initialization. Fixes: 41c445ff0f48 ("i40e: main driver core") Signed-off-by: Lukasz Cieplicki Signed-off-by: Jedrzej Jagielski Tested-by: Gurucharan G Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/i40e/i40e_main.c | 32 ++++++++++++++++----- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 17c3f6d697401..61afc220fc6cd 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -8740,6 +8740,27 @@ int i40e_open(struct net_device *netdev) return 0; } +/** + * i40e_netif_set_realnum_tx_rx_queues - Update number of tx/rx queues + * @vsi: vsi structure + * + * This updates netdev's number of tx/rx queues + * + * Returns status of setting tx/rx queues + **/ +static int i40e_netif_set_realnum_tx_rx_queues(struct i40e_vsi *vsi) +{ + int ret; + + ret = netif_set_real_num_rx_queues(vsi->netdev, + vsi->num_queue_pairs); + if (ret) + return ret; + + return netif_set_real_num_tx_queues(vsi->netdev, + vsi->num_queue_pairs); +} + /** * i40e_vsi_open - * @vsi: the VSI to open @@ -8776,13 +8797,7 @@ int i40e_vsi_open(struct i40e_vsi *vsi) goto err_setup_rx; /* Notify the stack of the actual queue counts. */ - err = netif_set_real_num_tx_queues(vsi->netdev, - vsi->num_queue_pairs); - if (err) - goto err_set_queues; - - err = netif_set_real_num_rx_queues(vsi->netdev, - vsi->num_queue_pairs); + err = i40e_netif_set_realnum_tx_rx_queues(vsi); if (err) goto err_set_queues; @@ -14173,6 +14188,9 @@ struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, case I40E_VSI_MAIN: case I40E_VSI_VMDQ2: ret = i40e_config_netdev(vsi); + if (ret) + goto err_netdev; + ret = i40e_netif_set_realnum_tx_rx_queues(vsi); if (ret) goto err_netdev; ret = register_netdev(vsi->netdev); -- GitLab From b712941c8085e638bb92456e866ed3de4404e3d5 Mon Sep 17 00:00:00 2001 From: Karen Sornek Date: Wed, 1 Sep 2021 09:21:46 +0200 Subject: [PATCH 934/965] iavf: Fix limit of total number of queues to active queues of VF In the absence of this validation, if the user requests to configure queues more than the enabled queues, it results in sending the requested number of queues to the kernel stack (due to the asynchronous nature of VF response), in which case the stack might pick a queue to transmit that is not enabled and result in Tx hang. Fix this bug by limiting the total number of queues allocated for VF to active queues of VF. Fixes: d5b33d024496 ("i40evf: add ndo_setup_tc callback to i40evf") Signed-off-by: Ashwin Vijayavel Signed-off-by: Karen Sornek Tested-by: Konrad Jankowski Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/iavf/iavf_main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c index 4e7c04047f917..e4439b0955338 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_main.c +++ b/drivers/net/ethernet/intel/iavf/iavf_main.c @@ -2708,8 +2708,11 @@ static int iavf_validate_ch_config(struct iavf_adapter *adapter, total_max_rate += tx_rate; num_qps += mqprio_qopt->qopt.count[i]; } - if (num_qps > IAVF_MAX_REQ_QUEUES) + if (num_qps > adapter->num_active_queues) { + dev_err(&adapter->pdev->dev, + "Cannot support requested number of queues\n"); return -EINVAL; + } ret = iavf_validate_tx_bandwidth(adapter, total_max_rate); return ret; -- GitLab From 1d5a474240407c38ca8c7484a656ee39f585399c Mon Sep 17 00:00:00 2001 From: Martin Habets Date: Sun, 2 Jan 2022 08:41:22 +0000 Subject: [PATCH 935/965] sfc: The RX page_ring is optional The RX page_ring is an optional feature that improves performance. When allocation fails the driver can still function, but possibly with a lower bandwidth. Guard against dereferencing a NULL page_ring. Fixes: 2768935a4660 ("sfc: reuse pages to avoid DMA mapping/unmapping costs") Signed-off-by: Martin Habets Reported-by: Jiasheng Jiang Link: https://lore.kernel.org/r/164111288276.5798.10330502993729113868.stgit@palantir17.mph.net Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/sfc/falcon/rx.c | 5 +++++ drivers/net/ethernet/sfc/rx_common.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/net/ethernet/sfc/falcon/rx.c b/drivers/net/ethernet/sfc/falcon/rx.c index 11a6aee852e92..0c6cc21913693 100644 --- a/drivers/net/ethernet/sfc/falcon/rx.c +++ b/drivers/net/ethernet/sfc/falcon/rx.c @@ -110,6 +110,8 @@ static struct page *ef4_reuse_page(struct ef4_rx_queue *rx_queue) struct ef4_rx_page_state *state; unsigned index; + if (unlikely(!rx_queue->page_ring)) + return NULL; index = rx_queue->page_remove & rx_queue->page_ptr_mask; page = rx_queue->page_ring[index]; if (page == NULL) @@ -293,6 +295,9 @@ static void ef4_recycle_rx_pages(struct ef4_channel *channel, { struct ef4_rx_queue *rx_queue = ef4_channel_get_rx_queue(channel); + if (unlikely(!rx_queue->page_ring)) + return; + do { ef4_recycle_rx_page(channel, rx_buf); rx_buf = ef4_rx_buf_next(rx_queue, rx_buf); diff --git a/drivers/net/ethernet/sfc/rx_common.c b/drivers/net/ethernet/sfc/rx_common.c index 0983abc0cc5f0..633ca77a26fd1 100644 --- a/drivers/net/ethernet/sfc/rx_common.c +++ b/drivers/net/ethernet/sfc/rx_common.c @@ -45,6 +45,8 @@ static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue) unsigned int index; struct page *page; + if (unlikely(!rx_queue->page_ring)) + return NULL; index = rx_queue->page_remove & rx_queue->page_ptr_mask; page = rx_queue->page_ring[index]; if (page == NULL) @@ -114,6 +116,9 @@ void efx_recycle_rx_pages(struct efx_channel *channel, { struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel); + if (unlikely(!rx_queue->page_ring)) + return; + do { efx_recycle_rx_page(channel, rx_buf); rx_buf = efx_rx_buf_next(rx_queue, rx_buf); -- GitLab From 89d30b11507db7c24fe54cd4ccc498c145406028 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 15 Dec 2021 11:18:35 -0800 Subject: [PATCH 936/965] arm64: Drop outdated links in comments As started by commit 05a5f51ca566 ("Documentation: Replace lkml.org links with lore"), an effort was made to replace lkml.org links with lore to better use a single source that's more likely to stay available long-term. However, it seems these links don't offer much value here, so just remove them entirely. Cc: Joe Perches Suggested-by: Will Deacon Link: https://lore.kernel.org/lkml/20210211100213.GA29813@willie-the-truck/ Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20211215191835.1420010-1-keescook@chromium.org [catalin.marinas@arm.com: removed the arch/arm changes] Signed-off-by: Catalin Marinas --- arch/arm64/kernel/hibernate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c index 2758f75d6809a..6328308be2726 100644 --- a/arch/arm64/kernel/hibernate.c +++ b/arch/arm64/kernel/hibernate.c @@ -7,10 +7,6 @@ * Ubuntu project, hibernation support for mach-dove * Copyright (C) 2010 Nokia Corporation (Hiroshi Doyu) * Copyright (C) 2010 Texas Instruments, Inc. (Teerth Reddy et al.) - * https://lkml.org/lkml/2010/6/18/4 - * https://lists.linux-foundation.org/pipermail/linux-pm/2010-June/027422.html - * https://patchwork.kernel.org/patch/96442/ - * * Copyright (C) 2006 Rafael J. Wysocki */ #define pr_fmt(x) "hibernate: " x -- GitLab From 4163cb3d1980383220ad7043002b930995dcba33 Mon Sep 17 00:00:00 2001 From: Maor Gottlieb Date: Wed, 22 Dec 2021 12:13:12 +0200 Subject: [PATCH 937/965] Revert "RDMA/mlx5: Fix releasing unallocated memory in dereg MR flow" This patch is not the full fix and still causes to call traces during mlx5_ib_dereg_mr(). This reverts commit f0ae4afe3d35e67db042c58a52909e06262b740f. Fixes: f0ae4afe3d35 ("RDMA/mlx5: Fix releasing unallocated memory in dereg MR flow") Link: https://lore.kernel.org/r/20211222101312.1358616-1-maorg@nvidia.com Signed-off-by: Maor Gottlieb Acked-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/mlx5/mlx5_ib.h | 6 +++--- drivers/infiniband/hw/mlx5/mr.c | 26 ++++++++++++++------------ 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index 4a7a56ed740b9..e636e954f6bf2 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -664,6 +664,7 @@ struct mlx5_ib_mr { /* User MR data */ struct mlx5_cache_ent *cache_ent; + struct ib_umem *umem; /* This is zero'd when the MR is allocated */ union { @@ -675,7 +676,7 @@ struct mlx5_ib_mr { struct list_head list; }; - /* Used only by kernel MRs */ + /* Used only by kernel MRs (umem == NULL) */ struct { void *descs; void *descs_alloc; @@ -696,9 +697,8 @@ struct mlx5_ib_mr { int data_length; }; - /* Used only by User MRs */ + /* Used only by User MRs (umem != NULL) */ struct { - struct ib_umem *umem; unsigned int page_shift; /* Current access_flags */ int access_flags; diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index 63e2129f1142b..157d862fb8642 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -1904,18 +1904,19 @@ err: return ret; } -static void mlx5_free_priv_descs(struct mlx5_ib_mr *mr) +static void +mlx5_free_priv_descs(struct mlx5_ib_mr *mr) { - struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); - int size = mr->max_descs * mr->desc_size; - - if (!mr->descs) - return; + if (!mr->umem && mr->descs) { + struct ib_device *device = mr->ibmr.device; + int size = mr->max_descs * mr->desc_size; + struct mlx5_ib_dev *dev = to_mdev(device); - dma_unmap_single(&dev->mdev->pdev->dev, mr->desc_map, size, - DMA_TO_DEVICE); - kfree(mr->descs_alloc); - mr->descs = NULL; + dma_unmap_single(&dev->mdev->pdev->dev, mr->desc_map, size, + DMA_TO_DEVICE); + kfree(mr->descs_alloc); + mr->descs = NULL; + } } int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) @@ -1991,8 +1992,7 @@ int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) if (mr->cache_ent) { mlx5_mr_cache_free(dev, mr); } else { - if (!udata) - mlx5_free_priv_descs(mr); + mlx5_free_priv_descs(mr); kfree(mr); } return 0; @@ -2079,6 +2079,7 @@ static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd, if (err) goto err_free_in; + mr->umem = NULL; kfree(in); return mr; @@ -2205,6 +2206,7 @@ static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd, } mr->ibmr.device = pd->device; + mr->umem = NULL; switch (mr_type) { case IB_MR_TYPE_MEM_REG: -- GitLab From daa149dd8cd4ad8dc4f8dd47bd24f15992b3a8c1 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Fri, 22 Oct 2021 15:06:46 +0800 Subject: [PATCH 938/965] arm64: Use correct method to calculate nomap region boundaries Nomap regions are treated as "reserved". When region boundaries are not page aligned, we usually increase the "reserved" regions rather than decrease them. So, we should use memblock_region_reserved_base_pfn()/ memblock_region_reserved_end_pfn() instead of memblock_region_memory_ base_pfn()/memblock_region_memory_base_pfn() to calculate boundaries. Signed-off-by: Huacai Chen Link: https://lore.kernel.org/r/20211022070646.41923-1-chenhuacai@loongson.cn Signed-off-by: Catalin Marinas --- arch/arm64/kernel/setup.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index a80430550a737..f70573928f1bf 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -237,12 +237,14 @@ static void __init request_standard_resources(void) if (memblock_is_nomap(region)) { res->name = "reserved"; res->flags = IORESOURCE_MEM; + res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region)); + res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1; } else { res->name = "System RAM"; res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; + res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); + res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; } - res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); - res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; request_resource(&iomem_resource, res); -- GitLab From 00fcf8c7dd564c44448ff6a39728d2ca0c8efbd8 Mon Sep 17 00:00:00 2001 From: Aaron Ma Date: Wed, 5 Jan 2022 23:51:02 +0800 Subject: [PATCH 939/965] Revert "net: usb: r8152: Add MAC passthrough support for more Lenovo Docks" This reverts commit f77b83b5bbab53d2be339184838b19ed2c62c0a5. This change breaks multiple usb to ethernet dongles attached on Lenovo USB hub. Fixes: f77b83b5bbab ("net: usb: r8152: Add MAC passthrough support for more Lenovo Docks") Signed-off-by: Aaron Ma Link: https://lore.kernel.org/r/20220105155102.8557-1-aaron.ma@canonical.com Signed-off-by: Jakub Kicinski --- drivers/net/usb/r8152.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 3085e8118d7fa..ef6010a3d33ad 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -9638,9 +9638,12 @@ static int rtl8152_probe(struct usb_interface *intf, netdev->hw_features &= ~NETIF_F_RXCSUM; } - if (udev->parent && - le16_to_cpu(udev->parent->descriptor.idVendor) == VENDOR_ID_LENOVO) { - tp->lenovo_macpassthru = 1; + if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) { + switch (le16_to_cpu(udev->descriptor.idProduct)) { + case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2: + case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2: + tp->lenovo_macpassthru = 1; + } } if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && -- GitLab From 7694a7de22c53a312ea98960fcafc6ec62046531 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Fri, 31 Dec 2021 17:33:15 +0800 Subject: [PATCH 940/965] RDMA/uverbs: Check for null return of kmalloc_array Because of the possible failure of the allocation, data might be NULL pointer and will cause the dereference of the NULL pointer later. Therefore, it might be better to check it and return -ENOMEM. Fixes: 6884c6c4bd09 ("RDMA/verbs: Store the write/write_ex uapi entry points in the uverbs_api") Link: https://lore.kernel.org/r/20211231093315.1917667-1-jiasheng@iscas.ac.cn Signed-off-by: Jiasheng Jiang Reviewed-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/core/uverbs_uapi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/infiniband/core/uverbs_uapi.c b/drivers/infiniband/core/uverbs_uapi.c index 2f2c7646fce17..a02916a3a79ce 100644 --- a/drivers/infiniband/core/uverbs_uapi.c +++ b/drivers/infiniband/core/uverbs_uapi.c @@ -447,6 +447,9 @@ static int uapi_finalize(struct uverbs_api *uapi) uapi->num_write_ex = max_write_ex + 1; data = kmalloc_array(uapi->num_write + uapi->num_write_ex, sizeof(*uapi->write_methods), GFP_KERNEL); + if (!data) + return -ENOMEM; + for (i = 0; i != uapi->num_write + uapi->num_write_ex; i++) data[i] = &uapi->notsupp_method; uapi->write_methods = data; -- GitLab From db54c12a3d7e3eedd37aa08efc9362e905f07716 Mon Sep 17 00:00:00 2001 From: Taehee Yoo Date: Wed, 5 Jan 2022 14:44:36 +0000 Subject: [PATCH 941/965] selftests: set amt.sh executable amt.sh test script will not work because it doesn't have execution permission. So, it adds execution permission. Reported-by: Hangbin Liu Fixes: c08e8baea78e ("selftests: add amt interface selftest script") Signed-off-by: Taehee Yoo Link: https://lore.kernel.org/r/20220105144436.13415-1-ap420073@gmail.com Signed-off-by: Jakub Kicinski --- tools/testing/selftests/net/amt.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 tools/testing/selftests/net/amt.sh diff --git a/tools/testing/selftests/net/amt.sh b/tools/testing/selftests/net/amt.sh old mode 100644 new mode 100755 -- GitLab From b35a0f4dd544eaa6162b6d2f13a2557a121ae5fd Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Tue, 4 Jan 2022 14:21:52 +0200 Subject: [PATCH 942/965] RDMA/core: Don't infoleak GRH fields If dst->is_global field is not set, the GRH fields are not cleared and the following infoleak is reported. ===================================================== BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:121 [inline] BUG: KMSAN: kernel-infoleak in _copy_to_user+0x1c9/0x270 lib/usercopy.c:33 instrument_copy_to_user include/linux/instrumented.h:121 [inline] _copy_to_user+0x1c9/0x270 lib/usercopy.c:33 copy_to_user include/linux/uaccess.h:209 [inline] ucma_init_qp_attr+0x8c7/0xb10 drivers/infiniband/core/ucma.c:1242 ucma_write+0x637/0x6c0 drivers/infiniband/core/ucma.c:1732 vfs_write+0x8ce/0x2030 fs/read_write.c:588 ksys_write+0x28b/0x510 fs/read_write.c:643 __do_sys_write fs/read_write.c:655 [inline] __se_sys_write fs/read_write.c:652 [inline] __ia32_sys_write+0xdb/0x120 fs/read_write.c:652 do_syscall_32_irqs_on arch/x86/entry/common.c:114 [inline] __do_fast_syscall_32+0x96/0xf0 arch/x86/entry/common.c:180 do_fast_syscall_32+0x34/0x70 arch/x86/entry/common.c:205 do_SYSENTER_32+0x1b/0x20 arch/x86/entry/common.c:248 entry_SYSENTER_compat_after_hwframe+0x4d/0x5c Local variable resp created at: ucma_init_qp_attr+0xa4/0xb10 drivers/infiniband/core/ucma.c:1214 ucma_write+0x637/0x6c0 drivers/infiniband/core/ucma.c:1732 Bytes 40-59 of 144 are uninitialized Memory access of size 144 starts at ffff888167523b00 Data copied to user address 0000000020000100 CPU: 1 PID: 25910 Comm: syz-executor.1 Not tainted 5.16.0-rc5-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 ===================================================== Fixes: 4ba66093bdc6 ("IB/core: Check for global flag when using ah_attr") Link: https://lore.kernel.org/r/0e9dd51f93410b7b2f4f5562f52befc878b71afa.1641298868.git.leonro@nvidia.com Reported-by: syzbot+6d532fa8f9463da290bc@syzkaller.appspotmail.com Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/infiniband/core/uverbs_marshall.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/core/uverbs_marshall.c b/drivers/infiniband/core/uverbs_marshall.c index b8d715c68ca44..11a0806469162 100644 --- a/drivers/infiniband/core/uverbs_marshall.c +++ b/drivers/infiniband/core/uverbs_marshall.c @@ -66,7 +66,7 @@ void ib_copy_ah_attr_to_user(struct ib_device *device, struct rdma_ah_attr *src = ah_attr; struct rdma_ah_attr conv_ah; - memset(&dst->grh.reserved, 0, sizeof(dst->grh.reserved)); + memset(&dst->grh, 0, sizeof(dst->grh)); if ((ah_attr->type == RDMA_AH_ATTR_TYPE_OPA) && (rdma_ah_get_dlid(ah_attr) > be16_to_cpu(IB_LID_PERMISSIVE)) && -- GitLab From 0daf5cb217a9ca8ae91b8f966ddae322699fb71d Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Sun, 19 Dec 2021 14:53:17 +0100 Subject: [PATCH 943/965] ftrace/samples: Add missing prototypes direct functions There's another compilation fail (first here [1]) reported by kernel test robot for W=1 clang build: >> samples/ftrace/ftrace-direct-multi-modify.c:7:6: warning: no previous prototype for function 'my_direct_func1' [-Wmissing-prototypes] void my_direct_func1(unsigned long ip) Direct functions in ftrace direct sample modules need to have prototypes defined. They are already global in order to be visible for the inline assembly, so there's no problem. The kernel test robot reported just error for ftrace-direct-multi-modify, but I got same errors also for the rest of the modules touched by this patch. [1] 67d4f6e3bf5d ftrace/samples: Add missing prototype for my_direct_func Link: https://lkml.kernel.org/r/20211219135317.212430-1-jolsa@kernel.org Reported-by: kernel test robot Fixes: e1067a07cfbc ("ftrace/samples: Add module to test multi direct modify interface") Fixes: ae0cc3b7e7f5 ("ftrace/samples: Add a sample module that implements modify_ftrace_direct()") Fixes: 156473a0ff4f ("ftrace: Add another example of register_ftrace_direct() use case") Fixes: b06457c83af6 ("ftrace: Add sample module that uses register_ftrace_direct()") Signed-off-by: Jiri Olsa Signed-off-by: Steven Rostedt --- samples/ftrace/ftrace-direct-modify.c | 3 +++ samples/ftrace/ftrace-direct-multi-modify.c | 3 +++ samples/ftrace/ftrace-direct-too.c | 3 +++ samples/ftrace/ftrace-direct.c | 2 ++ 4 files changed, 11 insertions(+) diff --git a/samples/ftrace/ftrace-direct-modify.c b/samples/ftrace/ftrace-direct-modify.c index 690e4a9ff3330..2877cb053a829 100644 --- a/samples/ftrace/ftrace-direct-modify.c +++ b/samples/ftrace/ftrace-direct-modify.c @@ -4,6 +4,9 @@ #include #include +extern void my_direct_func1(void); +extern void my_direct_func2(void); + void my_direct_func1(void) { trace_printk("my direct func1\n"); diff --git a/samples/ftrace/ftrace-direct-multi-modify.c b/samples/ftrace/ftrace-direct-multi-modify.c index 91bc42a7adb91..6f43a39decd02 100644 --- a/samples/ftrace/ftrace-direct-multi-modify.c +++ b/samples/ftrace/ftrace-direct-multi-modify.c @@ -4,6 +4,9 @@ #include #include +extern void my_direct_func1(unsigned long ip); +extern void my_direct_func2(unsigned long ip); + void my_direct_func1(unsigned long ip) { trace_printk("my direct func1 ip %lx\n", ip); diff --git a/samples/ftrace/ftrace-direct-too.c b/samples/ftrace/ftrace-direct-too.c index 6e0de725bf221..b97e5ed46233b 100644 --- a/samples/ftrace/ftrace-direct-too.c +++ b/samples/ftrace/ftrace-direct-too.c @@ -5,6 +5,9 @@ #include #include +extern void my_direct_func(struct vm_area_struct *vma, + unsigned long address, unsigned int flags); + void my_direct_func(struct vm_area_struct *vma, unsigned long address, unsigned int flags) { diff --git a/samples/ftrace/ftrace-direct.c b/samples/ftrace/ftrace-direct.c index a30aa42ec76a8..c918b13edb490 100644 --- a/samples/ftrace/ftrace-direct.c +++ b/samples/ftrace/ftrace-direct.c @@ -5,6 +5,8 @@ #include #include +extern void my_direct_func(struct task_struct *p); + void my_direct_func(struct task_struct *p) { trace_printk("waking up %s-%d\n", p->comm, p->pid); -- GitLab From 823e670f7ed616d0ce993075c8afe0217885f79d Mon Sep 17 00:00:00 2001 From: "Naveen N. Rao" Date: Thu, 23 Dec 2021 16:04:38 +0530 Subject: [PATCH 944/965] tracing: Fix check for trace_percpu_buffer validity in get_trace_buf() With the new osnoise tracer, we are seeing the below splat: Kernel attempted to read user page (c7d880000) - exploit attempt? (uid: 0) BUG: Unable to handle kernel data access on read at 0xc7d880000 Faulting instruction address: 0xc0000000002ffa10 Oops: Kernel access of bad area, sig: 11 [#1] LE PAGE_SIZE=64K MMU=Radix SMP NR_CPUS=2048 NUMA pSeries ... NIP [c0000000002ffa10] __trace_array_vprintk.part.0+0x70/0x2f0 LR [c0000000002ff9fc] __trace_array_vprintk.part.0+0x5c/0x2f0 Call Trace: [c0000008bdd73b80] [c0000000001c49cc] put_prev_task_fair+0x3c/0x60 (unreliable) [c0000008bdd73be0] [c000000000301430] trace_array_printk_buf+0x70/0x90 [c0000008bdd73c00] [c0000000003178b0] trace_sched_switch_callback+0x250/0x290 [c0000008bdd73c90] [c000000000e70d60] __schedule+0x410/0x710 [c0000008bdd73d40] [c000000000e710c0] schedule+0x60/0x130 [c0000008bdd73d70] [c000000000030614] interrupt_exit_user_prepare_main+0x264/0x270 [c0000008bdd73de0] [c000000000030a70] syscall_exit_prepare+0x150/0x180 [c0000008bdd73e10] [c00000000000c174] system_call_vectored_common+0xf4/0x278 osnoise tracer on ppc64le is triggering osnoise_taint() for negative duration in get_int_safe_duration() called from trace_sched_switch_callback()->thread_exit(). The problem though is that the check for a valid trace_percpu_buffer is incorrect in get_trace_buf(). The check is being done after calculating the pointer for the current cpu, rather than on the main percpu pointer. Fix the check to be against trace_percpu_buffer. Link: https://lkml.kernel.org/r/a920e4272e0b0635cf20c444707cbce1b2c8973d.1640255304.git.naveen.n.rao@linux.vnet.ibm.com Cc: stable@vger.kernel.org Fixes: e2ace001176dc9 ("tracing: Choose static tp_printk buffer by explicit nesting count") Signed-off-by: Naveen N. Rao Signed-off-by: Steven Rostedt --- kernel/trace/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 88de94da596b1..e1f55851e53fa 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -3217,7 +3217,7 @@ static char *get_trace_buf(void) { struct trace_buffer_struct *buffer = this_cpu_ptr(trace_percpu_buffer); - if (!buffer || buffer->nesting >= 4) + if (!trace_percpu_buffer || buffer->nesting >= 4) return NULL; buffer->nesting++; -- GitLab From f28439db470cca8b6b082239314e9fd10bd39034 Mon Sep 17 00:00:00 2001 From: "Naveen N. Rao" Date: Thu, 23 Dec 2021 16:04:39 +0530 Subject: [PATCH 945/965] tracing: Tag trace_percpu_buffer as a percpu pointer Tag trace_percpu_buffer as a percpu pointer to resolve warnings reported by sparse: /linux/kernel/trace/trace.c:3218:46: warning: incorrect type in initializer (different address spaces) /linux/kernel/trace/trace.c:3218:46: expected void const [noderef] __percpu *__vpp_verify /linux/kernel/trace/trace.c:3218:46: got struct trace_buffer_struct * /linux/kernel/trace/trace.c:3234:9: warning: incorrect type in initializer (different address spaces) /linux/kernel/trace/trace.c:3234:9: expected void const [noderef] __percpu *__vpp_verify /linux/kernel/trace/trace.c:3234:9: got int * Link: https://lkml.kernel.org/r/ebabd3f23101d89cb75671b68b6f819f5edc830b.1640255304.git.naveen.n.rao@linux.vnet.ibm.com Cc: stable@vger.kernel.org Reported-by: kernel test robot Fixes: 07d777fe8c398 ("tracing: Add percpu buffers for trace_printk()") Signed-off-by: Naveen N. Rao Signed-off-by: Steven Rostedt --- kernel/trace/trace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index e1f55851e53fa..78ea542ce3bc2 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -3207,7 +3207,7 @@ struct trace_buffer_struct { char buffer[4][TRACE_BUF_SIZE]; }; -static struct trace_buffer_struct *trace_percpu_buffer; +static struct trace_buffer_struct __percpu *trace_percpu_buffer; /* * This allows for lockless recording. If we're nested too deeply, then @@ -3236,7 +3236,7 @@ static void put_trace_buf(void) static int alloc_percpu_trace_buffer(void) { - struct trace_buffer_struct *buffers; + struct trace_buffer_struct __percpu *buffers; if (trace_percpu_buffer) return 0; -- GitLab From 72a4a87da8f7bcf868b338615a814b6542f277f3 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 5 Jan 2022 14:53:04 +1300 Subject: [PATCH 946/965] i2c: mpc: Avoid out of bounds memory access When performing an I2C transfer where the last message was a write KASAN would complain: BUG: KASAN: slab-out-of-bounds in mpc_i2c_do_action+0x154/0x630 Read of size 2 at addr c814e310 by task swapper/2/0 CPU: 2 PID: 0 Comm: swapper/2 Tainted: G B 5.16.0-rc8 #1 Call Trace: [e5ee9d50] [c08418e8] dump_stack_lvl+0x4c/0x6c (unreliable) [e5ee9d70] [c02f8a14] print_address_description.constprop.13+0x64/0x3b0 [e5ee9da0] [c02f9030] kasan_report+0x1f0/0x204 [e5ee9de0] [c0c76ee4] mpc_i2c_do_action+0x154/0x630 [e5ee9e30] [c0c782c4] mpc_i2c_isr+0x164/0x240 [e5ee9e60] [c00f3a04] __handle_irq_event_percpu+0xf4/0x3b0 [e5ee9ec0] [c00f3d40] handle_irq_event_percpu+0x80/0x110 [e5ee9f40] [c00f3e48] handle_irq_event+0x78/0xd0 [e5ee9f60] [c00fcfec] handle_fasteoi_irq+0x19c/0x370 [e5ee9fa0] [c00f1d84] generic_handle_irq+0x54/0x80 [e5ee9fc0] [c0006b54] __do_irq+0x64/0x200 [e5ee9ff0] [c0007958] __do_IRQ+0xe8/0x1c0 [c812dd50] [e3eaab20] 0xe3eaab20 [c812dd90] [c0007a4c] do_IRQ+0x1c/0x30 [c812dda0] [c0000c04] ExternalInput+0x144/0x160 --- interrupt: 500 at arch_cpu_idle+0x34/0x60 NIP: c000b684 LR: c000b684 CTR: c0019688 REGS: c812ddb0 TRAP: 0500 Tainted: G B (5.16.0-rc8) MSR: 00029002 CR: 22000488 XER: 20000000 GPR00: c10ef7fc c812de90 c80ff200 c2394718 00000001 00000001 c10e3f90 00000003 GPR08: 00000000 c0019688 c2394718 fc7d625b 22000484 00000000 21e17000 c208228c GPR16: e3e99284 00000000 ffffffff c2390000 c001bac0 c2082288 c812df60 c001ba60 GPR24: c23949c0 00000018 00080000 00000004 c80ff200 00000002 c2348ee4 c2394718 NIP [c000b684] arch_cpu_idle+0x34/0x60 LR [c000b684] arch_cpu_idle+0x34/0x60 --- interrupt: 500 [c812de90] [c10e3f90] rcu_eqs_enter.isra.60+0xc0/0x110 (unreliable) [c812deb0] [c10ef7fc] default_idle_call+0xbc/0x230 [c812dee0] [c00af0e8] do_idle+0x1c8/0x200 [c812df10] [c00af3c0] cpu_startup_entry+0x20/0x30 [c812df20] [c001e010] start_secondary+0x5d0/0xba0 [c812dff0] [c00028a0] __secondary_start+0x90/0xdc This happened because we would overrun the i2c->msgs array on the final interrupt for the I2C STOP. This didn't happen if the last message was a read because there is no interrupt in that case. Ensure that we only access the current message if we are not processing a I2C STOP condition. Fixes: 1538d82f4647 ("i2c: mpc: Interrupt driven transfer") Reported-by: Maxime Bizon Signed-off-by: Chris Packham Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-mpc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 53b8da6dbb23f..db26cc36e13fe 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -492,7 +492,7 @@ static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc) static void mpc_i2c_do_action(struct mpc_i2c *i2c) { - struct i2c_msg *msg = &i2c->msgs[i2c->curr_msg]; + struct i2c_msg *msg = NULL; int dir = 0; int recv_len = 0; u8 byte; @@ -501,10 +501,13 @@ static void mpc_i2c_do_action(struct mpc_i2c *i2c) i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK); - if (msg->flags & I2C_M_RD) - dir = 1; - if (msg->flags & I2C_M_RECV_LEN) - recv_len = 1; + if (i2c->action != MPC_I2C_ACTION_STOP) { + msg = &i2c->msgs[i2c->curr_msg]; + if (msg->flags & I2C_M_RD) + dir = 1; + if (msg->flags & I2C_M_RECV_LEN) + recv_len = 1; + } switch (i2c->action) { case MPC_I2C_ACTION_RESTART: @@ -581,7 +584,7 @@ static void mpc_i2c_do_action(struct mpc_i2c *i2c) break; } - if (msg->len == i2c->byte_posn) { + if (msg && msg->len == i2c->byte_posn) { i2c->curr_msg++; i2c->byte_posn = 0; -- GitLab From 1756d7994ad85c2479af6ae5a9750b92324685af Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:28 -1000 Subject: [PATCH 947/965] cgroup: Use open-time credentials for process migraton perm checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cgroup process migration permission checks are performed at write time as whether a given operation is allowed or not is dependent on the content of the write - the PID. This currently uses current's credentials which is a potential security weakness as it may allow scenarios where a less privileged process tricks a more privileged one into writing into a fd that it created. This patch makes both cgroup2 and cgroup1 process migration interfaces to use the credentials saved at the time of open (file->f_cred) instead of current's. Reported-by: "Eric W. Biederman" Suggested-by: Linus Torvalds Fixes: 187fe84067bd ("cgroup: require write perm on common ancestor when moving processes on the default hierarchy") Reviewed-by: Michal Koutný Signed-off-by: Tejun Heo --- kernel/cgroup/cgroup-v1.c | 7 ++++--- kernel/cgroup/cgroup.c | 9 ++++++++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index 81c9e0685948c..0e7369103ba61 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -504,10 +504,11 @@ static ssize_t __cgroup1_procs_write(struct kernfs_open_file *of, goto out_unlock; /* - * Even if we're attaching all tasks in the thread group, we only - * need to check permissions on one of them. + * Even if we're attaching all tasks in the thread group, we only need + * to check permissions on one of them. Check permissions using the + * credentials from file open to protect against inherited fd attacks. */ - cred = current_cred(); + cred = of->file->f_cred; tcred = get_task_cred(task); if (!uid_eq(cred->euid, GLOBAL_ROOT_UID) && !uid_eq(cred->euid, tcred->uid) && diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 919194de39c83..2632e46da1d4a 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -4892,6 +4892,7 @@ static ssize_t __cgroup_procs_write(struct kernfs_open_file *of, char *buf, { struct cgroup *src_cgrp, *dst_cgrp; struct task_struct *task; + const struct cred *saved_cred; ssize_t ret; bool locked; @@ -4909,9 +4910,15 @@ static ssize_t __cgroup_procs_write(struct kernfs_open_file *of, char *buf, src_cgrp = task_cgroup_from_root(task, &cgrp_dfl_root); spin_unlock_irq(&css_set_lock); - /* process and thread migrations follow same delegation rule */ + /* + * Process and thread migrations follow same delegation rule. Check + * permissions using the credentials from file open to protect against + * inherited fd attacks. + */ + saved_cred = override_creds(of->file->f_cred); ret = cgroup_attach_permissions(src_cgrp, dst_cgrp, of->file->f_path.dentry->d_sb, threadgroup); + revert_creds(saved_cred); if (ret) goto out_finish; -- GitLab From 0d2b5955b36250a9428c832664f2079cbf723bec Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:29 -1000 Subject: [PATCH 948/965] cgroup: Allocate cgroup_file_ctx for kernfs_open_file->priv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit of->priv is currently used by each interface file implementation to store private information. This patch collects the current two private data usages into struct cgroup_file_ctx which is allocated and freed by the common path. This allows generic private data which applies to multiple files, which will be used to in the following patch. Note that cgroup_procs iterator is now embedded as procs.iter in the new cgroup_file_ctx so that it doesn't need to be allocated and freed separately. v2: union dropped from cgroup_file_ctx and the procs iterator is embedded in cgroup_file_ctx as suggested by Linus. v3: Michal pointed out that cgroup1's procs pidlist uses of->priv too. Converted. Didn't change to embedded allocation as cgroup1 pidlists get stored for caching. Signed-off-by: Tejun Heo Cc: Linus Torvalds Reviewed-by: Michal Koutný --- kernel/cgroup/cgroup-internal.h | 17 +++++++++++ kernel/cgroup/cgroup-v1.c | 26 ++++++++-------- kernel/cgroup/cgroup.c | 53 +++++++++++++++++++++------------ 3 files changed, 65 insertions(+), 31 deletions(-) diff --git a/kernel/cgroup/cgroup-internal.h b/kernel/cgroup/cgroup-internal.h index bfbeabc17a9df..cf637bc4ab453 100644 --- a/kernel/cgroup/cgroup-internal.h +++ b/kernel/cgroup/cgroup-internal.h @@ -65,6 +65,23 @@ static inline struct cgroup_fs_context *cgroup_fc2context(struct fs_context *fc) return container_of(kfc, struct cgroup_fs_context, kfc); } +struct cgroup_pidlist; + +struct cgroup_file_ctx { + struct { + void *trigger; + } psi; + + struct { + bool started; + struct css_task_iter iter; + } procs; + + struct { + struct cgroup_pidlist *pidlist; + } procs1; +}; + /* * A cgroup can be associated with multiple css_sets as different tasks may * belong to different cgroups on different hierarchies. In the other diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index 0e7369103ba61..41e0837a5a0bd 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -394,6 +394,7 @@ static void *cgroup_pidlist_start(struct seq_file *s, loff_t *pos) * next pid to display, if any */ struct kernfs_open_file *of = s->private; + struct cgroup_file_ctx *ctx = of->priv; struct cgroup *cgrp = seq_css(s)->cgroup; struct cgroup_pidlist *l; enum cgroup_filetype type = seq_cft(s)->private; @@ -403,25 +404,24 @@ static void *cgroup_pidlist_start(struct seq_file *s, loff_t *pos) mutex_lock(&cgrp->pidlist_mutex); /* - * !NULL @of->priv indicates that this isn't the first start() - * after open. If the matching pidlist is around, we can use that. - * Look for it. Note that @of->priv can't be used directly. It - * could already have been destroyed. + * !NULL @ctx->procs1.pidlist indicates that this isn't the first + * start() after open. If the matching pidlist is around, we can use + * that. Look for it. Note that @ctx->procs1.pidlist can't be used + * directly. It could already have been destroyed. */ - if (of->priv) - of->priv = cgroup_pidlist_find(cgrp, type); + if (ctx->procs1.pidlist) + ctx->procs1.pidlist = cgroup_pidlist_find(cgrp, type); /* * Either this is the first start() after open or the matching * pidlist has been destroyed inbetween. Create a new one. */ - if (!of->priv) { - ret = pidlist_array_load(cgrp, type, - (struct cgroup_pidlist **)&of->priv); + if (!ctx->procs1.pidlist) { + ret = pidlist_array_load(cgrp, type, &ctx->procs1.pidlist); if (ret) return ERR_PTR(ret); } - l = of->priv; + l = ctx->procs1.pidlist; if (pid) { int end = l->length; @@ -449,7 +449,8 @@ static void *cgroup_pidlist_start(struct seq_file *s, loff_t *pos) static void cgroup_pidlist_stop(struct seq_file *s, void *v) { struct kernfs_open_file *of = s->private; - struct cgroup_pidlist *l = of->priv; + struct cgroup_file_ctx *ctx = of->priv; + struct cgroup_pidlist *l = ctx->procs1.pidlist; if (l) mod_delayed_work(cgroup_pidlist_destroy_wq, &l->destroy_dwork, @@ -460,7 +461,8 @@ static void cgroup_pidlist_stop(struct seq_file *s, void *v) static void *cgroup_pidlist_next(struct seq_file *s, void *v, loff_t *pos) { struct kernfs_open_file *of = s->private; - struct cgroup_pidlist *l = of->priv; + struct cgroup_file_ctx *ctx = of->priv; + struct cgroup_pidlist *l = ctx->procs1.pidlist; pid_t *p = v; pid_t *end = l->list + l->length; /* diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 2632e46da1d4a..a84631d08d98c 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -3630,6 +3630,7 @@ static int cgroup_cpu_pressure_show(struct seq_file *seq, void *v) static ssize_t cgroup_pressure_write(struct kernfs_open_file *of, char *buf, size_t nbytes, enum psi_res res) { + struct cgroup_file_ctx *ctx = of->priv; struct psi_trigger *new; struct cgroup *cgrp; struct psi_group *psi; @@ -3648,7 +3649,7 @@ static ssize_t cgroup_pressure_write(struct kernfs_open_file *of, char *buf, return PTR_ERR(new); } - psi_trigger_replace(&of->priv, new); + psi_trigger_replace(&ctx->psi.trigger, new); cgroup_put(cgrp); @@ -3679,12 +3680,16 @@ static ssize_t cgroup_cpu_pressure_write(struct kernfs_open_file *of, static __poll_t cgroup_pressure_poll(struct kernfs_open_file *of, poll_table *pt) { - return psi_trigger_poll(&of->priv, of->file, pt); + struct cgroup_file_ctx *ctx = of->priv; + + return psi_trigger_poll(&ctx->psi.trigger, of->file, pt); } static void cgroup_pressure_release(struct kernfs_open_file *of) { - psi_trigger_replace(&of->priv, NULL); + struct cgroup_file_ctx *ctx = of->priv; + + psi_trigger_replace(&ctx->psi.trigger, NULL); } bool cgroup_psi_enabled(void) @@ -3811,18 +3816,31 @@ static ssize_t cgroup_kill_write(struct kernfs_open_file *of, char *buf, static int cgroup_file_open(struct kernfs_open_file *of) { struct cftype *cft = of_cft(of); + struct cgroup_file_ctx *ctx; + int ret; - if (cft->open) - return cft->open(of); - return 0; + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + of->priv = ctx; + + if (!cft->open) + return 0; + + ret = cft->open(of); + if (ret) + kfree(ctx); + return ret; } static void cgroup_file_release(struct kernfs_open_file *of) { struct cftype *cft = of_cft(of); + struct cgroup_file_ctx *ctx = of->priv; if (cft->release) cft->release(of); + kfree(ctx); } static ssize_t cgroup_file_write(struct kernfs_open_file *of, char *buf, @@ -4751,21 +4769,21 @@ void css_task_iter_end(struct css_task_iter *it) static void cgroup_procs_release(struct kernfs_open_file *of) { - if (of->priv) { - css_task_iter_end(of->priv); - kfree(of->priv); - } + struct cgroup_file_ctx *ctx = of->priv; + + if (ctx->procs.started) + css_task_iter_end(&ctx->procs.iter); } static void *cgroup_procs_next(struct seq_file *s, void *v, loff_t *pos) { struct kernfs_open_file *of = s->private; - struct css_task_iter *it = of->priv; + struct cgroup_file_ctx *ctx = of->priv; if (pos) (*pos)++; - return css_task_iter_next(it); + return css_task_iter_next(&ctx->procs.iter); } static void *__cgroup_procs_start(struct seq_file *s, loff_t *pos, @@ -4773,21 +4791,18 @@ static void *__cgroup_procs_start(struct seq_file *s, loff_t *pos, { struct kernfs_open_file *of = s->private; struct cgroup *cgrp = seq_css(s)->cgroup; - struct css_task_iter *it = of->priv; + struct cgroup_file_ctx *ctx = of->priv; + struct css_task_iter *it = &ctx->procs.iter; /* * When a seq_file is seeked, it's always traversed sequentially * from position 0, so we can simply keep iterating on !0 *pos. */ - if (!it) { + if (!ctx->procs.started) { if (WARN_ON_ONCE((*pos))) return ERR_PTR(-EINVAL); - - it = kzalloc(sizeof(*it), GFP_KERNEL); - if (!it) - return ERR_PTR(-ENOMEM); - of->priv = it; css_task_iter_start(&cgrp->self, iter_flags, it); + ctx->procs.started = true; } else if (!(*pos)) { css_task_iter_end(it); css_task_iter_start(&cgrp->self, iter_flags, it); -- GitLab From e57457641613fef0d147ede8bd6a3047df588b95 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:29 -1000 Subject: [PATCH 949/965] cgroup: Use open-time cgroup namespace for process migration perm checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cgroup process migration permission checks are performed at write time as whether a given operation is allowed or not is dependent on the content of the write - the PID. This currently uses current's cgroup namespace which is a potential security weakness as it may allow scenarios where a less privileged process tricks a more privileged one into writing into a fd that it created. This patch makes cgroup remember the cgroup namespace at the time of open and uses it for migration permission checks instad of current's. Note that this only applies to cgroup2 as cgroup1 doesn't have namespace support. This also fixes a use-after-free bug on cgroupns reported in https://lore.kernel.org/r/00000000000048c15c05d0083397@google.com Note that backporting this fix also requires the preceding patch. Reported-by: "Eric W. Biederman" Suggested-by: Linus Torvalds Cc: Michal Koutný Cc: Oleg Nesterov Reviewed-by: Michal Koutný Reported-by: syzbot+50f5cf33a284ce738b62@syzkaller.appspotmail.com Link: https://lore.kernel.org/r/00000000000048c15c05d0083397@google.com Fixes: 5136f6365ce3 ("cgroup: implement "nsdelegate" mount option") Signed-off-by: Tejun Heo --- kernel/cgroup/cgroup-internal.h | 2 ++ kernel/cgroup/cgroup.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/kernel/cgroup/cgroup-internal.h b/kernel/cgroup/cgroup-internal.h index cf637bc4ab453..6e36e854b5124 100644 --- a/kernel/cgroup/cgroup-internal.h +++ b/kernel/cgroup/cgroup-internal.h @@ -68,6 +68,8 @@ static inline struct cgroup_fs_context *cgroup_fc2context(struct fs_context *fc) struct cgroup_pidlist; struct cgroup_file_ctx { + struct cgroup_namespace *ns; + struct { void *trigger; } psi; diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index a84631d08d98c..cafb8c114a21c 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -3822,14 +3822,19 @@ static int cgroup_file_open(struct kernfs_open_file *of) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); if (!ctx) return -ENOMEM; + + ctx->ns = current->nsproxy->cgroup_ns; + get_cgroup_ns(ctx->ns); of->priv = ctx; if (!cft->open) return 0; ret = cft->open(of); - if (ret) + if (ret) { + put_cgroup_ns(ctx->ns); kfree(ctx); + } return ret; } @@ -3840,13 +3845,14 @@ static void cgroup_file_release(struct kernfs_open_file *of) if (cft->release) cft->release(of); + put_cgroup_ns(ctx->ns); kfree(ctx); } static ssize_t cgroup_file_write(struct kernfs_open_file *of, char *buf, size_t nbytes, loff_t off) { - struct cgroup_namespace *ns = current->nsproxy->cgroup_ns; + struct cgroup_file_ctx *ctx = of->priv; struct cgroup *cgrp = of->kn->parent->priv; struct cftype *cft = of_cft(of); struct cgroup_subsys_state *css; @@ -3863,7 +3869,7 @@ static ssize_t cgroup_file_write(struct kernfs_open_file *of, char *buf, */ if ((cgrp->root->flags & CGRP_ROOT_NS_DELEGATE) && !(cft->flags & CFTYPE_NS_DELEGATABLE) && - ns != &init_cgroup_ns && ns->root_cset->dfl_cgrp == cgrp) + ctx->ns != &init_cgroup_ns && ctx->ns->root_cset->dfl_cgrp == cgrp) return -EPERM; if (cft->write) @@ -4853,9 +4859,9 @@ static int cgroup_may_write(const struct cgroup *cgrp, struct super_block *sb) static int cgroup_procs_write_permission(struct cgroup *src_cgrp, struct cgroup *dst_cgrp, - struct super_block *sb) + struct super_block *sb, + struct cgroup_namespace *ns) { - struct cgroup_namespace *ns = current->nsproxy->cgroup_ns; struct cgroup *com_cgrp = src_cgrp; int ret; @@ -4884,11 +4890,12 @@ static int cgroup_procs_write_permission(struct cgroup *src_cgrp, static int cgroup_attach_permissions(struct cgroup *src_cgrp, struct cgroup *dst_cgrp, - struct super_block *sb, bool threadgroup) + struct super_block *sb, bool threadgroup, + struct cgroup_namespace *ns) { int ret = 0; - ret = cgroup_procs_write_permission(src_cgrp, dst_cgrp, sb); + ret = cgroup_procs_write_permission(src_cgrp, dst_cgrp, sb, ns); if (ret) return ret; @@ -4905,6 +4912,7 @@ static int cgroup_attach_permissions(struct cgroup *src_cgrp, static ssize_t __cgroup_procs_write(struct kernfs_open_file *of, char *buf, bool threadgroup) { + struct cgroup_file_ctx *ctx = of->priv; struct cgroup *src_cgrp, *dst_cgrp; struct task_struct *task; const struct cred *saved_cred; @@ -4932,7 +4940,8 @@ static ssize_t __cgroup_procs_write(struct kernfs_open_file *of, char *buf, */ saved_cred = override_creds(of->file->f_cred); ret = cgroup_attach_permissions(src_cgrp, dst_cgrp, - of->file->f_path.dentry->d_sb, threadgroup); + of->file->f_path.dentry->d_sb, + threadgroup, ctx->ns); revert_creds(saved_cred); if (ret) goto out_finish; @@ -6152,7 +6161,8 @@ static int cgroup_css_set_fork(struct kernel_clone_args *kargs) goto err; ret = cgroup_attach_permissions(cset->dfl_cgrp, dst_cgrp, sb, - !(kargs->flags & CLONE_THREAD)); + !(kargs->flags & CLONE_THREAD), + current->nsproxy->cgroup_ns); if (ret) goto err; -- GitLab From b09c2baa56347ae65795350dfcc633dedb1c2970 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:29 -1000 Subject: [PATCH 950/965] selftests: cgroup: Make cg_create() use 0755 for permission instead of 0644 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 0644 is an odd perm to create a cgroup which is a directory. Use the regular 0755 instead. This is necessary for euid switching test case. Reviewed-by: Michal Koutný Signed-off-by: Tejun Heo --- tools/testing/selftests/cgroup/cgroup_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/cgroup/cgroup_util.c b/tools/testing/selftests/cgroup/cgroup_util.c index 623cec04ad422..0cf7e90c0052e 100644 --- a/tools/testing/selftests/cgroup/cgroup_util.c +++ b/tools/testing/selftests/cgroup/cgroup_util.c @@ -221,7 +221,7 @@ int cg_find_unified_root(char *root, size_t len) int cg_create(const char *cgroup) { - return mkdir(cgroup, 0644); + return mkdir(cgroup, 0755); } int cg_wait_for_proc_count(const char *cgroup, int count) -- GitLab From 613e040e4dc285367bff0f8f75ea59839bc10947 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:29 -1000 Subject: [PATCH 951/965] selftests: cgroup: Test open-time credential usage for migration checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a task is writing to an fd opened by a different task, the perm check should use the credentials of the latter task. Add a test for it. Tested-by: Michal Koutný Signed-off-by: Tejun Heo --- tools/testing/selftests/cgroup/test_core.c | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/tools/testing/selftests/cgroup/test_core.c b/tools/testing/selftests/cgroup/test_core.c index 3df648c378765..01b7665069735 100644 --- a/tools/testing/selftests/cgroup/test_core.c +++ b/tools/testing/selftests/cgroup/test_core.c @@ -674,6 +674,73 @@ cleanup: return ret; } +/* + * cgroup migration permission check should be performed based on the + * credentials at the time of open instead of write. + */ +static int test_cgcore_lesser_euid_open(const char *root) +{ + const uid_t test_euid = 65534; /* usually nobody, any !root is fine */ + int ret = KSFT_FAIL; + char *cg_test_a = NULL, *cg_test_b = NULL; + char *cg_test_a_procs = NULL, *cg_test_b_procs = NULL; + int cg_test_b_procs_fd = -1; + uid_t saved_uid; + + cg_test_a = cg_name(root, "cg_test_a"); + cg_test_b = cg_name(root, "cg_test_b"); + + if (!cg_test_a || !cg_test_b) + goto cleanup; + + cg_test_a_procs = cg_name(cg_test_a, "cgroup.procs"); + cg_test_b_procs = cg_name(cg_test_b, "cgroup.procs"); + + if (!cg_test_a_procs || !cg_test_b_procs) + goto cleanup; + + if (cg_create(cg_test_a) || cg_create(cg_test_b)) + goto cleanup; + + if (cg_enter_current(cg_test_a)) + goto cleanup; + + if (chown(cg_test_a_procs, test_euid, -1) || + chown(cg_test_b_procs, test_euid, -1)) + goto cleanup; + + saved_uid = geteuid(); + if (seteuid(test_euid)) + goto cleanup; + + cg_test_b_procs_fd = open(cg_test_b_procs, O_RDWR); + + if (seteuid(saved_uid)) + goto cleanup; + + if (cg_test_b_procs_fd < 0) + goto cleanup; + + if (write(cg_test_b_procs_fd, "0", 1) >= 0 || errno != EACCES) + goto cleanup; + + ret = KSFT_PASS; + +cleanup: + cg_enter_current(root); + if (cg_test_b_procs_fd >= 0) + close(cg_test_b_procs_fd); + if (cg_test_b) + cg_destroy(cg_test_b); + if (cg_test_a) + cg_destroy(cg_test_a); + free(cg_test_b_procs); + free(cg_test_a_procs); + free(cg_test_b); + free(cg_test_a); + return ret; +} + #define T(x) { x, #x } struct corecg_test { int (*fn)(const char *root); @@ -689,6 +756,7 @@ struct corecg_test { T(test_cgcore_proc_migration), T(test_cgcore_thread_migration), T(test_cgcore_destroy), + T(test_cgcore_lesser_euid_open), }; #undef T -- GitLab From bf35a7879f1dfb0d050fe779168bcf25c7de66f5 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 6 Jan 2022 11:02:29 -1000 Subject: [PATCH 952/965] selftests: cgroup: Test open-time cgroup namespace usage for migration checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a task is writing to an fd opened by a different task, the perm check should use the cgroup namespace of the latter task. Add a test for it. Tested-by: Michal Koutný Signed-off-by: Tejun Heo --- tools/testing/selftests/cgroup/test_core.c | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/tools/testing/selftests/cgroup/test_core.c b/tools/testing/selftests/cgroup/test_core.c index 01b7665069735..6001235030631 100644 --- a/tools/testing/selftests/cgroup/test_core.c +++ b/tools/testing/selftests/cgroup/test_core.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 */ +#define _GNU_SOURCE #include +#include #include #include #include #include #include +#include #include #include #include @@ -741,6 +744,99 @@ cleanup: return ret; } +struct lesser_ns_open_thread_arg { + const char *path; + int fd; + int err; +}; + +static int lesser_ns_open_thread_fn(void *arg) +{ + struct lesser_ns_open_thread_arg *targ = arg; + + targ->fd = open(targ->path, O_RDWR); + targ->err = errno; + return 0; +} + +/* + * cgroup migration permission check should be performed based on the cgroup + * namespace at the time of open instead of write. + */ +static int test_cgcore_lesser_ns_open(const char *root) +{ + static char stack[65536]; + const uid_t test_euid = 65534; /* usually nobody, any !root is fine */ + int ret = KSFT_FAIL; + char *cg_test_a = NULL, *cg_test_b = NULL; + char *cg_test_a_procs = NULL, *cg_test_b_procs = NULL; + int cg_test_b_procs_fd = -1; + struct lesser_ns_open_thread_arg targ = { .fd = -1 }; + pid_t pid; + int status; + + cg_test_a = cg_name(root, "cg_test_a"); + cg_test_b = cg_name(root, "cg_test_b"); + + if (!cg_test_a || !cg_test_b) + goto cleanup; + + cg_test_a_procs = cg_name(cg_test_a, "cgroup.procs"); + cg_test_b_procs = cg_name(cg_test_b, "cgroup.procs"); + + if (!cg_test_a_procs || !cg_test_b_procs) + goto cleanup; + + if (cg_create(cg_test_a) || cg_create(cg_test_b)) + goto cleanup; + + if (cg_enter_current(cg_test_b)) + goto cleanup; + + if (chown(cg_test_a_procs, test_euid, -1) || + chown(cg_test_b_procs, test_euid, -1)) + goto cleanup; + + targ.path = cg_test_b_procs; + pid = clone(lesser_ns_open_thread_fn, stack + sizeof(stack), + CLONE_NEWCGROUP | CLONE_FILES | CLONE_VM | SIGCHLD, + &targ); + if (pid < 0) + goto cleanup; + + if (waitpid(pid, &status, 0) < 0) + goto cleanup; + + if (!WIFEXITED(status)) + goto cleanup; + + cg_test_b_procs_fd = targ.fd; + if (cg_test_b_procs_fd < 0) + goto cleanup; + + if (cg_enter_current(cg_test_a)) + goto cleanup; + + if ((status = write(cg_test_b_procs_fd, "0", 1)) >= 0 || errno != ENOENT) + goto cleanup; + + ret = KSFT_PASS; + +cleanup: + cg_enter_current(root); + if (cg_test_b_procs_fd >= 0) + close(cg_test_b_procs_fd); + if (cg_test_b) + cg_destroy(cg_test_b); + if (cg_test_a) + cg_destroy(cg_test_a); + free(cg_test_b_procs); + free(cg_test_a_procs); + free(cg_test_b); + free(cg_test_a); + return ret; +} + #define T(x) { x, #x } struct corecg_test { int (*fn)(const char *root); @@ -757,6 +853,7 @@ struct corecg_test { T(test_cgcore_thread_migration), T(test_cgcore_destroy), T(test_cgcore_lesser_euid_open), + T(test_cgcore_lesser_ns_open), }; #undef T -- GitLab From 7b2932162f66ab33a00a7cdb6d3b2db6dfdbf634 Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Wed, 5 Jan 2022 16:10:54 +0100 Subject: [PATCH 953/965] s390/pci: simplify __pciwb_mio() inline asm The PCI Write Barrier instruction ignores the registers encoded in it. There is thus no need to explicitly set the register to zero or to associate it with a variable at all. In the resulting binary this removes an unnecessary lghi and it makes the code simpler. Signed-off-by: Niklas Schnelle Signed-off-by: Heiko Carstens --- arch/s390/pci/pci_insn.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/s390/pci/pci_insn.c b/arch/s390/pci/pci_insn.c index 28d863aaafea5..4dd58b196cea7 100644 --- a/arch/s390/pci/pci_insn.c +++ b/arch/s390/pci/pci_insn.c @@ -365,10 +365,7 @@ EXPORT_SYMBOL_GPL(zpci_write_block); static inline void __pciwb_mio(void) { - unsigned long unused = 0; - - asm volatile (".insn rre,0xb9d50000,%[op],%[op]\n" - : [op] "+d" (unused)); + asm volatile (".insn rre,0xb9d50000,0,0\n"); } void zpci_barrier(void) -- GitLab From 2056e2989bf47ad7274ecc5e9dda2add53c112f9 Mon Sep 17 00:00:00 2001 From: Dave Hansen Date: Tue, 4 Jan 2022 09:15:27 -0800 Subject: [PATCH 954/965] x86/sgx: Fix NULL pointer dereference on non-SGX systems == Problem == Nathan Chancellor reported an oops when aceessing the 'sgx_total_bytes' sysfs file: https://lore.kernel.org/all/YbzhBrimHGGpddDM@archlinux-ax161/ The sysfs output code accesses the sgx_numa_nodes[] array unconditionally. However, this array is allocated during SGX initialization, which only occurs on systems where SGX is supported. If the sysfs file is accessed on systems without SGX support, sgx_numa_nodes[] is NULL and an oops occurs. == Solution == To fix this, hide the entire nodeX/x86/ attribute group on systems without SGX support using the ->is_visible attribute group callback. Unfortunately, SGX is initialized via a device_initcall() which occurs _after_ the ->is_visible() callback. Instead of moving SGX initialization earlier, call sysfs_update_group() during SGX initialization to update the group visiblility. This update requires moving the SGX sysfs code earlier in sgx/main.c. There are no code changes other than the addition of arch_update_sysfs_visibility() and a minor whitespace fixup to arch_node_attr_is_visible() which checkpatch caught. CC: Greg Kroah-Hartman Cc: linux-sgx@vger.kernel.org Cc: x86@kernel.org Fixes: 50468e431335 ("x86/sgx: Add an attribute for the amount of SGX memory in a NUMA node") Reported-by: Nathan Chancellor Signed-off-by: Dave Hansen Reviewed-by: Greg Kroah-Hartman Reviewed-by: Jarkko Sakkinen Tested-by: Nathan Chancellor Tested-by: Jarkko Sakkinen Link: https://lkml.kernel.org/r/20220104171527.5E8416A8@davehans-spike.ostc.intel.com --- arch/x86/kernel/cpu/sgx/main.c | 65 ++++++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 2857a49f23359..4b41efc9e367a 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -6,11 +6,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include "driver.h" #include "encl.h" @@ -780,6 +782,48 @@ static inline u64 __init sgx_calc_section_metric(u64 low, u64 high) ((high & GENMASK_ULL(19, 0)) << 32); } +#ifdef CONFIG_NUMA +static ssize_t sgx_total_bytes_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%lu\n", sgx_numa_nodes[dev->id].size); +} +static DEVICE_ATTR_RO(sgx_total_bytes); + +static umode_t arch_node_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ + /* Make all x86/ attributes invisible when SGX is not initialized: */ + if (nodes_empty(sgx_numa_mask)) + return 0; + + return attr->mode; +} + +static struct attribute *arch_node_dev_attrs[] = { + &dev_attr_sgx_total_bytes.attr, + NULL, +}; + +const struct attribute_group arch_node_dev_group = { + .name = "x86", + .attrs = arch_node_dev_attrs, + .is_visible = arch_node_attr_is_visible, +}; + +static void __init arch_update_sysfs_visibility(int nid) +{ + struct node *node = node_devices[nid]; + int ret; + + ret = sysfs_update_group(&node->dev.kobj, &arch_node_dev_group); + + if (ret) + pr_err("sysfs update failed (%d), files may be invisible", ret); +} +#else /* !CONFIG_NUMA */ +static void __init arch_update_sysfs_visibility(int nid) {} +#endif + static bool __init sgx_page_cache_init(void) { u32 eax, ebx, ecx, edx, type; @@ -826,6 +870,9 @@ static bool __init sgx_page_cache_init(void) INIT_LIST_HEAD(&sgx_numa_nodes[nid].sgx_poison_page_list); node_set(nid, sgx_numa_mask); sgx_numa_nodes[nid].size = 0; + + /* Make SGX-specific node sysfs files visible: */ + arch_update_sysfs_visibility(nid); } sgx_epc_sections[i].node = &sgx_numa_nodes[nid]; @@ -903,24 +950,6 @@ int sgx_set_attribute(unsigned long *allowed_attributes, } EXPORT_SYMBOL_GPL(sgx_set_attribute); -#ifdef CONFIG_NUMA -static ssize_t sgx_total_bytes_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - return sysfs_emit(buf, "%lu\n", sgx_numa_nodes[dev->id].size); -} -static DEVICE_ATTR_RO(sgx_total_bytes); - -static struct attribute *arch_node_dev_attrs[] = { - &dev_attr_sgx_total_bytes.attr, - NULL, -}; - -const struct attribute_group arch_node_dev_group = { - .name = "x86", - .attrs = arch_node_dev_attrs, -}; -#endif /* CONFIG_NUMA */ - static int __init sgx_init(void) { int ret; -- GitLab From 597cb7968cb6243e915ba9599195656be14773e5 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Tue, 4 Jan 2022 22:41:03 -0800 Subject: [PATCH 955/965] KVM: SEV: Mark nested locking of kvm->lock Both source and dest vms' kvm->locks are held in sev_lock_two_vms. Mark one with a different subtype to avoid false positives from lockdep. Fixes: c9d61dcb0bc26 (KVM: SEV: accept signals in sev_lock_two_vms) Reported-by: Yiru Xu Tested-by: Jinrong Liang Signed-off-by: Wanpeng Li Message-Id: <1641364863-26331-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini --- arch/x86/kvm/svm/sev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 7656a2c5662a6..be28831412209 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -1565,7 +1565,7 @@ static int sev_lock_two_vms(struct kvm *dst_kvm, struct kvm *src_kvm) r = -EINTR; if (mutex_lock_killable(&dst_kvm->lock)) goto release_src; - if (mutex_lock_killable(&src_kvm->lock)) + if (mutex_lock_killable_nested(&src_kvm->lock, SINGLE_DEPTH_NESTING)) goto unlock_dst; return 0; -- GitLab From fffb5323780786c81ba005f8b8603d4a558aad28 Mon Sep 17 00:00:00 2001 From: Nikunj A Dadhania Date: Wed, 5 Jan 2022 09:33:37 +0530 Subject: [PATCH 956/965] KVM: x86: Check for rmaps allocation With TDP MMU being the default now, access to mmu_rmaps_stat debugfs file causes following oops: BUG: kernel NULL pointer dereference, address: 0000000000000000 PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP NOPTI CPU: 7 PID: 3185 Comm: cat Not tainted 5.16.0-rc4+ #204 RIP: 0010:pte_list_count+0x6/0x40 Call Trace: ? kvm_mmu_rmaps_stat_show+0x15e/0x320 seq_read_iter+0x126/0x4b0 ? aa_file_perm+0x124/0x490 seq_read+0xf5/0x140 full_proxy_read+0x5c/0x80 vfs_read+0x9f/0x1a0 ksys_read+0x67/0xe0 __x64_sys_read+0x19/0x20 do_syscall_64+0x3b/0xc0 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7fca6fc13912 Return early when rmaps are not present. Reported-by: Vasant Hegde Tested-by: Vasant Hegde Signed-off-by: Nikunj A Dadhania Reviewed-by: Peter Xu Reviewed-by: Sean Christopherson Message-Id: <20220105040337.4234-1-nikunj@amd.com> Cc: stable@vger.kernel.org Fixes: 3bcd0662d66f ("KVM: X86: Introduce mmu_rmaps_stat per-vm debugfs file") Signed-off-by: Paolo Bonzini --- arch/x86/kvm/debugfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/debugfs.c b/arch/x86/kvm/debugfs.c index 54a83a7445384..f33c804a922ac 100644 --- a/arch/x86/kvm/debugfs.c +++ b/arch/x86/kvm/debugfs.c @@ -95,6 +95,9 @@ static int kvm_mmu_rmaps_stat_show(struct seq_file *m, void *v) unsigned int *log[KVM_NR_PAGE_SIZES], *cur; int i, j, k, l, ret; + if (!kvm_memslots_have_rmaps(kvm)) + return 0; + ret = -ENOMEM; memset(log, 0, sizeof(log)); for (i = 0; i < KVM_NR_PAGE_SIZES; i++) { -- GitLab From f06a82f9d31a87878a9295bac1defdadbc77bbc0 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Thu, 6 Jan 2022 23:20:30 +0100 Subject: [PATCH 957/965] perf trace: Avoid early exit due to running SIGCHLD handler before it makes sense to When running 'perf trace' with an BPF object like: # perf trace -e openat,tools/perf/examples/bpf/hello.c the event parsing eventually calls llvm__get_kbuild_opts() that runs a script and that ends up with SIGCHLD delivered to the 'perf trace' handler, which assumes the workload process is done and quits 'perf trace'. Move the SIGCHLD handler setup directly to trace__run(), where the event is parsed and the object is already compiled. Signed-off-by: Jiri Olsa Tested-by: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Christy Lee Cc: Ian Rogers Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220106222030.227499-1-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 0b52e08e558e3..ef94388e83234 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -3925,6 +3925,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv) bool draining = false; trace->live = true; + signal(SIGCHLD, sig_handler); if (!trace->raw_augmented_syscalls) { if (trace->trace_syscalls && trace__add_syscall_newtp(trace)) @@ -4873,7 +4874,6 @@ int cmd_trace(int argc, const char **argv) signal(SIGSEGV, sighandler_dump_stack); signal(SIGFPE, sighandler_dump_stack); - signal(SIGCHLD, sig_handler); signal(SIGINT, sig_handler); trace.evlist = evlist__new(); -- GitLab From dc9f2dd5de04d2bbcccbabdf5df9715c2ddcf25f Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Fri, 7 Jan 2022 16:02:54 -0300 Subject: [PATCH 958/965] Revert "libtraceevent: Increase libtraceevent logging when verbose" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 08efcb4a638d260ef7fcbae64ecf7ceceb3f1841. This breaks the build as it will prefer using libbpf-devel header files, even when not using LIBBPF_DYNAMIC=1, breaking the build. This was detected on OpenSuSE Tumbleweed with libtraceevent-devel 1.3.0, as described by Jiri Slaby: ======================================================================= It breaks build with LIBTRACEEVENT_DYNAMIC and version 1.3.0: > util/debug.c: In function ‘perf_debug_option’: > util/debug.c:243:17: error: implicit declaration of function ‘tep_set_loglevel’ [-Werror=implicit-function-declaration] > 243 | tep_set_loglevel(TEP_LOG_INFO); > | ^~~~~~~~~~~~~~~~ > util/debug.c:243:34: error: ‘TEP_LOG_INFO’ undeclared (first use in this function); did you mean ‘TEP_PRINT_INFO’? > 243 | tep_set_loglevel(TEP_LOG_INFO); > | ^~~~~~~~~~~~ > | TEP_PRINT_INFO > util/debug.c:243:34: note: each undeclared identifier is reported only once for each function it appears in > util/debug.c:245:34: error: ‘TEP_LOG_DEBUG’ undeclared (first use in this function) > 245 | tep_set_loglevel(TEP_LOG_DEBUG); > | ^~~~~~~~~~~~~ > util/debug.c:247:34: error: ‘TEP_LOG_ALL’ undeclared (first use in this function) > 247 | tep_set_loglevel(TEP_LOG_ALL); > | ^~~~~~~~~~~ It is because the gcc's command line looks like: gcc ... -I/home/abuild/rpmbuild/BUILD/tools/lib/ ... -DLIBTRACEEVENT_VERSION=65790 ... ======================================================================= The proper way to fix this is more involved and so not suitable for this late in the 5.16-rc stage. Reported-by: Jiri Slaby Link: https://lore.kernel.org/lkml/bc2b0786-8965-1bcd-2316-9d9bb37b9c31@kernel.org Cc: Andrii Nakryiko Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Song Liu Cc: Steven Rostedt Link: https://lore.kernel.org/lkml/YddGjjmlMZzxUZbN@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/debug.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/tools/perf/util/debug.c b/tools/perf/util/debug.c index c7a9fa0ffae9d..2c06abf6dcd26 100644 --- a/tools/perf/util/debug.c +++ b/tools/perf/util/debug.c @@ -24,16 +24,6 @@ #include "util/parse-sublevel-options.h" #include -#include - -#define MAKE_LIBTRACEEVENT_VERSION(a, b, c) ((a)*255*255+(b)*255+(c)) -#ifndef LIBTRACEEVENT_VERSION -/* - * If LIBTRACEEVENT_VERSION wasn't computed then set to version 1.1.0 that ships - * with the Linux kernel tools. - */ -#define LIBTRACEEVENT_VERSION MAKE_LIBTRACEEVENT_VERSION(1, 1, 0) -#endif int verbose; int debug_peo_args; @@ -238,15 +228,6 @@ int perf_debug_option(const char *str) /* Allow only verbose value in range (0, 10), otherwise set 0. */ verbose = (verbose < 0) || (verbose > 10) ? 0 : verbose; -#if MAKE_LIBTRACEEVENT_VERSION(1, 3, 0) <= LIBTRACEEVENT_VERSION - if (verbose == 1) - tep_set_loglevel(TEP_LOG_INFO); - else if (verbose == 2) - tep_set_loglevel(TEP_LOG_DEBUG); - else if (verbose >= 3) - tep_set_loglevel(TEP_LOG_ALL); -#endif - return 0; } -- GitLab From a19f75de73c220b4496d2aefb7a605dd032f7c01 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 6 Jan 2022 13:24:52 +0100 Subject: [PATCH 959/965] Revert "i2c: core: support bus regulator controlling in adapter" This largely reverts commit 5a7b95fb993ec399c8a685552aa6a8fc995c40bd. It breaks suspend with AMD GPUs, and we couldn't incrementally fix it. So, let's remove the code and go back to the drawing board. We keep the header extension to not break drivers already populating the regulator. We expect to re-add the code handling it soon. Fixes: 5a7b95fb993e ("i2c: core: support bus regulator controlling in adapter") Reported-by: "Tareque Md.Hanif" Link: https://lore.kernel.org/r/1295184560.182511.1639075777725@mail.yahoo.com Reported-by: Konstantin Kharlamov Link: https://lore.kernel.org/r/7143a7147978f4104171072d9f5225d2ce355ec1.camel@yandex.ru BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1850 Tested-by: "Tareque Md.Hanif" Tested-by: Konstantin Kharlamov Signed-off-by: Wolfram Sang Cc: # 5.14+ --- drivers/i2c/i2c-core-base.c | 95 ------------------------------------- 1 file changed, 95 deletions(-) diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index f193f90585841..73253e667de1d 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -466,14 +466,12 @@ static int i2c_smbus_host_notify_to_irq(const struct i2c_client *client) static int i2c_device_probe(struct device *dev) { struct i2c_client *client = i2c_verify_client(dev); - struct i2c_adapter *adap; struct i2c_driver *driver; int status; if (!client) return 0; - adap = client->adapter; client->irq = client->init_irq; if (!client->irq) { @@ -539,14 +537,6 @@ static int i2c_device_probe(struct device *dev) dev_dbg(dev, "probe\n"); - if (adap->bus_regulator) { - status = regulator_enable(adap->bus_regulator); - if (status < 0) { - dev_err(&adap->dev, "Failed to enable bus regulator\n"); - goto err_clear_wakeup_irq; - } - } - status = of_clk_set_defaults(dev->of_node, false); if (status < 0) goto err_clear_wakeup_irq; @@ -605,10 +595,8 @@ put_sync_adapter: static void i2c_device_remove(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); - struct i2c_adapter *adap; struct i2c_driver *driver; - adap = client->adapter; driver = to_i2c_driver(dev->driver); if (driver->remove) { int status; @@ -623,8 +611,6 @@ static void i2c_device_remove(struct device *dev) devres_release_group(&client->dev, client->devres_group_id); dev_pm_domain_detach(&client->dev, !i2c_acpi_waive_d0_probe(dev)); - if (!pm_runtime_status_suspended(&client->dev) && adap->bus_regulator) - regulator_disable(adap->bus_regulator); dev_pm_clear_wake_irq(&client->dev); device_init_wakeup(&client->dev, false); @@ -634,86 +620,6 @@ static void i2c_device_remove(struct device *dev) pm_runtime_put(&client->adapter->dev); } -#ifdef CONFIG_PM_SLEEP -static int i2c_resume_early(struct device *dev) -{ - struct i2c_client *client = i2c_verify_client(dev); - int err; - - if (!client) - return 0; - - if (pm_runtime_status_suspended(&client->dev) && - client->adapter->bus_regulator) { - err = regulator_enable(client->adapter->bus_regulator); - if (err) - return err; - } - - return pm_generic_resume_early(&client->dev); -} - -static int i2c_suspend_late(struct device *dev) -{ - struct i2c_client *client = i2c_verify_client(dev); - int err; - - if (!client) - return 0; - - err = pm_generic_suspend_late(&client->dev); - if (err) - return err; - - if (!pm_runtime_status_suspended(&client->dev) && - client->adapter->bus_regulator) - return regulator_disable(client->adapter->bus_regulator); - - return 0; -} -#endif - -#ifdef CONFIG_PM -static int i2c_runtime_resume(struct device *dev) -{ - struct i2c_client *client = i2c_verify_client(dev); - int err; - - if (!client) - return 0; - - if (client->adapter->bus_regulator) { - err = regulator_enable(client->adapter->bus_regulator); - if (err) - return err; - } - - return pm_generic_runtime_resume(&client->dev); -} - -static int i2c_runtime_suspend(struct device *dev) -{ - struct i2c_client *client = i2c_verify_client(dev); - int err; - - if (!client) - return 0; - - err = pm_generic_runtime_suspend(&client->dev); - if (err) - return err; - - if (client->adapter->bus_regulator) - return regulator_disable(client->adapter->bus_regulator); - return 0; -} -#endif - -static const struct dev_pm_ops i2c_device_pm = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(i2c_suspend_late, i2c_resume_early) - SET_RUNTIME_PM_OPS(i2c_runtime_suspend, i2c_runtime_resume, NULL) -}; - static void i2c_device_shutdown(struct device *dev) { struct i2c_client *client = i2c_verify_client(dev); @@ -773,7 +679,6 @@ struct bus_type i2c_bus_type = { .probe = i2c_device_probe, .remove = i2c_device_remove, .shutdown = i2c_device_shutdown, - .pm = &i2c_device_pm, }; EXPORT_SYMBOL_GPL(i2c_bus_type); -- GitLab From 1350f36d3825e8f9563bbffb047d6ee634949667 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 6 Jan 2022 10:52:52 +0100 Subject: [PATCH 960/965] s390/sclp_sd: use default_groups in kobj_type There are currently 2 ways to create a set of sysfs files for a kobj_type, through the default_attrs field, and the default_groups field. Move the sclp_sd sysfs code to use default_groups field which has been the preferred way since commit aa30f47cf666 ("kobject: Add support for default attribute groups to kobj_type") so that we can soon get rid of the obsolete default_attrs field. Cc: Vasily Gorbik Cc: Christian Borntraeger Cc: Alexander Gordeev Cc: Peter Oberparleiter Signed-off-by: Greg Kroah-Hartman Link: https://lore.kernel.org/r/20220106095252.3273905-1-gregkh@linuxfoundation.org Signed-off-by: Heiko Carstens --- drivers/s390/char/sclp_sd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/s390/char/sclp_sd.c b/drivers/s390/char/sclp_sd.c index 25c2d760f6e68..f9e164be7568f 100644 --- a/drivers/s390/char/sclp_sd.c +++ b/drivers/s390/char/sclp_sd.c @@ -438,11 +438,12 @@ static struct attribute *sclp_sd_file_default_attrs[] = { &reload_attr.attr, NULL, }; +ATTRIBUTE_GROUPS(sclp_sd_file_default); static struct kobj_type sclp_sd_file_ktype = { .sysfs_ops = &kobj_sysfs_ops, .release = sclp_sd_file_release, - .default_attrs = sclp_sd_file_default_attrs, + .default_groups = sclp_sd_file_default_groups, }; /** -- GitLab From 0704a8586f75663cf30a283bbeeca09eb4e60a07 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 6 Jan 2022 10:54:01 +0100 Subject: [PATCH 961/965] s390/dasd: use default_groups in kobj_type There are currently 2 ways to create a set of sysfs files for a kobj_type, through the default_attrs field, and the default_groups field. Move the s390 dasd sysfs code to use default_groups field which has been the preferred way since commit aa30f47cf666 ("kobject: Add support for default attribute groups to kobj_type") so that we can soon get rid of the obsolete default_attrs field. Cc: Stefan Haberland Cc: Jan Hoeppner Cc: Vasily Gorbik Cc: Christian Borntraeger Cc: Alexander Gordeev Signed-off-by: Greg Kroah-Hartman Link: https://lore.kernel.org/r/20220106095401.3274637-1-gregkh@linuxfoundation.org Signed-off-by: Heiko Carstens --- drivers/s390/block/dasd_devmap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/s390/block/dasd_devmap.c b/drivers/s390/block/dasd_devmap.c index 6043c832d09e4..811e79c9f59c8 100644 --- a/drivers/s390/block/dasd_devmap.c +++ b/drivers/s390/block/dasd_devmap.c @@ -1824,10 +1824,11 @@ static struct attribute *paths_info_attrs[] = { &path_fcs_attribute.attr, NULL, }; +ATTRIBUTE_GROUPS(paths_info); static struct kobj_type path_attr_type = { .release = dasd_path_release, - .default_attrs = paths_info_attrs, + .default_groups = paths_info_groups, .sysfs_ops = &kobj_sysfs_ops, }; -- GitLab From c8013355ead68dce152cf426686f8a5f80d88b40 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 4 Jan 2022 18:02:47 +0100 Subject: [PATCH 962/965] ARM: dts: gpio-ranges property is now required Since [1], added in 5.7, the absence of a gpio-ranges property has prevented GPIOs from being restored to inputs when released. Add those properties for BCM283x and BCM2711 devices. [1] commit 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") Link: https://lore.kernel.org/r/20220104170247.956760-1-linus.walleij@linaro.org Fixes: 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs") Reported-by: Stefan Wahren Reported-by: Florian Fainelli Reported-by: Jan Kiszka Signed-off-by: Phil Elwell Acked-by: Florian Fainelli Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20211206092237.4105895-3-phil@raspberrypi.com Signed-off-by: Linus Walleij Acked-by: Florian Fainelli Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm2711.dtsi | 2 ++ arch/arm/boot/dts/bcm283x.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 9e01dbca4a011..dff18fc9a9065 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -582,6 +582,8 @@ , ; + gpio-ranges = <&gpio 0 0 58>; + gpclk0_gpio49: gpclk0_gpio49 { pin-gpclk { pins = "gpio49"; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index a3e06b6809476..c113661a6668f 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -126,6 +126,8 @@ interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&gpio 0 0 54>; + /* Defines common pin muxing groups * * While each pin can have its mux selected -- GitLab From cf73ed894ee939d6706d65e0cd186e4a64e3af6d Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 8 Jan 2022 23:19:19 -0800 Subject: [PATCH 963/965] Input: zinitix - make sure the IRQ is allocated before it gets enabled Since irq request is the last thing in the driver probe, it happens later than the input device registration. This means that there is a small time window where if the open method is called the driver will attempt to enable not yet available irq. Fix that by moving the irq request before the input device registration. Reviewed-by: Linus Walleij Fixes: 26822652c85e ("Input: add zinitix touchscreen driver") Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20220106072840.36851-2-nikita@trvn.ru Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/zinitix.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/input/touchscreen/zinitix.c b/drivers/input/touchscreen/zinitix.c index b8d901099378d..1e70b8d2a8d79 100644 --- a/drivers/input/touchscreen/zinitix.c +++ b/drivers/input/touchscreen/zinitix.c @@ -488,6 +488,15 @@ static int zinitix_ts_probe(struct i2c_client *client) return error; } + error = devm_request_threaded_irq(&client->dev, client->irq, + NULL, zinitix_ts_irq_handler, + IRQF_ONESHOT | IRQF_NO_AUTOEN, + client->name, bt541); + if (error) { + dev_err(&client->dev, "Failed to request IRQ: %d\n", error); + return error; + } + error = zinitix_init_input_dev(bt541); if (error) { dev_err(&client->dev, @@ -513,15 +522,6 @@ static int zinitix_ts_probe(struct i2c_client *client) return -EINVAL; } - error = devm_request_threaded_irq(&client->dev, client->irq, - NULL, zinitix_ts_irq_handler, - IRQF_ONESHOT | IRQF_NO_AUTOEN, - client->name, bt541); - if (error) { - dev_err(&client->dev, "Failed to request IRQ: %d\n", error); - return error; - } - return 0; } -- GitLab From df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Sun, 9 Jan 2022 13:11:37 -0500 Subject: [PATCH 964/965] Revert "drm/amdgpu: stop scheduler when calling hw_fini (v2)" This reverts commit f7d6779df642720e22bffd449e683bb8690bd3bf. This bisected regression has impacted suspend-resume stability since 5.15-rc1. It regressed -stable via 5.14.10. Link: https://bugzilla.kernel.org/show_bug.cgi?id=215315 Fixes: f7d6779df64 ("drm/amdgpu: stop scheduler when calling hw_fini (v2)") Cc: Guchun Chen Cc: Andrey Grodzovsky Cc: Christian Koenig Cc: Alex Deucher Cc: # 5.14+ Signed-off-by: Len Brown Signed-off-by: Linus Torvalds --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 9afd11ca2709d..45977a72b5ddd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -547,9 +547,6 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) if (!ring || !ring->fence_drv.initialized) continue; - if (!ring->no_scheduler) - drm_sched_stop(&ring->sched, NULL); - /* You can't wait for HW to signal if it's gone */ if (!drm_dev_is_unplugged(adev_to_drm(adev))) r = amdgpu_fence_wait_empty(ring); @@ -609,11 +606,6 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) if (!ring || !ring->fence_drv.initialized) continue; - if (!ring->no_scheduler) { - drm_sched_resubmit_jobs(&ring->sched); - drm_sched_start(&ring->sched, true); - } - /* enable the interrupt */ if (ring->fence_drv.irq_src) amdgpu_irq_get(adev, ring->fence_drv.irq_src, -- GitLab From df0cc57e057f18e44dac8e6c18aba47ab53202f9 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 9 Jan 2022 14:55:34 -0800 Subject: [PATCH 965/965] Linux 5.16 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 16d7f83ac3688..08510230b42f3 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 5 PATCHLEVEL = 16 SUBLEVEL = 0 -EXTRAVERSION = -rc8 +EXTRAVERSION = NAME = Gobble Gobble # *DOCUMENTATION* -- GitLab