drm/amd/display: On clock init, maintain DISPCLK freq

[Description]
- On init if a display is connected, we need to maintain the DISPCLK
  frequency
- Even though DPG_EN=1, the display still requires the correct
  timing or it could cause audio corruption (if DISPCLK freq
  is reduced)
- Read the current DISPCLK freq and request the same value to ensure
  the timing is valid and unchanged
- However, add option to do a full pipe power down (including link)
  which will also avoid audio related issues
	- Disabled for the time being on dcn32

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>