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Commit cdc86e47 authored by Peng Fan's avatar Peng Fan Committed by Abel Vesa
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clk: imx8mq: add 27m phy pll ref clock



According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225090002.2497057-3-peng.fan@oss.nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
parent 31231092
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