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Commit c5a8e907 authored by Zong-Zhe Yang's avatar Zong-Zhe Yang Committed by Kalle Valo
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rtw88: fix RX clock gate setting while fifo dump



When fw fifo dumps, RX clock gating should be disabled to avoid
something unexpected. However, the register operation ran into
a mistake. So, we fix it.

Signed-off-by: default avatarZong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210927111830.5354-1-pkshih@realtek.com
parent a8e5387f
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